3 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * This file contains the driver for the ATMEGA series USB OTG Controller. This
29 * driver currently only supports the DCI mode of the USB hardware.
33 * NOTE: When the chip detects BUS-reset it will also reset the
34 * endpoints, Function-address and more.
37 #ifdef USB_GLOBAL_INCLUDE_FILE
38 #include USB_GLOBAL_INCLUDE_FILE
40 #include <sys/stdint.h>
41 #include <sys/stddef.h>
42 #include <sys/param.h>
43 #include <sys/queue.h>
44 #include <sys/types.h>
45 #include <sys/systm.h>
46 #include <sys/kernel.h>
48 #include <sys/module.h>
50 #include <sys/mutex.h>
51 #include <sys/condvar.h>
52 #include <sys/sysctl.h>
54 #include <sys/unistd.h>
55 #include <sys/callout.h>
56 #include <sys/malloc.h>
59 #include <dev/usb/usb.h>
60 #include <dev/usb/usbdi.h>
62 #define USB_DEBUG_VAR atmegadci_debug
64 #include <dev/usb/usb_core.h>
65 #include <dev/usb/usb_debug.h>
66 #include <dev/usb/usb_busdma.h>
67 #include <dev/usb/usb_process.h>
68 #include <dev/usb/usb_transfer.h>
69 #include <dev/usb/usb_device.h>
70 #include <dev/usb/usb_hub.h>
71 #include <dev/usb/usb_util.h>
73 #include <dev/usb/usb_controller.h>
74 #include <dev/usb/usb_bus.h>
75 #endif /* USB_GLOBAL_INCLUDE_FILE */
77 #include <dev/usb/controller/atmegadci.h>
79 #define ATMEGA_BUS2SC(bus) \
80 ((struct atmegadci_softc *)(((uint8_t *)(bus)) - \
81 ((uint8_t *)&(((struct atmegadci_softc *)0)->sc_bus))))
83 #define ATMEGA_PC2SC(pc) \
84 ATMEGA_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
87 static int atmegadci_debug = 0;
89 static SYSCTL_NODE(_hw_usb, OID_AUTO, atmegadci, CTLFLAG_RW, 0,
91 SYSCTL_INT(_hw_usb_atmegadci, OID_AUTO, debug, CTLFLAG_RWTUN,
92 &atmegadci_debug, 0, "ATMEGA DCI debug level");
95 #define ATMEGA_INTR_ENDPT 1
99 static const struct usb_bus_methods atmegadci_bus_methods;
100 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods;
101 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods;
103 static atmegadci_cmd_t atmegadci_setup_rx;
104 static atmegadci_cmd_t atmegadci_data_rx;
105 static atmegadci_cmd_t atmegadci_data_tx;
106 static atmegadci_cmd_t atmegadci_data_tx_sync;
107 static void atmegadci_device_done(struct usb_xfer *, usb_error_t);
108 static void atmegadci_do_poll(struct usb_bus *);
109 static void atmegadci_standard_done(struct usb_xfer *);
110 static void atmegadci_root_intr(struct atmegadci_softc *sc);
113 * Here is a list of what the chip supports:
115 static const struct usb_hw_ep_profile
116 atmegadci_ep_profile[2] = {
119 .max_in_frame_size = 64,
120 .max_out_frame_size = 64,
122 .support_control = 1,
125 .max_in_frame_size = 64,
126 .max_out_frame_size = 64,
129 .support_interrupt = 1,
130 .support_isochronous = 1,
137 atmegadci_get_hw_ep_profile(struct usb_device *udev,
138 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
141 *ppf = atmegadci_ep_profile;
142 else if (ep_addr < ATMEGA_EP_MAX)
143 *ppf = atmegadci_ep_profile + 1;
149 atmegadci_clocks_on(struct atmegadci_softc *sc)
151 if (sc->sc_flags.clocks_off &&
152 sc->sc_flags.port_powered) {
157 (sc->sc_clocks_on) (&sc->sc_bus);
159 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
161 ATMEGA_USBCON_OTGPADE |
162 ATMEGA_USBCON_VBUSTE);
164 sc->sc_flags.clocks_off = 0;
166 /* enable transceiver ? */
171 atmegadci_clocks_off(struct atmegadci_softc *sc)
173 if (!sc->sc_flags.clocks_off) {
177 /* disable Transceiver ? */
179 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
181 ATMEGA_USBCON_OTGPADE |
182 ATMEGA_USBCON_FRZCLK |
183 ATMEGA_USBCON_VBUSTE);
185 /* turn clocks off */
186 (sc->sc_clocks_off) (&sc->sc_bus);
188 sc->sc_flags.clocks_off = 1;
193 atmegadci_pull_up(struct atmegadci_softc *sc)
195 /* pullup D+, if possible */
197 if (!sc->sc_flags.d_pulled_up &&
198 sc->sc_flags.port_powered) {
199 sc->sc_flags.d_pulled_up = 1;
200 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, 0);
205 atmegadci_pull_down(struct atmegadci_softc *sc)
207 /* pulldown D+, if possible */
209 if (sc->sc_flags.d_pulled_up) {
210 sc->sc_flags.d_pulled_up = 0;
211 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
216 atmegadci_wakeup_peer(struct atmegadci_softc *sc)
220 if (!sc->sc_flags.status_suspend) {
224 temp = ATMEGA_READ_1(sc, ATMEGA_UDCON);
225 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, temp | ATMEGA_UDCON_RMWKUP);
227 /* wait 8 milliseconds */
228 /* Wait for reset to complete. */
229 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
231 /* hardware should have cleared RMWKUP bit */
235 atmegadci_set_address(struct atmegadci_softc *sc, uint8_t addr)
237 DPRINTFN(5, "addr=%d\n", addr);
239 addr |= ATMEGA_UDADDR_ADDEN;
241 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, addr);
245 atmegadci_setup_rx(struct atmegadci_td *td)
247 struct atmegadci_softc *sc;
248 struct usb_device_request req;
252 /* get pointer to softc */
253 sc = ATMEGA_PC2SC(td->pc);
255 /* select endpoint number */
256 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
258 /* check endpoint status */
259 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
261 DPRINTFN(5, "UEINTX=0x%02x\n", temp);
263 if (!(temp & ATMEGA_UEINTX_RXSTPI)) {
266 /* clear did stall */
268 /* get the packet byte count */
270 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
271 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
273 /* mask away undefined bits */
276 /* verify data length */
277 if (count != td->remainder) {
278 DPRINTFN(0, "Invalid SETUP packet "
279 "length, %d bytes\n", count);
282 if (count != sizeof(req)) {
283 DPRINTFN(0, "Unsupported SETUP packet "
284 "length, %d bytes\n", count);
288 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
289 (void *)&req, sizeof(req));
291 /* copy data into real buffer */
292 usbd_copy_in(td->pc, 0, &req, sizeof(req));
294 td->offset = sizeof(req);
297 /* sneak peek the set address */
298 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
299 (req.bRequest == UR_SET_ADDRESS)) {
300 sc->sc_dv_addr = req.wValue[0] & 0x7F;
301 /* must write address before ZLP */
302 ATMEGA_WRITE_1(sc, ATMEGA_UDADDR, sc->sc_dv_addr);
304 sc->sc_dv_addr = 0xFF;
307 /* Clear SETUP packet interrupt and all other previous interrupts */
308 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0);
309 return (0); /* complete */
312 /* abort any ongoing transfer */
313 if (!td->did_stall) {
314 DPRINTFN(5, "stalling\n");
315 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
317 ATMEGA_UECONX_STALLRQ);
320 if (temp & ATMEGA_UEINTX_RXSTPI) {
321 /* clear SETUP packet interrupt */
322 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ~ATMEGA_UEINTX_RXSTPI);
324 /* we only want to know if there is a SETUP packet */
325 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, ATMEGA_UEIENX_RXSTPE);
326 return (1); /* not complete */
330 atmegadci_data_rx(struct atmegadci_td *td)
332 struct atmegadci_softc *sc;
333 struct usb_page_search buf_res;
339 to = 3; /* don't loop forever! */
342 /* get pointer to softc */
343 sc = ATMEGA_PC2SC(td->pc);
345 /* select endpoint number */
346 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
349 /* check if any of the FIFO banks have data */
350 /* check endpoint status */
351 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
353 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
355 if (temp & ATMEGA_UEINTX_RXSTPI) {
356 if (td->remainder == 0) {
358 * We are actually complete and have
359 * received the next SETUP
361 DPRINTFN(5, "faking complete\n");
362 return (0); /* complete */
365 * USB Host Aborted the transfer.
368 return (0); /* complete */
371 if (!(temp & (ATMEGA_UEINTX_FIFOCON |
372 ATMEGA_UEINTX_RXOUTI))) {
376 /* get the packet byte count */
378 (ATMEGA_READ_1(sc, ATMEGA_UEBCHX) << 8) |
379 (ATMEGA_READ_1(sc, ATMEGA_UEBCLX));
381 /* mask away undefined bits */
384 /* verify the packet byte count */
385 if (count != td->max_packet_size) {
386 if (count < td->max_packet_size) {
387 /* we have a short packet */
391 /* invalid USB packet */
393 return (0); /* we are complete */
396 /* verify the packet byte count */
397 if (count > td->remainder) {
398 /* invalid USB packet */
400 return (0); /* we are complete */
403 usbd_get_page(td->pc, td->offset, &buf_res);
405 /* get correct length */
406 if (buf_res.length > count) {
407 buf_res.length = count;
410 ATMEGA_READ_MULTI_1(sc, ATMEGA_UEDATX,
411 buf_res.buffer, buf_res.length);
413 /* update counters */
414 count -= buf_res.length;
415 td->offset += buf_res.length;
416 td->remainder -= buf_res.length;
419 /* clear OUT packet interrupt */
420 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_RXOUTI ^ 0xFF);
422 /* release FIFO bank */
423 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, ATMEGA_UEINTX_FIFOCON ^ 0xFF);
425 /* check if we are complete */
426 if ((td->remainder == 0) || got_short) {
428 /* we are complete */
431 /* else need to receive a zero length packet */
437 /* we only want to know if there is a SETUP packet or OUT packet */
438 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
439 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_RXOUTE);
440 return (1); /* not complete */
444 atmegadci_data_tx(struct atmegadci_td *td)
446 struct atmegadci_softc *sc;
447 struct usb_page_search buf_res;
452 to = 3; /* don't loop forever! */
454 /* get pointer to softc */
455 sc = ATMEGA_PC2SC(td->pc);
457 /* select endpoint number */
458 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
462 /* check endpoint status */
463 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
465 DPRINTFN(5, "temp=0x%02x rem=%u\n", temp, td->remainder);
467 if (temp & ATMEGA_UEINTX_RXSTPI) {
469 * The current transfer was aborted
473 return (0); /* complete */
476 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
478 /* cannot write any data - a bank is busy */
482 count = td->max_packet_size;
483 if (td->remainder < count) {
484 /* we have a short packet */
486 count = td->remainder;
490 usbd_get_page(td->pc, td->offset, &buf_res);
492 /* get correct length */
493 if (buf_res.length > count) {
494 buf_res.length = count;
497 ATMEGA_WRITE_MULTI_1(sc, ATMEGA_UEDATX,
498 buf_res.buffer, buf_res.length);
500 /* update counters */
501 count -= buf_res.length;
502 td->offset += buf_res.length;
503 td->remainder -= buf_res.length;
506 /* clear IN packet interrupt */
507 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_TXINI);
509 /* allocate FIFO bank */
510 ATMEGA_WRITE_1(sc, ATMEGA_UEINTX, 0xFF ^ ATMEGA_UEINTX_FIFOCON);
512 /* check remainder */
513 if (td->remainder == 0) {
515 return (0); /* complete */
517 /* else we need to transmit a short packet */
523 /* we only want to know if there is a SETUP packet or free IN packet */
524 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
525 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
526 return (1); /* not complete */
530 atmegadci_data_tx_sync(struct atmegadci_td *td)
532 struct atmegadci_softc *sc;
535 /* get pointer to softc */
536 sc = ATMEGA_PC2SC(td->pc);
538 /* select endpoint number */
539 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, td->ep_no);
541 /* check endpoint status */
542 temp = ATMEGA_READ_1(sc, ATMEGA_UEINTX);
544 DPRINTFN(5, "temp=0x%02x\n", temp);
546 if (temp & ATMEGA_UEINTX_RXSTPI) {
547 DPRINTFN(5, "faking complete\n");
549 return (0); /* complete */
552 * The control endpoint has only got one bank, so if that bank
553 * is free the packet has been transferred!
555 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
557 /* cannot write any data - a bank is busy */
560 if (sc->sc_dv_addr != 0xFF) {
561 /* set new address */
562 atmegadci_set_address(sc, sc->sc_dv_addr);
564 return (0); /* complete */
567 /* we only want to know if there is a SETUP packet or free IN packet */
568 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX,
569 ATMEGA_UEIENX_RXSTPE | ATMEGA_UEIENX_TXINE);
570 return (1); /* not complete */
574 atmegadci_xfer_do_fifo(struct usb_xfer *xfer)
576 struct atmegadci_td *td;
580 td = xfer->td_transfer_cache;
582 if ((td->func) (td)) {
583 /* operation in progress */
586 if (((void *)td) == xfer->td_transfer_last) {
591 } else if (td->remainder > 0) {
593 * We had a short transfer. If there is no alternate
594 * next, stop processing !
601 * Fetch the next transfer descriptor and transfer
602 * some flags to the next transfer descriptor
605 xfer->td_transfer_cache = td;
607 return (1); /* not complete */
610 /* compute all actual lengths */
612 atmegadci_standard_done(xfer);
613 return (0); /* complete */
617 atmegadci_interrupt_poll(struct atmegadci_softc *sc)
619 struct usb_xfer *xfer;
622 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
623 if (!atmegadci_xfer_do_fifo(xfer)) {
624 /* queue has been modified */
631 atmegadci_vbus_interrupt(struct atmegadci_softc *sc, uint8_t is_on)
633 DPRINTFN(5, "vbus = %u\n", is_on);
636 if (!sc->sc_flags.status_vbus) {
637 sc->sc_flags.status_vbus = 1;
639 /* complete root HUB interrupt endpoint */
641 atmegadci_root_intr(sc);
644 if (sc->sc_flags.status_vbus) {
645 sc->sc_flags.status_vbus = 0;
646 sc->sc_flags.status_bus_reset = 0;
647 sc->sc_flags.status_suspend = 0;
648 sc->sc_flags.change_suspend = 0;
649 sc->sc_flags.change_connect = 1;
651 /* complete root HUB interrupt endpoint */
653 atmegadci_root_intr(sc);
659 atmegadci_interrupt(struct atmegadci_softc *sc)
663 USB_BUS_LOCK(&sc->sc_bus);
665 /* read interrupt status */
666 status = ATMEGA_READ_1(sc, ATMEGA_UDINT);
668 /* clear all set interrupts */
669 ATMEGA_WRITE_1(sc, ATMEGA_UDINT, (~status) & 0x7D);
671 DPRINTFN(14, "UDINT=0x%02x\n", status);
673 /* check for any bus state change interrupts */
674 if (status & ATMEGA_UDINT_EORSTI) {
676 DPRINTFN(5, "end of reset\n");
678 /* set correct state */
679 sc->sc_flags.status_bus_reset = 1;
680 sc->sc_flags.status_suspend = 0;
681 sc->sc_flags.change_suspend = 0;
682 sc->sc_flags.change_connect = 1;
684 /* disable resume interrupt */
685 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
687 ATMEGA_UDINT_EORSTE);
689 /* complete root HUB interrupt endpoint */
690 atmegadci_root_intr(sc);
693 * If resume and suspend is set at the same time we interpret
694 * that like RESUME. Resume is set when there is at least 3
695 * milliseconds of inactivity on the USB BUS.
697 if (status & ATMEGA_UDINT_WAKEUPI) {
699 DPRINTFN(5, "resume interrupt\n");
701 if (sc->sc_flags.status_suspend) {
702 /* update status bits */
703 sc->sc_flags.status_suspend = 0;
704 sc->sc_flags.change_suspend = 1;
706 /* disable resume interrupt */
707 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
709 ATMEGA_UDINT_EORSTE);
711 /* complete root HUB interrupt endpoint */
712 atmegadci_root_intr(sc);
714 } else if (status & ATMEGA_UDINT_SUSPI) {
716 DPRINTFN(5, "suspend interrupt\n");
718 if (!sc->sc_flags.status_suspend) {
719 /* update status bits */
720 sc->sc_flags.status_suspend = 1;
721 sc->sc_flags.change_suspend = 1;
723 /* disable suspend interrupt */
724 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
725 ATMEGA_UDINT_WAKEUPE |
726 ATMEGA_UDINT_EORSTE);
728 /* complete root HUB interrupt endpoint */
729 atmegadci_root_intr(sc);
733 status = ATMEGA_READ_1(sc, ATMEGA_USBINT);
735 /* clear all set interrupts */
736 ATMEGA_WRITE_1(sc, ATMEGA_USBINT, (~status) & 0x03);
738 if (status & ATMEGA_USBINT_VBUSTI) {
741 DPRINTFN(5, "USBINT=0x%02x\n", status);
743 temp = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
744 atmegadci_vbus_interrupt(sc, temp & ATMEGA_USBSTA_VBUS);
746 /* check for any endpoint interrupts */
747 status = ATMEGA_READ_1(sc, ATMEGA_UEINT);
748 /* the hardware will clear the UEINT bits automatically */
751 DPRINTFN(5, "real endpoint interrupt UEINT=0x%02x\n", status);
753 atmegadci_interrupt_poll(sc);
755 USB_BUS_UNLOCK(&sc->sc_bus);
759 atmegadci_setup_standard_chain_sub(struct atmegadci_std_temp *temp)
761 struct atmegadci_td *td;
763 /* get current Transfer Descriptor */
767 /* prepare for next TD */
768 temp->td_next = td->obj_next;
770 /* fill out the Transfer Descriptor */
771 td->func = temp->func;
773 td->offset = temp->offset;
774 td->remainder = temp->len;
776 td->did_stall = temp->did_stall;
777 td->short_pkt = temp->short_pkt;
778 td->alt_next = temp->setup_alt_next;
782 atmegadci_setup_standard_chain(struct usb_xfer *xfer)
784 struct atmegadci_std_temp temp;
785 struct atmegadci_softc *sc;
786 struct atmegadci_td *td;
791 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
792 xfer->address, UE_GET_ADDR(xfer->endpointno),
793 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
795 temp.max_frame_size = xfer->max_frame_size;
797 td = xfer->td_start[0];
798 xfer->td_transfer_first = td;
799 xfer->td_transfer_cache = td;
805 temp.td_next = xfer->td_start[0];
807 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
808 xfer->flags_int.isochronous_xfr;
809 temp.did_stall = !xfer->flags_int.control_stall;
811 sc = ATMEGA_BUS2SC(xfer->xroot->bus);
812 ep_no = (xfer->endpointno & UE_ADDR);
814 /* check if we should prepend a setup message */
816 if (xfer->flags_int.control_xfr) {
817 if (xfer->flags_int.control_hdr) {
819 temp.func = &atmegadci_setup_rx;
820 temp.len = xfer->frlengths[0];
821 temp.pc = xfer->frbuffers + 0;
822 temp.short_pkt = temp.len ? 1 : 0;
823 /* check for last frame */
824 if (xfer->nframes == 1) {
825 /* no STATUS stage yet, SETUP is last */
826 if (xfer->flags_int.control_act)
827 temp.setup_alt_next = 0;
830 atmegadci_setup_standard_chain_sub(&temp);
837 if (x != xfer->nframes) {
838 if (xfer->endpointno & UE_DIR_IN) {
839 temp.func = &atmegadci_data_tx;
842 temp.func = &atmegadci_data_rx;
846 /* setup "pc" pointer */
847 temp.pc = xfer->frbuffers + x;
851 while (x != xfer->nframes) {
853 /* DATA0 / DATA1 message */
855 temp.len = xfer->frlengths[x];
859 if (x == xfer->nframes) {
860 if (xfer->flags_int.control_xfr) {
861 if (xfer->flags_int.control_act) {
862 temp.setup_alt_next = 0;
865 temp.setup_alt_next = 0;
870 /* make sure that we send an USB packet */
876 /* regular data transfer */
878 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
881 atmegadci_setup_standard_chain_sub(&temp);
883 if (xfer->flags_int.isochronous_xfr) {
884 temp.offset += temp.len;
886 /* get next Page Cache pointer */
887 temp.pc = xfer->frbuffers + x;
891 if (xfer->flags_int.control_xfr) {
893 /* always setup a valid "pc" pointer for status and sync */
894 temp.pc = xfer->frbuffers + 0;
897 temp.setup_alt_next = 0;
899 /* check if we need to sync */
901 /* we need a SYNC point after TX */
902 temp.func = &atmegadci_data_tx_sync;
903 atmegadci_setup_standard_chain_sub(&temp);
906 /* check if we should append a status stage */
907 if (!xfer->flags_int.control_act) {
910 * Send a DATA1 message and invert the current
911 * endpoint direction.
913 if (xfer->endpointno & UE_DIR_IN) {
914 temp.func = &atmegadci_data_rx;
917 temp.func = &atmegadci_data_tx;
921 atmegadci_setup_standard_chain_sub(&temp);
923 /* we need a SYNC point after TX */
924 temp.func = &atmegadci_data_tx_sync;
925 atmegadci_setup_standard_chain_sub(&temp);
929 /* must have at least one frame! */
931 xfer->td_transfer_last = td;
935 atmegadci_timeout(void *arg)
937 struct usb_xfer *xfer = arg;
939 DPRINTF("xfer=%p\n", xfer);
941 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
943 /* transfer is transferred */
944 atmegadci_device_done(xfer, USB_ERR_TIMEOUT);
948 atmegadci_start_standard_chain(struct usb_xfer *xfer)
952 /* poll one time - will turn on interrupts */
953 if (atmegadci_xfer_do_fifo(xfer)) {
955 /* put transfer on interrupt queue */
956 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
958 /* start timeout, if any */
959 if (xfer->timeout != 0) {
960 usbd_transfer_timeout_ms(xfer,
961 &atmegadci_timeout, xfer->timeout);
967 atmegadci_root_intr(struct atmegadci_softc *sc)
971 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
974 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
976 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
977 sizeof(sc->sc_hub_idata));
981 atmegadci_standard_done_sub(struct usb_xfer *xfer)
983 struct atmegadci_td *td;
989 td = xfer->td_transfer_cache;
994 if (xfer->aframes != xfer->nframes) {
996 * Verify the length and subtract
997 * the remainder from "frlengths[]":
999 if (len > xfer->frlengths[xfer->aframes]) {
1002 xfer->frlengths[xfer->aframes] -= len;
1005 /* Check for transfer error */
1007 /* the transfer is finished */
1012 /* Check for short transfer */
1014 if (xfer->flags_int.short_frames_ok ||
1015 xfer->flags_int.isochronous_xfr) {
1016 /* follow alt next */
1023 /* the transfer is finished */
1031 /* this USB frame is complete */
1037 /* update transfer cache */
1039 xfer->td_transfer_cache = td;
1042 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1046 atmegadci_standard_done(struct usb_xfer *xfer)
1048 usb_error_t err = 0;
1050 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1051 xfer, xfer->endpoint);
1055 xfer->td_transfer_cache = xfer->td_transfer_first;
1057 if (xfer->flags_int.control_xfr) {
1059 if (xfer->flags_int.control_hdr) {
1061 err = atmegadci_standard_done_sub(xfer);
1065 if (xfer->td_transfer_cache == NULL) {
1069 while (xfer->aframes != xfer->nframes) {
1071 err = atmegadci_standard_done_sub(xfer);
1074 if (xfer->td_transfer_cache == NULL) {
1079 if (xfer->flags_int.control_xfr &&
1080 !xfer->flags_int.control_act) {
1082 err = atmegadci_standard_done_sub(xfer);
1085 atmegadci_device_done(xfer, err);
1088 /*------------------------------------------------------------------------*
1089 * atmegadci_device_done
1091 * NOTE: this function can be called more than one time on the
1092 * same USB transfer!
1093 *------------------------------------------------------------------------*/
1095 atmegadci_device_done(struct usb_xfer *xfer, usb_error_t error)
1097 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1100 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1102 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
1103 xfer, xfer->endpoint, error);
1105 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1106 ep_no = (xfer->endpointno & UE_ADDR);
1108 /* select endpoint number */
1109 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1111 /* disable endpoint interrupt */
1112 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1114 DPRINTFN(15, "disabled interrupts!\n");
1116 /* dequeue transfer and start next transfer */
1117 usbd_transfer_done(xfer, error);
1121 atmegadci_xfer_stall(struct usb_xfer *xfer)
1123 atmegadci_device_done(xfer, USB_ERR_STALLED);
1127 atmegadci_set_stall(struct usb_device *udev,
1128 struct usb_endpoint *ep, uint8_t *did_stall)
1130 struct atmegadci_softc *sc;
1133 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1135 DPRINTFN(5, "endpoint=%p\n", ep);
1137 sc = ATMEGA_BUS2SC(udev->bus);
1138 /* get endpoint number */
1139 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1140 /* select endpoint number */
1141 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1143 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1144 ATMEGA_UECONX_EPEN |
1145 ATMEGA_UECONX_STALLRQ);
1149 atmegadci_clear_stall_sub(struct atmegadci_softc *sc, uint8_t ep_no,
1150 uint8_t ep_type, uint8_t ep_dir)
1154 if (ep_type == UE_CONTROL) {
1155 /* clearing stall is not needed */
1158 /* select endpoint number */
1159 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, ep_no);
1161 /* set endpoint reset */
1162 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(ep_no));
1164 /* clear endpoint reset */
1165 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1168 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1169 ATMEGA_UECONX_EPEN |
1170 ATMEGA_UECONX_STALLRQ);
1172 /* reset data toggle */
1173 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1174 ATMEGA_UECONX_EPEN |
1175 ATMEGA_UECONX_RSTDT);
1178 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1179 ATMEGA_UECONX_EPEN |
1180 ATMEGA_UECONX_STALLRQC);
1183 if (ep_type == UE_BULK) {
1184 temp = ATMEGA_UECFG0X_EPTYPE2;
1185 } else if (ep_type == UE_INTERRUPT) {
1186 temp = ATMEGA_UECFG0X_EPTYPE3;
1188 temp = ATMEGA_UECFG0X_EPTYPE1;
1190 if (ep_dir & UE_DIR_IN) {
1191 temp |= ATMEGA_UECFG0X_EPDIR;
1193 /* two banks, 64-bytes wMaxPacket */
1194 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X, temp);
1195 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1196 ATMEGA_UECFG1X_ALLOC |
1197 ATMEGA_UECFG1X_EPBK0 | /* one bank */
1198 ATMEGA_UECFG1X_EPSIZE(3));
1200 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1201 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1202 device_printf(sc->sc_bus.bdev,
1203 "Chip rejected configuration\n");
1209 atmegadci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1211 struct atmegadci_softc *sc;
1212 struct usb_endpoint_descriptor *ed;
1214 DPRINTFN(5, "endpoint=%p\n", ep);
1216 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1219 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1224 sc = ATMEGA_BUS2SC(udev->bus);
1226 /* get endpoint descriptor */
1229 /* reset endpoint */
1230 atmegadci_clear_stall_sub(sc,
1231 (ed->bEndpointAddress & UE_ADDR),
1232 (ed->bmAttributes & UE_XFERTYPE),
1233 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1237 atmegadci_init(struct atmegadci_softc *sc)
1243 /* set up the bus structure */
1244 sc->sc_bus.usbrev = USB_REV_1_1;
1245 sc->sc_bus.methods = &atmegadci_bus_methods;
1247 USB_BUS_LOCK(&sc->sc_bus);
1249 /* make sure USB is enabled */
1250 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1251 ATMEGA_USBCON_USBE |
1252 ATMEGA_USBCON_FRZCLK);
1254 /* enable USB PAD regulator */
1255 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON,
1256 ATMEGA_UHWCON_UVREGE |
1257 ATMEGA_UHWCON_UIMOD);
1259 /* the following register sets up the USB PLL, assuming 16MHz X-tal */
1260 ATMEGA_WRITE_1(sc, 0x49 /* PLLCSR */, 0x14 | 0x02);
1262 /* wait for PLL to lock */
1263 for (n = 0; n != 20; n++) {
1264 if (ATMEGA_READ_1(sc, 0x49) & 0x01)
1266 /* wait a little bit for PLL to start */
1267 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1270 /* make sure USB is enabled */
1271 ATMEGA_WRITE_1(sc, ATMEGA_USBCON,
1272 ATMEGA_USBCON_USBE |
1273 ATMEGA_USBCON_OTGPADE |
1274 ATMEGA_USBCON_VBUSTE);
1276 /* turn on clocks */
1277 (sc->sc_clocks_on) (&sc->sc_bus);
1279 /* make sure device is re-enumerated */
1280 ATMEGA_WRITE_1(sc, ATMEGA_UDCON, ATMEGA_UDCON_DETACH);
1282 /* wait a little for things to stabilise */
1283 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1285 /* enable interrupts */
1286 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN,
1287 ATMEGA_UDINT_SUSPE |
1288 ATMEGA_UDINT_EORSTE);
1290 /* reset all endpoints */
1291 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1292 (1 << ATMEGA_EP_MAX) - 1);
1295 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1297 /* disable all endpoints */
1298 for (n = 0; n != ATMEGA_EP_MAX; n++) {
1300 /* select endpoint */
1301 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, n);
1303 /* disable endpoint interrupt */
1304 ATMEGA_WRITE_1(sc, ATMEGA_UEIENX, 0);
1306 /* disable endpoint */
1307 ATMEGA_WRITE_1(sc, ATMEGA_UECONX, 0);
1310 /* turn off clocks */
1312 atmegadci_clocks_off(sc);
1314 /* read initial VBUS state */
1316 n = ATMEGA_READ_1(sc, ATMEGA_USBSTA);
1317 atmegadci_vbus_interrupt(sc, n & ATMEGA_USBSTA_VBUS);
1319 USB_BUS_UNLOCK(&sc->sc_bus);
1321 /* catch any lost interrupts */
1323 atmegadci_do_poll(&sc->sc_bus);
1325 return (0); /* success */
1329 atmegadci_uninit(struct atmegadci_softc *sc)
1331 USB_BUS_LOCK(&sc->sc_bus);
1333 /* turn on clocks */
1334 (sc->sc_clocks_on) (&sc->sc_bus);
1336 /* disable interrupts */
1337 ATMEGA_WRITE_1(sc, ATMEGA_UDIEN, 0);
1339 /* reset all endpoints */
1340 ATMEGA_WRITE_1(sc, ATMEGA_UERST,
1341 (1 << ATMEGA_EP_MAX) - 1);
1344 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1346 sc->sc_flags.port_powered = 0;
1347 sc->sc_flags.status_vbus = 0;
1348 sc->sc_flags.status_bus_reset = 0;
1349 sc->sc_flags.status_suspend = 0;
1350 sc->sc_flags.change_suspend = 0;
1351 sc->sc_flags.change_connect = 1;
1353 atmegadci_pull_down(sc);
1354 atmegadci_clocks_off(sc);
1356 /* disable USB PAD regulator */
1357 ATMEGA_WRITE_1(sc, ATMEGA_UHWCON, 0);
1359 USB_BUS_UNLOCK(&sc->sc_bus);
1363 atmegadci_suspend(struct atmegadci_softc *sc)
1369 atmegadci_resume(struct atmegadci_softc *sc)
1375 atmegadci_do_poll(struct usb_bus *bus)
1377 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
1379 USB_BUS_LOCK(&sc->sc_bus);
1380 atmegadci_interrupt_poll(sc);
1381 USB_BUS_UNLOCK(&sc->sc_bus);
1384 /*------------------------------------------------------------------------*
1385 * atmegadci bulk support
1386 * atmegadci control support
1387 * atmegadci interrupt support
1388 *------------------------------------------------------------------------*/
1390 atmegadci_device_non_isoc_open(struct usb_xfer *xfer)
1396 atmegadci_device_non_isoc_close(struct usb_xfer *xfer)
1398 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1402 atmegadci_device_non_isoc_enter(struct usb_xfer *xfer)
1408 atmegadci_device_non_isoc_start(struct usb_xfer *xfer)
1411 atmegadci_setup_standard_chain(xfer);
1412 atmegadci_start_standard_chain(xfer);
1415 static const struct usb_pipe_methods atmegadci_device_non_isoc_methods =
1417 .open = atmegadci_device_non_isoc_open,
1418 .close = atmegadci_device_non_isoc_close,
1419 .enter = atmegadci_device_non_isoc_enter,
1420 .start = atmegadci_device_non_isoc_start,
1423 /*------------------------------------------------------------------------*
1424 * atmegadci full speed isochronous support
1425 *------------------------------------------------------------------------*/
1427 atmegadci_device_isoc_fs_open(struct usb_xfer *xfer)
1433 atmegadci_device_isoc_fs_close(struct usb_xfer *xfer)
1435 atmegadci_device_done(xfer, USB_ERR_CANCELLED);
1439 atmegadci_device_isoc_fs_enter(struct usb_xfer *xfer)
1441 struct atmegadci_softc *sc = ATMEGA_BUS2SC(xfer->xroot->bus);
1445 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1446 xfer, xfer->endpoint->isoc_next, xfer->nframes);
1448 /* get the current frame index */
1451 (ATMEGA_READ_1(sc, ATMEGA_UDFNUMH) << 8) |
1452 (ATMEGA_READ_1(sc, ATMEGA_UDFNUML));
1454 nframes &= ATMEGA_FRAME_MASK;
1457 * check if the frame index is within the window where the frames
1460 temp = (nframes - xfer->endpoint->isoc_next) & ATMEGA_FRAME_MASK;
1462 if ((xfer->endpoint->is_synced == 0) ||
1463 (temp < xfer->nframes)) {
1465 * If there is data underflow or the pipe queue is
1466 * empty we schedule the transfer a few frames ahead
1467 * of the current frame position. Else two isochronous
1468 * transfers might overlap.
1470 xfer->endpoint->isoc_next = (nframes + 3) & ATMEGA_FRAME_MASK;
1471 xfer->endpoint->is_synced = 1;
1472 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1475 * compute how many milliseconds the insertion is ahead of the
1476 * current frame position:
1478 temp = (xfer->endpoint->isoc_next - nframes) & ATMEGA_FRAME_MASK;
1481 * pre-compute when the isochronous transfer will be finished:
1483 xfer->isoc_time_complete =
1484 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1487 /* compute frame number for next insertion */
1488 xfer->endpoint->isoc_next += xfer->nframes;
1491 atmegadci_setup_standard_chain(xfer);
1495 atmegadci_device_isoc_fs_start(struct usb_xfer *xfer)
1497 /* start TD chain */
1498 atmegadci_start_standard_chain(xfer);
1501 static const struct usb_pipe_methods atmegadci_device_isoc_fs_methods =
1503 .open = atmegadci_device_isoc_fs_open,
1504 .close = atmegadci_device_isoc_fs_close,
1505 .enter = atmegadci_device_isoc_fs_enter,
1506 .start = atmegadci_device_isoc_fs_start,
1509 /*------------------------------------------------------------------------*
1510 * atmegadci root control support
1511 *------------------------------------------------------------------------*
1512 * Simulate a hardware HUB by handling all the necessary requests.
1513 *------------------------------------------------------------------------*/
1515 static const struct usb_device_descriptor atmegadci_devd = {
1516 .bLength = sizeof(struct usb_device_descriptor),
1517 .bDescriptorType = UDESC_DEVICE,
1518 .bcdUSB = {0x00, 0x02},
1519 .bDeviceClass = UDCLASS_HUB,
1520 .bDeviceSubClass = UDSUBCLASS_HUB,
1521 .bDeviceProtocol = UDPROTO_FSHUB,
1522 .bMaxPacketSize = 64,
1523 .bcdDevice = {0x00, 0x01},
1526 .bNumConfigurations = 1,
1529 static const struct atmegadci_config_desc atmegadci_confd = {
1531 .bLength = sizeof(struct usb_config_descriptor),
1532 .bDescriptorType = UDESC_CONFIG,
1533 .wTotalLength[0] = sizeof(atmegadci_confd),
1535 .bConfigurationValue = 1,
1536 .iConfiguration = 0,
1537 .bmAttributes = UC_SELF_POWERED,
1541 .bLength = sizeof(struct usb_interface_descriptor),
1542 .bDescriptorType = UDESC_INTERFACE,
1544 .bInterfaceClass = UICLASS_HUB,
1545 .bInterfaceSubClass = UISUBCLASS_HUB,
1546 .bInterfaceProtocol = 0,
1549 .bLength = sizeof(struct usb_endpoint_descriptor),
1550 .bDescriptorType = UDESC_ENDPOINT,
1551 .bEndpointAddress = (UE_DIR_IN | ATMEGA_INTR_ENDPT),
1552 .bmAttributes = UE_INTERRUPT,
1553 .wMaxPacketSize[0] = 8,
1558 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1560 static const struct usb_hub_descriptor_min atmegadci_hubd = {
1561 .bDescLength = sizeof(atmegadci_hubd),
1562 .bDescriptorType = UDESC_HUB,
1564 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1565 .bPwrOn2PwrGood = 50,
1566 .bHubContrCurrent = 0,
1567 .DeviceRemovable = {0}, /* port is removable */
1570 #define STRING_VENDOR \
1573 #define STRING_PRODUCT \
1574 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
1576 USB_MAKE_STRING_DESC(STRING_VENDOR, atmegadci_vendor);
1577 USB_MAKE_STRING_DESC(STRING_PRODUCT, atmegadci_product);
1580 atmegadci_roothub_exec(struct usb_device *udev,
1581 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1583 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
1591 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1594 ptr = (const void *)&sc->sc_hub_temp;
1598 value = UGETW(req->wValue);
1599 index = UGETW(req->wIndex);
1601 /* demultiplex the control request */
1603 switch (req->bmRequestType) {
1604 case UT_READ_DEVICE:
1605 switch (req->bRequest) {
1606 case UR_GET_DESCRIPTOR:
1607 goto tr_handle_get_descriptor;
1609 goto tr_handle_get_config;
1611 goto tr_handle_get_status;
1617 case UT_WRITE_DEVICE:
1618 switch (req->bRequest) {
1619 case UR_SET_ADDRESS:
1620 goto tr_handle_set_address;
1622 goto tr_handle_set_config;
1623 case UR_CLEAR_FEATURE:
1624 goto tr_valid; /* nop */
1625 case UR_SET_DESCRIPTOR:
1626 goto tr_valid; /* nop */
1627 case UR_SET_FEATURE:
1633 case UT_WRITE_ENDPOINT:
1634 switch (req->bRequest) {
1635 case UR_CLEAR_FEATURE:
1636 switch (UGETW(req->wValue)) {
1637 case UF_ENDPOINT_HALT:
1638 goto tr_handle_clear_halt;
1639 case UF_DEVICE_REMOTE_WAKEUP:
1640 goto tr_handle_clear_wakeup;
1645 case UR_SET_FEATURE:
1646 switch (UGETW(req->wValue)) {
1647 case UF_ENDPOINT_HALT:
1648 goto tr_handle_set_halt;
1649 case UF_DEVICE_REMOTE_WAKEUP:
1650 goto tr_handle_set_wakeup;
1655 case UR_SYNCH_FRAME:
1656 goto tr_valid; /* nop */
1662 case UT_READ_ENDPOINT:
1663 switch (req->bRequest) {
1665 goto tr_handle_get_ep_status;
1671 case UT_WRITE_INTERFACE:
1672 switch (req->bRequest) {
1673 case UR_SET_INTERFACE:
1674 goto tr_handle_set_interface;
1675 case UR_CLEAR_FEATURE:
1676 goto tr_valid; /* nop */
1677 case UR_SET_FEATURE:
1683 case UT_READ_INTERFACE:
1684 switch (req->bRequest) {
1685 case UR_GET_INTERFACE:
1686 goto tr_handle_get_interface;
1688 goto tr_handle_get_iface_status;
1694 case UT_WRITE_CLASS_INTERFACE:
1695 case UT_WRITE_VENDOR_INTERFACE:
1699 case UT_READ_CLASS_INTERFACE:
1700 case UT_READ_VENDOR_INTERFACE:
1704 case UT_WRITE_CLASS_DEVICE:
1705 switch (req->bRequest) {
1706 case UR_CLEAR_FEATURE:
1708 case UR_SET_DESCRIPTOR:
1709 case UR_SET_FEATURE:
1716 case UT_WRITE_CLASS_OTHER:
1717 switch (req->bRequest) {
1718 case UR_CLEAR_FEATURE:
1719 goto tr_handle_clear_port_feature;
1720 case UR_SET_FEATURE:
1721 goto tr_handle_set_port_feature;
1722 case UR_CLEAR_TT_BUFFER:
1732 case UT_READ_CLASS_OTHER:
1733 switch (req->bRequest) {
1734 case UR_GET_TT_STATE:
1735 goto tr_handle_get_tt_state;
1737 goto tr_handle_get_port_status;
1743 case UT_READ_CLASS_DEVICE:
1744 switch (req->bRequest) {
1745 case UR_GET_DESCRIPTOR:
1746 goto tr_handle_get_class_descriptor;
1748 goto tr_handle_get_class_status;
1759 tr_handle_get_descriptor:
1760 switch (value >> 8) {
1765 len = sizeof(atmegadci_devd);
1766 ptr = (const void *)&atmegadci_devd;
1772 len = sizeof(atmegadci_confd);
1773 ptr = (const void *)&atmegadci_confd;
1776 switch (value & 0xff) {
1777 case 0: /* Language table */
1778 len = sizeof(usb_string_lang_en);
1779 ptr = (const void *)&usb_string_lang_en;
1782 case 1: /* Vendor */
1783 len = sizeof(atmegadci_vendor);
1784 ptr = (const void *)&atmegadci_vendor;
1787 case 2: /* Product */
1788 len = sizeof(atmegadci_product);
1789 ptr = (const void *)&atmegadci_product;
1800 tr_handle_get_config:
1802 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1805 tr_handle_get_status:
1807 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1810 tr_handle_set_address:
1811 if (value & 0xFF00) {
1814 sc->sc_rt_addr = value;
1817 tr_handle_set_config:
1821 sc->sc_conf = value;
1824 tr_handle_get_interface:
1826 sc->sc_hub_temp.wValue[0] = 0;
1829 tr_handle_get_tt_state:
1830 tr_handle_get_class_status:
1831 tr_handle_get_iface_status:
1832 tr_handle_get_ep_status:
1834 USETW(sc->sc_hub_temp.wValue, 0);
1838 tr_handle_set_interface:
1839 tr_handle_set_wakeup:
1840 tr_handle_clear_wakeup:
1841 tr_handle_clear_halt:
1844 tr_handle_clear_port_feature:
1848 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1851 case UHF_PORT_SUSPEND:
1852 atmegadci_wakeup_peer(sc);
1855 case UHF_PORT_ENABLE:
1856 sc->sc_flags.port_enabled = 0;
1860 case UHF_PORT_INDICATOR:
1861 case UHF_C_PORT_ENABLE:
1862 case UHF_C_PORT_OVER_CURRENT:
1863 case UHF_C_PORT_RESET:
1866 case UHF_PORT_POWER:
1867 sc->sc_flags.port_powered = 0;
1868 atmegadci_pull_down(sc);
1869 atmegadci_clocks_off(sc);
1871 case UHF_C_PORT_CONNECTION:
1872 /* clear connect change flag */
1873 sc->sc_flags.change_connect = 0;
1875 if (!sc->sc_flags.status_bus_reset) {
1876 /* we are not connected */
1880 /* configure the control endpoint */
1882 /* select endpoint number */
1883 ATMEGA_WRITE_1(sc, ATMEGA_UENUM, 0);
1885 /* set endpoint reset */
1886 ATMEGA_WRITE_1(sc, ATMEGA_UERST, ATMEGA_UERST_MASK(0));
1888 /* clear endpoint reset */
1889 ATMEGA_WRITE_1(sc, ATMEGA_UERST, 0);
1891 /* enable and stall endpoint */
1892 ATMEGA_WRITE_1(sc, ATMEGA_UECONX,
1893 ATMEGA_UECONX_EPEN |
1894 ATMEGA_UECONX_STALLRQ);
1896 /* one bank, 64-bytes wMaxPacket */
1897 ATMEGA_WRITE_1(sc, ATMEGA_UECFG0X,
1898 ATMEGA_UECFG0X_EPTYPE0);
1899 ATMEGA_WRITE_1(sc, ATMEGA_UECFG1X,
1900 ATMEGA_UECFG1X_ALLOC |
1901 ATMEGA_UECFG1X_EPBK0 |
1902 ATMEGA_UECFG1X_EPSIZE(3));
1904 /* check valid config */
1905 temp = ATMEGA_READ_1(sc, ATMEGA_UESTA0X);
1906 if (!(temp & ATMEGA_UESTA0X_CFGOK)) {
1907 device_printf(sc->sc_bus.bdev,
1908 "Chip rejected EP0 configuration\n");
1911 case UHF_C_PORT_SUSPEND:
1912 sc->sc_flags.change_suspend = 0;
1915 err = USB_ERR_IOERROR;
1920 tr_handle_set_port_feature:
1924 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1927 case UHF_PORT_ENABLE:
1928 sc->sc_flags.port_enabled = 1;
1930 case UHF_PORT_SUSPEND:
1931 case UHF_PORT_RESET:
1933 case UHF_PORT_INDICATOR:
1936 case UHF_PORT_POWER:
1937 sc->sc_flags.port_powered = 1;
1940 err = USB_ERR_IOERROR;
1945 tr_handle_get_port_status:
1947 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1952 if (sc->sc_flags.status_vbus) {
1953 atmegadci_clocks_on(sc);
1954 atmegadci_pull_up(sc);
1956 atmegadci_pull_down(sc);
1957 atmegadci_clocks_off(sc);
1960 /* Select FULL-speed and Device Side Mode */
1962 value = UPS_PORT_MODE_DEVICE;
1964 if (sc->sc_flags.port_powered) {
1965 value |= UPS_PORT_POWER;
1967 if (sc->sc_flags.port_enabled) {
1968 value |= UPS_PORT_ENABLED;
1970 if (sc->sc_flags.status_vbus &&
1971 sc->sc_flags.status_bus_reset) {
1972 value |= UPS_CURRENT_CONNECT_STATUS;
1974 if (sc->sc_flags.status_suspend) {
1975 value |= UPS_SUSPEND;
1977 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1981 if (sc->sc_flags.change_connect) {
1982 value |= UPS_C_CONNECT_STATUS;
1984 if (sc->sc_flags.change_suspend) {
1985 value |= UPS_C_SUSPEND;
1987 USETW(sc->sc_hub_temp.ps.wPortChange, value);
1988 len = sizeof(sc->sc_hub_temp.ps);
1991 tr_handle_get_class_descriptor:
1995 ptr = (const void *)&atmegadci_hubd;
1996 len = sizeof(atmegadci_hubd);
2000 err = USB_ERR_STALLED;
2009 atmegadci_xfer_setup(struct usb_setup_params *parm)
2011 const struct usb_hw_ep_profile *pf;
2012 struct atmegadci_softc *sc;
2013 struct usb_xfer *xfer;
2019 sc = ATMEGA_BUS2SC(parm->udev->bus);
2020 xfer = parm->curr_xfer;
2023 * NOTE: This driver does not use any of the parameters that
2024 * are computed from the following values. Just set some
2025 * reasonable dummies:
2027 parm->hc_max_packet_size = 0x500;
2028 parm->hc_max_packet_count = 1;
2029 parm->hc_max_frame_size = 0x500;
2031 usbd_transfer_setup_sub(parm);
2034 * compute maximum number of TDs
2036 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
2038 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
2042 ntd = xfer->nframes + 1 /* SYNC */ ;
2046 * check if "usbd_transfer_setup_sub" set an error
2052 * allocate transfer descriptors
2059 ep_no = xfer->endpointno & UE_ADDR;
2060 atmegadci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2063 /* should not happen */
2064 parm->err = USB_ERR_INVAL;
2069 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2071 for (n = 0; n != ntd; n++) {
2073 struct atmegadci_td *td;
2077 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2080 td->max_packet_size = xfer->max_packet_size;
2082 if (pf->support_multi_buffer) {
2083 td->support_multi_buffer = 1;
2085 td->obj_next = last_obj;
2089 parm->size[0] += sizeof(*td);
2092 xfer->td_start[0] = last_obj;
2096 atmegadci_xfer_unsetup(struct usb_xfer *xfer)
2102 atmegadci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2103 struct usb_endpoint *ep)
2105 struct atmegadci_softc *sc = ATMEGA_BUS2SC(udev->bus);
2107 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2109 edesc->bEndpointAddress, udev->flags.usb_mode,
2110 sc->sc_rt_addr, udev->device_index);
2112 if (udev->device_index != sc->sc_rt_addr) {
2114 if (udev->speed != USB_SPEED_FULL) {
2118 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2119 ep->methods = &atmegadci_device_isoc_fs_methods;
2121 ep->methods = &atmegadci_device_non_isoc_methods;
2126 atmegadci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2128 struct atmegadci_softc *sc = ATMEGA_BUS2SC(bus);
2131 case USB_HW_POWER_SUSPEND:
2132 atmegadci_suspend(sc);
2134 case USB_HW_POWER_SHUTDOWN:
2135 atmegadci_uninit(sc);
2137 case USB_HW_POWER_RESUME:
2138 atmegadci_resume(sc);
2145 static const struct usb_bus_methods atmegadci_bus_methods =
2147 .endpoint_init = &atmegadci_ep_init,
2148 .xfer_setup = &atmegadci_xfer_setup,
2149 .xfer_unsetup = &atmegadci_xfer_unsetup,
2150 .get_hw_ep_profile = &atmegadci_get_hw_ep_profile,
2151 .xfer_stall = &atmegadci_xfer_stall,
2152 .set_stall = &atmegadci_set_stall,
2153 .clear_stall = &atmegadci_clear_stall,
2154 .roothub_exec = &atmegadci_roothub_exec,
2155 .xfer_poll = &atmegadci_do_poll,
2156 .set_hw_power_sleep = &atmegadci_set_hw_power_sleep,