3 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * USB Device Port register definitions, copied from ATMEGA documentation
35 #define ATMEGA_MAX_DEVICES (USB_MIN_DEVICES + 1)
37 #define ATMEGA_UEINT 0xF4
38 #define ATMEGA_UEINT_MASK(n) (1 << (n)) /* endpoint interrupt mask */
40 #define ATMEGA_UEBCHX 0xF3 /* FIFO byte count high */
41 #define ATMEGA_UEBCLX 0xF2 /* FIFO byte count low */
42 #define ATMEGA_UEDATX 0xF1 /* FIFO data */
44 #define ATMEGA_UEIENX 0xF0 /* interrupt enable register */
45 #define ATMEGA_UEIENX_TXINE (1 << 0)
46 #define ATMEGA_UEIENX_STALLEDE (1 << 1)
47 #define ATMEGA_UEIENX_RXOUTE (1 << 2)
48 #define ATMEGA_UEIENX_RXSTPE (1 << 3) /* received SETUP packet */
49 #define ATMEGA_UEIENX_NAKOUTE (1 << 4)
50 #define ATMEGA_UEIENX_NAKINE (1 << 6)
51 #define ATMEGA_UEIENX_FLERRE (1 << 7)
53 #define ATMEGA_UESTA1X 0xEF
54 #define ATMEGA_UESTA1X_CURRBK (3 << 0) /* current bank */
55 #define ATMEGA_UESTA1X_CTRLDIR (1 << 2) /* control endpoint direction */
57 #define ATMEGA_UESTA0X 0xEE
58 #define ATMEGA_UESTA0X_NBUSYBK (3 << 0)
59 #define ATMEGA_UESTA0X_DTSEQ (3 << 2)
60 #define ATMEGA_UESTA0X_UNDERFI (1 << 5) /* underflow */
61 #define ATMEGA_UESTA0X_OVERFI (1 << 6) /* overflow */
62 #define ATMEGA_UESTA0X_CFGOK (1 << 7)
64 #define ATMEGA_UECFG1X 0xED /* endpoint config register */
65 #define ATMEGA_UECFG1X_ALLOC (1 << 1)
66 #define ATMEGA_UECFG1X_EPBK0 (0 << 2)
67 #define ATMEGA_UECFG1X_EPBK1 (1 << 2)
68 #define ATMEGA_UECFG1X_EPBK2 (2 << 2)
69 #define ATMEGA_UECFG1X_EPBK3 (3 << 2)
70 #define ATMEGA_UECFG1X_EPSIZE(n) ((n) << 4)
72 #define ATMEGA_UECFG0X 0xEC
73 #define ATMEGA_UECFG0X_EPDIR (1 << 0) /* endpoint direction */
74 #define ATMEGA_UECFG0X_EPTYPE0 (0 << 6)
75 #define ATMEGA_UECFG0X_EPTYPE1 (1 << 6)
76 #define ATMEGA_UECFG0X_EPTYPE2 (2 << 6)
77 #define ATMEGA_UECFG0X_EPTYPE3 (3 << 6)
79 #define ATMEGA_UECONX 0xEB
80 #define ATMEGA_UECONX_EPEN (1 << 0)
81 #define ATMEGA_UECONX_RSTDT (1 << 3)
82 #define ATMEGA_UECONX_STALLRQC (1 << 4) /* stall request clear */
83 #define ATMEGA_UECONX_STALLRQ (1 << 5) /* stall request set */
85 #define ATMEGA_UERST 0xEA /* endpoint reset register */
86 #define ATMEGA_UERST_MASK(n) (1 << (n))
88 #define ATMEGA_UENUM 0xE9 /* endpoint number */
90 #define ATMEGA_UEINTX 0xE8 /* interrupt register */
91 #define ATMEGA_UEINTX_TXINI (1 << 0)
92 #define ATMEGA_UEINTX_STALLEDI (1 << 1)
93 #define ATMEGA_UEINTX_RXOUTI (1 << 2)
94 #define ATMEGA_UEINTX_RXSTPI (1 << 3) /* received setup packet */
95 #define ATMEGA_UEINTX_NAKOUTI (1 << 4)
96 #define ATMEGA_UEINTX_RWAL (1 << 5)
97 #define ATMEGA_UEINTX_NAKINI (1 << 6)
98 #define ATMEGA_UEINTX_FIFOCON (1 << 7)
100 #define ATMEGA_UDMFN 0xE6
101 #define ATMEGA_UDMFN_FNCERR (1 << 4)
103 #define ATMEGA_UDFNUMH 0xE5 /* frame number high */
104 #define ATMEGA_UDFNUMH_MASK 7
106 #define ATMEGA_UDFNUML 0xE4 /* frame number low */
107 #define ATMEGA_UDFNUML_MASK 0xFF
109 #define ATMEGA_FRAME_MASK 0x7FF
111 #define ATMEGA_UDADDR 0xE3 /* USB address */
112 #define ATMEGA_UDADDR_MASK 0x7F
113 #define ATMEGA_UDADDR_ADDEN (1 << 7)
115 #define ATMEGA_UDIEN 0xE2 /* USB device interrupt enable */
116 #define ATMEGA_UDINT_SUSPE (1 << 0)
117 #define ATMEGA_UDINT_MSOFE (1 << 1)
118 #define ATMEGA_UDINT_SOFE (1 << 2)
119 #define ATMEGA_UDINT_EORSTE (1 << 3)
120 #define ATMEGA_UDINT_WAKEUPE (1 << 4)
121 #define ATMEGA_UDINT_EORSME (1 << 5)
122 #define ATMEGA_UDINT_UPRSME (1 << 6)
124 #define ATMEGA_UDINT 0xE1 /* USB device interrupt status */
125 #define ATMEGA_UDINT_SUSPI (1 << 0)
126 #define ATMEGA_UDINT_MSOFI (1 << 1)
127 #define ATMEGA_UDINT_SOFI (1 << 2)
128 #define ATMEGA_UDINT_EORSTI (1 << 3)
129 #define ATMEGA_UDINT_WAKEUPI (1 << 4)
130 #define ATMEGA_UDINT_EORSMI (1 << 5)
131 #define ATMEGA_UDINT_UPRSMI (1 << 6)
133 #define ATMEGA_UDCON 0xE0 /* USB device connection register */
134 #define ATMEGA_UDCON_DETACH (1 << 0)
135 #define ATMEGA_UDCON_RMWKUP (1 << 1)
136 #define ATMEGA_UDCON_LSM (1 << 2)
137 #define ATMEGA_UDCON_RSTCPU (1 << 3)
139 #define ATMEGA_USBINT 0xDA
140 #define ATMEGA_USBINT_VBUSTI (1 << 0) /* USB VBUS interrupt */
142 #define ATMEGA_USBSTA 0xD9
143 #define ATMEGA_USBSTA_VBUS (1 << 0)
144 #define ATMEGA_USBSTA_ID (1 << 1)
146 #define ATMEGA_USBCON 0xD8
147 #define ATMEGA_USBCON_VBUSTE (1 << 0)
148 #define ATMEGA_USBCON_OTGPADE (1 << 4)
149 #define ATMEGA_USBCON_FRZCLK (1 << 5)
150 #define ATMEGA_USBCON_USBE (1 << 7)
152 #define ATMEGA_UHWCON 0xD7
153 #define ATMEGA_UHWCON_UVREGE (1 << 0)
154 #define ATMEGA_UHWCON_UVCONE (1 << 4)
155 #define ATMEGA_UHWCON_UIDE (1 << 6)
156 #define ATMEGA_UHWCON_UIMOD (1 << 7)
158 #define ATMEGA_READ_1(sc, reg) \
159 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
161 #define ATMEGA_WRITE_1(sc, reg, data) \
162 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
164 #define ATMEGA_WRITE_MULTI_1(sc, reg, ptr, len) \
165 bus_space_write_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
167 #define ATMEGA_READ_MULTI_1(sc, reg, ptr, len) \
168 bus_space_read_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
171 * Maximum number of endpoints supported:
173 #define ATMEGA_EP_MAX 7
177 typedef uint8_t (atmegadci_cmd_t)(struct atmegadci_td *td);
178 typedef void (atmegadci_clocks_t)(struct usb2_bus *);
180 struct atmegadci_td {
181 struct atmegadci_td *obj_next;
182 atmegadci_cmd_t *func;
183 struct usb2_page_cache *pc;
186 uint16_t max_packet_size;
190 uint8_t support_multi_buffer:1;
195 struct atmegadci_std_temp {
196 atmegadci_cmd_t *func;
197 struct usb2_page_cache *pc;
198 struct atmegadci_td *td;
199 struct atmegadci_td *td_next;
202 uint16_t max_frame_size;
205 * short_pkt = 0: transfer should be short terminated
206 * short_pkt = 1: transfer should not be short terminated
208 uint8_t setup_alt_next;
211 struct atmegadci_config_desc {
212 struct usb2_config_descriptor confd;
213 struct usb2_interface_descriptor ifcd;
214 struct usb2_endpoint_descriptor endpd;
217 union atmegadci_hub_temp {
219 struct usb2_port_status ps;
222 struct atmegadci_flags {
223 uint8_t change_connect:1;
224 uint8_t change_suspend:1;
225 uint8_t status_suspend:1; /* set if suspended */
226 uint8_t status_vbus:1; /* set if present */
227 uint8_t status_bus_reset:1; /* set if reset complete */
228 uint8_t remote_wakeup:1;
229 uint8_t self_powered:1;
230 uint8_t clocks_off:1;
231 uint8_t port_powered:1;
232 uint8_t port_enabled:1;
233 uint8_t d_pulled_up:1;
236 struct atmegadci_softc {
237 struct usb2_bus sc_bus;
238 union atmegadci_hub_temp sc_hub_temp;
240 /* must be set by by the bus interface layer */
241 atmegadci_clocks_t *sc_clocks_on;
242 atmegadci_clocks_t *sc_clocks_off;
244 struct usb2_device *sc_devices[ATMEGA_MAX_DEVICES];
245 struct resource *sc_irq_res;
247 struct resource *sc_io_res;
248 bus_space_tag_t sc_io_tag;
249 bus_space_handle_t sc_io_hdl;
251 uint8_t sc_rt_addr; /* root hub address */
252 uint8_t sc_dv_addr; /* device address */
253 uint8_t sc_conf; /* root hub config */
255 uint8_t sc_hub_idata[1];
257 struct atmegadci_flags sc_flags;
262 usb2_error_t atmegadci_init(struct atmegadci_softc *sc);
263 void atmegadci_uninit(struct atmegadci_softc *sc);
264 void atmegadci_suspend(struct atmegadci_softc *sc);
265 void atmegadci_resume(struct atmegadci_softc *sc);
266 void atmegadci_interrupt(struct atmegadci_softc *sc);
268 #endif /* _ATMEGADCI_H_ */