3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * This file contains the driver for the AVR32 series USB Device
35 * NOTE: When the chip detects BUS-reset it will also reset the
36 * endpoints, Function-address and more.
38 #ifdef USB_GLOBAL_INCLUDE_FILE
39 #include USB_GLOBAL_INCLUDE_FILE
41 #include <sys/stdint.h>
42 #include <sys/stddef.h>
43 #include <sys/param.h>
44 #include <sys/queue.h>
45 #include <sys/types.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
49 #include <sys/module.h>
51 #include <sys/mutex.h>
52 #include <sys/condvar.h>
53 #include <sys/sysctl.h>
55 #include <sys/unistd.h>
56 #include <sys/callout.h>
57 #include <sys/malloc.h>
60 #include <dev/usb/usb.h>
61 #include <dev/usb/usbdi.h>
63 #define USB_DEBUG_VAR avr32dci_debug
65 #include <dev/usb/usb_core.h>
66 #include <dev/usb/usb_debug.h>
67 #include <dev/usb/usb_busdma.h>
68 #include <dev/usb/usb_process.h>
69 #include <dev/usb/usb_transfer.h>
70 #include <dev/usb/usb_device.h>
71 #include <dev/usb/usb_hub.h>
72 #include <dev/usb/usb_util.h>
74 #include <dev/usb/usb_controller.h>
75 #include <dev/usb/usb_bus.h>
76 #endif /* USB_GLOBAL_INCLUDE_FILE */
78 #include <dev/usb/controller/avr32dci.h>
80 #define AVR32_BUS2SC(bus) \
81 ((struct avr32dci_softc *)(((uint8_t *)(bus)) - \
82 ((uint8_t *)&(((struct avr32dci_softc *)0)->sc_bus))))
84 #define AVR32_PC2SC(pc) \
85 AVR32_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
88 static int avr32dci_debug = 0;
90 static SYSCTL_NODE(_hw_usb, OID_AUTO, avr32dci, CTLFLAG_RW, 0, "USB AVR32 DCI");
91 SYSCTL_INT(_hw_usb_avr32dci, OID_AUTO, debug, CTLFLAG_RWTUN,
92 &avr32dci_debug, 0, "AVR32 DCI debug level");
95 #define AVR32_INTR_ENDPT 1
99 static const struct usb_bus_methods avr32dci_bus_methods;
100 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods;
101 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods;
103 static avr32dci_cmd_t avr32dci_setup_rx;
104 static avr32dci_cmd_t avr32dci_data_rx;
105 static avr32dci_cmd_t avr32dci_data_tx;
106 static avr32dci_cmd_t avr32dci_data_tx_sync;
107 static void avr32dci_device_done(struct usb_xfer *, usb_error_t);
108 static void avr32dci_do_poll(struct usb_bus *);
109 static void avr32dci_standard_done(struct usb_xfer *);
110 static void avr32dci_root_intr(struct avr32dci_softc *sc);
113 * Here is a list of what the chip supports:
115 static const struct usb_hw_ep_profile
116 avr32dci_ep_profile[4] = {
119 .max_in_frame_size = 64,
120 .max_out_frame_size = 64,
122 .support_control = 1,
126 .max_in_frame_size = 512,
127 .max_out_frame_size = 512,
130 .support_interrupt = 1,
131 .support_isochronous = 1,
137 .max_in_frame_size = 64,
138 .max_out_frame_size = 64,
141 .support_interrupt = 1,
147 .max_in_frame_size = 1024,
148 .max_out_frame_size = 1024,
151 .support_interrupt = 1,
152 .support_isochronous = 1,
159 avr32dci_get_hw_ep_profile(struct usb_device *udev,
160 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
163 *ppf = avr32dci_ep_profile;
164 else if (ep_addr < 3)
165 *ppf = avr32dci_ep_profile + 1;
166 else if (ep_addr < 5)
167 *ppf = avr32dci_ep_profile + 2;
168 else if (ep_addr < 7)
169 *ppf = avr32dci_ep_profile + 3;
175 avr32dci_mod_ctrl(struct avr32dci_softc *sc, uint32_t set, uint32_t clear)
179 temp = AVR32_READ_4(sc, AVR32_CTRL);
182 AVR32_WRITE_4(sc, AVR32_CTRL, temp);
186 avr32dci_mod_ien(struct avr32dci_softc *sc, uint32_t set, uint32_t clear)
190 temp = AVR32_READ_4(sc, AVR32_IEN);
193 AVR32_WRITE_4(sc, AVR32_IEN, temp);
197 avr32dci_clocks_on(struct avr32dci_softc *sc)
199 if (sc->sc_flags.clocks_off &&
200 sc->sc_flags.port_powered) {
205 (sc->sc_clocks_on) (&sc->sc_bus);
207 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0);
209 sc->sc_flags.clocks_off = 0;
214 avr32dci_clocks_off(struct avr32dci_softc *sc)
216 if (!sc->sc_flags.clocks_off) {
220 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_EN_USBA);
222 /* turn clocks off */
223 (sc->sc_clocks_off) (&sc->sc_bus);
225 sc->sc_flags.clocks_off = 1;
230 avr32dci_pull_up(struct avr32dci_softc *sc)
232 /* pullup D+, if possible */
234 if (!sc->sc_flags.d_pulled_up &&
235 sc->sc_flags.port_powered) {
236 sc->sc_flags.d_pulled_up = 1;
237 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_DETACH);
242 avr32dci_pull_down(struct avr32dci_softc *sc)
244 /* pulldown D+, if possible */
246 if (sc->sc_flags.d_pulled_up) {
247 sc->sc_flags.d_pulled_up = 0;
248 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0);
253 avr32dci_wakeup_peer(struct avr32dci_softc *sc)
255 if (!sc->sc_flags.status_suspend) {
258 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_REWAKEUP, 0);
260 /* wait 8 milliseconds */
261 /* Wait for reset to complete. */
262 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
264 /* hardware should have cleared RMWKUP bit */
268 avr32dci_set_address(struct avr32dci_softc *sc, uint8_t addr)
270 DPRINTFN(5, "addr=%d\n", addr);
272 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_FADDR_EN | addr, 0);
276 avr32dci_setup_rx(struct avr32dci_td *td)
278 struct avr32dci_softc *sc;
279 struct usb_device_request req;
283 /* get pointer to softc */
284 sc = AVR32_PC2SC(td->pc);
286 /* check endpoint status */
287 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
289 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
291 if (!(temp & AVR32_EPTSTA_RX_SETUP)) {
294 /* clear did stall */
296 /* get the packet byte count */
297 count = AVR32_EPTSTA_BYTE_COUNT(temp);
299 /* verify data length */
300 if (count != td->remainder) {
301 DPRINTFN(0, "Invalid SETUP packet "
302 "length, %d bytes\n", count);
305 if (count != sizeof(req)) {
306 DPRINTFN(0, "Unsupported SETUP packet "
307 "length, %d bytes\n", count);
311 memcpy(&req, sc->physdata, sizeof(req));
313 /* copy data into real buffer */
314 usbd_copy_in(td->pc, 0, &req, sizeof(req));
316 td->offset = sizeof(req);
319 /* sneak peek the set address */
320 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
321 (req.bRequest == UR_SET_ADDRESS)) {
322 sc->sc_dv_addr = req.wValue[0] & 0x7F;
323 /* must write address before ZLP */
324 avr32dci_mod_ctrl(sc, 0, AVR32_CTRL_DEV_FADDR_EN |
325 AVR32_CTRL_DEV_ADDR);
326 avr32dci_mod_ctrl(sc, sc->sc_dv_addr, 0);
328 sc->sc_dv_addr = 0xFF;
331 /* clear SETUP packet interrupt */
332 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP);
333 return (0); /* complete */
336 if (temp & AVR32_EPTSTA_RX_SETUP) {
337 /* clear SETUP packet interrupt */
338 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_SETUP);
340 /* abort any ongoing transfer */
341 if (!td->did_stall) {
342 DPRINTFN(5, "stalling\n");
343 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(td->ep_no),
344 AVR32_EPTSTA_FRCESTALL);
347 return (1); /* not complete */
351 avr32dci_data_rx(struct avr32dci_td *td)
353 struct avr32dci_softc *sc;
354 struct usb_page_search buf_res;
360 to = 4; /* don't loop forever! */
363 /* get pointer to softc */
364 sc = AVR32_PC2SC(td->pc);
367 /* check if any of the FIFO banks have data */
368 /* check endpoint status */
369 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
371 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
373 if (temp & AVR32_EPTSTA_RX_SETUP) {
374 if (td->remainder == 0) {
376 * We are actually complete and have
377 * received the next SETUP
379 DPRINTFN(5, "faking complete\n");
380 return (0); /* complete */
383 * USB Host Aborted the transfer.
386 return (0); /* complete */
389 if (!(temp & AVR32_EPTSTA_RX_BK_RDY)) {
393 /* get the packet byte count */
394 count = AVR32_EPTSTA_BYTE_COUNT(temp);
396 /* verify the packet byte count */
397 if (count != td->max_packet_size) {
398 if (count < td->max_packet_size) {
399 /* we have a short packet */
403 /* invalid USB packet */
405 return (0); /* we are complete */
408 /* verify the packet byte count */
409 if (count > td->remainder) {
410 /* invalid USB packet */
412 return (0); /* we are complete */
415 usbd_get_page(td->pc, td->offset, &buf_res);
417 /* get correct length */
418 if (buf_res.length > count) {
419 buf_res.length = count;
422 memcpy(buf_res.buffer, sc->physdata +
423 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) +
424 (td->ep_no << 16) + (td->offset % td->max_packet_size), buf_res.length);
425 /* update counters */
426 count -= buf_res.length;
427 td->offset += buf_res.length;
428 td->remainder -= buf_res.length;
431 /* clear OUT packet interrupt */
432 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(td->ep_no), AVR32_EPTSTA_RX_BK_RDY);
434 /* check if we are complete */
435 if ((td->remainder == 0) || got_short) {
437 /* we are complete */
440 /* else need to receive a zero length packet */
446 return (1); /* not complete */
450 avr32dci_data_tx(struct avr32dci_td *td)
452 struct avr32dci_softc *sc;
453 struct usb_page_search buf_res;
458 to = 4; /* don't loop forever! */
460 /* get pointer to softc */
461 sc = AVR32_PC2SC(td->pc);
465 /* check endpoint status */
466 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
468 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
470 if (temp & AVR32_EPTSTA_RX_SETUP) {
472 * The current transfer was aborted
476 return (0); /* complete */
478 if (temp & AVR32_EPTSTA_TX_PK_RDY) {
479 /* cannot write any data - all banks are busy */
482 count = td->max_packet_size;
483 if (td->remainder < count) {
484 /* we have a short packet */
486 count = td->remainder;
490 usbd_get_page(td->pc, td->offset, &buf_res);
492 /* get correct length */
493 if (buf_res.length > count) {
494 buf_res.length = count;
497 memcpy(sc->physdata +
498 (AVR32_EPTSTA_CURRENT_BANK(temp) << td->bank_shift) +
499 (td->ep_no << 16) + (td->offset % td->max_packet_size),
500 buf_res.buffer, buf_res.length);
501 /* update counters */
502 count -= buf_res.length;
503 td->offset += buf_res.length;
504 td->remainder -= buf_res.length;
507 /* allocate FIFO bank */
508 AVR32_WRITE_4(sc, AVR32_EPTCTL(td->ep_no), AVR32_EPTCTL_TX_PK_RDY);
510 /* check remainder */
511 if (td->remainder == 0) {
513 return (0); /* complete */
515 /* else we need to transmit a short packet */
521 return (1); /* not complete */
525 avr32dci_data_tx_sync(struct avr32dci_td *td)
527 struct avr32dci_softc *sc;
530 /* get pointer to softc */
531 sc = AVR32_PC2SC(td->pc);
533 /* check endpoint status */
534 temp = AVR32_READ_4(sc, AVR32_EPTSTA(td->ep_no));
536 DPRINTFN(5, "EPTSTA(%u)=0x%08x\n", td->ep_no, temp);
538 if (temp & AVR32_EPTSTA_RX_SETUP) {
539 DPRINTFN(5, "faking complete\n");
541 return (0); /* complete */
544 * The control endpoint has only got one bank, so if that bank
545 * is free the packet has been transferred!
547 if (AVR32_EPTSTA_BUSY_BANK_STA(temp) != 0) {
548 /* cannot write any data - a bank is busy */
551 if (sc->sc_dv_addr != 0xFF) {
552 /* set new address */
553 avr32dci_set_address(sc, sc->sc_dv_addr);
555 return (0); /* complete */
558 return (1); /* not complete */
562 avr32dci_xfer_do_fifo(struct usb_xfer *xfer)
564 struct avr32dci_td *td;
568 td = xfer->td_transfer_cache;
570 if ((td->func) (td)) {
571 /* operation in progress */
574 if (((void *)td) == xfer->td_transfer_last) {
579 } else if (td->remainder > 0) {
581 * We had a short transfer. If there is no alternate
582 * next, stop processing !
589 * Fetch the next transfer descriptor and transfer
590 * some flags to the next transfer descriptor
593 xfer->td_transfer_cache = td;
595 return (1); /* not complete */
598 /* compute all actual lengths */
600 avr32dci_standard_done(xfer);
601 return (0); /* complete */
605 avr32dci_interrupt_poll(struct avr32dci_softc *sc)
607 struct usb_xfer *xfer;
610 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
611 if (!avr32dci_xfer_do_fifo(xfer)) {
612 /* queue has been modified */
619 avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on)
621 DPRINTFN(5, "vbus = %u\n", is_on);
624 if (!sc->sc_flags.status_vbus) {
625 sc->sc_flags.status_vbus = 1;
627 /* complete root HUB interrupt endpoint */
629 avr32dci_root_intr(sc);
632 if (sc->sc_flags.status_vbus) {
633 sc->sc_flags.status_vbus = 0;
634 sc->sc_flags.status_bus_reset = 0;
635 sc->sc_flags.status_suspend = 0;
636 sc->sc_flags.change_suspend = 0;
637 sc->sc_flags.change_connect = 1;
639 /* complete root HUB interrupt endpoint */
641 avr32dci_root_intr(sc);
647 avr32dci_interrupt(struct avr32dci_softc *sc)
651 USB_BUS_LOCK(&sc->sc_bus);
653 /* read interrupt status */
654 status = AVR32_READ_4(sc, AVR32_INTSTA);
656 /* clear all set interrupts */
657 AVR32_WRITE_4(sc, AVR32_CLRINT, status);
659 DPRINTFN(14, "INTSTA=0x%08x\n", status);
661 /* check for any bus state change interrupts */
662 if (status & AVR32_INT_ENDRESET) {
664 DPRINTFN(5, "end of reset\n");
666 /* set correct state */
667 sc->sc_flags.status_bus_reset = 1;
668 sc->sc_flags.status_suspend = 0;
669 sc->sc_flags.change_suspend = 0;
670 sc->sc_flags.change_connect = 1;
672 /* disable resume interrupt */
673 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
674 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP);
676 /* complete root HUB interrupt endpoint */
677 avr32dci_root_intr(sc);
680 * If resume and suspend is set at the same time we interpret
681 * that like RESUME. Resume is set when there is at least 3
682 * milliseconds of inactivity on the USB BUS.
684 if (status & AVR32_INT_WAKE_UP) {
686 DPRINTFN(5, "resume interrupt\n");
688 if (sc->sc_flags.status_suspend) {
689 /* update status bits */
690 sc->sc_flags.status_suspend = 0;
691 sc->sc_flags.change_suspend = 1;
693 /* disable resume interrupt */
694 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
695 AVR32_INT_ENDRESET, AVR32_INT_WAKE_UP);
697 /* complete root HUB interrupt endpoint */
698 avr32dci_root_intr(sc);
700 } else if (status & AVR32_INT_DET_SUSPD) {
702 DPRINTFN(5, "suspend interrupt\n");
704 if (!sc->sc_flags.status_suspend) {
705 /* update status bits */
706 sc->sc_flags.status_suspend = 1;
707 sc->sc_flags.change_suspend = 1;
709 /* disable suspend interrupt */
710 avr32dci_mod_ien(sc, AVR32_INT_WAKE_UP |
711 AVR32_INT_ENDRESET, AVR32_INT_DET_SUSPD);
713 /* complete root HUB interrupt endpoint */
714 avr32dci_root_intr(sc);
717 /* check for any endpoint interrupts */
718 if (status & -AVR32_INT_EPT_INT(0)) {
720 DPRINTFN(5, "real endpoint interrupt\n");
722 avr32dci_interrupt_poll(sc);
724 USB_BUS_UNLOCK(&sc->sc_bus);
728 avr32dci_setup_standard_chain_sub(struct avr32dci_std_temp *temp)
730 struct avr32dci_td *td;
732 /* get current Transfer Descriptor */
736 /* prepare for next TD */
737 temp->td_next = td->obj_next;
739 /* fill out the Transfer Descriptor */
740 td->func = temp->func;
742 td->offset = temp->offset;
743 td->remainder = temp->len;
745 td->did_stall = temp->did_stall;
746 td->short_pkt = temp->short_pkt;
747 td->alt_next = temp->setup_alt_next;
751 avr32dci_setup_standard_chain(struct usb_xfer *xfer)
753 struct avr32dci_std_temp temp;
754 struct avr32dci_softc *sc;
755 struct avr32dci_td *td;
760 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
761 xfer->address, UE_GET_ADDR(xfer->endpointno),
762 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
764 temp.max_frame_size = xfer->max_frame_size;
766 td = xfer->td_start[0];
767 xfer->td_transfer_first = td;
768 xfer->td_transfer_cache = td;
774 temp.td_next = xfer->td_start[0];
776 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
777 xfer->flags_int.isochronous_xfr;
778 temp.did_stall = !xfer->flags_int.control_stall;
780 sc = AVR32_BUS2SC(xfer->xroot->bus);
781 ep_no = (xfer->endpointno & UE_ADDR);
783 /* check if we should prepend a setup message */
785 if (xfer->flags_int.control_xfr) {
786 if (xfer->flags_int.control_hdr) {
788 temp.func = &avr32dci_setup_rx;
789 temp.len = xfer->frlengths[0];
790 temp.pc = xfer->frbuffers + 0;
791 temp.short_pkt = temp.len ? 1 : 0;
792 /* check for last frame */
793 if (xfer->nframes == 1) {
794 /* no STATUS stage yet, SETUP is last */
795 if (xfer->flags_int.control_act)
796 temp.setup_alt_next = 0;
798 avr32dci_setup_standard_chain_sub(&temp);
805 if (x != xfer->nframes) {
806 if (xfer->endpointno & UE_DIR_IN) {
807 temp.func = &avr32dci_data_tx;
810 temp.func = &avr32dci_data_rx;
814 /* setup "pc" pointer */
815 temp.pc = xfer->frbuffers + x;
819 while (x != xfer->nframes) {
821 /* DATA0 / DATA1 message */
823 temp.len = xfer->frlengths[x];
827 if (x == xfer->nframes) {
828 if (xfer->flags_int.control_xfr) {
829 if (xfer->flags_int.control_act) {
830 temp.setup_alt_next = 0;
833 temp.setup_alt_next = 0;
838 /* make sure that we send an USB packet */
844 /* regular data transfer */
846 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
849 avr32dci_setup_standard_chain_sub(&temp);
851 if (xfer->flags_int.isochronous_xfr) {
852 temp.offset += temp.len;
854 /* get next Page Cache pointer */
855 temp.pc = xfer->frbuffers + x;
859 if (xfer->flags_int.control_xfr) {
861 /* always setup a valid "pc" pointer for status and sync */
862 temp.pc = xfer->frbuffers + 0;
865 temp.setup_alt_next = 0;
867 /* check if we need to sync */
869 /* we need a SYNC point after TX */
870 temp.func = &avr32dci_data_tx_sync;
871 avr32dci_setup_standard_chain_sub(&temp);
873 /* check if we should append a status stage */
874 if (!xfer->flags_int.control_act) {
877 * Send a DATA1 message and invert the current
878 * endpoint direction.
880 if (xfer->endpointno & UE_DIR_IN) {
881 temp.func = &avr32dci_data_rx;
884 temp.func = &avr32dci_data_tx;
888 avr32dci_setup_standard_chain_sub(&temp);
890 /* we need a SYNC point after TX */
891 temp.func = &avr32dci_data_tx_sync;
892 avr32dci_setup_standard_chain_sub(&temp);
896 /* must have at least one frame! */
898 xfer->td_transfer_last = td;
902 avr32dci_timeout(void *arg)
904 struct usb_xfer *xfer = arg;
906 DPRINTF("xfer=%p\n", xfer);
908 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
910 /* transfer is transferred */
911 avr32dci_device_done(xfer, USB_ERR_TIMEOUT);
915 avr32dci_start_standard_chain(struct usb_xfer *xfer)
919 /* poll one time - will turn on interrupts */
920 if (avr32dci_xfer_do_fifo(xfer)) {
921 uint8_t ep_no = xfer->endpointno & UE_ADDR;
922 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
924 avr32dci_mod_ien(sc, AVR32_INT_EPT_INT(ep_no), 0);
926 /* put transfer on interrupt queue */
927 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
929 /* start timeout, if any */
930 if (xfer->timeout != 0) {
931 usbd_transfer_timeout_ms(xfer,
932 &avr32dci_timeout, xfer->timeout);
938 avr32dci_root_intr(struct avr32dci_softc *sc)
942 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
945 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
947 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
948 sizeof(sc->sc_hub_idata));
952 avr32dci_standard_done_sub(struct usb_xfer *xfer)
954 struct avr32dci_td *td;
960 td = xfer->td_transfer_cache;
965 if (xfer->aframes != xfer->nframes) {
967 * Verify the length and subtract
968 * the remainder from "frlengths[]":
970 if (len > xfer->frlengths[xfer->aframes]) {
973 xfer->frlengths[xfer->aframes] -= len;
976 /* Check for transfer error */
978 /* the transfer is finished */
983 /* Check for short transfer */
985 if (xfer->flags_int.short_frames_ok ||
986 xfer->flags_int.isochronous_xfr) {
987 /* follow alt next */
994 /* the transfer is finished */
1002 /* this USB frame is complete */
1008 /* update transfer cache */
1010 xfer->td_transfer_cache = td;
1013 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1017 avr32dci_standard_done(struct usb_xfer *xfer)
1019 usb_error_t err = 0;
1021 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n",
1022 xfer, xfer->endpoint);
1026 xfer->td_transfer_cache = xfer->td_transfer_first;
1028 if (xfer->flags_int.control_xfr) {
1030 if (xfer->flags_int.control_hdr) {
1032 err = avr32dci_standard_done_sub(xfer);
1036 if (xfer->td_transfer_cache == NULL) {
1040 while (xfer->aframes != xfer->nframes) {
1042 err = avr32dci_standard_done_sub(xfer);
1045 if (xfer->td_transfer_cache == NULL) {
1050 if (xfer->flags_int.control_xfr &&
1051 !xfer->flags_int.control_act) {
1053 err = avr32dci_standard_done_sub(xfer);
1056 avr32dci_device_done(xfer, err);
1059 /*------------------------------------------------------------------------*
1060 * avr32dci_device_done
1062 * NOTE: this function can be called more than one time on the
1063 * same USB transfer!
1064 *------------------------------------------------------------------------*/
1066 avr32dci_device_done(struct usb_xfer *xfer, usb_error_t error)
1068 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
1071 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1073 DPRINTFN(9, "xfer=%p, pipe=%p, error=%d\n",
1074 xfer, xfer->endpoint, error);
1076 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1077 ep_no = (xfer->endpointno & UE_ADDR);
1079 /* disable endpoint interrupt */
1080 avr32dci_mod_ien(sc, 0, AVR32_INT_EPT_INT(ep_no));
1082 DPRINTFN(15, "disabled interrupts!\n");
1084 /* dequeue transfer and start next transfer */
1085 usbd_transfer_done(xfer, error);
1089 avr32dci_xfer_stall(struct usb_xfer *xfer)
1091 avr32dci_device_done(xfer, USB_ERR_STALLED);
1095 avr32dci_set_stall(struct usb_device *udev,
1096 struct usb_endpoint *pipe, uint8_t *did_stall)
1098 struct avr32dci_softc *sc;
1101 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1103 DPRINTFN(5, "pipe=%p\n", pipe);
1105 sc = AVR32_BUS2SC(udev->bus);
1106 /* get endpoint number */
1107 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR);
1109 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1113 avr32dci_clear_stall_sub(struct avr32dci_softc *sc, uint8_t ep_no,
1114 uint8_t ep_type, uint8_t ep_dir)
1116 const struct usb_hw_ep_profile *pf;
1121 if (ep_type == UE_CONTROL) {
1122 /* clearing stall is not needed */
1125 /* set endpoint reset */
1126 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(ep_no));
1129 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1131 /* reset data toggle */
1132 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_TOGGLESQ);
1135 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(ep_no), AVR32_EPTSTA_FRCESTALL);
1137 if (ep_type == UE_BULK) {
1138 temp = AVR32_EPTCFG_TYPE_BULK;
1139 } else if (ep_type == UE_INTERRUPT) {
1140 temp = AVR32_EPTCFG_TYPE_INTR;
1142 temp = AVR32_EPTCFG_TYPE_ISOC |
1143 AVR32_EPTCFG_NB_TRANS(1);
1145 if (ep_dir & UE_DIR_IN) {
1146 temp |= AVR32_EPTCFG_EPDIR_IN;
1148 avr32dci_get_hw_ep_profile(NULL, &pf, ep_no);
1150 /* compute endpoint size (use maximum) */
1151 epsize = pf->max_in_frame_size | pf->max_out_frame_size;
1153 while ((epsize /= 2))
1155 temp |= AVR32_EPTCFG_EPSIZE(n);
1157 /* use the maximum number of banks supported */
1159 temp |= AVR32_EPTCFG_NBANK(1);
1161 temp |= AVR32_EPTCFG_NBANK(2);
1163 temp |= AVR32_EPTCFG_NBANK(3);
1165 AVR32_WRITE_4(sc, AVR32_EPTCFG(ep_no), temp);
1167 temp = AVR32_READ_4(sc, AVR32_EPTCFG(ep_no));
1169 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) {
1170 device_printf(sc->sc_bus.bdev, "Chip rejected configuration\n");
1172 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(ep_no),
1173 AVR32_EPTCTL_EPT_ENABL);
1178 avr32dci_clear_stall(struct usb_device *udev, struct usb_endpoint *pipe)
1180 struct avr32dci_softc *sc;
1181 struct usb_endpoint_descriptor *ed;
1183 DPRINTFN(5, "pipe=%p\n", pipe);
1185 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1188 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1193 sc = AVR32_BUS2SC(udev->bus);
1195 /* get endpoint descriptor */
1198 /* reset endpoint */
1199 avr32dci_clear_stall_sub(sc,
1200 (ed->bEndpointAddress & UE_ADDR),
1201 (ed->bmAttributes & UE_XFERTYPE),
1202 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1206 avr32dci_init(struct avr32dci_softc *sc)
1212 /* set up the bus structure */
1213 sc->sc_bus.usbrev = USB_REV_1_1;
1214 sc->sc_bus.methods = &avr32dci_bus_methods;
1216 USB_BUS_LOCK(&sc->sc_bus);
1218 /* make sure USB is enabled */
1219 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_EN_USBA, 0);
1221 /* turn on clocks */
1222 (sc->sc_clocks_on) (&sc->sc_bus);
1224 /* make sure device is re-enumerated */
1225 avr32dci_mod_ctrl(sc, AVR32_CTRL_DEV_DETACH, 0);
1227 /* wait a little for things to stabilise */
1228 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 20);
1230 /* disable interrupts */
1231 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF);
1233 /* enable interrupts */
1234 avr32dci_mod_ien(sc, AVR32_INT_DET_SUSPD |
1235 AVR32_INT_ENDRESET, 0);
1237 /* reset all endpoints */
1238 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1);
1240 /* disable all endpoints */
1241 for (n = 0; n != AVR32_EP_MAX; n++) {
1242 /* disable endpoint */
1243 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL);
1246 /* turn off clocks */
1248 avr32dci_clocks_off(sc);
1250 USB_BUS_UNLOCK(&sc->sc_bus);
1252 /* catch any lost interrupts */
1254 avr32dci_do_poll(&sc->sc_bus);
1256 return (0); /* success */
1260 avr32dci_uninit(struct avr32dci_softc *sc)
1264 USB_BUS_LOCK(&sc->sc_bus);
1266 /* turn on clocks */
1267 (sc->sc_clocks_on) (&sc->sc_bus);
1269 /* disable interrupts */
1270 avr32dci_mod_ien(sc, 0, 0xFFFFFFFF);
1272 /* reset all endpoints */
1273 AVR32_WRITE_4(sc, AVR32_EPTRST, (1 << AVR32_EP_MAX) - 1);
1275 /* disable all endpoints */
1276 for (n = 0; n != AVR32_EP_MAX; n++) {
1277 /* disable endpoint */
1278 AVR32_WRITE_4(sc, AVR32_EPTCTLDIS(n), AVR32_EPTCTL_EPT_ENABL);
1281 sc->sc_flags.port_powered = 0;
1282 sc->sc_flags.status_vbus = 0;
1283 sc->sc_flags.status_bus_reset = 0;
1284 sc->sc_flags.status_suspend = 0;
1285 sc->sc_flags.change_suspend = 0;
1286 sc->sc_flags.change_connect = 1;
1288 avr32dci_pull_down(sc);
1289 avr32dci_clocks_off(sc);
1291 USB_BUS_UNLOCK(&sc->sc_bus);
1295 avr32dci_suspend(struct avr32dci_softc *sc)
1301 avr32dci_resume(struct avr32dci_softc *sc)
1307 avr32dci_do_poll(struct usb_bus *bus)
1309 struct avr32dci_softc *sc = AVR32_BUS2SC(bus);
1311 USB_BUS_LOCK(&sc->sc_bus);
1312 avr32dci_interrupt_poll(sc);
1313 USB_BUS_UNLOCK(&sc->sc_bus);
1316 /*------------------------------------------------------------------------*
1317 * avr32dci bulk support
1318 * avr32dci control support
1319 * avr32dci interrupt support
1320 *------------------------------------------------------------------------*/
1322 avr32dci_device_non_isoc_open(struct usb_xfer *xfer)
1328 avr32dci_device_non_isoc_close(struct usb_xfer *xfer)
1330 avr32dci_device_done(xfer, USB_ERR_CANCELLED);
1334 avr32dci_device_non_isoc_enter(struct usb_xfer *xfer)
1340 avr32dci_device_non_isoc_start(struct usb_xfer *xfer)
1343 avr32dci_setup_standard_chain(xfer);
1344 avr32dci_start_standard_chain(xfer);
1347 static const struct usb_pipe_methods avr32dci_device_non_isoc_methods =
1349 .open = avr32dci_device_non_isoc_open,
1350 .close = avr32dci_device_non_isoc_close,
1351 .enter = avr32dci_device_non_isoc_enter,
1352 .start = avr32dci_device_non_isoc_start,
1355 /*------------------------------------------------------------------------*
1356 * avr32dci full speed isochronous support
1357 *------------------------------------------------------------------------*/
1359 avr32dci_device_isoc_fs_open(struct usb_xfer *xfer)
1365 avr32dci_device_isoc_fs_close(struct usb_xfer *xfer)
1367 avr32dci_device_done(xfer, USB_ERR_CANCELLED);
1371 avr32dci_device_isoc_fs_enter(struct usb_xfer *xfer)
1373 struct avr32dci_softc *sc = AVR32_BUS2SC(xfer->xroot->bus);
1378 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1379 xfer, xfer->endpoint->isoc_next, xfer->nframes);
1381 /* get the current frame index */
1382 ep_no = xfer->endpointno & UE_ADDR;
1383 nframes = (AVR32_READ_4(sc, AVR32_FNUM) / 8);
1385 nframes &= AVR32_FRAME_MASK;
1388 * check if the frame index is within the window where the frames
1391 temp = (nframes - xfer->endpoint->isoc_next) & AVR32_FRAME_MASK;
1393 if ((xfer->endpoint->is_synced == 0) ||
1394 (temp < xfer->nframes)) {
1396 * If there is data underflow or the pipe queue is
1397 * empty we schedule the transfer a few frames ahead
1398 * of the current frame position. Else two isochronous
1399 * transfers might overlap.
1401 xfer->endpoint->isoc_next = (nframes + 3) & AVR32_FRAME_MASK;
1402 xfer->endpoint->is_synced = 1;
1403 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1406 * compute how many milliseconds the insertion is ahead of the
1407 * current frame position:
1409 temp = (xfer->endpoint->isoc_next - nframes) & AVR32_FRAME_MASK;
1412 * pre-compute when the isochronous transfer will be finished:
1414 xfer->isoc_time_complete =
1415 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1418 /* compute frame number for next insertion */
1419 xfer->endpoint->isoc_next += xfer->nframes;
1422 avr32dci_setup_standard_chain(xfer);
1426 avr32dci_device_isoc_fs_start(struct usb_xfer *xfer)
1428 /* start TD chain */
1429 avr32dci_start_standard_chain(xfer);
1432 static const struct usb_pipe_methods avr32dci_device_isoc_fs_methods =
1434 .open = avr32dci_device_isoc_fs_open,
1435 .close = avr32dci_device_isoc_fs_close,
1436 .enter = avr32dci_device_isoc_fs_enter,
1437 .start = avr32dci_device_isoc_fs_start,
1440 /*------------------------------------------------------------------------*
1441 * avr32dci root control support
1442 *------------------------------------------------------------------------*
1443 * Simulate a hardware HUB by handling all the necessary requests.
1444 *------------------------------------------------------------------------*/
1446 static const struct usb_device_descriptor avr32dci_devd = {
1447 .bLength = sizeof(struct usb_device_descriptor),
1448 .bDescriptorType = UDESC_DEVICE,
1449 .bcdUSB = {0x00, 0x02},
1450 .bDeviceClass = UDCLASS_HUB,
1451 .bDeviceSubClass = UDSUBCLASS_HUB,
1452 .bDeviceProtocol = UDPROTO_HSHUBSTT,
1453 .bMaxPacketSize = 64,
1454 .bcdDevice = {0x00, 0x01},
1457 .bNumConfigurations = 1,
1460 static const struct usb_device_qualifier avr32dci_odevd = {
1461 .bLength = sizeof(struct usb_device_qualifier),
1462 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
1463 .bcdUSB = {0x00, 0x02},
1464 .bDeviceClass = UDCLASS_HUB,
1465 .bDeviceSubClass = UDSUBCLASS_HUB,
1466 .bDeviceProtocol = UDPROTO_FSHUB,
1467 .bMaxPacketSize0 = 0,
1468 .bNumConfigurations = 0,
1471 static const struct avr32dci_config_desc avr32dci_confd = {
1473 .bLength = sizeof(struct usb_config_descriptor),
1474 .bDescriptorType = UDESC_CONFIG,
1475 .wTotalLength[0] = sizeof(avr32dci_confd),
1477 .bConfigurationValue = 1,
1478 .iConfiguration = 0,
1479 .bmAttributes = UC_SELF_POWERED,
1483 .bLength = sizeof(struct usb_interface_descriptor),
1484 .bDescriptorType = UDESC_INTERFACE,
1486 .bInterfaceClass = UICLASS_HUB,
1487 .bInterfaceSubClass = UISUBCLASS_HUB,
1488 .bInterfaceProtocol = 0,
1491 .bLength = sizeof(struct usb_endpoint_descriptor),
1492 .bDescriptorType = UDESC_ENDPOINT,
1493 .bEndpointAddress = (UE_DIR_IN | AVR32_INTR_ENDPT),
1494 .bmAttributes = UE_INTERRUPT,
1495 .wMaxPacketSize[0] = 8,
1500 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1502 static const struct usb_hub_descriptor_min avr32dci_hubd = {
1503 .bDescLength = sizeof(avr32dci_hubd),
1504 .bDescriptorType = UDESC_HUB,
1506 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1507 .bPwrOn2PwrGood = 50,
1508 .bHubContrCurrent = 0,
1509 .DeviceRemovable = {0}, /* port is removable */
1512 #define STRING_VENDOR \
1515 #define STRING_PRODUCT \
1516 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
1518 USB_MAKE_STRING_DESC(STRING_VENDOR, avr32dci_vendor);
1519 USB_MAKE_STRING_DESC(STRING_PRODUCT, avr32dci_product);
1522 avr32dci_roothub_exec(struct usb_device *udev,
1523 struct usb_device_request *req, const void **pptr, uint16_t *plength)
1525 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus);
1533 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1536 ptr = (const void *)&sc->sc_hub_temp;
1540 value = UGETW(req->wValue);
1541 index = UGETW(req->wIndex);
1543 /* demultiplex the control request */
1545 switch (req->bmRequestType) {
1546 case UT_READ_DEVICE:
1547 switch (req->bRequest) {
1548 case UR_GET_DESCRIPTOR:
1549 goto tr_handle_get_descriptor;
1551 goto tr_handle_get_config;
1553 goto tr_handle_get_status;
1559 case UT_WRITE_DEVICE:
1560 switch (req->bRequest) {
1561 case UR_SET_ADDRESS:
1562 goto tr_handle_set_address;
1564 goto tr_handle_set_config;
1565 case UR_CLEAR_FEATURE:
1566 goto tr_valid; /* nop */
1567 case UR_SET_DESCRIPTOR:
1568 goto tr_valid; /* nop */
1569 case UR_SET_FEATURE:
1575 case UT_WRITE_ENDPOINT:
1576 switch (req->bRequest) {
1577 case UR_CLEAR_FEATURE:
1578 switch (UGETW(req->wValue)) {
1579 case UF_ENDPOINT_HALT:
1580 goto tr_handle_clear_halt;
1581 case UF_DEVICE_REMOTE_WAKEUP:
1582 goto tr_handle_clear_wakeup;
1587 case UR_SET_FEATURE:
1588 switch (UGETW(req->wValue)) {
1589 case UF_ENDPOINT_HALT:
1590 goto tr_handle_set_halt;
1591 case UF_DEVICE_REMOTE_WAKEUP:
1592 goto tr_handle_set_wakeup;
1597 case UR_SYNCH_FRAME:
1598 goto tr_valid; /* nop */
1604 case UT_READ_ENDPOINT:
1605 switch (req->bRequest) {
1607 goto tr_handle_get_ep_status;
1613 case UT_WRITE_INTERFACE:
1614 switch (req->bRequest) {
1615 case UR_SET_INTERFACE:
1616 goto tr_handle_set_interface;
1617 case UR_CLEAR_FEATURE:
1618 goto tr_valid; /* nop */
1619 case UR_SET_FEATURE:
1625 case UT_READ_INTERFACE:
1626 switch (req->bRequest) {
1627 case UR_GET_INTERFACE:
1628 goto tr_handle_get_interface;
1630 goto tr_handle_get_iface_status;
1636 case UT_WRITE_CLASS_INTERFACE:
1637 case UT_WRITE_VENDOR_INTERFACE:
1641 case UT_READ_CLASS_INTERFACE:
1642 case UT_READ_VENDOR_INTERFACE:
1646 case UT_WRITE_CLASS_DEVICE:
1647 switch (req->bRequest) {
1648 case UR_CLEAR_FEATURE:
1650 case UR_SET_DESCRIPTOR:
1651 case UR_SET_FEATURE:
1658 case UT_WRITE_CLASS_OTHER:
1659 switch (req->bRequest) {
1660 case UR_CLEAR_FEATURE:
1661 goto tr_handle_clear_port_feature;
1662 case UR_SET_FEATURE:
1663 goto tr_handle_set_port_feature;
1664 case UR_CLEAR_TT_BUFFER:
1674 case UT_READ_CLASS_OTHER:
1675 switch (req->bRequest) {
1676 case UR_GET_TT_STATE:
1677 goto tr_handle_get_tt_state;
1679 goto tr_handle_get_port_status;
1685 case UT_READ_CLASS_DEVICE:
1686 switch (req->bRequest) {
1687 case UR_GET_DESCRIPTOR:
1688 goto tr_handle_get_class_descriptor;
1690 goto tr_handle_get_class_status;
1701 tr_handle_get_descriptor:
1702 switch (value >> 8) {
1707 len = sizeof(avr32dci_devd);
1708 ptr = (const void *)&avr32dci_devd;
1714 len = sizeof(avr32dci_confd);
1715 ptr = (const void *)&avr32dci_confd;
1718 switch (value & 0xff) {
1719 case 0: /* Language table */
1720 len = sizeof(usb_string_lang_en);
1721 ptr = (const void *)&usb_string_lang_en;
1724 case 1: /* Vendor */
1725 len = sizeof(avr32dci_vendor);
1726 ptr = (const void *)&avr32dci_vendor;
1729 case 2: /* Product */
1730 len = sizeof(avr32dci_product);
1731 ptr = (const void *)&avr32dci_product;
1742 tr_handle_get_config:
1744 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
1747 tr_handle_get_status:
1749 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
1752 tr_handle_set_address:
1753 if (value & 0xFF00) {
1756 sc->sc_rt_addr = value;
1759 tr_handle_set_config:
1763 sc->sc_conf = value;
1766 tr_handle_get_interface:
1768 sc->sc_hub_temp.wValue[0] = 0;
1771 tr_handle_get_tt_state:
1772 tr_handle_get_class_status:
1773 tr_handle_get_iface_status:
1774 tr_handle_get_ep_status:
1776 USETW(sc->sc_hub_temp.wValue, 0);
1780 tr_handle_set_interface:
1781 tr_handle_set_wakeup:
1782 tr_handle_clear_wakeup:
1783 tr_handle_clear_halt:
1786 tr_handle_clear_port_feature:
1790 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
1793 case UHF_PORT_SUSPEND:
1794 avr32dci_wakeup_peer(sc);
1797 case UHF_PORT_ENABLE:
1798 sc->sc_flags.port_enabled = 0;
1802 case UHF_PORT_INDICATOR:
1803 case UHF_C_PORT_ENABLE:
1804 case UHF_C_PORT_OVER_CURRENT:
1805 case UHF_C_PORT_RESET:
1808 case UHF_PORT_POWER:
1809 sc->sc_flags.port_powered = 0;
1810 avr32dci_pull_down(sc);
1811 avr32dci_clocks_off(sc);
1813 case UHF_C_PORT_CONNECTION:
1814 /* clear connect change flag */
1815 sc->sc_flags.change_connect = 0;
1817 if (!sc->sc_flags.status_bus_reset) {
1818 /* we are not connected */
1821 /* configure the control endpoint */
1822 /* set endpoint reset */
1823 AVR32_WRITE_4(sc, AVR32_EPTRST, AVR32_EPTRST_MASK(0));
1826 AVR32_WRITE_4(sc, AVR32_EPTSETSTA(0), AVR32_EPTSTA_FRCESTALL);
1828 /* reset data toggle */
1829 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_TOGGLESQ);
1832 AVR32_WRITE_4(sc, AVR32_EPTCLRSTA(0), AVR32_EPTSTA_FRCESTALL);
1835 AVR32_WRITE_4(sc, AVR32_EPTCFG(0), AVR32_EPTCFG_TYPE_CTRL |
1836 AVR32_EPTCFG_NBANK(1) | AVR32_EPTCFG_EPSIZE(6));
1838 temp = AVR32_READ_4(sc, AVR32_EPTCFG(0));
1840 if (!(temp & AVR32_EPTCFG_EPT_MAPD)) {
1841 device_printf(sc->sc_bus.bdev,
1842 "Chip rejected configuration\n");
1844 AVR32_WRITE_4(sc, AVR32_EPTCTLENB(0),
1845 AVR32_EPTCTL_EPT_ENABL);
1848 case UHF_C_PORT_SUSPEND:
1849 sc->sc_flags.change_suspend = 0;
1852 err = USB_ERR_IOERROR;
1857 tr_handle_set_port_feature:
1861 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
1864 case UHF_PORT_ENABLE:
1865 sc->sc_flags.port_enabled = 1;
1867 case UHF_PORT_SUSPEND:
1868 case UHF_PORT_RESET:
1870 case UHF_PORT_INDICATOR:
1873 case UHF_PORT_POWER:
1874 sc->sc_flags.port_powered = 1;
1877 err = USB_ERR_IOERROR;
1882 tr_handle_get_port_status:
1884 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
1889 if (sc->sc_flags.status_vbus) {
1890 avr32dci_clocks_on(sc);
1891 avr32dci_pull_up(sc);
1893 avr32dci_pull_down(sc);
1894 avr32dci_clocks_off(sc);
1897 /* Select Device Side Mode */
1899 value = UPS_PORT_MODE_DEVICE;
1901 /* Check for High Speed */
1902 if (AVR32_READ_4(sc, AVR32_INTSTA) & AVR32_INT_SPEED)
1903 value |= UPS_HIGH_SPEED;
1905 if (sc->sc_flags.port_powered) {
1906 value |= UPS_PORT_POWER;
1908 if (sc->sc_flags.port_enabled) {
1909 value |= UPS_PORT_ENABLED;
1911 if (sc->sc_flags.status_vbus &&
1912 sc->sc_flags.status_bus_reset) {
1913 value |= UPS_CURRENT_CONNECT_STATUS;
1915 if (sc->sc_flags.status_suspend) {
1916 value |= UPS_SUSPEND;
1918 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
1922 if (sc->sc_flags.change_connect) {
1923 value |= UPS_C_CONNECT_STATUS;
1925 if (sc->sc_flags.change_suspend) {
1926 value |= UPS_C_SUSPEND;
1928 USETW(sc->sc_hub_temp.ps.wPortChange, value);
1929 len = sizeof(sc->sc_hub_temp.ps);
1932 tr_handle_get_class_descriptor:
1936 ptr = (const void *)&avr32dci_hubd;
1937 len = sizeof(avr32dci_hubd);
1941 err = USB_ERR_STALLED;
1950 avr32dci_xfer_setup(struct usb_setup_params *parm)
1952 const struct usb_hw_ep_profile *pf;
1953 struct avr32dci_softc *sc;
1954 struct usb_xfer *xfer;
1960 sc = AVR32_BUS2SC(parm->udev->bus);
1961 xfer = parm->curr_xfer;
1964 * NOTE: This driver does not use any of the parameters that
1965 * are computed from the following values. Just set some
1966 * reasonable dummies:
1968 parm->hc_max_packet_size = 0x400;
1969 parm->hc_max_packet_count = 1;
1970 parm->hc_max_frame_size = 0x400;
1972 usbd_transfer_setup_sub(parm);
1975 * compute maximum number of TDs
1977 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) {
1979 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
1983 ntd = xfer->nframes + 1 /* SYNC */ ;
1987 * check if "usbd_transfer_setup_sub" set an error
1993 * allocate transfer descriptors
2000 ep_no = xfer->endpointno & UE_ADDR;
2001 avr32dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2004 /* should not happen */
2005 parm->err = USB_ERR_INVAL;
2009 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2011 for (n = 0; n != ntd; n++) {
2013 struct avr32dci_td *td;
2018 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2021 td->max_packet_size = xfer->max_packet_size;
2023 temp = pf->max_in_frame_size | pf->max_out_frame_size;
2027 if (pf->support_multi_buffer) {
2028 td->support_multi_buffer = 1;
2030 td->obj_next = last_obj;
2034 parm->size[0] += sizeof(*td);
2037 xfer->td_start[0] = last_obj;
2041 avr32dci_xfer_unsetup(struct usb_xfer *xfer)
2047 avr32dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2048 struct usb_endpoint *pipe)
2050 struct avr32dci_softc *sc = AVR32_BUS2SC(udev->bus);
2052 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
2053 pipe, udev->address,
2054 edesc->bEndpointAddress, udev->flags.usb_mode,
2055 sc->sc_rt_addr, udev->device_index);
2057 if (udev->device_index != sc->sc_rt_addr) {
2059 if ((udev->speed != USB_SPEED_FULL) &&
2060 (udev->speed != USB_SPEED_HIGH)) {
2064 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
2065 pipe->methods = &avr32dci_device_isoc_fs_methods;
2067 pipe->methods = &avr32dci_device_non_isoc_methods;
2072 avr32dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2074 struct avr32dci_softc *sc = AVR32_BUS2SC(bus);
2077 case USB_HW_POWER_SUSPEND:
2078 avr32dci_suspend(sc);
2080 case USB_HW_POWER_SHUTDOWN:
2081 avr32dci_uninit(sc);
2083 case USB_HW_POWER_RESUME:
2084 avr32dci_resume(sc);
2091 static const struct usb_bus_methods avr32dci_bus_methods =
2093 .endpoint_init = &avr32dci_ep_init,
2094 .xfer_setup = &avr32dci_xfer_setup,
2095 .xfer_unsetup = &avr32dci_xfer_unsetup,
2096 .get_hw_ep_profile = &avr32dci_get_hw_ep_profile,
2097 .xfer_stall = &avr32dci_xfer_stall,
2098 .set_stall = &avr32dci_set_stall,
2099 .clear_stall = &avr32dci_clear_stall,
2100 .roothub_exec = &avr32dci_roothub_exec,
2101 .xfer_poll = &avr32dci_do_poll,
2102 .set_hw_power_sleep = &avr32dci_set_hw_power_sleep,