3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #define AVR32_MAX_DEVICES (USB_MIN_DEVICES + 1)
34 /* Register definitions */
36 #define AVR32_CTRL 0x00 /* Control */
37 #define AVR32_CTRL_DEV_ADDR 0x7F
38 #define AVR32_CTRL_DEV_FADDR_EN 0x80
39 #define AVR32_CTRL_DEV_EN_USBA 0x100
40 #define AVR32_CTRL_DEV_DETACH 0x200
41 #define AVR32_CTRL_DEV_REWAKEUP 0x400
43 #define AVR32_FNUM 0x04 /* Frame Number */
44 #define AVR32_FNUM_MASK 0x3FFF
45 #define AVR32_FRAME_MASK 0x7FF
47 /* 0x08 - 0x0C Reserved */
48 #define AVR32_IEN 0x10 /* Interrupt Enable */
49 #define AVR32_INTSTA 0x14 /* Interrupt Status */
50 #define AVR32_CLRINT 0x18 /* Clear Interrupt */
52 #define AVR32_INT_SPEED 0x00000001 /* set if High Speed else Full Speed */
53 #define AVR32_INT_DET_SUSPD 0x00000002
54 #define AVR32_INT_MICRO_SOF 0x00000004
55 #define AVR32_INT_INT_SOF 0x00000008
56 #define AVR32_INT_ENDRESET 0x00000010
57 #define AVR32_INT_WAKE_UP 0x00000020
58 #define AVR32_INT_ENDOFRSM 0x00000040
59 #define AVR32_INT_UPSTR_RES 0x00000080
60 #define AVR32_INT_EPT_INT(n) (0x00000100 << (n))
61 #define AVR32_INT_DMA_INT(n) (0x01000000 << (n))
63 #define AVR32_EPTRST 0x1C /* Endpoints Reset */
64 #define AVR32_EPTRST_MASK(n) (0x00000001 << (n))
66 /* 0x20 - 0xCC Reserved */
67 #define AVR32_TSTSOFCNT 0xD0 /* Test SOF Counter */
68 #define AVR32_TSTCNTA 0xD4 /* Test A Counter */
69 #define AVR32_TSTCNTB 0xD8 /* Test B Counter */
70 #define AVR32_TSTMODEREG 0xDC /* Test Mode */
71 #define AVR32_TST 0xE0 /* Test */
72 #define AVR32_TST_NORMAL 0x00000000
73 #define AVR32_TST_HS_ONLY 0x00000002
74 #define AVR32_TST_FS_ONLY 0x00000003
76 /* 0xE4 - 0xE8 Reserved */
77 #define AVR32_IPPADDRSIZE 0xEC /* PADDRSIZE */
78 #define AVR32_IPNAME1 0xF0 /* Name1 */
79 #define AVR32_IPNAME2 0xF4 /* Name2 */
80 #define AVR32_IPFEATURES 0xF8 /* Features */
81 #define AVR32_IPFEATURES_NEP(x) (((x) & 0xF) ? ((x) & 0xF) : 0x10)
83 #define AVR32_IPVERSION 0xFC /* IP Version */
85 #define _A(base,n) ((base) + (0x20*(n)))
86 #define AVR32_EPTCFG(n) _A(0x100, n) /* Endpoint Configuration */
87 #define AVR32_EPTCFG_EPSIZE(n) ((n)-3) /* power of two */
88 #define AVR32_EPTCFG_EPDIR_OUT 0x00000000
89 #define AVR32_EPTCFG_EPDIR_IN 0x00000008
90 #define AVR32_EPTCFG_TYPE_CTRL 0x00000000
91 #define AVR32_EPTCFG_TYPE_ISOC 0x00000100
92 #define AVR32_EPTCFG_TYPE_BULK 0x00000200
93 #define AVR32_EPTCFG_TYPE_INTR 0x00000300
94 #define AVR32_EPTCFG_NBANK(n) (0x00000400*(n))
95 #define AVR32_EPTCFG_NB_TRANS(n) (0x00001000*(n))
96 #define AVR32_EPTCFG_EPT_MAPD 0x80000000
98 #define AVR32_EPTCTLENB(n) _A(0x104, n) /* Endpoint Control Enable */
99 #define AVR32_EPTCTLDIS(n) _A(0x108, n) /* Endpoint Control Disable */
100 #define AVR32_EPTCTL(n) _A(0x10C, n) /* Endpoint Control */
101 #define AVR32_EPTCTL_EPT_ENABL 0x00000001
102 #define AVR32_EPTCTL_AUTO_VALID 0x00000002
103 #define AVR32_EPTCTL_INTDIS_DMA 0x00000008
104 #define AVR32_EPTCTL_NYET_DIS 0x00000010
105 #define AVR32_EPTCTL_DATAX_RX 0x00000040
106 #define AVR32_EPTCTL_MDATA_RX 0x00000080
107 #define AVR32_EPTCTL_ERR_OVFLW 0x00000100
108 #define AVR32_EPTCTL_RX_BK_RDY 0x00000200
109 #define AVR32_EPTCTL_TX_COMPLT 0x00000400
110 #define AVR32_EPTCTL_TX_PK_RDY 0x00000800
111 #define AVR32_EPTCTL_RX_SETUP 0x00001000
112 #define AVR32_EPTCTL_STALL_SNT 0x00002000
113 #define AVR32_EPTCTL_NAK_IN 0x00004000
114 #define AVR32_EPTCTL_NAK_OUT 0x00008000
115 #define AVR32_EPTCTL_BUSY_BANK 0x00040000
116 #define AVR32_EPTCTL_SHORT_PCKT 0x80000000
119 #define AVR32_EPTSETSTA(n) _A(0x114, n) /* Endpoint Set Status */
120 #define AVR32_EPTCLRSTA(n) _A(0x118, n) /* Endpoint Clear Status */
121 #define AVR32_EPTSTA(n) _A(0x11C, n) /* Endpoint Status */
122 #define AVR32_EPTSTA_FRCESTALL 0x00000020
123 #define AVR32_EPTSTA_TOGGLESQ_STA(x) (((x) & 0xC0) >> 6)
124 #define AVR32_EPTSTA_TOGGLESQ 0x00000040
125 #define AVR32_EPTSTA_ERR_OVFLW 0x00000100
126 #define AVR32_EPTSTA_RX_BK_RDY 0x00000200
127 #define AVR32_EPTSTA_TX_COMPLT 0x00000400
128 #define AVR32_EPTSTA_TX_PK_RDY 0x00000800
129 #define AVR32_EPTSTA_RX_SETUP 0x00001000
130 #define AVR32_EPTSTA_STALL_SNT 0x00002000
131 #define AVR32_EPTSTA_NAK_IN 0x00004000
132 #define AVR32_EPTSTA_NAK_OUT 0x00008000
133 #define AVR32_EPTSTA_CURRENT_BANK(x) (((x) & 0x00030000) >> 16)
134 #define AVR32_EPTSTA_BUSY_BANK_STA(x) (((x) & 0x000C0000) >> 18)
135 #define AVR32_EPTSTA_BYTE_COUNT(x) (((x) & 0x7FF00000) >> 20)
136 #define AVR32_EPTSTA_SHRT_PCKT 0x80000000
138 /* 0x300 - 0x30C Reserved */
139 #define AVR32_DMANXTDSC 0x310 /* DMA Next Descriptor Address */
140 #define AVR32_DMAADDRESS 0x314 /* DMA Channel Address */
142 #define AVR32_READ_4(sc, reg) \
143 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
145 #define AVR32_WRITE_4(sc, reg, data) \
146 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
148 #define AVR32_WRITE_MULTI_4(sc, reg, ptr, len) \
149 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
151 #define AVR32_READ_MULTI_4(sc, reg, ptr, len) \
152 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len)
155 * Maximum number of endpoints supported:
157 #define AVR32_EP_MAX 7
161 typedef uint8_t (avr32dci_cmd_t)(struct avr32dci_td *td);
162 typedef void (avr32dci_clocks_t)(struct usb_bus *);
165 struct avr32dci_td *obj_next;
166 avr32dci_cmd_t *func;
167 struct usb_page_cache *pc;
170 uint16_t max_packet_size;
175 uint8_t support_multi_buffer:1;
180 struct avr32dci_std_temp {
181 avr32dci_cmd_t *func;
182 struct usb_page_cache *pc;
183 struct avr32dci_td *td;
184 struct avr32dci_td *td_next;
187 uint16_t max_frame_size;
191 * short_pkt = 0: transfer should be short terminated
192 * short_pkt = 1: transfer should not be short terminated
194 uint8_t setup_alt_next;
198 struct avr32dci_config_desc {
199 struct usb_config_descriptor confd;
200 struct usb_interface_descriptor ifcd;
201 struct usb_endpoint_descriptor endpd;
204 union avr32dci_hub_temp {
206 struct usb_port_status ps;
209 struct avr32dci_flags {
210 uint8_t change_connect:1;
211 uint8_t change_suspend:1;
212 uint8_t status_suspend:1; /* set if suspended */
213 uint8_t status_vbus:1; /* set if present */
214 uint8_t status_bus_reset:1; /* set if reset complete */
215 uint8_t remote_wakeup:1;
216 uint8_t self_powered:1;
217 uint8_t clocks_off:1;
218 uint8_t port_powered:1;
219 uint8_t port_enabled:1;
220 uint8_t d_pulled_up:1;
223 struct avr32dci_softc {
224 struct usb_bus sc_bus;
225 union avr32dci_hub_temp sc_hub_temp;
227 /* must be set by by the bus interface layer */
228 avr32dci_clocks_t *sc_clocks_on;
229 avr32dci_clocks_t *sc_clocks_off;
231 struct usb_device *sc_devices[AVR32_MAX_DEVICES];
232 struct resource *sc_irq_res;
234 struct resource *sc_io_res;
235 bus_space_tag_t sc_io_tag;
236 bus_space_handle_t sc_io_hdl;
239 uint8_t sc_rt_addr; /* root hub address */
240 uint8_t sc_dv_addr; /* device address */
241 uint8_t sc_conf; /* root hub config */
243 uint8_t sc_hub_idata[1];
245 struct avr32dci_flags sc_flags;
250 usb_error_t avr32dci_init(struct avr32dci_softc *sc);
251 void avr32dci_uninit(struct avr32dci_softc *sc);
252 void avr32dci_interrupt(struct avr32dci_softc *sc);
253 void avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on);
255 #endif /* _AVR32DCI_H_ */