sys/dev/usb/controller/dwc_otg.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2015 Daisuke Aoyama. All rights reserved.
   4  * Copyright (c) 2012 Hans Petter Selasky. All rights reserved.
   5  * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * This file contains the driver for the DesignWare series USB 2.0 OTG
  31  * Controller.
  32  */
  33
  34 /*
  35  * LIMITATION: Drivers must be bound to all OUT endpoints in the
  36  * active configuration for this driver to work properly. Blocking any
  37  * OUT endpoint will block all OUT endpoints including the control
  38  * endpoint. Usually this is not a problem.
  39  */
  40
  41 /*
  42  * NOTE: Writing to non-existing registers appears to cause an
  43  * internal reset.
  44  */
  45
  46 #ifdef USB_GLOBAL_INCLUDE_FILE
  47 #include USB_GLOBAL_INCLUDE_FILE
  48 #else
  49 #include <sys/stdint.h>
  50 #include <sys/stddef.h>
  51 #include <sys/param.h>
  52 #include <sys/queue.h>
  53 #include <sys/types.h>
  54 #include <sys/systm.h>
  55 #include <sys/kernel.h>
  56 #include <sys/bus.h>
  57 #include <sys/module.h>
  58 #include <sys/lock.h>
  59 #include <sys/mutex.h>
  60 #include <sys/condvar.h>
  61 #include <sys/sysctl.h>
  62 #include <sys/sx.h>
  63 #include <sys/unistd.h>
  64 #include <sys/callout.h>
  65 #include <sys/malloc.h>
  66 #include <sys/priv.h>
  67
  68 #include <dev/usb/usb.h>
  69 #include <dev/usb/usbdi.h>
  70
  71 #define USB_DEBUG_VAR dwc_otg_debug
  72
  73 #include <dev/usb/usb_core.h>
  74 #include <dev/usb/usb_debug.h>
  75 #include <dev/usb/usb_busdma.h>
  76 #include <dev/usb/usb_process.h>
  77 #include <dev/usb/usb_transfer.h>
  78 #include <dev/usb/usb_device.h>
  79 #include <dev/usb/usb_hub.h>
  80 #include <dev/usb/usb_util.h>
  81
  82 #include <dev/usb/usb_controller.h>
  83 #include <dev/usb/usb_bus.h>
  84 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  85
  86 #include <dev/usb/controller/dwc_otg.h>
  87 #include <dev/usb/controller/dwc_otgreg.h>
  88
  89 #define DWC_OTG_BUS2SC(bus) \
  90    ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \
  91     ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus))))
  92
  93 #define DWC_OTG_PC2UDEV(pc) \
  94    (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
  95
  96 #define DWC_OTG_MSK_GINT_ENABLED        \
  97    (GINTMSK_ENUMDONEMSK |               \
  98    GINTMSK_USBRSTMSK |                  \
  99    GINTMSK_USBSUSPMSK |                 \
 100    GINTMSK_IEPINTMSK |                  \
 101    GINTMSK_SESSREQINTMSK |              \
 102    GINTMSK_RXFLVLMSK |                  \
 103    GINTMSK_HCHINTMSK |                  \
 104    GINTMSK_OTGINTMSK |                  \
 105    GINTMSK_PRTINTMSK)
 106
 107 #define DWC_OTG_MSK_GINT_THREAD_IRQ                             \
 108    (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT |        \
 109    GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK |      \
 110    GINTSTS_SESSREQINT)
 111
 112 #define DWC_OTG_PHY_ULPI 0
 113 #define DWC_OTG_PHY_HSIC 1
 114 #define DWC_OTG_PHY_INTERNAL 2
 115
 116 #ifndef DWC_OTG_PHY_DEFAULT
 117 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI
 118 #endif
 119
 120 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT;
 121
 122 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG");
 123 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN,
 124     &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL");
 125
 126 #ifdef USB_DEBUG
 127 static int dwc_otg_debug;
 128
 129 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN,
 130     &dwc_otg_debug, 0, "DWC OTG debug level");
 131 #endif
 132
 133 #define DWC_OTG_INTR_ENDPT 1
 134
 135 /* prototypes */
 136
 137 static const struct usb_bus_methods dwc_otg_bus_methods;
 138 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods;
 139 static const struct usb_pipe_methods dwc_otg_device_isoc_methods;
 140
 141 static dwc_otg_cmd_t dwc_otg_setup_rx;
 142 static dwc_otg_cmd_t dwc_otg_data_rx;
 143 static dwc_otg_cmd_t dwc_otg_data_tx;
 144 static dwc_otg_cmd_t dwc_otg_data_tx_sync;
 145
 146 static dwc_otg_cmd_t dwc_otg_host_setup_tx;
 147 static dwc_otg_cmd_t dwc_otg_host_data_tx;
 148 static dwc_otg_cmd_t dwc_otg_host_data_rx;
 149
 150 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t);
 151 static void dwc_otg_do_poll(struct usb_bus *);
 152 static void dwc_otg_standard_done(struct usb_xfer *);
 153 static void dwc_otg_root_intr(struct dwc_otg_softc *);
 154 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *);
 155
 156 /*
 157  * Here is a configuration that the chip supports.
 158  */
 159 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = {
 160
 161         [0] = {
 162                 .max_in_frame_size = 64,/* fixed */
 163                 .max_out_frame_size = 64,       /* fixed */
 164                 .is_simplex = 1,
 165                 .support_control = 1,
 166         }
 167 };
 168
 169 static void
 170 dwc_otg_get_hw_ep_profile(struct usb_device *udev,
 171     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 172 {
 173         struct dwc_otg_softc *sc;
 174
 175         sc = DWC_OTG_BUS2SC(udev->bus);
 176
 177         if (ep_addr < sc->sc_dev_ep_max)
 178                 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb;
 179         else
 180                 *ppf = NULL;
 181 }
 182
 183 static void
 184 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value)
 185 {
 186         uint32_t temp;
 187
 188         /* reset FIFO */
 189         DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value);
 190
 191         /* wait for reset to complete */
 192         for (temp = 0; temp != 16; temp++) {
 193                 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL);
 194                 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)))
 195                         break;
 196         }
 197 }
 198
 199 static int
 200 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode)
 201 {
 202         struct dwc_otg_profile *pf;
 203         uint32_t fifo_size;
 204         uint32_t fifo_regs;
 205         uint32_t tx_start;
 206         uint8_t x;
 207
 208         fifo_size = sc->sc_fifo_size;
 209
 210         /*
 211          * NOTE: Reserved fixed size area at end of RAM, which must
 212          * not be allocated to the FIFOs:
 213          */
 214         fifo_regs = 4 * 16;
 215
 216         if (fifo_size < fifo_regs) {
 217                 DPRINTF("Too little FIFO\n");
 218                 return (EINVAL);
 219         }
 220
 221         /* subtract FIFO regs from total once */
 222         fifo_size -= fifo_regs;
 223
 224         /* split equally for IN and OUT */
 225         fifo_size /= 2;
 226
 227         /* Align to 4 bytes boundary (refer to PGM) */
 228         fifo_size &= ~3;
 229
 230         /* set global receive FIFO size */
 231         DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4);
 232
 233         tx_start = fifo_size;
 234
 235         if (fifo_size < 64) {
 236                 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n");
 237                 return (EINVAL);
 238         }
 239
 240         if (mode == DWC_MODE_HOST) {
 241
 242                 /* reset active endpoints */
 243                 sc->sc_active_rx_ep = 0;
 244
 245                 /* split equally for periodic and non-periodic */
 246                 fifo_size /= 2;
 247
 248                 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size);
 249
 250                 /* align to 4 bytes boundary */
 251                 fifo_size &= ~3;
 252
 253                 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ,
 254                     ((fifo_size / 4) << 16) |
 255                     (tx_start / 4));
 256
 257                 tx_start += fifo_size;
 258
 259                 for (x = 0; x != sc->sc_host_ch_max; x++) {
 260                         /* enable all host interrupts */
 261                         DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x),
 262                             HCINT_DEFAULT_MASK);
 263                 }
 264
 265                 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ,
 266                     ((fifo_size / 4) << 16) |
 267                     (tx_start / 4));
 268
 269                 /* reset host channel state */
 270                 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
 271
 272                 /* enable all host channel interrupts */
 273                 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK,
 274                     (1U << sc->sc_host_ch_max) - 1U);
 275         }
 276
 277         if (mode == DWC_MODE_DEVICE) {
 278
 279             DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ,
 280                 (0x10 << 16) | (tx_start / 4));
 281             fifo_size -= 0x40;
 282             tx_start += 0x40;
 283
 284             /* setup control endpoint profile */
 285             sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0];
 286
 287             /* reset active endpoints */
 288             sc->sc_active_rx_ep = 1;
 289
 290             for (x = 1; x != sc->sc_dev_ep_max; x++) {
 291
 292                 pf = sc->sc_hw_ep_profile + x;
 293
 294                 pf->usb.max_out_frame_size = 1024 * 3;
 295                 pf->usb.is_simplex = 0; /* assume duplex */
 296                 pf->usb.support_bulk = 1;
 297                 pf->usb.support_interrupt = 1;
 298                 pf->usb.support_isochronous = 1;
 299                 pf->usb.support_out = 1;
 300
 301                 if (x < sc->sc_dev_in_ep_max) {
 302                         uint32_t limit;
 303
 304                         limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE,
 305                             DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2,
 306                             DWC_OTG_TX_MAX_FIFO_SIZE);
 307
 308                         /* see if there is enough FIFO space */
 309                         if (limit <= fifo_size) {
 310                                 pf->max_buffer = limit;
 311                                 pf->usb.support_in = 1;
 312                         } else {
 313                                 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40);
 314                                 if (limit <= fifo_size) {
 315                                         pf->usb.support_in = 1;
 316                                 } else {
 317                                         pf->usb.is_simplex = 1;
 318                                         limit = 0;
 319                                 }
 320                         }
 321                         /* set FIFO size */
 322                         DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x),
 323                             ((limit / 4) << 16) | (tx_start / 4));
 324                         tx_start += limit;
 325                         fifo_size -= limit;
 326                         pf->usb.max_in_frame_size = limit;
 327                 } else {
 328                         pf->usb.is_simplex = 1;
 329                 }
 330
 331                 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x,
 332                     pf->usb.max_in_frame_size,
 333                     pf->usb.max_out_frame_size);
 334             }
 335         }
 336
 337         /* reset RX FIFO */
 338         dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH);
 339
 340         if (mode != DWC_MODE_OTG) {
 341                 /* reset all TX FIFOs */
 342                 dwc_otg_tx_fifo_reset(sc,
 343                     GRSTCTL_TXFIFO(0x10) |
 344                     GRSTCTL_TXFFLSH);
 345         } else {
 346                 /* reset active endpoints */
 347                 sc->sc_active_rx_ep = 0;
 348
 349                 /* reset host channel state */
 350                 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
 351         }
 352         return (0);
 353 }
 354
 355 static void
 356 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc)
 357 {
 358
 359   /*
 360    * Disabled until further. Assuming that the register is already
 361    * programmed correctly by the boot loader.
 362    */
 363 #if 0
 364         uint32_t temp;
 365
 366         /* setup HOST frame interval register, based on existing value */
 367         temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK;
 368         if (temp >= 10000)
 369                 temp /= 1000;
 370         else
 371                 temp /= 125;
 372
 373         /* figure out nearest X-tal value */
 374         if (temp >= 54)
 375                 temp = 60;      /* MHz */
 376         else if (temp >= 39)
 377                 temp = 48;      /* MHz */
 378         else
 379                 temp = 30;      /* MHz */
 380
 381         if (sc->sc_flags.status_high_speed)
 382                 temp *= 125;
 383         else
 384                 temp *= 1000;
 385
 386         DPRINTF("HFIR=0x%08x\n", temp);
 387
 388         DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp);
 389 #endif
 390 }
 391
 392 static void
 393 dwc_otg_clocks_on(struct dwc_otg_softc *sc)
 394 {
 395         if (sc->sc_flags.clocks_off &&
 396             sc->sc_flags.port_powered) {
 397
 398                 DPRINTFN(5, "\n");
 399
 400                 /* TODO - platform specific */
 401
 402                 sc->sc_flags.clocks_off = 0;
 403         }
 404 }
 405
 406 static void
 407 dwc_otg_clocks_off(struct dwc_otg_softc *sc)
 408 {
 409         if (!sc->sc_flags.clocks_off) {
 410
 411                 DPRINTFN(5, "\n");
 412
 413                 /* TODO - platform specific */
 414
 415                 sc->sc_flags.clocks_off = 1;
 416         }
 417 }
 418
 419 static void
 420 dwc_otg_pull_up(struct dwc_otg_softc *sc)
 421 {
 422         uint32_t temp;
 423
 424         /* pullup D+, if possible */
 425
 426         if (!sc->sc_flags.d_pulled_up &&
 427             sc->sc_flags.port_powered) {
 428                 sc->sc_flags.d_pulled_up = 1;
 429
 430                 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
 431                 temp &= ~DCTL_SFTDISCON;
 432                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 433         }
 434 }
 435
 436 static void
 437 dwc_otg_pull_down(struct dwc_otg_softc *sc)
 438 {
 439         uint32_t temp;
 440
 441         /* pulldown D+, if possible */
 442
 443         if (sc->sc_flags.d_pulled_up) {
 444                 sc->sc_flags.d_pulled_up = 0;
 445
 446                 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
 447                 temp |= DCTL_SFTDISCON;
 448                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 449         }
 450 }
 451
 452 static void
 453 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc)
 454 {
 455         /* In device mode we don't use the SOF interrupt */
 456         if (sc->sc_flags.status_device_mode != 0)
 457                 return;
 458         /* Ensure the SOF interrupt is not disabled */
 459         sc->sc_needsof = 1;
 460         /* Check if the SOF interrupt is already enabled */
 461         if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0)
 462                 return;
 463         sc->sc_irq_mask |= GINTMSK_SOFMSK;
 464         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 465 }
 466
 467 static void
 468 dwc_otg_resume_irq(struct dwc_otg_softc *sc)
 469 {
 470         if (sc->sc_flags.status_suspend) {
 471                 /* update status bits */
 472                 sc->sc_flags.status_suspend = 0;
 473                 sc->sc_flags.change_suspend = 1;
 474
 475                 if (sc->sc_flags.status_device_mode) {
 476                         /*
 477                          * Disable resume interrupt and enable suspend
 478                          * interrupt:
 479                          */
 480                         sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK;
 481                         sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
 482                         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 483                 }
 484
 485                 /* complete root HUB interrupt endpoint */
 486                 dwc_otg_root_intr(sc);
 487         }
 488 }
 489
 490 static void
 491 dwc_otg_suspend_irq(struct dwc_otg_softc *sc)
 492 {
 493         if (!sc->sc_flags.status_suspend) {
 494                 /* update status bits */
 495                 sc->sc_flags.status_suspend = 1;
 496                 sc->sc_flags.change_suspend = 1;
 497
 498                 if (sc->sc_flags.status_device_mode) {
 499                         /*
 500                          * Disable suspend interrupt and enable resume
 501                          * interrupt:
 502                          */
 503                         sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK;
 504                         sc->sc_irq_mask |= GINTMSK_WKUPINTMSK;
 505                         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 506                 }
 507
 508                 /* complete root HUB interrupt endpoint */
 509                 dwc_otg_root_intr(sc);
 510         }
 511 }
 512
 513 static void
 514 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc)
 515 {
 516         if (!sc->sc_flags.status_suspend)
 517                 return;
 518
 519         DPRINTFN(5, "Remote wakeup\n");
 520
 521         if (sc->sc_flags.status_device_mode) {
 522                 uint32_t temp;
 523
 524                 /* enable remote wakeup signalling */
 525                 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
 526                 temp |= DCTL_RMTWKUPSIG;
 527                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 528
 529                 /* Wait 8ms for remote wakeup to complete. */
 530                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 531
 532                 temp &= ~DCTL_RMTWKUPSIG;
 533                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 534         } else {
 535                 /* enable USB port */
 536                 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0);
 537
 538                 /* wait 10ms */
 539                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
 540
 541                 /* resume port */
 542                 sc->sc_hprt_val |= HPRT_PRTRES;
 543                 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
 544
 545                 /* Wait 100ms for resume signalling to complete. */
 546                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
 547
 548                 /* clear suspend and resume */
 549                 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES);
 550                 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
 551
 552                 /* Wait 4ms */
 553                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
 554         }
 555
 556         /* need to fake resume IRQ */
 557         dwc_otg_resume_irq(sc);
 558 }
 559
 560 static void
 561 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr)
 562 {
 563         uint32_t temp;
 564
 565         DPRINTFN(5, "addr=%d\n", addr);
 566
 567         temp = DWC_OTG_READ_4(sc, DOTG_DCFG);
 568         temp &= ~DCFG_DEVADDR_SET(0x7F);
 569         temp |= DCFG_DEVADDR_SET(addr);
 570         DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp);
 571 }
 572
 573 static void
 574 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc)
 575 {
 576         DPRINTFN(5, "RX status clear\n");
 577
 578         /* enable RX FIFO level interrupt */
 579         sc->sc_irq_mask |= GINTMSK_RXFLVLMSK;
 580         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 581
 582         /* clear cached status */
 583         sc->sc_last_rx_status = 0;
 584 }
 585
 586 static void
 587 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x)
 588 {
 589         uint32_t hcint;
 590
 591         /* clear all pending interrupts */
 592         hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
 593         DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint);
 594
 595         /* clear buffered interrupts */
 596         sc->sc_chan_state[x].hcint = 0;
 597 }
 598
 599 static uint8_t
 600 dwc_otg_host_check_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 601 {
 602         uint32_t temp;
 603
 604         temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
 605
 606         if (td->ep_type == UE_INTERRUPT ||
 607             td->ep_type == UE_ISOCHRONOUS) {
 608                 if (!(temp & GINTSTS_PTXFEMP)) {
 609                         DPRINTF("Periodic TX FIFO is not empty\n");
 610                         if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) {
 611                                 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK;
 612                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 613                         }
 614                         return (1);     /* busy */
 615                 }
 616         } else {
 617                 if (!(temp & GINTSTS_NPTXFEMP)) {
 618                         DPRINTF("Non-periodic TX FIFO is not empty\n");
 619                         if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) {
 620                                 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK;
 621                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 622                         }
 623                         return (1);     /* busy */
 624                 }
 625         }
 626         return (0);     /* ready for transmit */
 627 }
 628
 629 static uint8_t
 630 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc,
 631     struct dwc_otg_td *td, uint8_t is_out)
 632 {
 633         uint8_t x;
 634
 635         if (td->channel < DWC_OTG_MAX_CHANNELS)
 636                 return (0);             /* already allocated */
 637
 638         /* check if device is suspended */
 639         if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
 640                 return (1);             /* busy - cannot transfer data */
 641
 642         /* compute needed TX FIFO size */
 643         if (is_out != 0) {
 644                 if (dwc_otg_host_check_fifo_empty(sc, td) != 0)
 645                         return (1);     /* busy - cannot transfer data */
 646         }
 647
 648         for (x = 0; x != sc->sc_host_ch_max; x++) {
 649                 /* check if channel is allocated */
 650                 if (sc->sc_chan_state[x].allocated != 0)
 651                         continue;
 652                 /* check if channel is still enabled */
 653                 if (sc->sc_chan_state[x].wait_halted != 0)
 654                         continue;
 655
 656                 sc->sc_chan_state[x].allocated = 1;
 657
 658                 /* clear interrupts */
 659                 dwc_otg_clear_hcint(sc, x);
 660
 661                 DPRINTF("CH=%d HCCHAR=0x%08x "
 662                     "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt);
 663
 664                 /* set active channel */
 665                 sc->sc_active_rx_ep |= (1 << x);
 666
 667                 /* set channel */
 668                 td->channel = x;
 669
 670                 return (0);     /* allocated */
 671         }
 672         /* wait a bit */
 673         dwc_otg_enable_sof_irq(sc);
 674         return (1);     /* busy */
 675 }
 676
 677 static void
 678 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 679 {
 680         uint32_t hcchar;
 681         uint8_t x;
 682
 683         if (td->channel >= DWC_OTG_MAX_CHANNELS)
 684                 return;         /* already freed */
 685
 686         /* free channel */
 687         x = td->channel;
 688         td->channel = DWC_OTG_MAX_CHANNELS;
 689
 690         DPRINTF("CH=%d\n", x);
 691
 692         /*
 693          * We need to let programmed host channels run till complete
 694          * else the host channel will stop functioning.
 695          */
 696         sc->sc_chan_state[x].allocated = 0;
 697
 698         /* ack any pending messages */
 699         if (sc->sc_last_rx_status != 0 &&
 700             GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) {
 701                 dwc_otg_common_rx_ack(sc);
 702         }
 703
 704         /* clear active channel */
 705         sc->sc_active_rx_ep &= ~(1 << x);
 706
 707         /* disable host channel */
 708         hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x));
 709         if (hcchar & HCCHAR_CHENA) {
 710                 DPRINTF("Halting channel %d\n", x);
 711                 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x),
 712                     hcchar | HCCHAR_CHDIS);
 713                 sc->sc_chan_state[x].wait_halted = 1;
 714                 /* don't write HCCHAR until the channel is halted */
 715         }
 716 }
 717
 718 static void
 719 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 720 {
 721         /* dump any pending messages */
 722         if (sc->sc_last_rx_status != 0) {
 723                 if (td->channel < DWC_OTG_MAX_CHANNELS &&
 724                     td->channel == GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) {
 725                         dwc_otg_common_rx_ack(sc);
 726                 }
 727         }
 728 }
 729
 730 static uint8_t
 731 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 732 {
 733         struct usb_device_request req __aligned(4);
 734         uint32_t hcint;
 735         uint32_t hcchar;
 736         uint8_t delta;
 737
 738         dwc_otg_host_dump_rx(sc, td);
 739
 740         if (td->channel < DWC_OTG_MAX_CHANNELS) {
 741                 hcint = sc->sc_chan_state[td->channel].hcint;
 742
 743                 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
 744                     td->channel, td->state, hcint,
 745                     DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)),
 746                     DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel)));
 747         } else {
 748                 hcint = 0;
 749                 goto check_state;
 750         }
 751
 752         if (hcint & (HCINT_RETRY |
 753             HCINT_ACK | HCINT_NYET)) {
 754                 /* give success bits priority over failure bits */
 755         } else if (hcint & HCINT_STALL) {
 756                 DPRINTF("CH=%d STALL\n", td->channel);
 757                 td->error_stall = 1;
 758                 td->error_any = 1;
 759                 goto complete;
 760         } else if (hcint & HCINT_ERRORS) {
 761                 DPRINTF("CH=%d ERROR\n", td->channel);
 762                 td->errcnt++;
 763                 if (td->hcsplt != 0 || td->errcnt >= 3) {
 764                         td->error_any = 1;
 765                         goto complete;
 766                 }
 767         }
 768
 769         if (hcint & (HCINT_ERRORS | HCINT_RETRY |
 770             HCINT_ACK | HCINT_NYET)) {
 771                 if (!(hcint & HCINT_ERRORS))
 772                         td->errcnt = 0;
 773         }
 774
 775 check_state:
 776         switch (td->state) {
 777         case DWC_CHAN_ST_START:
 778                 goto send_pkt;
 779
 780         case DWC_CHAN_ST_WAIT_ANE:
 781                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
 782                         td->did_nak = 1;
 783                         td->tt_scheduled = 0;
 784                         goto send_pkt;
 785                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
 786                         td->offset += td->tx_bytes;
 787                         td->remainder -= td->tx_bytes;
 788                         td->toggle = 1;
 789                         td->tt_scheduled = 0;
 790                         goto complete;
 791                 }
 792                 break;
 793
 794         case DWC_CHAN_ST_WAIT_S_ANE:
 795                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
 796                         td->did_nak = 1;
 797                         td->tt_scheduled = 0;
 798                         goto send_pkt;
 799                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
 800                         goto send_cpkt;
 801                 }
 802                 break;
 803
 804         case DWC_CHAN_ST_WAIT_C_ANE:
 805                 if (hcint & HCINT_NYET) {
 806                         goto send_cpkt;
 807                 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
 808                         td->did_nak = 1;
 809                         td->tt_scheduled = 0;
 810                         goto send_pkt;
 811                 } else if (hcint & HCINT_ACK) {
 812                         td->offset += td->tx_bytes;
 813                         td->remainder -= td->tx_bytes;
 814                         td->toggle = 1;
 815                         goto complete;
 816                 }
 817                 break;
 818
 819         case DWC_CHAN_ST_WAIT_C_PKT:
 820                 goto send_cpkt;
 821
 822         default:
 823                 break;
 824         }
 825         goto busy;
 826
 827 send_pkt:
 828         /* free existing channel, if any */
 829         dwc_otg_host_channel_free(sc, td);
 830
 831         if (sizeof(req) != td->remainder) {
 832                 td->error_any = 1;
 833                 goto complete;
 834         }
 835
 836         if (td->hcsplt != 0) {
 837                 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
 838                 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
 839                         td->state = DWC_CHAN_ST_START;
 840                         goto busy;
 841                 }
 842                 delta = sc->sc_last_frame_num - td->tt_start_slot;
 843                 if (delta > 5) {
 844                         /* missed it */
 845                         td->tt_scheduled = 0;
 846                         td->state = DWC_CHAN_ST_START;
 847                         goto busy;
 848                 }
 849         }
 850
 851         /* allocate a new channel */
 852         if (dwc_otg_host_channel_alloc(sc, td, 1)) {
 853                 td->state = DWC_CHAN_ST_START;
 854                 goto busy;
 855         }
 856
 857         if (td->hcsplt != 0) {
 858                 td->hcsplt &= ~HCSPLT_COMPSPLT;
 859                 td->state = DWC_CHAN_ST_WAIT_S_ANE;
 860         } else {
 861                 td->state = DWC_CHAN_ST_WAIT_ANE;
 862         }
 863
 864         usbd_copy_out(td->pc, 0, &req, sizeof(req));
 865
 866         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel),
 867             (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) |
 868             (1 << HCTSIZ_PKTCNT_SHIFT) |
 869             (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT));
 870
 871         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt);
 872
 873         hcchar = td->hcchar;
 874         hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK);
 875         hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT;
 876
 877         /* must enable channel before writing data to FIFO */
 878         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar);
 879
 880         /* transfer data into FIFO */
 881         bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
 882             DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4);
 883
 884         /* wait until next slot before trying complete split */
 885         td->tt_complete_slot = sc->sc_last_frame_num + 1;
 886
 887         /* store number of bytes transmitted */
 888         td->tx_bytes = sizeof(req);
 889         goto busy;
 890
 891 send_cpkt:
 892         /* free existing channel, if any */
 893         dwc_otg_host_channel_free(sc, td);
 894
 895         delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
 896         if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
 897                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
 898                 goto busy;
 899         }
 900         delta = sc->sc_last_frame_num - td->tt_start_slot;
 901         if (delta > DWC_OTG_TT_SLOT_MAX) {
 902                 /* we missed the service interval */
 903                 if (td->ep_type != UE_ISOCHRONOUS)
 904                         td->error_any = 1;
 905                 goto complete;
 906         }
 907         /* allocate a new channel */
 908         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
 909                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
 910                 goto busy;
 911         }
 912
 913         /* wait until next slot before trying complete split */
 914         td->tt_complete_slot = sc->sc_last_frame_num + 1;
 915
 916         td->hcsplt |= HCSPLT_COMPSPLT;
 917         td->state = DWC_CHAN_ST_WAIT_C_ANE;
 918
 919         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel),
 920             (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT));
 921
 922         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt);
 923
 924         hcchar = td->hcchar;
 925         hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK);
 926         hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT;
 927
 928         /* must enable channel before writing data to FIFO */
 929         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar);
 930
 931 busy:
 932         return (1);     /* busy */
 933
 934 complete:
 935         dwc_otg_host_channel_free(sc, td);
 936         return (0);     /* complete */
 937 }
 938
 939 static uint8_t
 940 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 941 {
 942         struct usb_device_request req __aligned(4);
 943         uint32_t temp;
 944         uint16_t count;
 945
 946         /* check endpoint status */
 947
 948         if (sc->sc_last_rx_status == 0)
 949                 goto not_complete;
 950
 951         if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0)
 952                 goto not_complete;
 953
 954         if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
 955             GRXSTSRD_STP_DATA) {
 956                 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
 957                     GRXSTSRD_STP_COMPLETE || td->remainder != 0) {
 958                         /* release FIFO */
 959                         dwc_otg_common_rx_ack(sc);
 960                         goto not_complete;
 961                 }
 962                 /* release FIFO */
 963                 dwc_otg_common_rx_ack(sc);
 964                 return (0);     /* complete */
 965         }
 966
 967         if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
 968             GRXSTSRD_DPID_DATA0) {
 969                 /* release FIFO */
 970                 dwc_otg_common_rx_ack(sc);
 971                 goto not_complete;
 972         }
 973
 974         DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status);
 975
 976         /* clear did stall */
 977         td->did_stall = 0;
 978
 979         /* get the packet byte count */
 980         count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
 981
 982         if (count != sizeof(req)) {
 983                 DPRINTFN(0, "Unsupported SETUP packet "
 984                     "length, %d bytes\n", count);
 985                 /* release FIFO */
 986                 dwc_otg_common_rx_ack(sc);
 987                 goto not_complete;
 988         }
 989
 990         /* copy in control request */
 991         memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req));
 992
 993         /* copy data into real buffer */
 994         usbd_copy_in(td->pc, 0, &req, sizeof(req));
 995
 996         td->offset = sizeof(req);
 997         td->remainder = 0;
 998
 999         /* sneak peek the set address */
1000         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1001             (req.bRequest == UR_SET_ADDRESS)) {
1002                 /* must write address before ZLP */
1003                 dwc_otg_set_address(sc, req.wValue[0] & 0x7F);
1004         }
1005
1006         /* don't send any data by default */
1007         DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS);
1008         DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS);
1009
1010         /* reset IN endpoint buffer */
1011         dwc_otg_tx_fifo_reset(sc,
1012             GRSTCTL_TXFIFO(0) |
1013             GRSTCTL_TXFFLSH);
1014
1015         /* acknowledge RX status */
1016         dwc_otg_common_rx_ack(sc);
1017         td->did_stall = 1;
1018
1019 not_complete:
1020         /* abort any ongoing transfer, before enabling again */
1021         if (!td->did_stall) {
1022                 td->did_stall = 1;
1023
1024                 DPRINTFN(5, "stalling IN and OUT direction\n");
1025
1026                 temp = sc->sc_out_ctl[0];
1027
1028                 /* set stall after enabling endpoint */
1029                 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0),
1030                     temp | DOEPCTL_STALL);
1031
1032                 temp = sc->sc_in_ctl[0];
1033
1034                 /* set stall assuming endpoint is enabled */
1035                 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0),
1036                     temp | DIEPCTL_STALL);
1037         }
1038         return (1);                     /* not complete */
1039 }
1040
1041 static uint8_t
1042 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1043 {
1044         uint8_t delta;
1045
1046         delta = sc->sc_tmr_val - td->tmr_val;
1047         if (delta >= 128)
1048                 return (1);     /* busy */
1049
1050         td->tmr_val = sc->sc_tmr_val + td->tmr_res;
1051
1052         /* set toggle, if any */
1053         if (td->set_toggle) {
1054                 td->set_toggle = 0;
1055                 td->toggle = 1;
1056         }
1057         return (0);
1058 }
1059
1060 static uint8_t
1061 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1062 {
1063         if (td->ep_type == UE_ISOCHRONOUS) {
1064                 /* non TT isochronous traffic */
1065                 if ((td->tmr_val != 0) ||
1066                     (sc->sc_last_frame_num & (td->tmr_res - 1))) {
1067                         goto busy;
1068                 }
1069                 td->tmr_val = 1;        /* executed */
1070                 td->toggle = 0;
1071
1072         } else if (td->ep_type == UE_INTERRUPT) {
1073                 if (!td->tt_scheduled)
1074                         goto busy;
1075                 td->tt_scheduled = 0;
1076         } else if (td->did_nak != 0) {
1077                 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num;
1078                 /* check if we should pause sending queries for 125us */
1079                 if (td->tmr_res == frame_num) {
1080                         /* wait a bit */
1081                         dwc_otg_enable_sof_irq(sc);
1082                         goto busy;
1083                 }
1084                 /* query for data one more time */
1085                 td->tmr_res = frame_num;
1086                 td->did_nak = 0;
1087         } else if (td->set_toggle) {
1088                 td->set_toggle = 0;
1089                 td->toggle = 1;
1090         }
1091         return (0);
1092 busy:
1093         return (1);
1094 }
1095
1096 static uint8_t
1097 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1098 {
1099         uint32_t count;
1100         uint8_t channel;
1101
1102         /* check endpoint status */
1103         if (sc->sc_last_rx_status == 0)
1104                 goto busy;
1105
1106         channel = td->channel;
1107         if (channel >= DWC_OTG_MAX_CHANNELS)
1108                 goto busy;
1109
1110         if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel)
1111                 goto busy;
1112
1113         switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) {
1114         case GRXSTSRH_IN_DATA:
1115
1116                 DPRINTF("DATA ST=%d STATUS=0x%08x\n",
1117                     (int)td->state, (int)sc->sc_last_rx_status);
1118
1119                 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) {
1120                         /*
1121                          * When using SPLIT transactions on interrupt
1122                          * endpoints, sometimes data occurs twice.
1123                          */
1124                         DPRINTF("Data already received\n");
1125                         break;
1126                 }
1127
1128                 /* get the packet byte count */
1129                 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1130
1131                 /* check for isochronous transfer or high-speed bandwidth endpoint */
1132                 if (td->ep_type == UE_ISOCHRONOUS || td->max_packet_count > 1) {
1133                         if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) {
1134                                 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE;
1135                         } else {
1136                                 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
1137
1138                                 /* verify the packet byte count */
1139                                 if (count < td->max_packet_size) {
1140                                         /* we have a short packet */
1141                                         td->short_pkt = 1;
1142                                         td->got_short = 1;
1143                                 }
1144                         }
1145                         td->toggle = 0;
1146                 } else {
1147                         /* verify the packet byte count */
1148                         if (count != td->max_packet_size) {
1149                                 if (count < td->max_packet_size) {
1150                                         /* we have a short packet */
1151                                         td->short_pkt = 1;
1152                                         td->got_short = 1;
1153                                 } else {
1154                                         /* invalid USB packet */
1155                                         td->error_any = 1;
1156
1157                                         /* release FIFO */
1158                                         dwc_otg_common_rx_ack(sc);
1159                                         goto complete;
1160                                 }
1161                         }
1162                         td->toggle ^= 1;
1163                         td->tt_scheduled = 0;
1164                 }
1165
1166                 /* verify the packet byte count */
1167                 if (count > td->remainder) {
1168                         /* invalid USB packet */
1169                         td->error_any = 1;
1170
1171                         /* release FIFO */
1172                         dwc_otg_common_rx_ack(sc);
1173                         goto complete;
1174                 }
1175
1176                 usbd_copy_in(td->pc, td->offset,
1177                     sc->sc_rx_bounce_buffer, count);
1178
1179                 td->remainder -= count;
1180                 td->offset += count;
1181                 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY;
1182                 break;
1183         default:
1184                 break;
1185         }
1186         /* release FIFO */
1187         dwc_otg_common_rx_ack(sc);
1188 busy:
1189         return (0);
1190 complete:
1191         return (1);
1192 }
1193
1194 static uint8_t
1195 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1196 {
1197         uint32_t hcint;
1198         uint32_t hcchar;
1199         uint8_t delta;
1200         uint8_t channel;
1201
1202         channel = td->channel;
1203
1204         if (channel < DWC_OTG_MAX_CHANNELS) {
1205                 hcint = sc->sc_chan_state[channel].hcint;
1206
1207                 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
1208                     channel, td->state, hcint,
1209                     DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1210                     DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1211
1212                 /* check interrupt bits */
1213                 if (hcint & (HCINT_RETRY |
1214                     HCINT_ACK | HCINT_NYET)) {
1215                         /* give success bits priority over failure bits */
1216                 } else if (hcint & HCINT_STALL) {
1217                         DPRINTF("CH=%d STALL\n", channel);
1218                         td->error_stall = 1;
1219                         td->error_any = 1;
1220                         goto complete;
1221                 } else if (hcint & HCINT_ERRORS) {
1222                         DPRINTF("CH=%d ERROR\n", channel);
1223                         td->errcnt++;
1224                         if (td->hcsplt != 0 || td->errcnt >= 3) {
1225                                 if (td->ep_type != UE_ISOCHRONOUS) {
1226                                         td->error_any = 1;
1227                                         goto complete;
1228                                 }
1229                         }
1230                 }
1231
1232                 /* check channels for data, if any */
1233                 if (dwc_otg_host_data_rx_sub(sc, td))
1234                         goto complete;
1235
1236                 /* refresh interrupt status */
1237                 hcint = sc->sc_chan_state[channel].hcint;
1238
1239                 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
1240                     HCINT_ACK | HCINT_NYET)) {
1241                         if (!(hcint & HCINT_ERRORS))
1242                                 td->errcnt = 0;
1243                 }
1244         } else {
1245                 hcint = 0;
1246         }
1247
1248         switch (td->state) {
1249         case DWC_CHAN_ST_START:
1250                 if (td->hcsplt != 0)
1251                         goto receive_spkt;
1252                 else
1253                         goto receive_pkt;
1254
1255         case DWC_CHAN_ST_WAIT_ANE:
1256                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1257                         if (td->ep_type == UE_INTERRUPT) {
1258                                 /*
1259                                  * The USB specification does not
1260                                  * mandate a particular data toggle
1261                                  * value for USB INTERRUPT
1262                                  * transfers. Switch the data toggle
1263                                  * value to receive the packet
1264                                  * correctly:
1265                                  */
1266                                 if (hcint & HCINT_DATATGLERR) {
1267                                         DPRINTF("Retrying packet due to "
1268                                             "data toggle error\n");
1269                                         td->toggle ^= 1;
1270                                         goto receive_pkt;
1271                                 }
1272                         }
1273                         td->did_nak = 1;
1274                         td->tt_scheduled = 0;
1275                         if (td->hcsplt != 0)
1276                                 goto receive_spkt;
1277                         else
1278                                 goto receive_pkt;
1279                 } else if (hcint & HCINT_NYET) {
1280                         if (td->hcsplt != 0) {
1281                                 /* try again */
1282                                 goto receive_pkt;
1283                         } else {
1284                                 /* not a valid token for IN endpoints */
1285                                 td->error_any = 1;
1286                                 goto complete;
1287                         }
1288                 } else if (hcint & HCINT_ACK) {
1289                         /* wait for data - ACK arrived first */
1290                         if (!(hcint & HCINT_SOFTWARE_ONLY))
1291                                 goto busy;
1292
1293                         if (td->ep_type == UE_ISOCHRONOUS) {
1294                                 /* check if we are complete */
1295                                 if ((td->remainder == 0) ||
1296                                     (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN)) {
1297                                         goto complete;
1298                                 }
1299                                 /* get another packet */
1300                                 goto receive_pkt;
1301                         } else {
1302                                 /* check if we are complete */
1303                                 if ((td->remainder == 0) || (td->got_short != 0)) {
1304                                         if (td->short_pkt)
1305                                                 goto complete;
1306
1307                                         /*
1308                                          * Else need to receive a zero length
1309                                          * packet.
1310                                          */
1311                                 }
1312                                 td->tt_scheduled = 0;
1313                                 td->did_nak = 0;
1314                                 if (td->hcsplt != 0)
1315                                         goto receive_spkt;
1316                                 else
1317                                         goto receive_pkt;
1318                         }
1319                 }
1320                 break;
1321
1322         case DWC_CHAN_ST_WAIT_S_ANE:
1323                 /*
1324                  * NOTE: The DWC OTG hardware provides a fake ACK in
1325                  * case of interrupt and isochronous transfers:
1326                  */
1327                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1328                         td->did_nak = 1;
1329                         td->tt_scheduled = 0;
1330                         goto receive_spkt;
1331                 } else if (hcint & HCINT_NYET) {
1332                         td->tt_scheduled = 0;
1333                         goto receive_spkt;
1334                 } else if (hcint & HCINT_ACK) {
1335                         td->did_nak = 0;
1336                         goto receive_pkt;
1337                 }
1338                 break;
1339
1340         case DWC_CHAN_ST_WAIT_C_PKT:
1341                 goto receive_pkt;
1342
1343         default:
1344                 break;
1345         }
1346         goto busy;
1347
1348 receive_pkt:
1349         /* free existing channel, if any */
1350         dwc_otg_host_channel_free(sc, td);
1351
1352         if (td->hcsplt != 0) {
1353                 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1354                 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1355                         td->state = DWC_CHAN_ST_WAIT_C_PKT;
1356                         goto busy;
1357                 }
1358                 delta = sc->sc_last_frame_num - td->tt_start_slot;
1359                 if (delta > DWC_OTG_TT_SLOT_MAX) {
1360                         if (td->ep_type != UE_ISOCHRONOUS) {
1361                                 /* we missed the service interval */
1362                                 td->error_any = 1;
1363                         }
1364                         goto complete;
1365                 }
1366                 /* complete split */
1367                 td->hcsplt |= HCSPLT_COMPSPLT;
1368         } else if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN &&
1369             dwc_otg_host_rate_check(sc, td)) {
1370                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1371                 goto busy;
1372         }
1373
1374         /* allocate a new channel */
1375         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1376                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1377                 goto busy;
1378         }
1379
1380         channel = td->channel;
1381
1382         /* set toggle, if any */
1383         if (td->set_toggle) {
1384                 td->set_toggle = 0;
1385                 td->toggle = 1;
1386         }
1387
1388         td->state = DWC_CHAN_ST_WAIT_ANE;
1389
1390         /* receive one packet */
1391         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1392             (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) |
1393             (1 << HCTSIZ_PKTCNT_SHIFT) |
1394             (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
1395             (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
1396
1397         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1398
1399         hcchar = td->hcchar;
1400         hcchar |= HCCHAR_EPDIR_IN;
1401
1402         /* receive complete split ASAP */
1403         if ((sc->sc_last_frame_num & 1) != 0 &&
1404             (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS))
1405                 hcchar |= HCCHAR_ODDFRM;
1406         else
1407                 hcchar &= ~HCCHAR_ODDFRM;
1408
1409         /* must enable channel before data can be received */
1410         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1411
1412         /* wait until next slot before trying complete split */
1413         td->tt_complete_slot = sc->sc_last_frame_num + 1;
1414
1415         goto busy;
1416
1417 receive_spkt:
1418         /* free existing channel(s), if any */
1419         dwc_otg_host_channel_free(sc, td);
1420
1421         delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1422         if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1423                 td->state = DWC_CHAN_ST_START;
1424                 goto busy;
1425         }
1426         delta = sc->sc_last_frame_num - td->tt_start_slot;
1427         if (delta > 5) {
1428                 /* missed it */
1429                 td->tt_scheduled = 0;
1430                 td->state = DWC_CHAN_ST_START;
1431                 goto busy;
1432         }
1433
1434         /* allocate a new channel */
1435         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1436                 td->state = DWC_CHAN_ST_START;
1437                 goto busy;
1438         }
1439
1440         channel = td->channel;
1441
1442         td->hcsplt &= ~HCSPLT_COMPSPLT;
1443         td->state = DWC_CHAN_ST_WAIT_S_ANE;
1444
1445         /* receive one packet */
1446         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1447             (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT));
1448
1449         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1450
1451         /* send after next SOF event */
1452         if ((sc->sc_last_frame_num & 1) == 0 &&
1453             (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS))
1454                 td->hcchar |= HCCHAR_ODDFRM;
1455         else
1456                 td->hcchar &= ~HCCHAR_ODDFRM;
1457
1458         hcchar = td->hcchar;
1459         hcchar |= HCCHAR_EPDIR_IN;
1460
1461         /* wait until next slot before trying complete split */
1462         td->tt_complete_slot = sc->sc_last_frame_num + 1;
1463
1464         /* must enable channel before data can be received */
1465         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1466 busy:
1467         return (1);     /* busy */
1468
1469 complete:
1470         dwc_otg_host_channel_free(sc, td);
1471         return (0);     /* complete */
1472 }
1473
1474 static uint8_t
1475 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1476 {
1477         uint32_t temp;
1478         uint16_t count;
1479         uint8_t got_short;
1480
1481         got_short = 0;
1482
1483         /* check endpoint status */
1484         if (sc->sc_last_rx_status == 0)
1485                 goto not_complete;
1486
1487         if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no)
1488                 goto not_complete;
1489
1490         /* check for SETUP packet */
1491         if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1492             GRXSTSRD_STP_DATA ||
1493             (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1494             GRXSTSRD_STP_COMPLETE) {
1495                 if (td->remainder == 0) {
1496                         /*
1497                          * We are actually complete and have
1498                          * received the next SETUP
1499                          */
1500                         DPRINTFN(5, "faking complete\n");
1501                         return (0);     /* complete */
1502                 }
1503                 /*
1504                  * USB Host Aborted the transfer.
1505                  */
1506                 td->error_any = 1;
1507                 return (0);             /* complete */
1508         }
1509
1510         if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1511             GRXSTSRD_OUT_DATA) {
1512                 /* release FIFO */
1513                 dwc_otg_common_rx_ack(sc);
1514                 goto not_complete;
1515         }
1516
1517         /* get the packet byte count */
1518         count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1519
1520         /* verify the packet byte count */
1521         if (count != td->max_packet_size) {
1522                 if (count < td->max_packet_size) {
1523                         /* we have a short packet */
1524                         td->short_pkt = 1;
1525                         got_short = 1;
1526                 } else {
1527                         /* invalid USB packet */
1528                         td->error_any = 1;
1529
1530                         /* release FIFO */
1531                         dwc_otg_common_rx_ack(sc);
1532                         return (0);     /* we are complete */
1533                 }
1534         }
1535         /* verify the packet byte count */
1536         if (count > td->remainder) {
1537                 /* invalid USB packet */
1538                 td->error_any = 1;
1539
1540                 /* release FIFO */
1541                 dwc_otg_common_rx_ack(sc);
1542                 return (0);             /* we are complete */
1543         }
1544
1545         usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count);
1546         td->remainder -= count;
1547         td->offset += count;
1548
1549         /* release FIFO */
1550         dwc_otg_common_rx_ack(sc);
1551
1552         temp = sc->sc_out_ctl[td->ep_no];
1553
1554         /* check for isochronous mode */
1555         if ((temp & DIEPCTL_EPTYPE_MASK) ==
1556             (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) {
1557                 /* toggle odd or even frame bit */
1558                 if (temp & DIEPCTL_SETD1PID) {
1559                         temp &= ~DIEPCTL_SETD1PID;
1560                         temp |= DIEPCTL_SETD0PID;
1561                 } else {
1562                         temp &= ~DIEPCTL_SETD0PID;
1563                         temp |= DIEPCTL_SETD1PID;
1564                 }
1565                 sc->sc_out_ctl[td->ep_no] = temp;
1566         }
1567
1568         /* check if we are complete */
1569         if ((td->remainder == 0) || got_short) {
1570                 if (td->short_pkt) {
1571                         /* we are complete */
1572                         return (0);
1573                 }
1574                 /* else need to receive a zero length packet */
1575         }
1576
1577 not_complete:
1578
1579         /* enable SETUP and transfer complete interrupt */
1580         if (td->ep_no == 0) {
1581                 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0),
1582                     DXEPTSIZ_SET_MULTI(3) |
1583                     DXEPTSIZ_SET_NPKT(1) |
1584                     DXEPTSIZ_SET_NBYTES(td->max_packet_size));
1585         } else {
1586                 /* allow reception of multiple packets */
1587                 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no),
1588                     DXEPTSIZ_SET_MULTI(1) |
1589                     DXEPTSIZ_SET_NPKT(4) |
1590                     DXEPTSIZ_SET_NBYTES(4 *
1591                         ((td->max_packet_size + 3) & ~3)));
1592         }
1593         temp = sc->sc_out_ctl[td->ep_no];
1594         DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp |
1595             DOEPCTL_EPENA | DOEPCTL_CNAK);
1596
1597         return (1);                     /* not complete */
1598 }
1599
1600 static uint8_t
1601 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1602 {
1603         uint32_t count;
1604         uint32_t hcint;
1605         uint32_t hcchar;
1606         uint8_t delta;
1607         uint8_t channel;
1608
1609         dwc_otg_host_dump_rx(sc, td);
1610
1611         channel = td->channel;
1612
1613         if (channel < DWC_OTG_MAX_CHANNELS) {
1614                 hcint = sc->sc_chan_state[channel].hcint;
1615
1616                 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
1617                     channel, td->state, hcint,
1618                     DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1619                     DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1620
1621                 if (hcint & (HCINT_RETRY |
1622                     HCINT_ACK | HCINT_NYET)) {
1623                         /* give success bits priority over failure bits */
1624                 } else if (hcint & HCINT_STALL) {
1625                         DPRINTF("CH=%d STALL\n", channel);
1626                         td->error_stall = 1;
1627                         td->error_any = 1;
1628                         goto complete;
1629                 } else if (hcint & HCINT_ERRORS) {
1630                         DPRINTF("CH=%d ERROR\n", channel);
1631                         td->errcnt++;
1632                         if (td->hcsplt != 0 || td->errcnt >= 3) {
1633                                 td->error_any = 1;
1634                                 goto complete;
1635                         }
1636                 }
1637
1638                 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
1639                     HCINT_ACK | HCINT_NYET)) {
1640
1641                         if (!(hcint & HCINT_ERRORS))
1642                                 td->errcnt = 0;
1643                 }
1644         } else {
1645                 hcint = 0;
1646         }
1647
1648         switch (td->state) {
1649         case DWC_CHAN_ST_START:
1650                 goto send_pkt;
1651
1652         case DWC_CHAN_ST_WAIT_ANE:
1653                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1654                         td->did_nak = 1;
1655                         td->tt_scheduled = 0;
1656                         goto send_pkt;
1657                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
1658                         td->offset += td->tx_bytes;
1659                         td->remainder -= td->tx_bytes;
1660                         td->toggle ^= 1;
1661                         td->did_nak = 0;
1662                         td->tt_scheduled = 0;
1663
1664                         /* check remainder */
1665                         if (td->remainder == 0) {
1666                                 if (td->short_pkt)
1667                                         goto complete;
1668
1669                                 /*
1670                                  * Else we need to transmit a short
1671                                  * packet:
1672                                  */
1673                         }
1674                         goto send_pkt;
1675                 }
1676                 break;
1677
1678         case DWC_CHAN_ST_WAIT_S_ANE:
1679                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1680                         td->did_nak = 1;
1681                         td->tt_scheduled = 0;
1682                         goto send_pkt;
1683                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
1684                         td->did_nak = 0;
1685                         goto send_cpkt;
1686                 }
1687                 break;
1688
1689         case DWC_CHAN_ST_WAIT_C_ANE:
1690                 if (hcint & HCINT_NYET) {
1691                         goto send_cpkt;
1692                 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1693                         td->did_nak = 1;
1694                         td->tt_scheduled = 0;
1695                         goto send_pkt;
1696                 } else if (hcint & HCINT_ACK) {
1697                         td->offset += td->tx_bytes;
1698                         td->remainder -= td->tx_bytes;
1699                         td->toggle ^= 1;
1700                         td->did_nak = 0;
1701                         td->tt_scheduled = 0;
1702
1703                         /* check remainder */
1704                         if (td->remainder == 0) {
1705                                 if (td->short_pkt)
1706                                         goto complete;
1707
1708                                 /* else we need to transmit a short packet */
1709                         }
1710                         goto send_pkt;
1711                 }
1712                 break;
1713
1714         case DWC_CHAN_ST_WAIT_C_PKT:
1715                 goto send_cpkt;
1716
1717         case DWC_CHAN_ST_TX_WAIT_ISOC:
1718
1719                 /* Check if isochronous OUT traffic is complete */
1720                 if ((hcint & HCINT_HCH_DONE_MASK) == 0)
1721                         break;
1722
1723                 td->offset += td->tx_bytes;
1724                 td->remainder -= td->tx_bytes;
1725
1726                 if (td->hcsplt != 0 || td->remainder == 0)
1727                         goto complete;
1728
1729                 /* check for next packet */
1730                 if (td->max_packet_count > 1)
1731                         td->tt_xactpos++;
1732
1733                 /* free existing channel, if any */
1734                 dwc_otg_host_channel_free(sc, td);
1735
1736                 td->state = DWC_CHAN_ST_TX_PKT_ISOC;
1737
1738                 /* FALLTHROUGH */
1739
1740         case DWC_CHAN_ST_TX_PKT_ISOC:
1741                 if (dwc_otg_host_channel_alloc(sc, td, 1))
1742                         break;
1743                 channel = td->channel;
1744                 goto send_isoc_pkt;
1745         default:
1746                 break;
1747         }
1748         goto busy;
1749
1750 send_pkt:
1751         /* free existing channel(s), if any */
1752         dwc_otg_host_channel_free(sc, td);
1753
1754         if (td->hcsplt != 0) {
1755                 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1756                 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1757                         td->state = DWC_CHAN_ST_START;
1758                         goto busy;
1759                 }
1760                 delta = sc->sc_last_frame_num - td->tt_start_slot;
1761                 if (delta > 5) {
1762                         /* missed it */
1763                         td->tt_scheduled = 0;
1764                         td->state = DWC_CHAN_ST_START;
1765                         goto busy;
1766                 }
1767         } else if (dwc_otg_host_rate_check(sc, td)) {
1768                 td->state = DWC_CHAN_ST_START;
1769                 goto busy;
1770         }
1771
1772         /* allocate a new channel */
1773         if (dwc_otg_host_channel_alloc(sc, td, 1)) {
1774                 td->state = DWC_CHAN_ST_START;
1775                 goto busy;
1776         }
1777
1778         channel = td->channel;
1779
1780         /* set toggle, if any */
1781         if (td->set_toggle) {
1782                 td->set_toggle = 0;
1783                 td->toggle = 1;
1784         }
1785
1786         if (td->ep_type == UE_ISOCHRONOUS) {
1787 send_isoc_pkt:
1788                 /* Isochronous OUT transfers don't have any ACKs */
1789                 td->state = DWC_CHAN_ST_TX_WAIT_ISOC;
1790                 td->hcsplt &= ~HCSPLT_COMPSPLT;
1791                 if (td->hcsplt != 0) {
1792                         /* get maximum transfer length */
1793                         count = td->remainder;
1794                         if (count > HCSPLT_XACTLEN_BURST) {
1795                                 DPRINTF("TT overflow\n");
1796                                 td->error_any = 1;
1797                                 goto complete;
1798                         }
1799                         /* Update transaction position */
1800                         td->hcsplt &= ~HCSPLT_XACTPOS_MASK;
1801                         td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT);
1802                 } else {
1803                         /* send one packet at a time */
1804                         count = td->max_packet_size;
1805                         if (td->remainder < count) {
1806                                 /* we have a short packet */
1807                                 td->short_pkt = 1;
1808                                 count = td->remainder;
1809                         }
1810                 }
1811         } else if (td->hcsplt != 0) {
1812
1813                 td->hcsplt &= ~HCSPLT_COMPSPLT;
1814
1815                 /* Wait for ACK/NAK/ERR from TT */
1816                 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1817
1818                 /* send one packet at a time */
1819                 count = td->max_packet_size;
1820                 if (td->remainder < count) {
1821                         /* we have a short packet */
1822                         td->short_pkt = 1;
1823                         count = td->remainder;
1824                 }
1825         } else {
1826                 /* Wait for ACK/NAK/STALL from device */
1827                 td->state = DWC_CHAN_ST_WAIT_ANE;
1828
1829                 /* send one packet at a time */
1830                 count = td->max_packet_size;
1831                 if (td->remainder < count) {
1832                         /* we have a short packet */
1833                         td->short_pkt = 1;
1834                         count = td->remainder;
1835                 }
1836         }
1837
1838         /* check for High-Speed multi-packets */
1839         if ((td->hcsplt == 0) && (td->max_packet_count > 1)) {
1840                 if (td->npkt == 0) {
1841                         if (td->remainder >= (3 * td->max_packet_size))
1842                                 td->npkt = 3;
1843                         else if (td->remainder >= (2 * td->max_packet_size))
1844                                 td->npkt = 2;
1845                         else
1846                                 td->npkt = 1;
1847
1848                         if (td->npkt > td->max_packet_count)
1849                                 td->npkt = td->max_packet_count;
1850
1851                         td->tt_xactpos = 1;     /* overload */
1852                 }
1853                 if (td->tt_xactpos == td->npkt) {
1854                         if (td->npkt == 1) {
1855                                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1856                                     (count << HCTSIZ_XFERSIZE_SHIFT) |
1857                                     (1 << HCTSIZ_PKTCNT_SHIFT) |
1858                                     (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT));
1859                         } else if (td->npkt == 2) {
1860                                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1861                                     (count << HCTSIZ_XFERSIZE_SHIFT) |
1862                                     (1 << HCTSIZ_PKTCNT_SHIFT) |
1863                                     (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT));
1864                         } else {
1865                                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1866                                     (count << HCTSIZ_XFERSIZE_SHIFT) |
1867                                     (1 << HCTSIZ_PKTCNT_SHIFT) |
1868                                     (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT));
1869                         }
1870                         td->npkt = 0;
1871                 } else {
1872                         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1873                             (count << HCTSIZ_XFERSIZE_SHIFT) |
1874                             (1 << HCTSIZ_PKTCNT_SHIFT) |
1875                             (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT));
1876                 }
1877         } else {
1878                 /* TODO: HCTSIZ_DOPNG */
1879
1880                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1881                     (count << HCTSIZ_XFERSIZE_SHIFT) |
1882                     (1 << HCTSIZ_PKTCNT_SHIFT) |
1883                     (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
1884                     (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
1885         }
1886
1887         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1888
1889         hcchar = td->hcchar;
1890         hcchar &= ~HCCHAR_EPDIR_IN;
1891
1892         /* send after next SOF event */
1893         if ((sc->sc_last_frame_num & 1) == 0 &&
1894             (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS))
1895                 hcchar |= HCCHAR_ODDFRM;
1896         else
1897                 hcchar &= ~HCCHAR_ODDFRM;
1898
1899         /* must enable before writing data to FIFO */
1900         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1901
1902         if (count != 0) {
1903
1904                 /* clear topmost word before copy */
1905                 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0;
1906
1907                 /* copy out data */
1908                 usbd_copy_out(td->pc, td->offset,
1909                     sc->sc_tx_bounce_buffer, count);
1910
1911                 /* transfer data into FIFO */
1912                 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
1913                     DOTG_DFIFO(channel),
1914                     sc->sc_tx_bounce_buffer, (count + 3) / 4);
1915         }
1916
1917         /* store number of bytes transmitted */
1918         td->tx_bytes = count;
1919         goto busy;
1920
1921 send_cpkt:
1922         /* free existing channel, if any */
1923         dwc_otg_host_channel_free(sc, td);
1924
1925         delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1926         if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1927                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1928                 goto busy;
1929         }
1930         delta = sc->sc_last_frame_num - td->tt_start_slot;
1931         if (delta > DWC_OTG_TT_SLOT_MAX) {
1932                 /* we missed the service interval */
1933                 if (td->ep_type != UE_ISOCHRONOUS)
1934                         td->error_any = 1;
1935                 goto complete;
1936         }
1937
1938         /* allocate a new channel */
1939         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1940                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1941                 goto busy;
1942         }
1943
1944         channel = td->channel;
1945
1946         td->hcsplt |= HCSPLT_COMPSPLT;
1947         td->state = DWC_CHAN_ST_WAIT_C_ANE;
1948
1949         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1950             (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT));
1951
1952         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1953
1954         hcchar = td->hcchar;
1955         hcchar &= ~HCCHAR_EPDIR_IN;
1956
1957         /* receive complete split ASAP */
1958         if ((sc->sc_last_frame_num & 1) != 0 &&
1959             (td->ep_type == UE_INTERRUPT || td->ep_type == UE_ISOCHRONOUS))
1960                 hcchar |= HCCHAR_ODDFRM;
1961         else
1962                 hcchar &= ~HCCHAR_ODDFRM;
1963
1964         /* must enable channel before data can be received */
1965         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1966
1967         /* wait until next slot before trying complete split */
1968         td->tt_complete_slot = sc->sc_last_frame_num + 1;
1969 busy:
1970         return (1);     /* busy */
1971
1972 complete:
1973         dwc_otg_host_channel_free(sc, td);
1974         return (0);     /* complete */
1975 }
1976
1977 static uint8_t
1978 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1979 {
1980         uint32_t max_buffer;
1981         uint32_t count;
1982         uint32_t fifo_left;
1983         uint32_t mpkt;
1984         uint32_t temp;
1985         uint8_t to;
1986
1987         to = 3;                         /* don't loop forever! */
1988
1989         max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer;
1990
1991 repeat:
1992         /* check for for endpoint 0 data */
1993
1994         temp = sc->sc_last_rx_status;
1995
1996         if ((td->ep_no == 0) && (temp != 0) &&
1997             (GRXSTSRD_CHNUM_GET(temp) == 0)) {
1998
1999                 if ((temp & GRXSTSRD_PKTSTS_MASK) !=
2000                     GRXSTSRD_STP_DATA &&
2001                     (temp & GRXSTSRD_PKTSTS_MASK) !=
2002                     GRXSTSRD_STP_COMPLETE) {
2003
2004                         /* dump data - wrong direction */
2005                         dwc_otg_common_rx_ack(sc);
2006                 } else {
2007                         /*
2008                          * The current transfer was cancelled
2009                          * by the USB Host:
2010                          */
2011                         td->error_any = 1;
2012                         return (0);             /* complete */
2013                 }
2014         }
2015
2016         /* fill in more TX data, if possible */
2017         if (td->tx_bytes != 0) {
2018
2019                 uint16_t cpkt;
2020
2021                 /* check if packets have been transferred */
2022                 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2023
2024                 /* get current packet number */
2025                 cpkt = DXEPTSIZ_GET_NPKT(temp);
2026
2027                 if (cpkt >= td->npkt) {
2028                         fifo_left = 0;
2029                 } else {
2030                         if (max_buffer != 0) {
2031                                 fifo_left = (td->npkt - cpkt) *
2032                                     td->max_packet_size;
2033
2034                                 if (fifo_left > max_buffer)
2035                                         fifo_left = max_buffer;
2036                         } else {
2037                                 fifo_left = td->max_packet_size;
2038                         }
2039                 }
2040
2041                 count = td->tx_bytes;
2042                 if (count > fifo_left)
2043                         count = fifo_left;
2044
2045                 if (count != 0) {
2046
2047                         /* clear topmost word before copy */
2048                         sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0;
2049
2050                         /* copy out data */
2051                         usbd_copy_out(td->pc, td->offset,
2052                             sc->sc_tx_bounce_buffer, count);
2053
2054                         /* transfer data into FIFO */
2055                         bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
2056                             DOTG_DFIFO(td->ep_no),
2057                             sc->sc_tx_bounce_buffer, (count + 3) / 4);
2058
2059                         td->tx_bytes -= count;
2060                         td->remainder -= count;
2061                         td->offset += count;
2062                         td->npkt = cpkt;
2063                 }
2064                 if (td->tx_bytes != 0)
2065                         goto not_complete;
2066
2067                 /* check remainder */
2068                 if (td->remainder == 0) {
2069                         if (td->short_pkt)
2070                                 return (0);     /* complete */
2071
2072                         /* else we need to transmit a short packet */
2073                 }
2074         }
2075
2076         if (!to--)
2077                 goto not_complete;
2078
2079         /* check if not all packets have been transferred */
2080         temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2081
2082         if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2083
2084                 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x "
2085                     "DIEPCTL=0x%08x\n", td->ep_no,
2086                     DXEPTSIZ_GET_NPKT(temp),
2087                     temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no)));
2088
2089                 goto not_complete;
2090         }
2091
2092         DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no);
2093
2094         /* try to optimise by sending more data */
2095         if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) {
2096
2097                 /* send multiple packets at the same time */
2098                 mpkt = max_buffer / td->max_packet_size;
2099
2100                 if (mpkt > 0x3FE)
2101                         mpkt = 0x3FE;
2102
2103                 count = td->remainder;
2104                 if (count > 0x7FFFFF)
2105                         count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size);
2106
2107                 td->npkt = count / td->max_packet_size;
2108
2109                 /*
2110                  * NOTE: We could use 0x3FE instead of "mpkt" in the
2111                  * check below to get more throughput, but then we
2112                  * have a dependency towards non-generic chip features
2113                  * to disable the TX-FIFO-EMPTY interrupts on a per
2114                  * endpoint basis. Increase the maximum buffer size of
2115                  * the IN endpoint to increase the performance.
2116                  */
2117                 if (td->npkt > mpkt) {
2118                         td->npkt = mpkt;
2119                         count = td->max_packet_size * mpkt;
2120                 } else if ((count == 0) || (count % td->max_packet_size)) {
2121                         /* we are transmitting a short packet */
2122                         td->npkt++;
2123                         td->short_pkt = 1;
2124                 }
2125         } else {
2126                 /* send one packet at a time */
2127                 mpkt = 1;
2128                 count = td->max_packet_size;
2129                 if (td->remainder < count) {
2130                         /* we have a short packet */
2131                         td->short_pkt = 1;
2132                         count = td->remainder;
2133                 }
2134                 td->npkt = 1;
2135         }
2136         DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no),
2137             DXEPTSIZ_SET_MULTI(1) |
2138             DXEPTSIZ_SET_NPKT(td->npkt) |
2139             DXEPTSIZ_SET_NBYTES(count));
2140
2141         /* make room for buffering */
2142         td->npkt += mpkt;
2143
2144         temp = sc->sc_in_ctl[td->ep_no];
2145
2146         /* check for isochronous mode */
2147         if ((temp & DIEPCTL_EPTYPE_MASK) ==
2148             (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) {
2149                 /* toggle odd or even frame bit */
2150                 if (temp & DIEPCTL_SETD1PID) {
2151                         temp &= ~DIEPCTL_SETD1PID;
2152                         temp |= DIEPCTL_SETD0PID;
2153                 } else {
2154                         temp &= ~DIEPCTL_SETD0PID;
2155                         temp |= DIEPCTL_SETD1PID;
2156                 }
2157                 sc->sc_in_ctl[td->ep_no] = temp;
2158         }
2159
2160         /* must enable before writing data to FIFO */
2161         DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp |
2162             DIEPCTL_EPENA | DIEPCTL_CNAK);
2163
2164         td->tx_bytes = count;
2165
2166         /* check remainder */
2167         if (td->tx_bytes == 0 &&
2168             td->remainder == 0) {
2169                 if (td->short_pkt)
2170                         return (0);     /* complete */
2171
2172                 /* else we need to transmit a short packet */
2173         }
2174         goto repeat;
2175
2176 not_complete:
2177         return (1);                     /* not complete */
2178 }
2179
2180 static uint8_t
2181 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
2182 {
2183         uint32_t temp;
2184
2185         /*
2186          * If all packets are transferred we are complete:
2187          */
2188         temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2189
2190         /* check that all packets have been transferred */
2191         if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2192                 DPRINTFN(5, "busy ep=%d\n", td->ep_no);
2193                 goto not_complete;
2194         }
2195         return (0);
2196
2197 not_complete:
2198
2199         /* we only want to know if there is a SETUP packet or free IN packet */
2200
2201         temp = sc->sc_last_rx_status;
2202
2203         if ((td->ep_no == 0) && (temp != 0) &&
2204             (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2205
2206                 if ((temp & GRXSTSRD_PKTSTS_MASK) ==
2207                     GRXSTSRD_STP_DATA ||
2208                     (temp & GRXSTSRD_PKTSTS_MASK) ==
2209                     GRXSTSRD_STP_COMPLETE) {
2210                         DPRINTFN(5, "faking complete\n");
2211                         /*
2212                          * Race condition: We are complete!
2213                          */
2214                         return (0);
2215                 } else {
2216                         /* dump data - wrong direction */
2217                         dwc_otg_common_rx_ack(sc);
2218                 }
2219         }
2220         return (1);                     /* not complete */
2221 }
2222
2223 static void
2224 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer)
2225 {
2226         struct dwc_otg_td *td;
2227         uint8_t toggle;
2228         uint8_t tmr_val;
2229         uint8_t tmr_res;
2230
2231         DPRINTFN(9, "\n");
2232
2233         td = xfer->td_transfer_cache;
2234         if (td == NULL)
2235                 return;
2236
2237         while (1) {
2238                 if ((td->func) (sc, td)) {
2239                         /* operation in progress */
2240                         break;
2241                 }
2242                 if (((void *)td) == xfer->td_transfer_last) {
2243                         goto done;
2244                 }
2245                 if (td->error_any) {
2246                         goto done;
2247                 } else if (td->remainder > 0) {
2248                         /*
2249                          * We had a short transfer. If there is no alternate
2250                          * next, stop processing !
2251                          */
2252                         if (!td->alt_next)
2253                                 goto done;
2254                 }
2255
2256                 /*
2257                  * Fetch the next transfer descriptor and transfer
2258                  * some flags to the next transfer descriptor
2259                  */
2260                 tmr_res = td->tmr_res;
2261                 tmr_val = td->tmr_val;
2262                 toggle = td->toggle;
2263                 td = td->obj_next;
2264                 xfer->td_transfer_cache = td;
2265                 td->toggle = toggle;    /* transfer toggle */
2266                 td->tmr_res = tmr_res;
2267                 td->tmr_val = tmr_val;
2268         }
2269         return;
2270
2271 done:
2272         xfer->td_transfer_cache = NULL;
2273         sc->sc_xfer_complete = 1;
2274 }
2275
2276 static uint8_t
2277 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer)
2278 {
2279         struct dwc_otg_td *td;
2280
2281         DPRINTFN(9, "\n");
2282
2283         td = xfer->td_transfer_cache;
2284         if (td == NULL) {
2285                 /* compute all actual lengths */
2286                 dwc_otg_standard_done(xfer);
2287                 return (1);
2288         }
2289         return (0);
2290 }
2291
2292 static void
2293 dwc_otg_timer(void *_sc)
2294 {
2295         struct dwc_otg_softc *sc = _sc;
2296
2297         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2298
2299         DPRINTF("\n");
2300
2301         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2302
2303         /* increment timer value */
2304         sc->sc_tmr_val++;
2305
2306         /* enable SOF interrupt, which will poll jobs */
2307         dwc_otg_enable_sof_irq(sc);
2308
2309         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2310
2311         if (sc->sc_timer_active) {
2312                 /* restart timer */
2313                 usb_callout_reset(&sc->sc_timer,
2314                     hz / (1000 / DWC_OTG_HOST_TIMER_RATE),
2315                     &dwc_otg_timer, sc);
2316         }
2317 }
2318
2319 static void
2320 dwc_otg_timer_start(struct dwc_otg_softc *sc)
2321 {
2322         if (sc->sc_timer_active != 0)
2323                 return;
2324
2325         sc->sc_timer_active = 1;
2326
2327         /* restart timer */
2328         usb_callout_reset(&sc->sc_timer,
2329             hz / (1000 / DWC_OTG_HOST_TIMER_RATE),
2330             &dwc_otg_timer, sc);
2331 }
2332
2333 static void
2334 dwc_otg_timer_stop(struct dwc_otg_softc *sc)
2335 {
2336         if (sc->sc_timer_active == 0)
2337                 return;
2338
2339         sc->sc_timer_active = 0;
2340
2341         /* stop timer */
2342         usb_callout_stop(&sc->sc_timer);
2343 }
2344
2345 static uint16_t
2346 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo)
2347 {
2348         if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX)
2349                 pinfo->slot_index++;
2350         return (pinfo->slot_index);
2351 }
2352
2353 static uint8_t
2354 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc)
2355 {
2356         TAILQ_HEAD(, usb_xfer) head;
2357         struct usb_xfer *xfer;
2358         struct usb_xfer *xfer_next;
2359         struct dwc_otg_td *td;
2360         uint16_t temp;
2361         uint16_t slot;
2362
2363         temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK;
2364
2365         if (sc->sc_last_frame_num == temp)
2366                 return (0);
2367
2368         sc->sc_last_frame_num = temp;
2369
2370         TAILQ_INIT(&head);
2371
2372         if ((temp & 7) == 0) {
2373
2374                 /* reset the schedule */
2375                 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info));
2376
2377                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2378                         td = xfer->td_transfer_cache;
2379                         if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2380                                 continue;
2381
2382                         /* check for IN direction */
2383                         if ((td->hcchar & HCCHAR_EPDIR_IN) != 0)
2384                                 continue;
2385
2386                         /* execute more frames */
2387                         td->tmr_val = 0;
2388
2389                         sc->sc_needsof = 1;
2390
2391                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2392                                 continue;
2393
2394                         /* compute slot */
2395                         slot = dwc_otg_compute_isoc_rx_tt_slot(
2396                             sc->sc_tt_info + td->tt_index);
2397                         if (slot > 3) {
2398                                 /*
2399                                  * Not enough time to get complete
2400                                  * split executed.
2401                                  */
2402                                 continue;
2403                         }
2404                         /* Delayed start */
2405                         td->tt_start_slot = temp + slot;
2406                         td->tt_scheduled = 1;
2407                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2408                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2409                 }
2410
2411                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2412                         td = xfer->td_transfer_cache;
2413                         if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2414                                 continue;
2415
2416                         /* check for OUT direction */
2417                         if ((td->hcchar & HCCHAR_EPDIR_IN) == 0)
2418                                 continue;
2419
2420                         /* execute more frames */
2421                         td->tmr_val = 0;
2422
2423                         sc->sc_needsof = 1;
2424
2425                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2426                                 continue;
2427
2428                         /* Start ASAP */
2429                         td->tt_start_slot = temp;
2430                         td->tt_scheduled = 1;
2431                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2432                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2433                 }
2434
2435                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2436                         td = xfer->td_transfer_cache;
2437                         if (td == NULL || td->ep_type != UE_INTERRUPT)
2438                                 continue;
2439
2440                         if (td->tt_scheduled != 0) {
2441                                 sc->sc_needsof = 1;
2442                                 continue;
2443                         }
2444
2445                         if (dwc_otg_host_rate_check_interrupt(sc, td))
2446                                 continue;
2447
2448                         if (td->hcsplt == 0) {
2449                                 sc->sc_needsof = 1;
2450                                 td->tt_scheduled = 1;
2451                                 continue;
2452                         }
2453
2454                         /* start ASAP */
2455                         td->tt_start_slot = temp;
2456                         sc->sc_needsof = 1;
2457                         td->tt_scheduled = 1;
2458                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2459                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2460                 }
2461
2462                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2463                         td = xfer->td_transfer_cache;
2464                         if (td == NULL ||
2465                             td->ep_type != UE_CONTROL) {
2466                                 continue;
2467                         }
2468
2469                         sc->sc_needsof = 1;
2470
2471                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2472                                 continue;
2473
2474                         /* start ASAP */
2475                         td->tt_start_slot = temp;
2476                         td->tt_scheduled = 1;
2477                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2478                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2479                 }
2480         }
2481         if ((temp & 7) < 6) {
2482                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2483                         td = xfer->td_transfer_cache;
2484                         if (td == NULL ||
2485                             td->ep_type != UE_BULK) {
2486                                 continue;
2487                         }
2488
2489                         sc->sc_needsof = 1;
2490
2491                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2492                                 continue;
2493
2494                         /* start ASAP */
2495                         td->tt_start_slot = temp;
2496                         td->tt_scheduled = 1;
2497                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2498                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2499                 }
2500         }
2501
2502         /* Put TT transfers in execution order at the end */
2503         TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2504
2505         /* move all TT transfers in front, keeping the current order */
2506         TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2507                 td = xfer->td_transfer_cache;
2508                 if (td == NULL || td->hcsplt == 0)
2509                         continue;
2510                 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2511                 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2512         }
2513         TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry);
2514         TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2515
2516         /* put non-TT BULK transfers last */
2517         TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2518                 td = xfer->td_transfer_cache;
2519                 if (td == NULL || td->hcsplt != 0 || td->ep_type != UE_BULK)
2520                         continue;
2521                 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2522                 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2523         }
2524         TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2525
2526         if ((temp & 7) == 0) {
2527
2528                 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n",
2529                     (int)temp, (int)sc->sc_needsof);
2530
2531                 /* update SOF IRQ mask */
2532                 if (sc->sc_irq_mask & GINTMSK_SOFMSK) {
2533                         if (sc->sc_needsof == 0) {
2534                                 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2535                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2536                         }
2537                 } else {
2538                         if (sc->sc_needsof != 0) {
2539                                 sc->sc_irq_mask |= GINTMSK_SOFMSK;
2540                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2541                         }
2542                 }
2543
2544                 /* clear need SOF flag */
2545                 sc->sc_needsof = 0;
2546         }
2547         return (1);
2548 }
2549
2550 static void
2551 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc)
2552 {
2553         struct usb_xfer *xfer;
2554         uint32_t temp;
2555         uint8_t got_rx_status;
2556         uint8_t x;
2557
2558 repeat:
2559         /* get all channel interrupts */
2560         for (x = 0; x != sc->sc_host_ch_max; x++) {
2561                 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
2562                 if (temp != 0) {
2563                         DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp);
2564                         temp &= ~HCINT_SOFTWARE_ONLY;
2565                         sc->sc_chan_state[x].hcint |= temp;
2566                 }
2567         }
2568
2569         if (sc->sc_last_rx_status == 0) {
2570
2571                 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2572                 if (temp & GINTSTS_RXFLVL) {
2573                         /* pop current status */
2574                         sc->sc_last_rx_status =
2575                             DWC_OTG_READ_4(sc, DOTG_GRXSTSPD);
2576                 }
2577
2578                 if (sc->sc_last_rx_status != 0) {
2579
2580                         uint8_t ep_no;
2581
2582                         temp = sc->sc_last_rx_status &
2583                             GRXSTSRD_PKTSTS_MASK;
2584
2585                         /* non-data messages we simply skip */
2586                         if (temp != GRXSTSRD_STP_DATA &&
2587                             temp != GRXSTSRD_STP_COMPLETE &&
2588                             temp != GRXSTSRD_OUT_DATA) {
2589                                 /* check for halted channel */
2590                                 if (temp == GRXSTSRH_HALTED) {
2591                                         ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status);
2592                                         sc->sc_chan_state[ep_no].wait_halted = 0;
2593                                         DPRINTFN(5, "channel halt complete ch=%u\n", ep_no);
2594                                 }
2595                                 dwc_otg_common_rx_ack(sc);
2596                                 goto repeat;
2597                         }
2598
2599                         temp = GRXSTSRD_BCNT_GET(
2600                             sc->sc_last_rx_status);
2601                         ep_no = GRXSTSRD_CHNUM_GET(
2602                             sc->sc_last_rx_status);
2603
2604                         /* receive data, if any */
2605                         if (temp != 0) {
2606                                 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no);
2607                                 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
2608                                     DOTG_DFIFO(ep_no),
2609                                     sc->sc_rx_bounce_buffer, (temp + 3) / 4);
2610                         }
2611
2612                         /* check if we should dump the data */
2613                         if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2614                                 dwc_otg_common_rx_ack(sc);
2615                                 goto repeat;
2616                         }
2617
2618                         got_rx_status = 1;
2619
2620                         DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n",
2621                             sc->sc_last_rx_status, ep_no,
2622                             (sc->sc_last_rx_status >> 15) & 3,
2623                             GRXSTSRD_BCNT_GET(sc->sc_last_rx_status),
2624                             (sc->sc_last_rx_status >> 17) & 15);
2625                 } else {
2626                         got_rx_status = 0;
2627                 }
2628         } else {
2629                 uint8_t ep_no;
2630
2631                 ep_no = GRXSTSRD_CHNUM_GET(
2632                     sc->sc_last_rx_status);
2633
2634                 /* check if we should dump the data */
2635                 if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2636                         dwc_otg_common_rx_ack(sc);
2637                         goto repeat;
2638                 }
2639
2640                 got_rx_status = 1;
2641         }
2642
2643         /* execute FIFOs */
2644         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
2645                 dwc_otg_xfer_do_fifo(sc, xfer);
2646
2647         if (got_rx_status) {
2648                 /* check if data was consumed */
2649                 if (sc->sc_last_rx_status == 0)
2650                         goto repeat;
2651
2652                 /* disable RX FIFO level interrupt */
2653                 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK;
2654                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2655         }
2656
2657         if (sc->sc_flags.status_device_mode == 0 && sc->sc_xfer_complete == 0) {
2658                 /* update host transfer schedule, so that new transfers can be issued */
2659                 if (dwc_otg_update_host_transfer_schedule_locked(sc))
2660                         goto repeat;
2661         }
2662 }
2663
2664 static void
2665 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc)
2666 {
2667         struct usb_xfer *xfer;
2668 repeat:
2669         /* scan for completion events */
2670         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2671                 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
2672                         goto repeat;
2673         }
2674 }
2675
2676 static void
2677 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on)
2678 {
2679         DPRINTFN(5, "vbus = %u\n", is_on);
2680
2681         /*
2682          * If the USB host mode is forced, then assume VBUS is always
2683          * present else rely on the input to this function:
2684          */
2685         if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) {
2686
2687                 if (!sc->sc_flags.status_vbus) {
2688                         sc->sc_flags.status_vbus = 1;
2689
2690                         /* complete root HUB interrupt endpoint */
2691
2692                         dwc_otg_root_intr(sc);
2693                 }
2694         } else {
2695                 if (sc->sc_flags.status_vbus) {
2696                         sc->sc_flags.status_vbus = 0;
2697                         sc->sc_flags.status_bus_reset = 0;
2698                         sc->sc_flags.status_suspend = 0;
2699                         sc->sc_flags.change_suspend = 0;
2700                         sc->sc_flags.change_connect = 1;
2701
2702                         /* complete root HUB interrupt endpoint */
2703
2704                         dwc_otg_root_intr(sc);
2705                 }
2706         }
2707 }
2708
2709 int
2710 dwc_otg_filter_interrupt(void *arg)
2711 {
2712         struct dwc_otg_softc *sc = arg;
2713         int retval = FILTER_HANDLED;
2714         uint32_t status;
2715
2716         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2717
2718         /* read and clear interrupt status */
2719         status = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2720
2721         /* clear interrupts we are handling here */
2722         DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ);
2723
2724         /* check for USB state change interrupts */
2725         if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0)
2726                 retval = FILTER_SCHEDULE_THREAD;
2727
2728         /* clear FIFO empty interrupts */
2729         if (status & sc->sc_irq_mask &
2730             (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) {
2731                 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
2732                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2733         }
2734         /* clear all IN endpoint interrupts */
2735         if (status & GINTSTS_IEPINT) {
2736                 uint32_t temp;
2737                 uint8_t x;
2738
2739                 for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
2740                         temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x));
2741                         if (temp & DIEPMSK_XFERCOMPLMSK) {
2742                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x),
2743                                     DIEPMSK_XFERCOMPLMSK);
2744                         }
2745                 }
2746         }
2747
2748         /* poll FIFOs, if any */
2749         dwc_otg_interrupt_poll_locked(sc);
2750
2751         if (sc->sc_xfer_complete != 0)
2752                 retval = FILTER_SCHEDULE_THREAD;
2753
2754         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2755
2756         return (retval);
2757 }
2758
2759 void
2760 dwc_otg_interrupt(void *arg)
2761 {
2762         struct dwc_otg_softc *sc = arg;
2763         uint32_t status;
2764
2765         USB_BUS_LOCK(&sc->sc_bus);
2766         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2767
2768         /* read and clear interrupt status */
2769         status = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2770
2771         /* clear interrupts we are handling here */
2772         DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ);
2773
2774         DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n",
2775             status, DWC_OTG_READ_4(sc, DOTG_HAINT),
2776             DWC_OTG_READ_4(sc, DOTG_HFNUM));
2777
2778         if (status & GINTSTS_USBRST) {
2779
2780                 /* set correct state */
2781                 sc->sc_flags.status_device_mode = 1;
2782                 sc->sc_flags.status_bus_reset = 0;
2783                 sc->sc_flags.status_suspend = 0;
2784                 sc->sc_flags.change_suspend = 0;
2785                 sc->sc_flags.change_connect = 1;
2786
2787                 /* Disable SOF interrupt */
2788                 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2789                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2790
2791                 /* complete root HUB interrupt endpoint */
2792                 dwc_otg_root_intr(sc);
2793         }
2794
2795         /* check for any bus state change interrupts */
2796         if (status & GINTSTS_ENUMDONE) {
2797
2798                 uint32_t temp;
2799
2800                 DPRINTFN(5, "end of reset\n");
2801
2802                 /* set correct state */
2803                 sc->sc_flags.status_device_mode = 1;
2804                 sc->sc_flags.status_bus_reset = 1;
2805                 sc->sc_flags.status_suspend = 0;
2806                 sc->sc_flags.change_suspend = 0;
2807                 sc->sc_flags.change_connect = 1;
2808                 sc->sc_flags.status_low_speed = 0;
2809                 sc->sc_flags.port_enabled = 1;
2810
2811                 /* reset FIFOs */
2812                 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE);
2813
2814                 /* reset function address */
2815                 dwc_otg_set_address(sc, 0);
2816
2817                 /* figure out enumeration speed */
2818                 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
2819                 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI)
2820                         sc->sc_flags.status_high_speed = 1;
2821                 else
2822                         sc->sc_flags.status_high_speed = 0;
2823
2824                 /*
2825                  * Disable resume and SOF interrupt, and enable
2826                  * suspend and RX frame interrupt:
2827                  */
2828                 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK);
2829                 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
2830                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2831
2832                 /* complete root HUB interrupt endpoint */
2833                 dwc_otg_root_intr(sc);
2834         }
2835
2836         if (status & GINTSTS_PRTINT) {
2837                 uint32_t hprt;
2838
2839                 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT);
2840
2841                 /* clear change bits */
2842                 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & (
2843                     HPRT_PRTPWR | HPRT_PRTENCHNG |
2844                     HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) |
2845                     sc->sc_hprt_val);
2846
2847                 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt);
2848
2849                 sc->sc_flags.status_device_mode = 0;
2850
2851                 if (hprt & HPRT_PRTCONNSTS)
2852                         sc->sc_flags.status_bus_reset = 1;
2853                 else
2854                         sc->sc_flags.status_bus_reset = 0;
2855
2856                 if (hprt & HPRT_PRTENCHNG)
2857                         sc->sc_flags.change_enabled = 1;
2858
2859                 if (hprt & HPRT_PRTENA)
2860                         sc->sc_flags.port_enabled = 1;
2861                 else
2862                         sc->sc_flags.port_enabled = 0;
2863
2864                 if (hprt & HPRT_PRTOVRCURRCHNG)
2865                         sc->sc_flags.change_over_current = 1;
2866
2867                 if (hprt & HPRT_PRTOVRCURRACT)
2868                         sc->sc_flags.port_over_current = 1;
2869                 else
2870                         sc->sc_flags.port_over_current = 0;
2871
2872                 if (hprt & HPRT_PRTPWR)
2873                         sc->sc_flags.port_powered = 1;
2874                 else
2875                         sc->sc_flags.port_powered = 0;
2876
2877                 if (((hprt & HPRT_PRTSPD_MASK)
2878                     >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW)
2879                         sc->sc_flags.status_low_speed = 1;
2880                 else
2881                         sc->sc_flags.status_low_speed = 0;
2882
2883                 if (((hprt & HPRT_PRTSPD_MASK)
2884                     >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH)
2885                         sc->sc_flags.status_high_speed = 1;
2886                 else
2887                         sc->sc_flags.status_high_speed = 0;
2888
2889                 if (hprt & HPRT_PRTCONNDET)
2890                         sc->sc_flags.change_connect = 1;
2891
2892                 if (hprt & HPRT_PRTSUSP)
2893                         dwc_otg_suspend_irq(sc);
2894                 else
2895                         dwc_otg_resume_irq(sc);
2896
2897                 /* complete root HUB interrupt endpoint */
2898                 dwc_otg_root_intr(sc);
2899
2900                 /* update host frame interval */
2901                 dwc_otg_update_host_frame_interval(sc);
2902         }
2903
2904         /*
2905          * If resume and suspend is set at the same time we interpret
2906          * that like RESUME. Resume is set when there is at least 3
2907          * milliseconds of inactivity on the USB BUS.
2908          */
2909         if (status & GINTSTS_WKUPINT) {
2910
2911                 DPRINTFN(5, "resume interrupt\n");
2912
2913                 dwc_otg_resume_irq(sc);
2914
2915         } else if (status & GINTSTS_USBSUSP) {
2916
2917                 DPRINTFN(5, "suspend interrupt\n");
2918
2919                 dwc_otg_suspend_irq(sc);
2920         }
2921         /* check VBUS */
2922         if (status & (GINTSTS_USBSUSP |
2923             GINTSTS_USBRST |
2924             GINTMSK_OTGINTMSK |
2925             GINTSTS_SESSREQINT)) {
2926                 uint32_t temp;
2927
2928                 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
2929
2930                 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp);
2931
2932                 dwc_otg_vbus_interrupt(sc,
2933                     (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
2934         }
2935
2936         if (sc->sc_xfer_complete != 0) {
2937                 sc->sc_xfer_complete = 0;
2938
2939                 /* complete FIFOs, if any */
2940                 dwc_otg_interrupt_complete_locked(sc);
2941
2942                 if (sc->sc_flags.status_device_mode == 0) {
2943                         /* update host transfer schedule, so that new transfers can be issued */
2944                         if (dwc_otg_update_host_transfer_schedule_locked(sc))
2945                                 dwc_otg_interrupt_poll_locked(sc);
2946                 }
2947         }
2948         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2949         USB_BUS_UNLOCK(&sc->sc_bus);
2950 }
2951
2952 static void
2953 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp)
2954 {
2955         struct dwc_otg_td *td;
2956
2957         /* get current Transfer Descriptor */
2958         td = temp->td_next;
2959         temp->td = td;
2960
2961         /* prepare for next TD */
2962         temp->td_next = td->obj_next;
2963
2964         /* fill out the Transfer Descriptor */
2965         td->func = temp->func;
2966         td->pc = temp->pc;
2967         td->offset = temp->offset;
2968         td->remainder = temp->len;
2969         td->tx_bytes = 0;
2970         td->error_any = 0;
2971         td->error_stall = 0;
2972         td->npkt = 0;
2973         td->did_stall = temp->did_stall;
2974         td->short_pkt = temp->short_pkt;
2975         td->alt_next = temp->setup_alt_next;
2976         td->set_toggle = 0;
2977         td->got_short = 0;
2978         td->did_nak = 0;
2979         td->channel = DWC_OTG_MAX_CHANNELS;
2980         td->state = 0;
2981         td->errcnt = 0;
2982         td->tt_scheduled = 0;
2983         td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
2984 }
2985
2986 static void
2987 dwc_otg_setup_standard_chain(struct usb_xfer *xfer)
2988 {
2989         struct dwc_otg_std_temp temp;
2990         struct dwc_otg_td *td;
2991         uint32_t x;
2992         uint8_t need_sync;
2993         uint8_t is_host;
2994
2995         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2996             xfer->address, UE_GET_ADDR(xfer->endpointno),
2997             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2998
2999         temp.max_frame_size = xfer->max_frame_size;
3000
3001         td = xfer->td_start[0];
3002         xfer->td_transfer_first = td;
3003         xfer->td_transfer_cache = td;
3004
3005         /* setup temp */
3006
3007         temp.pc = NULL;
3008         temp.td = NULL;
3009         temp.td_next = xfer->td_start[0];
3010         temp.offset = 0;
3011         temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
3012             xfer->flags_int.isochronous_xfr;
3013         temp.did_stall = !xfer->flags_int.control_stall;
3014
3015         is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
3016
3017         /* check if we should prepend a setup message */
3018
3019         if (xfer->flags_int.control_xfr) {
3020                 if (xfer->flags_int.control_hdr) {
3021
3022                         if (is_host)
3023                                 temp.func = &dwc_otg_host_setup_tx;
3024                         else
3025                                 temp.func = &dwc_otg_setup_rx;
3026
3027                         temp.len = xfer->frlengths[0];
3028                         temp.pc = xfer->frbuffers + 0;
3029                         temp.short_pkt = temp.len ? 1 : 0;
3030
3031                         /* check for last frame */
3032                         if (xfer->nframes == 1) {
3033                                 /* no STATUS stage yet, SETUP is last */
3034                                 if (xfer->flags_int.control_act)
3035                                         temp.setup_alt_next = 0;
3036                         }
3037
3038                         dwc_otg_setup_standard_chain_sub(&temp);
3039                 }
3040                 x = 1;
3041         } else {
3042                 x = 0;
3043         }
3044
3045         if (x != xfer->nframes) {
3046                 if (xfer->endpointno & UE_DIR_IN) {
3047                         if (is_host) {
3048                                 temp.func = &dwc_otg_host_data_rx;
3049                                 need_sync = 0;
3050                         } else {
3051                                 temp.func = &dwc_otg_data_tx;
3052                                 need_sync = 1;
3053                         }
3054                 } else {
3055                         if (is_host) {
3056                                 temp.func = &dwc_otg_host_data_tx;
3057                                 need_sync = 0;
3058                         } else {
3059                                 temp.func = &dwc_otg_data_rx;
3060                                 need_sync = 0;
3061                         }
3062                 }
3063
3064                 /* setup "pc" pointer */
3065                 temp.pc = xfer->frbuffers + x;
3066         } else {
3067                 need_sync = 0;
3068         }
3069         while (x != xfer->nframes) {
3070
3071                 /* DATA0 / DATA1 message */
3072
3073                 temp.len = xfer->frlengths[x];
3074
3075                 x++;
3076
3077                 if (x == xfer->nframes) {
3078                         if (xfer->flags_int.control_xfr) {
3079                                 if (xfer->flags_int.control_act) {
3080                                         temp.setup_alt_next = 0;
3081                                 }
3082                         } else {
3083                                 temp.setup_alt_next = 0;
3084                         }
3085                 }
3086                 if (temp.len == 0) {
3087
3088                         /* make sure that we send an USB packet */
3089
3090                         temp.short_pkt = 0;
3091
3092                 } else {
3093
3094                         /* regular data transfer */
3095
3096                         temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
3097                 }
3098
3099                 dwc_otg_setup_standard_chain_sub(&temp);
3100
3101                 if (xfer->flags_int.isochronous_xfr) {
3102                         temp.offset += temp.len;
3103                 } else {
3104                         /* get next Page Cache pointer */
3105                         temp.pc = xfer->frbuffers + x;
3106                 }
3107         }
3108
3109         if (xfer->flags_int.control_xfr) {
3110
3111                 /* always setup a valid "pc" pointer for status and sync */
3112                 temp.pc = xfer->frbuffers + 0;
3113                 temp.len = 0;
3114                 temp.short_pkt = 0;
3115                 temp.setup_alt_next = 0;
3116
3117                 /* check if we need to sync */
3118                 if (need_sync) {
3119                         /* we need a SYNC point after TX */
3120                         temp.func = &dwc_otg_data_tx_sync;
3121                         dwc_otg_setup_standard_chain_sub(&temp);
3122                 }
3123
3124                 /* check if we should append a status stage */
3125                 if (!xfer->flags_int.control_act) {
3126
3127                         /*
3128                          * Send a DATA1 message and invert the current
3129                          * endpoint direction.
3130                          */
3131                         if (xfer->endpointno & UE_DIR_IN) {
3132                                 if (is_host) {
3133                                         temp.func = &dwc_otg_host_data_tx;
3134                                         need_sync = 0;
3135                                 } else {
3136                                         temp.func = &dwc_otg_data_rx;
3137                                         need_sync = 0;
3138                                 }
3139                         } else {
3140                                 if (is_host) {
3141                                         temp.func = &dwc_otg_host_data_rx;
3142                                         need_sync = 0;
3143                                 } else {
3144                                         temp.func = &dwc_otg_data_tx;
3145                                         need_sync = 1;
3146                                 }
3147                         }
3148
3149                         dwc_otg_setup_standard_chain_sub(&temp);
3150
3151                         /* data toggle should be DATA1 */
3152                         td = temp.td;
3153                         td->set_toggle = 1;
3154
3155                         if (need_sync) {
3156                                 /* we need a SYNC point after TX */
3157                                 temp.func = &dwc_otg_data_tx_sync;
3158                                 dwc_otg_setup_standard_chain_sub(&temp);
3159                         }
3160                 }
3161         } else {
3162                 /* check if we need to sync */
3163                 if (need_sync) {
3164
3165                         temp.pc = xfer->frbuffers + 0;
3166                         temp.len = 0;
3167                         temp.short_pkt = 0;
3168                         temp.setup_alt_next = 0;
3169
3170                         /* we need a SYNC point after TX */
3171                         temp.func = &dwc_otg_data_tx_sync;
3172                         dwc_otg_setup_standard_chain_sub(&temp);
3173                 }
3174         }
3175
3176         /* must have at least one frame! */
3177         td = temp.td;
3178         xfer->td_transfer_last = td;
3179
3180         if (is_host) {
3181
3182                 struct dwc_otg_softc *sc;
3183                 uint32_t hcchar;
3184                 uint32_t hcsplt;
3185
3186                 sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3187
3188                 /* get first again */
3189                 td = xfer->td_transfer_first;
3190                 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
3191
3192                 hcchar =
3193                         (xfer->address << HCCHAR_DEVADDR_SHIFT) |
3194                         ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) |
3195                         (xfer->max_packet_size << HCCHAR_MPS_SHIFT) |
3196                         HCCHAR_CHENA;
3197
3198                 /*
3199                  * We are not always able to meet the timing
3200                  * requirements of the USB interrupt endpoint's
3201                  * complete split token, when doing transfers going
3202                  * via a transaction translator. Use the CONTROL
3203                  * transfer type instead of the INTERRUPT transfer
3204                  * type in general, as a means to workaround
3205                  * that. This trick should work for both FULL and LOW
3206                  * speed USB traffic going through a TT. For non-TT
3207                  * traffic it works aswell. The reason for using
3208                  * CONTROL type instead of BULK is that some TTs might
3209                  * reject LOW speed BULK traffic.
3210                  */
3211                 if (td->ep_type == UE_INTERRUPT)
3212                         hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT);
3213                 else
3214                         hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT);
3215
3216                 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW)
3217                         hcchar |= HCCHAR_LSPDDEV;
3218                 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
3219                         hcchar |= HCCHAR_EPDIR_IN;
3220
3221                 switch (xfer->xroot->udev->speed) {
3222                 case USB_SPEED_FULL:
3223                 case USB_SPEED_LOW:
3224                         /* check if root HUB port is running High Speed */
3225                         if (xfer->xroot->udev->parent_hs_hub != NULL) {
3226                                 hcsplt = HCSPLT_SPLTENA |
3227                                     (xfer->xroot->udev->hs_port_no <<
3228                                     HCSPLT_PRTADDR_SHIFT) |
3229                                     (xfer->xroot->udev->hs_hub_addr <<
3230                                     HCSPLT_HUBADDR_SHIFT);
3231                         } else {
3232                                 hcsplt = 0;
3233                         }
3234                         if (td->ep_type == UE_INTERRUPT) {
3235                                 uint32_t ival;
3236                                 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3237                                 if (ival == 0)
3238                                         ival = 1;
3239                                 else if (ival > 127)
3240                                         ival = 127;
3241                                 td->tmr_val = sc->sc_tmr_val + ival;
3242                                 td->tmr_res = ival;
3243                         } else if (td->ep_type == UE_ISOCHRONOUS) {
3244                                 td->tmr_val = 0;
3245                                 td->tmr_res = 1;
3246                         } else {
3247                                 td->tmr_val = 0;
3248                                 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3249                         }
3250                         break;
3251                 case USB_SPEED_HIGH:
3252                         hcsplt = 0;
3253                         if (td->ep_type == UE_INTERRUPT) {
3254                                 uint32_t ival;
3255 #if 0
3256                                 hcchar |= ((xfer->max_packet_count & 3)
3257                                     << HCCHAR_MC_SHIFT);
3258 #endif
3259                                 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3260                                 if (ival == 0)
3261                                         ival = 1;
3262                                 else if (ival > 127)
3263                                         ival = 127;
3264                                 td->tmr_val = sc->sc_tmr_val + ival;
3265                                 td->tmr_res = ival;
3266                         } else if (td->ep_type == UE_ISOCHRONOUS) {
3267                                 hcchar |= ((xfer->max_packet_count & 3)
3268                                     << HCCHAR_MC_SHIFT);
3269                                 td->tmr_val = 0;
3270                                 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer);
3271                         } else {
3272                                 td->tmr_val = 0;
3273                                 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3274                         }
3275                         break;
3276                 default:
3277                         hcsplt = 0;
3278                         td->tmr_val = 0;
3279                         td->tmr_res = 0;
3280                         break;
3281                 }
3282
3283                 /* store configuration in all TD's */
3284                 while (1) {
3285                         td->hcchar = hcchar;
3286                         td->hcsplt = hcsplt;
3287
3288                         if (((void *)td) == xfer->td_transfer_last)
3289                                 break;
3290
3291                         td = td->obj_next;
3292                 }
3293         }
3294 }
3295
3296 static void
3297 dwc_otg_timeout(void *arg)
3298 {
3299         struct usb_xfer *xfer = arg;
3300
3301         DPRINTF("xfer=%p\n", xfer);
3302
3303         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
3304
3305         /* transfer is transferred */
3306         dwc_otg_device_done(xfer, USB_ERR_TIMEOUT);
3307 }
3308
3309 static void
3310 dwc_otg_start_standard_chain(struct usb_xfer *xfer)
3311 {
3312         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3313
3314         DPRINTFN(9, "\n");
3315
3316         /*
3317          * Poll one time in device mode, which will turn on the
3318          * endpoint interrupts. Else wait for SOF interrupt in host
3319          * mode.
3320          */
3321         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3322
3323         if (sc->sc_flags.status_device_mode != 0) {
3324                 dwc_otg_xfer_do_fifo(sc, xfer);
3325                 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
3326                         goto done;
3327         }
3328
3329         /* put transfer on interrupt queue */
3330         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3331
3332         /* start timeout, if any */
3333         if (xfer->timeout != 0) {
3334                 usbd_transfer_timeout_ms(xfer,
3335                     &dwc_otg_timeout, xfer->timeout);
3336         }
3337
3338         if (sc->sc_flags.status_device_mode != 0)
3339                 goto done;
3340
3341         /* enable SOF interrupt, if any */
3342         dwc_otg_enable_sof_irq(sc);
3343 done:
3344         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3345 }
3346
3347 static void
3348 dwc_otg_root_intr(struct dwc_otg_softc *sc)
3349 {
3350         DPRINTFN(9, "\n");
3351
3352         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3353
3354         /* set port bit */
3355         sc->sc_hub_idata[0] = 0x02;     /* we only have one port */
3356
3357         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3358             sizeof(sc->sc_hub_idata));
3359 }
3360
3361 static usb_error_t
3362 dwc_otg_standard_done_sub(struct usb_xfer *xfer)
3363 {
3364         struct dwc_otg_td *td;
3365         uint32_t len;
3366         usb_error_t error;
3367
3368         DPRINTFN(9, "\n");
3369
3370         td = xfer->td_transfer_cache;
3371
3372         do {
3373                 len = td->remainder;
3374
3375                 /* store last data toggle */
3376                 xfer->endpoint->toggle_next = td->toggle;
3377
3378                 if (xfer->aframes != xfer->nframes) {
3379                         /*
3380                          * Verify the length and subtract
3381                          * the remainder from "frlengths[]":
3382                          */
3383                         if (len > xfer->frlengths[xfer->aframes]) {
3384                                 td->error_any = 1;
3385                         } else {
3386                                 xfer->frlengths[xfer->aframes] -= len;
3387                         }
3388                 }
3389                 /* Check for transfer error */
3390                 if (td->error_any) {
3391                         /* the transfer is finished */
3392                         error = (td->error_stall ?
3393                             USB_ERR_STALLED : USB_ERR_IOERROR);
3394                         td = NULL;
3395                         break;
3396                 }
3397                 /* Check for short transfer */
3398                 if (len > 0) {
3399                         if (xfer->flags_int.short_frames_ok ||
3400                             xfer->flags_int.isochronous_xfr) {
3401                                 /* follow alt next */
3402                                 if (td->alt_next) {
3403                                         td = td->obj_next;
3404                                 } else {
3405                                         td = NULL;
3406                                 }
3407                         } else {
3408                                 /* the transfer is finished */
3409                                 td = NULL;
3410                         }
3411                         error = 0;
3412                         break;
3413                 }
3414                 td = td->obj_next;
3415
3416                 /* this USB frame is complete */
3417                 error = 0;
3418                 break;
3419
3420         } while (0);
3421
3422         /* update transfer cache */
3423
3424         xfer->td_transfer_cache = td;
3425
3426         return (error);
3427 }
3428
3429 static void
3430 dwc_otg_standard_done(struct usb_xfer *xfer)
3431 {
3432         usb_error_t err = 0;
3433
3434         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
3435             xfer, xfer->endpoint);
3436
3437         /* reset scanner */
3438
3439         xfer->td_transfer_cache = xfer->td_transfer_first;
3440
3441         if (xfer->flags_int.control_xfr) {
3442
3443                 if (xfer->flags_int.control_hdr) {
3444
3445                         err = dwc_otg_standard_done_sub(xfer);
3446                 }
3447                 xfer->aframes = 1;
3448
3449                 if (xfer->td_transfer_cache == NULL) {
3450                         goto done;
3451                 }
3452         }
3453         while (xfer->aframes != xfer->nframes) {
3454
3455                 err = dwc_otg_standard_done_sub(xfer);
3456                 xfer->aframes++;
3457
3458                 if (xfer->td_transfer_cache == NULL) {
3459                         goto done;
3460                 }
3461         }
3462
3463         if (xfer->flags_int.control_xfr &&
3464             !xfer->flags_int.control_act) {
3465
3466                 err = dwc_otg_standard_done_sub(xfer);
3467         }
3468 done:
3469         dwc_otg_device_done(xfer, err);
3470 }
3471
3472 /*------------------------------------------------------------------------*
3473  *      dwc_otg_device_done
3474  *
3475  * NOTE: this function can be called more than one time on the
3476  * same USB transfer!
3477  *------------------------------------------------------------------------*/
3478 static void
3479 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
3480 {
3481         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3482
3483         DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
3484             xfer, xfer->endpoint, error);
3485
3486         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3487
3488         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
3489                 /* Interrupts are cleared by the interrupt handler */
3490         } else {
3491                 struct dwc_otg_td *td;
3492
3493                 td = xfer->td_transfer_cache;
3494                 if (td != NULL)
3495                         dwc_otg_host_channel_free(sc, td);
3496         }
3497         /* dequeue transfer and start next transfer */
3498         usbd_transfer_done(xfer, error);
3499
3500         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3501 }
3502
3503 static void
3504 dwc_otg_xfer_stall(struct usb_xfer *xfer)
3505 {
3506         dwc_otg_device_done(xfer, USB_ERR_STALLED);
3507 }
3508
3509 static void
3510 dwc_otg_set_stall(struct usb_device *udev,
3511     struct usb_endpoint *ep, uint8_t *did_stall)
3512 {
3513         struct dwc_otg_softc *sc;
3514         uint32_t temp;
3515         uint32_t reg;
3516         uint8_t ep_no;
3517
3518         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3519
3520         /* check mode */
3521         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3522                 /* not supported */
3523                 return;
3524         }
3525
3526         sc = DWC_OTG_BUS2SC(udev->bus);
3527
3528         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3529
3530         /* get endpoint address */
3531         ep_no = ep->edesc->bEndpointAddress;
3532
3533         DPRINTFN(5, "endpoint=0x%x\n", ep_no);
3534
3535         if (ep_no & UE_DIR_IN) {
3536                 reg = DOTG_DIEPCTL(ep_no & UE_ADDR);
3537                 temp = sc->sc_in_ctl[ep_no & UE_ADDR];
3538         } else {
3539                 reg = DOTG_DOEPCTL(ep_no & UE_ADDR);
3540                 temp = sc->sc_out_ctl[ep_no & UE_ADDR];
3541         }
3542
3543         /* disable and stall endpoint */
3544         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3545         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL);
3546
3547         /* clear active OUT ep */
3548         if (!(ep_no & UE_DIR_IN)) {
3549
3550                 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR));
3551
3552                 if (sc->sc_last_rx_status != 0 &&
3553                     (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET(
3554                     sc->sc_last_rx_status)) {
3555                         /* dump data */
3556                         dwc_otg_common_rx_ack(sc);
3557                         /* poll interrupt */
3558                         dwc_otg_interrupt_poll_locked(sc);
3559                         dwc_otg_interrupt_complete_locked(sc);
3560                 }
3561         }
3562         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3563 }
3564
3565 static void
3566 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps,
3567     uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
3568 {
3569         uint32_t reg;
3570         uint32_t temp;
3571
3572         if (ep_type == UE_CONTROL) {
3573                 /* clearing stall is not needed */
3574                 return;
3575         }
3576
3577         if (ep_dir) {
3578                 reg = DOTG_DIEPCTL(ep_no);
3579         } else {
3580                 reg = DOTG_DOEPCTL(ep_no);
3581                 sc->sc_active_rx_ep |= (1U << ep_no);
3582         }
3583
3584         /* round up and mask away the multiplier count */
3585         mps = (mps + 3) & 0x7FC;
3586
3587         if (ep_type == UE_BULK) {
3588                 temp = DIEPCTL_EPTYPE_SET(
3589                     DIEPCTL_EPTYPE_BULK) |
3590                     DIEPCTL_USBACTEP;
3591         } else if (ep_type == UE_INTERRUPT) {
3592                 temp = DIEPCTL_EPTYPE_SET(
3593                     DIEPCTL_EPTYPE_INTERRUPT) |
3594                     DIEPCTL_USBACTEP;
3595         } else {
3596                 temp = DIEPCTL_EPTYPE_SET(
3597                     DIEPCTL_EPTYPE_ISOC) |
3598                     DIEPCTL_USBACTEP;
3599         }
3600
3601         temp |= DIEPCTL_MPS_SET(mps);
3602         temp |= DIEPCTL_TXFNUM_SET(ep_no);
3603
3604         if (ep_dir)
3605                 sc->sc_in_ctl[ep_no] = temp;
3606         else
3607                 sc->sc_out_ctl[ep_no] = temp;
3608
3609         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3610         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID);
3611         DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK);
3612
3613         /* we only reset the transmit FIFO */
3614         if (ep_dir) {
3615                 dwc_otg_tx_fifo_reset(sc,
3616                     GRSTCTL_TXFIFO(ep_no) |
3617                     GRSTCTL_TXFFLSH);
3618
3619                 DWC_OTG_WRITE_4(sc,
3620                     DOTG_DIEPTSIZ(ep_no), 0);
3621         }
3622
3623         /* poll interrupt */
3624         dwc_otg_interrupt_poll_locked(sc);
3625         dwc_otg_interrupt_complete_locked(sc);
3626 }
3627
3628 static void
3629 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3630 {
3631         struct dwc_otg_softc *sc;
3632         struct usb_endpoint_descriptor *ed;
3633
3634         DPRINTFN(5, "endpoint=%p\n", ep);
3635
3636         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3637
3638         /* check mode */
3639         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3640                 /* not supported */
3641                 return;
3642         }
3643         /* get softc */
3644         sc = DWC_OTG_BUS2SC(udev->bus);
3645
3646         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3647
3648         /* get endpoint descriptor */
3649         ed = ep->edesc;
3650
3651         /* reset endpoint */
3652         dwc_otg_clear_stall_sub_locked(sc,
3653             UGETW(ed->wMaxPacketSize),
3654             (ed->bEndpointAddress & UE_ADDR),
3655             (ed->bmAttributes & UE_XFERTYPE),
3656             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3657
3658         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3659 }
3660
3661 static void
3662 dwc_otg_device_state_change(struct usb_device *udev)
3663 {
3664         struct dwc_otg_softc *sc;
3665         uint8_t x;
3666
3667         /* check mode */
3668         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3669                 /* not supported */
3670                 return;
3671         }
3672
3673         /* get softc */
3674         sc = DWC_OTG_BUS2SC(udev->bus);
3675
3676         /* deactivate all other endpoint but the control endpoint */
3677         if (udev->state == USB_STATE_CONFIGURED ||
3678             udev->state == USB_STATE_ADDRESSED) {
3679
3680                 USB_BUS_LOCK(&sc->sc_bus);
3681
3682                 for (x = 1; x != sc->sc_dev_ep_max; x++) {
3683
3684                         if (x < sc->sc_dev_in_ep_max) {
3685                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x),
3686                                     DIEPCTL_EPDIS);
3687                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0);
3688                         }
3689
3690                         DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x),
3691                             DOEPCTL_EPDIS);
3692                         DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0);
3693                 }
3694                 USB_BUS_UNLOCK(&sc->sc_bus);
3695         }
3696 }
3697
3698 int
3699 dwc_otg_init(struct dwc_otg_softc *sc)
3700 {
3701         uint32_t temp;
3702
3703         DPRINTF("start\n");
3704
3705         /* set up the bus structure */
3706         sc->sc_bus.usbrev = USB_REV_2_0;
3707         sc->sc_bus.methods = &dwc_otg_bus_methods;
3708
3709         usb_callout_init_mtx(&sc->sc_timer,
3710             &sc->sc_bus.bus_mtx, 0);
3711
3712         USB_BUS_LOCK(&sc->sc_bus);
3713
3714         /* turn on clocks */
3715         dwc_otg_clocks_on(sc);
3716
3717         temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID);
3718         DPRINTF("Version = 0x%08x\n", temp);
3719
3720         /* disconnect */
3721         DWC_OTG_WRITE_4(sc, DOTG_DCTL,
3722             DCTL_SFTDISCON);
3723
3724         /* wait for host to detect disconnect */
3725         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32);
3726
3727         DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
3728             GRSTCTL_CSFTRST);
3729
3730         /* wait a little bit for block to reset */
3731         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128);
3732
3733         switch (sc->sc_mode) {
3734         case DWC_MODE_DEVICE:
3735                 temp = GUSBCFG_FORCEDEVMODE;
3736                 break;
3737         case DWC_MODE_HOST:
3738                 temp = GUSBCFG_FORCEHOSTMODE;
3739                 break;
3740         default:
3741                 temp = 0;
3742                 break;
3743         }
3744
3745         /* select HSIC, ULPI or internal PHY mode */
3746         switch (dwc_otg_phy_type) {
3747         case DWC_OTG_PHY_HSIC:
3748                 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3749                     GUSBCFG_PHYIF |
3750                     GUSBCFG_TRD_TIM_SET(5) | temp);
3751                 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL,
3752                     0x000000EC);
3753
3754                 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3755                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3756                     temp & ~GLPMCFG_HSIC_CONN);
3757                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3758                     temp | GLPMCFG_HSIC_CONN);
3759                 break;
3760         case DWC_OTG_PHY_ULPI:
3761                 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3762                     GUSBCFG_ULPI_UTMI_SEL |
3763                     GUSBCFG_TRD_TIM_SET(5) | temp);
3764                 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3765
3766                 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3767                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3768                     temp & ~GLPMCFG_HSIC_CONN);
3769                 break;
3770         case DWC_OTG_PHY_INTERNAL:
3771                 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3772                     GUSBCFG_PHYSEL |
3773                     GUSBCFG_TRD_TIM_SET(5) | temp);
3774                 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3775
3776                 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3777                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3778                     temp & ~GLPMCFG_HSIC_CONN);
3779
3780                 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO);
3781                 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN);
3782                 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN |
3783                     DOTG_GGPIO_PWRDWN);
3784                 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp);
3785                 break;
3786         default:
3787                 break;
3788         }
3789
3790         /* clear global nak */
3791         DWC_OTG_WRITE_4(sc, DOTG_DCTL,
3792             DCTL_CGOUTNAK |
3793             DCTL_CGNPINNAK);
3794
3795         /* disable USB port */
3796         DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF);
3797
3798         /* wait 10ms */
3799         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3800
3801         /* enable USB port */
3802         DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0);
3803
3804         /* wait 10ms */
3805         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3806
3807         temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3);
3808
3809         sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp);
3810
3811         temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
3812
3813         sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp);
3814
3815         if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS)
3816                 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS;
3817
3818         sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp);
3819
3820         if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS)
3821                 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS;
3822
3823         temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4);
3824
3825         sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp);
3826
3827         DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n",
3828             sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max,
3829             sc->sc_host_ch_max);
3830
3831         /* setup FIFO */
3832         if (dwc_otg_init_fifo(sc, sc->sc_mode)) {
3833                 USB_BUS_UNLOCK(&sc->sc_bus);
3834                 return (EINVAL);
3835         }
3836
3837         /* enable interrupts */
3838         sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED;
3839         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
3840
3841         if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) {
3842
3843                 /* enable all endpoint interrupts */
3844                 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
3845                 if (temp & GHWCFG2_MPI) {
3846                         uint8_t x;
3847
3848                         DPRINTF("Disable Multi Process Interrupts\n");
3849
3850                         for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
3851                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0);
3852                                 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0);
3853                         }
3854                         DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0);
3855                 }
3856                 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK,
3857                     DIEPMSK_XFERCOMPLMSK);
3858                 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0);
3859                 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF);
3860         }
3861
3862         if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) {
3863                 /* setup clocks */
3864                 temp = DWC_OTG_READ_4(sc, DOTG_HCFG);
3865                 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK);
3866                 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT);
3867                 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp);
3868         }
3869
3870         /* only enable global IRQ */
3871         DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG,
3872             GAHBCFG_GLBLINTRMSK);
3873
3874         /* turn off clocks */
3875         dwc_otg_clocks_off(sc);
3876
3877         /* read initial VBUS state */
3878
3879         temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
3880
3881         DPRINTFN(5, "GOTCTL=0x%08x\n", temp);
3882
3883         dwc_otg_vbus_interrupt(sc,
3884             (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
3885
3886         USB_BUS_UNLOCK(&sc->sc_bus);
3887
3888         /* catch any lost interrupts */
3889
3890         dwc_otg_do_poll(&sc->sc_bus);
3891
3892         return (0);                     /* success */
3893 }
3894
3895 void
3896 dwc_otg_uninit(struct dwc_otg_softc *sc)
3897 {
3898         USB_BUS_LOCK(&sc->sc_bus);
3899
3900         /* stop host timer */
3901         dwc_otg_timer_stop(sc);
3902
3903         /* set disconnect */
3904         DWC_OTG_WRITE_4(sc, DOTG_DCTL,
3905             DCTL_SFTDISCON);
3906
3907         /* turn off global IRQ */
3908         DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0);
3909
3910         sc->sc_flags.port_enabled = 0;
3911         sc->sc_flags.port_powered = 0;
3912         sc->sc_flags.status_vbus = 0;
3913         sc->sc_flags.status_bus_reset = 0;
3914         sc->sc_flags.status_suspend = 0;
3915         sc->sc_flags.change_suspend = 0;
3916         sc->sc_flags.change_connect = 1;
3917
3918         dwc_otg_pull_down(sc);
3919         dwc_otg_clocks_off(sc);
3920
3921         USB_BUS_UNLOCK(&sc->sc_bus);
3922
3923         usb_callout_drain(&sc->sc_timer);
3924 }
3925
3926 static void
3927 dwc_otg_suspend(struct dwc_otg_softc *sc)
3928 {
3929         return;
3930 }
3931
3932 static void
3933 dwc_otg_resume(struct dwc_otg_softc *sc)
3934 {
3935         return;
3936 }
3937
3938 static void
3939 dwc_otg_do_poll(struct usb_bus *bus)
3940 {
3941         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus);
3942
3943         USB_BUS_LOCK(&sc->sc_bus);
3944         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3945         dwc_otg_interrupt_poll_locked(sc);
3946         dwc_otg_interrupt_complete_locked(sc);
3947         if (sc->sc_flags.status_device_mode == 0) {
3948                 /* update host transfer schedule, so that new transfers can be issued */
3949                 if (dwc_otg_update_host_transfer_schedule_locked(sc))
3950                         dwc_otg_interrupt_poll_locked(sc);
3951         }
3952         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3953         USB_BUS_UNLOCK(&sc->sc_bus);
3954 }
3955
3956 /*------------------------------------------------------------------------*
3957  * DWC OTG bulk support
3958  * DWC OTG control support
3959  * DWC OTG interrupt support
3960  *------------------------------------------------------------------------*/
3961 static void
3962 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer)
3963 {
3964 }
3965
3966 static void
3967 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer)
3968 {
3969         dwc_otg_device_done(xfer, USB_ERR_CANCELLED);
3970 }
3971
3972 static void
3973 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer)
3974 {
3975 }
3976
3977 static void
3978 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer)
3979 {
3980         /* setup TDs */
3981         dwc_otg_setup_standard_chain(xfer);
3982         dwc_otg_start_standard_chain(xfer);
3983 }
3984
3985 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods =
3986 {
3987         .open = dwc_otg_device_non_isoc_open,
3988         .close = dwc_otg_device_non_isoc_close,
3989         .enter = dwc_otg_device_non_isoc_enter,
3990         .start = dwc_otg_device_non_isoc_start,
3991 };
3992
3993 /*------------------------------------------------------------------------*
3994  * DWC OTG full speed isochronous support
3995  *------------------------------------------------------------------------*/
3996 static void
3997 dwc_otg_device_isoc_open(struct usb_xfer *xfer)
3998 {
3999 }
4000
4001 static void
4002 dwc_otg_device_isoc_close(struct usb_xfer *xfer)
4003 {
4004         dwc_otg_device_done(xfer, USB_ERR_CANCELLED);
4005 }
4006
4007 static void
4008 dwc_otg_device_isoc_enter(struct usb_xfer *xfer)
4009 {
4010 }
4011
4012 static void
4013 dwc_otg_device_isoc_start(struct usb_xfer *xfer)
4014 {
4015         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
4016         uint32_t temp;
4017         uint32_t msframes;
4018         uint32_t framenum;
4019         uint8_t shift = usbd_xfer_get_fps_shift(xfer);
4020
4021         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
4022             xfer, xfer->endpoint->isoc_next, xfer->nframes);
4023
4024         if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) {
4025                 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM);
4026
4027                 /* get the current frame index */
4028                 framenum = (temp & HFNUM_FRNUM_MASK);
4029         } else {
4030                 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
4031
4032                 /* get the current frame index */
4033                 framenum = DSTS_SOFFN_GET(temp);
4034         }
4035
4036         if (xfer->xroot->udev->parent_hs_hub != NULL)
4037                 framenum /= 8;
4038
4039         framenum &= DWC_OTG_FRAME_MASK;
4040
4041         /*
4042          * Compute number of milliseconds worth of data traffic for
4043          * this USB transfer:
4044          */
4045         if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
4046                 msframes = ((xfer->nframes << shift) + 7) / 8;
4047         else
4048                 msframes = xfer->nframes;
4049
4050         /*
4051          * check if the frame index is within the window where the frames
4052          * will be inserted
4053          */
4054         temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK;
4055
4056         if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) {
4057                 /*
4058                  * If there is data underflow or the pipe queue is
4059                  * empty we schedule the transfer a few frames ahead
4060                  * of the current frame position. Else two isochronous
4061                  * transfers might overlap.
4062                  */
4063                 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK;
4064                 xfer->endpoint->is_synced = 1;
4065                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
4066         }
4067         /*
4068          * compute how many milliseconds the insertion is ahead of the
4069          * current frame position:
4070          */
4071         temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK;
4072
4073         /*
4074          * pre-compute when the isochronous transfer will be finished:
4075          */
4076         xfer->isoc_time_complete =
4077                 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes;
4078
4079         /* setup TDs */
4080         dwc_otg_setup_standard_chain(xfer);
4081
4082         /* compute frame number for next insertion */
4083         xfer->endpoint->isoc_next += msframes;
4084
4085         /* start TD chain */
4086         dwc_otg_start_standard_chain(xfer);
4087 }
4088
4089 static const struct usb_pipe_methods dwc_otg_device_isoc_methods =
4090 {
4091         .open = dwc_otg_device_isoc_open,
4092         .close = dwc_otg_device_isoc_close,
4093         .enter = dwc_otg_device_isoc_enter,
4094         .start = dwc_otg_device_isoc_start,
4095 };
4096
4097 /*------------------------------------------------------------------------*
4098  * DWC OTG root control support
4099  *------------------------------------------------------------------------*
4100  * Simulate a hardware HUB by handling all the necessary requests.
4101  *------------------------------------------------------------------------*/
4102
4103 static const struct usb_device_descriptor dwc_otg_devd = {
4104         .bLength = sizeof(struct usb_device_descriptor),
4105         .bDescriptorType = UDESC_DEVICE,
4106         .bcdUSB = {0x00, 0x02},
4107         .bDeviceClass = UDCLASS_HUB,
4108         .bDeviceSubClass = UDSUBCLASS_HUB,
4109         .bDeviceProtocol = UDPROTO_HSHUBSTT,
4110         .bMaxPacketSize = 64,
4111         .bcdDevice = {0x00, 0x01},
4112         .iManufacturer = 1,
4113         .iProduct = 2,
4114         .bNumConfigurations = 1,
4115 };
4116
4117 static const struct dwc_otg_config_desc dwc_otg_confd = {
4118         .confd = {
4119                 .bLength = sizeof(struct usb_config_descriptor),
4120                 .bDescriptorType = UDESC_CONFIG,
4121                 .wTotalLength[0] = sizeof(dwc_otg_confd),
4122                 .bNumInterface = 1,
4123                 .bConfigurationValue = 1,
4124                 .iConfiguration = 0,
4125                 .bmAttributes = UC_SELF_POWERED,
4126                 .bMaxPower = 0,
4127         },
4128         .ifcd = {
4129                 .bLength = sizeof(struct usb_interface_descriptor),
4130                 .bDescriptorType = UDESC_INTERFACE,
4131                 .bNumEndpoints = 1,
4132                 .bInterfaceClass = UICLASS_HUB,
4133                 .bInterfaceSubClass = UISUBCLASS_HUB,
4134                 .bInterfaceProtocol = 0,
4135         },
4136         .endpd = {
4137                 .bLength = sizeof(struct usb_endpoint_descriptor),
4138                 .bDescriptorType = UDESC_ENDPOINT,
4139                 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT),
4140                 .bmAttributes = UE_INTERRUPT,
4141                 .wMaxPacketSize[0] = 8,
4142                 .bInterval = 255,
4143         },
4144 };
4145
4146 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
4147
4148 static const struct usb_hub_descriptor_min dwc_otg_hubd = {
4149         .bDescLength = sizeof(dwc_otg_hubd),
4150         .bDescriptorType = UDESC_HUB,
4151         .bNbrPorts = 1,
4152         HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
4153         .bPwrOn2PwrGood = 50,
4154         .bHubContrCurrent = 0,
4155         .DeviceRemovable = {0},         /* port is removable */
4156 };
4157
4158 #define STRING_VENDOR \
4159   "D\0W\0C\0O\0T\0G"
4160
4161 #define STRING_PRODUCT \
4162   "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
4163
4164 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor);
4165 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product);
4166
4167 static usb_error_t
4168 dwc_otg_roothub_exec(struct usb_device *udev,
4169     struct usb_device_request *req, const void **pptr, uint16_t *plength)
4170 {
4171         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4172         const void *ptr;
4173         uint16_t len;
4174         uint16_t value;
4175         uint16_t index;
4176         usb_error_t err;
4177
4178         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
4179
4180         /* buffer reset */
4181         ptr = (const void *)&sc->sc_hub_temp;
4182         len = 0;
4183         err = 0;
4184
4185         value = UGETW(req->wValue);
4186         index = UGETW(req->wIndex);
4187
4188         /* demultiplex the control request */
4189
4190         switch (req->bmRequestType) {
4191         case UT_READ_DEVICE:
4192                 switch (req->bRequest) {
4193                 case UR_GET_DESCRIPTOR:
4194                         goto tr_handle_get_descriptor;
4195                 case UR_GET_CONFIG:
4196                         goto tr_handle_get_config;
4197                 case UR_GET_STATUS:
4198                         goto tr_handle_get_status;
4199                 default:
4200                         goto tr_stalled;
4201                 }
4202                 break;
4203
4204         case UT_WRITE_DEVICE:
4205                 switch (req->bRequest) {
4206                 case UR_SET_ADDRESS:
4207                         goto tr_handle_set_address;
4208                 case UR_SET_CONFIG:
4209                         goto tr_handle_set_config;
4210                 case UR_CLEAR_FEATURE:
4211                         goto tr_valid;  /* nop */
4212                 case UR_SET_DESCRIPTOR:
4213                         goto tr_valid;  /* nop */
4214                 case UR_SET_FEATURE:
4215                 default:
4216                         goto tr_stalled;
4217                 }
4218                 break;
4219
4220         case UT_WRITE_ENDPOINT:
4221                 switch (req->bRequest) {
4222                 case UR_CLEAR_FEATURE:
4223                         switch (UGETW(req->wValue)) {
4224                         case UF_ENDPOINT_HALT:
4225                                 goto tr_handle_clear_halt;
4226                         case UF_DEVICE_REMOTE_WAKEUP:
4227                                 goto tr_handle_clear_wakeup;
4228                         default:
4229                                 goto tr_stalled;
4230                         }
4231                         break;
4232                 case UR_SET_FEATURE:
4233                         switch (UGETW(req->wValue)) {
4234                         case UF_ENDPOINT_HALT:
4235                                 goto tr_handle_set_halt;
4236                         case UF_DEVICE_REMOTE_WAKEUP:
4237                                 goto tr_handle_set_wakeup;
4238                         default:
4239                                 goto tr_stalled;
4240                         }
4241                         break;
4242                 case UR_SYNCH_FRAME:
4243                         goto tr_valid;  /* nop */
4244                 default:
4245                         goto tr_stalled;
4246                 }
4247                 break;
4248
4249         case UT_READ_ENDPOINT:
4250                 switch (req->bRequest) {
4251                 case UR_GET_STATUS:
4252                         goto tr_handle_get_ep_status;
4253                 default:
4254                         goto tr_stalled;
4255                 }
4256                 break;
4257
4258         case UT_WRITE_INTERFACE:
4259                 switch (req->bRequest) {
4260                 case UR_SET_INTERFACE:
4261                         goto tr_handle_set_interface;
4262                 case UR_CLEAR_FEATURE:
4263                         goto tr_valid;  /* nop */
4264                 case UR_SET_FEATURE:
4265                 default:
4266                         goto tr_stalled;
4267                 }
4268                 break;
4269
4270         case UT_READ_INTERFACE:
4271                 switch (req->bRequest) {
4272                 case UR_GET_INTERFACE:
4273                         goto tr_handle_get_interface;
4274                 case UR_GET_STATUS:
4275                         goto tr_handle_get_iface_status;
4276                 default:
4277                         goto tr_stalled;
4278                 }
4279                 break;
4280
4281         case UT_WRITE_CLASS_INTERFACE:
4282         case UT_WRITE_VENDOR_INTERFACE:
4283                 /* XXX forward */
4284                 break;
4285
4286         case UT_READ_CLASS_INTERFACE:
4287         case UT_READ_VENDOR_INTERFACE:
4288                 /* XXX forward */
4289                 break;
4290
4291         case UT_WRITE_CLASS_DEVICE:
4292                 switch (req->bRequest) {
4293                 case UR_CLEAR_FEATURE:
4294                         goto tr_valid;
4295                 case UR_SET_DESCRIPTOR:
4296                 case UR_SET_FEATURE:
4297                         break;
4298                 default:
4299                         goto tr_stalled;
4300                 }
4301                 break;
4302
4303         case UT_WRITE_CLASS_OTHER:
4304                 switch (req->bRequest) {
4305                 case UR_CLEAR_FEATURE:
4306                         goto tr_handle_clear_port_feature;
4307                 case UR_SET_FEATURE:
4308                         goto tr_handle_set_port_feature;
4309                 case UR_CLEAR_TT_BUFFER:
4310                 case UR_RESET_TT:
4311                 case UR_STOP_TT:
4312                         goto tr_valid;
4313
4314                 default:
4315                         goto tr_stalled;
4316                 }
4317                 break;
4318
4319         case UT_READ_CLASS_OTHER:
4320                 switch (req->bRequest) {
4321                 case UR_GET_TT_STATE:
4322                         goto tr_handle_get_tt_state;
4323                 case UR_GET_STATUS:
4324                         goto tr_handle_get_port_status;
4325                 default:
4326                         goto tr_stalled;
4327                 }
4328                 break;
4329
4330         case UT_READ_CLASS_DEVICE:
4331                 switch (req->bRequest) {
4332                 case UR_GET_DESCRIPTOR:
4333                         goto tr_handle_get_class_descriptor;
4334                 case UR_GET_STATUS:
4335                         goto tr_handle_get_class_status;
4336
4337                 default:
4338                         goto tr_stalled;
4339                 }
4340                 break;
4341         default:
4342                 goto tr_stalled;
4343         }
4344         goto tr_valid;
4345
4346 tr_handle_get_descriptor:
4347         switch (value >> 8) {
4348         case UDESC_DEVICE:
4349                 if (value & 0xff) {
4350                         goto tr_stalled;
4351                 }
4352                 len = sizeof(dwc_otg_devd);
4353                 ptr = (const void *)&dwc_otg_devd;
4354                 goto tr_valid;
4355         case UDESC_CONFIG:
4356                 if (value & 0xff) {
4357                         goto tr_stalled;
4358                 }
4359                 len = sizeof(dwc_otg_confd);
4360                 ptr = (const void *)&dwc_otg_confd;
4361                 goto tr_valid;
4362         case UDESC_STRING:
4363                 switch (value & 0xff) {
4364                 case 0:         /* Language table */
4365                         len = sizeof(usb_string_lang_en);
4366                         ptr = (const void *)&usb_string_lang_en;
4367                         goto tr_valid;
4368
4369                 case 1:         /* Vendor */
4370                         len = sizeof(dwc_otg_vendor);
4371                         ptr = (const void *)&dwc_otg_vendor;
4372                         goto tr_valid;
4373
4374                 case 2:         /* Product */
4375                         len = sizeof(dwc_otg_product);
4376                         ptr = (const void *)&dwc_otg_product;
4377                         goto tr_valid;
4378                 default:
4379                         break;
4380                 }
4381                 break;
4382         default:
4383                 goto tr_stalled;
4384         }
4385         goto tr_stalled;
4386
4387 tr_handle_get_config:
4388         len = 1;
4389         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
4390         goto tr_valid;
4391
4392 tr_handle_get_status:
4393         len = 2;
4394         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
4395         goto tr_valid;
4396
4397 tr_handle_set_address:
4398         if (value & 0xFF00) {
4399                 goto tr_stalled;
4400         }
4401         sc->sc_rt_addr = value;
4402         goto tr_valid;
4403
4404 tr_handle_set_config:
4405         if (value >= 2) {
4406                 goto tr_stalled;
4407         }
4408         sc->sc_conf = value;
4409         goto tr_valid;
4410
4411 tr_handle_get_interface:
4412         len = 1;
4413         sc->sc_hub_temp.wValue[0] = 0;
4414         goto tr_valid;
4415
4416 tr_handle_get_tt_state:
4417 tr_handle_get_class_status:
4418 tr_handle_get_iface_status:
4419 tr_handle_get_ep_status:
4420         len = 2;
4421         USETW(sc->sc_hub_temp.wValue, 0);
4422         goto tr_valid;
4423
4424 tr_handle_set_halt:
4425 tr_handle_set_interface:
4426 tr_handle_set_wakeup:
4427 tr_handle_clear_wakeup:
4428 tr_handle_clear_halt:
4429         goto tr_valid;
4430
4431 tr_handle_clear_port_feature:
4432         if (index != 1)
4433                 goto tr_stalled;
4434
4435         DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
4436
4437         switch (value) {
4438         case UHF_PORT_SUSPEND:
4439                 dwc_otg_wakeup_peer(sc);
4440                 break;
4441
4442         case UHF_PORT_ENABLE:
4443                 if (sc->sc_flags.status_device_mode == 0) {
4444                         DWC_OTG_WRITE_4(sc, DOTG_HPRT,
4445                             sc->sc_hprt_val | HPRT_PRTENA);
4446                 }
4447                 sc->sc_flags.port_enabled = 0;
4448                 break;
4449
4450         case UHF_C_PORT_RESET:
4451                 sc->sc_flags.change_reset = 0;
4452                 break;
4453
4454         case UHF_C_PORT_ENABLE:
4455                 sc->sc_flags.change_enabled = 0;
4456                 break;
4457
4458         case UHF_C_PORT_OVER_CURRENT:
4459                 sc->sc_flags.change_over_current = 0;
4460                 break;
4461
4462         case UHF_PORT_TEST:
4463         case UHF_PORT_INDICATOR:
4464                 /* nops */
4465                 break;
4466
4467         case UHF_PORT_POWER:
4468                 sc->sc_flags.port_powered = 0;
4469                 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4470                         sc->sc_hprt_val = 0;
4471                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA);
4472                 }
4473                 dwc_otg_pull_down(sc);
4474                 dwc_otg_clocks_off(sc);
4475                 break;
4476
4477         case UHF_C_PORT_CONNECTION:
4478                 /* clear connect change flag */
4479                 sc->sc_flags.change_connect = 0;
4480                 break;
4481
4482         case UHF_C_PORT_SUSPEND:
4483                 sc->sc_flags.change_suspend = 0;
4484                 break;
4485
4486         default:
4487                 err = USB_ERR_IOERROR;
4488                 goto done;
4489         }
4490         goto tr_valid;
4491
4492 tr_handle_set_port_feature:
4493         if (index != 1) {
4494                 goto tr_stalled;
4495         }
4496         DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
4497
4498         switch (value) {
4499         case UHF_PORT_ENABLE:
4500                 break;
4501
4502         case UHF_PORT_SUSPEND:
4503                 if (sc->sc_flags.status_device_mode == 0) {
4504                         /* set suspend BIT */
4505                         sc->sc_hprt_val |= HPRT_PRTSUSP;
4506                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4507
4508                         /* generate HUB suspend event */
4509                         dwc_otg_suspend_irq(sc);
4510                 }
4511                 break;
4512
4513         case UHF_PORT_RESET:
4514                 if (sc->sc_flags.status_device_mode == 0) {
4515
4516                         DPRINTF("PORT RESET\n");
4517
4518                         /* enable PORT reset */
4519                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST);
4520
4521                         /* Wait 62.5ms for reset to complete */
4522                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4523
4524                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4525
4526                         /* Wait 62.5ms for reset to complete */
4527                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4528
4529                         /* reset FIFOs */
4530                         (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST);
4531
4532                         sc->sc_flags.change_reset = 1;
4533                 } else {
4534                         err = USB_ERR_IOERROR;
4535                 }
4536                 break;
4537
4538         case UHF_PORT_TEST:
4539         case UHF_PORT_INDICATOR:
4540                 /* nops */
4541                 break;
4542         case UHF_PORT_POWER:
4543                 sc->sc_flags.port_powered = 1;
4544                 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4545                         sc->sc_hprt_val |= HPRT_PRTPWR;
4546                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4547                 }
4548                 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) {
4549                         /* pull up D+, if any */
4550                         dwc_otg_pull_up(sc);
4551                 }
4552                 break;
4553         default:
4554                 err = USB_ERR_IOERROR;
4555                 goto done;
4556         }
4557         goto tr_valid;
4558
4559 tr_handle_get_port_status:
4560
4561         DPRINTFN(9, "UR_GET_PORT_STATUS\n");
4562
4563         if (index != 1)
4564                 goto tr_stalled;
4565
4566         if (sc->sc_flags.status_vbus)
4567                 dwc_otg_clocks_on(sc);
4568         else
4569                 dwc_otg_clocks_off(sc);
4570
4571         /* Select Device Side Mode */
4572
4573         if (sc->sc_flags.status_device_mode) {
4574                 value = UPS_PORT_MODE_DEVICE;
4575                 dwc_otg_timer_stop(sc);
4576         } else {
4577                 value = 0;
4578                 dwc_otg_timer_start(sc);
4579         }
4580
4581         if (sc->sc_flags.status_high_speed)
4582                 value |= UPS_HIGH_SPEED;
4583         else if (sc->sc_flags.status_low_speed)
4584                 value |= UPS_LOW_SPEED;
4585
4586         if (sc->sc_flags.port_powered)
4587                 value |= UPS_PORT_POWER;
4588
4589         if (sc->sc_flags.port_enabled)
4590                 value |= UPS_PORT_ENABLED;
4591
4592         if (sc->sc_flags.port_over_current)
4593                 value |= UPS_OVERCURRENT_INDICATOR;
4594
4595         if (sc->sc_flags.status_vbus &&
4596             sc->sc_flags.status_bus_reset)
4597                 value |= UPS_CURRENT_CONNECT_STATUS;
4598
4599         if (sc->sc_flags.status_suspend)
4600                 value |= UPS_SUSPEND;
4601
4602         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4603
4604         value = 0;
4605
4606         if (sc->sc_flags.change_connect)
4607                 value |= UPS_C_CONNECT_STATUS;
4608         if (sc->sc_flags.change_suspend)
4609                 value |= UPS_C_SUSPEND;
4610         if (sc->sc_flags.change_reset)
4611                 value |= UPS_C_PORT_RESET;
4612         if (sc->sc_flags.change_over_current)
4613                 value |= UPS_C_OVERCURRENT_INDICATOR;
4614
4615         USETW(sc->sc_hub_temp.ps.wPortChange, value);
4616         len = sizeof(sc->sc_hub_temp.ps);
4617         goto tr_valid;
4618
4619 tr_handle_get_class_descriptor:
4620         if (value & 0xFF) {
4621                 goto tr_stalled;
4622         }
4623         ptr = (const void *)&dwc_otg_hubd;
4624         len = sizeof(dwc_otg_hubd);
4625         goto tr_valid;
4626
4627 tr_stalled:
4628         err = USB_ERR_STALLED;
4629 tr_valid:
4630 done:
4631         *plength = len;
4632         *pptr = ptr;
4633         return (err);
4634 }
4635
4636 static void
4637 dwc_otg_xfer_setup(struct usb_setup_params *parm)
4638 {
4639         struct usb_xfer *xfer;
4640         void *last_obj;
4641         uint32_t ntd;
4642         uint32_t n;
4643         uint8_t ep_no;
4644         uint8_t ep_type;
4645
4646         xfer = parm->curr_xfer;
4647
4648         /*
4649          * NOTE: This driver does not use any of the parameters that
4650          * are computed from the following values. Just set some
4651          * reasonable dummies:
4652          */
4653         parm->hc_max_packet_size = 0x500;
4654         parm->hc_max_packet_count = 3;
4655         parm->hc_max_frame_size = 3 * 0x500;
4656
4657         usbd_transfer_setup_sub(parm);
4658
4659         /*
4660          * compute maximum number of TDs
4661          */
4662         ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
4663
4664         if (ep_type == UE_CONTROL) {
4665
4666                 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
4667                     + 1 /* SYNC 2 */ + 1 /* SYNC 3 */;
4668         } else {
4669
4670                 ntd = xfer->nframes + 1 /* SYNC */ ;
4671         }
4672
4673         /*
4674          * check if "usbd_transfer_setup_sub" set an error
4675          */
4676         if (parm->err)
4677                 return;
4678
4679         /*
4680          * allocate transfer descriptors
4681          */
4682         last_obj = NULL;
4683
4684         ep_no = xfer->endpointno & UE_ADDR;
4685
4686         /*
4687          * Check for a valid endpoint profile in USB device mode:
4688          */
4689         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4690                 const struct usb_hw_ep_profile *pf;
4691
4692                 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4693
4694                 if (pf == NULL) {
4695                         /* should not happen */
4696                         parm->err = USB_ERR_INVAL;
4697                         return;
4698                 }
4699         }
4700
4701         /* align data */
4702         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4703
4704         for (n = 0; n != ntd; n++) {
4705
4706                 struct dwc_otg_td *td;
4707
4708                 if (parm->buf) {
4709
4710                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4711
4712                         /* compute shared bandwidth resource index for TT */
4713                         if (parm->udev->parent_hs_hub != NULL && parm->udev->speed != USB_SPEED_HIGH) {
4714                                 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT)
4715                                         td->tt_index = parm->udev->device_index;
4716                                 else
4717                                         td->tt_index = parm->udev->parent_hs_hub->device_index;
4718                         } else {
4719                                 td->tt_index = parm->udev->device_index;
4720                         }
4721
4722                         /* init TD */
4723                         td->max_packet_size = xfer->max_packet_size;
4724                         td->max_packet_count = xfer->max_packet_count;
4725                         td->ep_no = ep_no;
4726                         td->ep_type = ep_type;
4727                         td->obj_next = last_obj;
4728
4729                         last_obj = td;
4730                 }
4731                 parm->size[0] += sizeof(*td);
4732         }
4733
4734         xfer->td_start[0] = last_obj;
4735 }
4736
4737 static void
4738 dwc_otg_xfer_unsetup(struct usb_xfer *xfer)
4739 {
4740         return;
4741 }
4742
4743 static void
4744 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4745     struct usb_endpoint *ep)
4746 {
4747         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4748
4749         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
4750             ep, udev->address,
4751             edesc->bEndpointAddress, udev->flags.usb_mode,
4752             sc->sc_rt_addr, udev->device_index);
4753
4754         if (udev->device_index != sc->sc_rt_addr) {
4755
4756                 if (udev->flags.usb_mode == USB_MODE_DEVICE) {
4757                         if (udev->speed != USB_SPEED_FULL &&
4758                             udev->speed != USB_SPEED_HIGH) {
4759                                 /* not supported */
4760                                 return;
4761                         }
4762                 } else {
4763                         if (udev->speed == USB_SPEED_HIGH) {
4764                                 if ((UGETW(edesc->wMaxPacketSize) >> 11) & 3) {
4765                                         /* high bandwidth endpoint - not tested */
4766                                         DPRINTF("High Bandwidth Endpoint - not tested\n");
4767                                         return;
4768                                 }
4769                         }
4770                 }
4771                 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
4772                         ep->methods = &dwc_otg_device_isoc_methods;
4773                 else
4774                         ep->methods = &dwc_otg_device_non_isoc_methods;
4775         }
4776 }
4777
4778 static void
4779 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4780 {
4781         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus);
4782
4783         switch (state) {
4784         case USB_HW_POWER_SUSPEND:
4785                 dwc_otg_suspend(sc);
4786                 break;
4787         case USB_HW_POWER_SHUTDOWN:
4788                 dwc_otg_uninit(sc);
4789                 break;
4790         case USB_HW_POWER_RESUME:
4791                 dwc_otg_resume(sc);
4792                 break;
4793         default:
4794                 break;
4795         }
4796 }
4797
4798 static void
4799 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4800 {
4801         /* DMA delay - wait until any use of memory is finished */
4802         *pus = (2125);                  /* microseconds */
4803 }
4804
4805 static void
4806 dwc_otg_device_resume(struct usb_device *udev)
4807 {
4808         DPRINTF("\n");
4809
4810         /* poll all transfers again to restart resumed ones */
4811         dwc_otg_do_poll(udev->bus);
4812 }
4813
4814 static void
4815 dwc_otg_device_suspend(struct usb_device *udev)
4816 {
4817         DPRINTF("\n");
4818 }
4819
4820 static const struct usb_bus_methods dwc_otg_bus_methods =
4821 {
4822         .endpoint_init = &dwc_otg_ep_init,
4823         .xfer_setup = &dwc_otg_xfer_setup,
4824         .xfer_unsetup = &dwc_otg_xfer_unsetup,
4825         .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile,
4826         .xfer_stall = &dwc_otg_xfer_stall,
4827         .set_stall = &dwc_otg_set_stall,
4828         .clear_stall = &dwc_otg_clear_stall,
4829         .roothub_exec = &dwc_otg_roothub_exec,
4830         .xfer_poll = &dwc_otg_do_poll,
4831         .device_state_change = &dwc_otg_device_state_change,
4832         .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep,
4833         .get_dma_delay = &dwc_otg_get_dma_delay,
4834         .device_resume = &dwc_otg_device_resume,
4835         .device_suspend = &dwc_otg_device_suspend,
4836 };