sys/dev/usb/controller/dwc_otg.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   4  *
   5  * Copyright (c) 2015 Daisuke Aoyama. All rights reserved.
   6  * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved.
   7  * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  */
  30
  31 /*
  32  * This file contains the driver for the DesignWare series USB 2.0 OTG
  33  * Controller.
  34  */
  35
  36 /*
  37  * LIMITATION: Drivers must be bound to all OUT endpoints in the
  38  * active configuration for this driver to work properly. Blocking any
  39  * OUT endpoint will block all OUT endpoints including the control
  40  * endpoint. Usually this is not a problem.
  41  */
  42
  43 /*
  44  * NOTE: Writing to non-existing registers appears to cause an
  45  * internal reset.
  46  */
  47
  48 #ifdef USB_GLOBAL_INCLUDE_FILE
  49 #include USB_GLOBAL_INCLUDE_FILE
  50 #else
  51 #include <sys/stdint.h>
  52 #include <sys/stddef.h>
  53 #include <sys/param.h>
  54 #include <sys/queue.h>
  55 #include <sys/types.h>
  56 #include <sys/systm.h>
  57 #include <sys/kernel.h>
  58 #include <sys/bus.h>
  59 #include <sys/module.h>
  60 #include <sys/lock.h>
  61 #include <sys/mutex.h>
  62 #include <sys/condvar.h>
  63 #include <sys/sysctl.h>
  64 #include <sys/sx.h>
  65 #include <sys/unistd.h>
  66 #include <sys/callout.h>
  67 #include <sys/malloc.h>
  68 #include <sys/priv.h>
  69
  70 #include <dev/usb/usb.h>
  71 #include <dev/usb/usbdi.h>
  72
  73 #define USB_DEBUG_VAR dwc_otg_debug
  74
  75 #include <dev/usb/usb_core.h>
  76 #include <dev/usb/usb_debug.h>
  77 #include <dev/usb/usb_busdma.h>
  78 #include <dev/usb/usb_process.h>
  79 #include <dev/usb/usb_transfer.h>
  80 #include <dev/usb/usb_device.h>
  81 #include <dev/usb/usb_hub.h>
  82 #include <dev/usb/usb_util.h>
  83
  84 #include <dev/usb/usb_controller.h>
  85 #include <dev/usb/usb_bus.h>
  86 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  87
  88 #include <dev/usb/controller/dwc_otg.h>
  89 #include <dev/usb/controller/dwc_otgreg.h>
  90
  91 #define DWC_OTG_BUS2SC(bus) \
  92    ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \
  93     ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus))))
  94
  95 #define DWC_OTG_PC2UDEV(pc) \
  96    (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
  97
  98 #define DWC_OTG_MSK_GINT_THREAD_IRQ                             \
  99    (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT |        \
 100    GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK |      \
 101    GINTSTS_SESSREQINT)
 102
 103 #ifndef DWC_OTG_PHY_DEFAULT
 104 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI
 105 #endif
 106
 107 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT;
 108
 109 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
 110     "USB DWC OTG");
 111 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN,
 112     &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2/3 - ULPI/HSIC/INTERNAL/UTMI+");
 113
 114 #ifdef USB_DEBUG
 115 static int dwc_otg_debug = 0;
 116
 117 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN,
 118     &dwc_otg_debug, 0, "DWC OTG debug level");
 119 #endif
 120
 121 #define DWC_OTG_INTR_ENDPT 1
 122
 123 /* prototypes */
 124
 125 static const struct usb_bus_methods dwc_otg_bus_methods;
 126 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods;
 127 static const struct usb_pipe_methods dwc_otg_device_isoc_methods;
 128
 129 static dwc_otg_cmd_t dwc_otg_setup_rx;
 130 static dwc_otg_cmd_t dwc_otg_data_rx;
 131 static dwc_otg_cmd_t dwc_otg_data_tx;
 132 static dwc_otg_cmd_t dwc_otg_data_tx_sync;
 133
 134 static dwc_otg_cmd_t dwc_otg_host_setup_tx;
 135 static dwc_otg_cmd_t dwc_otg_host_data_tx;
 136 static dwc_otg_cmd_t dwc_otg_host_data_rx;
 137
 138 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t);
 139 static void dwc_otg_do_poll(struct usb_bus *);
 140 static void dwc_otg_standard_done(struct usb_xfer *);
 141 static void dwc_otg_root_intr(struct dwc_otg_softc *);
 142 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *);
 143
 144 /*
 145  * Here is a configuration that the chip supports.
 146  */
 147 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = {
 148
 149         [0] = {
 150                 .max_in_frame_size = 64,/* fixed */
 151                 .max_out_frame_size = 64,       /* fixed */
 152                 .is_simplex = 1,
 153                 .support_control = 1,
 154         }
 155 };
 156
 157 static void
 158 dwc_otg_get_hw_ep_profile(struct usb_device *udev,
 159     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 160 {
 161         struct dwc_otg_softc *sc;
 162
 163         sc = DWC_OTG_BUS2SC(udev->bus);
 164
 165         if (ep_addr < sc->sc_dev_ep_max)
 166                 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb;
 167         else
 168                 *ppf = NULL;
 169 }
 170
 171 static void
 172 dwc_otg_write_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc,
 173     uint32_t offset, uint32_t fifo, uint32_t count)
 174 {
 175         uint32_t temp;
 176
 177         /* round down length to nearest 4-bytes */
 178         temp = count & ~3;
 179
 180         /* check if we can write the data directly */
 181         if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
 182                 struct usb_page_search buf_res;
 183
 184                 /* pre-subtract length */
 185                 count -= temp;
 186
 187                 /* iterate buffer list */
 188                 do {
 189                         /* get current buffer pointer */
 190                         usbd_get_page(pc, offset, &buf_res);
 191
 192                         if (buf_res.length > temp)
 193                                 buf_res.length = temp;
 194
 195                         /* transfer data into FIFO */
 196                         bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
 197                             fifo, buf_res.buffer, buf_res.length / 4);
 198
 199                         offset += buf_res.length;
 200                         fifo += buf_res.length;
 201                         temp -= buf_res.length;
 202                 } while (temp != 0);
 203         }
 204
 205         /* check for remainder */
 206         if (count != 0) {
 207                 /* clear topmost word before copy */
 208                 sc->sc_bounce_buffer[(count - 1) / 4] = 0;
 209
 210                 /* copy out data */
 211                 usbd_copy_out(pc, offset,
 212                     sc->sc_bounce_buffer, count);
 213
 214                 /* transfer data into FIFO */
 215                 bus_space_write_region_4(sc->sc_io_tag,
 216                     sc->sc_io_hdl, fifo, sc->sc_bounce_buffer,
 217                     (count + 3) / 4);
 218         }
 219 }
 220
 221 static void
 222 dwc_otg_read_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc,
 223     uint32_t offset, uint32_t count)
 224 {
 225         uint32_t temp;
 226
 227         /* round down length to nearest 4-bytes */
 228         temp = count & ~3;
 229
 230         /* check if we can read the data directly */
 231         if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
 232                 struct usb_page_search buf_res;
 233
 234                 /* pre-subtract length */
 235                 count -= temp;
 236
 237                 /* iterate buffer list */
 238                 do {
 239                         /* get current buffer pointer */
 240                         usbd_get_page(pc, offset, &buf_res);
 241
 242                         if (buf_res.length > temp)
 243                                 buf_res.length = temp;
 244
 245                         /* transfer data from FIFO */
 246                         bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
 247                             sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4);
 248
 249                         offset += buf_res.length;
 250                         sc->sc_current_rx_fifo += buf_res.length;
 251                         sc->sc_current_rx_bytes -= buf_res.length;
 252                         temp -= buf_res.length;
 253                 } while (temp != 0);
 254         }
 255
 256         /* check for remainder */
 257         if (count != 0) {
 258                 /* read data into bounce buffer */
 259                 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
 260                         sc->sc_current_rx_fifo,
 261                         sc->sc_bounce_buffer, (count + 3) / 4);
 262
 263                 /* store data into proper buffer */
 264                 usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count);
 265
 266                 /* round length up to nearest 4 bytes */
 267                 count = (count + 3) & ~3;
 268
 269                 /* update counters */
 270                 sc->sc_current_rx_bytes -= count;
 271                 sc->sc_current_rx_fifo += count;
 272         }
 273 }
 274
 275 static void
 276 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value)
 277 {
 278         uint32_t temp;
 279
 280         /* reset FIFO */
 281         DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value);
 282
 283         /* wait for reset to complete */
 284         for (temp = 0; temp != 16; temp++) {
 285                 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL);
 286                 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)))
 287                         break;
 288         }
 289 }
 290
 291 static int
 292 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode)
 293 {
 294         struct dwc_otg_profile *pf;
 295         uint32_t fifo_size;
 296         uint32_t fifo_regs;
 297         uint32_t tx_start;
 298         uint8_t x;
 299
 300         fifo_size = sc->sc_fifo_size;
 301
 302         /*
 303          * NOTE: Reserved fixed size area at end of RAM, which must
 304          * not be allocated to the FIFOs:
 305          */
 306         fifo_regs = 4 * 16;
 307
 308         if (fifo_size < fifo_regs) {
 309                 DPRINTF("Too little FIFO\n");
 310                 return (EINVAL);
 311         }
 312
 313         /* subtract FIFO regs from total once */
 314         fifo_size -= fifo_regs;
 315
 316         /* split equally for IN and OUT */
 317         fifo_size /= 2;
 318
 319         /* Align to 4 bytes boundary (refer to PGM) */
 320         fifo_size &= ~3;
 321
 322         /* set global receive FIFO size */
 323         DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4);
 324
 325         tx_start = fifo_size;
 326
 327         if (fifo_size < 64) {
 328                 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n");
 329                 return (EINVAL);
 330         }
 331
 332         if (mode == DWC_MODE_HOST) {
 333
 334                 /* reset active endpoints */
 335                 sc->sc_active_rx_ep = 0;
 336
 337                 /* split equally for periodic and non-periodic */
 338                 fifo_size /= 2;
 339
 340                 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size);
 341
 342                 /* align to 4 bytes boundary */
 343                 fifo_size &= ~3;
 344
 345                 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ,
 346                     ((fifo_size / 4) << 16) |
 347                     (tx_start / 4));
 348
 349                 tx_start += fifo_size;
 350
 351                 for (x = 0; x != sc->sc_host_ch_max; x++) {
 352                         /* enable all host interrupts */
 353                         DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x),
 354                             HCINT_DEFAULT_MASK);
 355                 }
 356
 357                 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ,
 358                     ((fifo_size / 4) << 16) |
 359                     (tx_start / 4));
 360
 361                 /* reset host channel state */
 362                 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
 363
 364                 /* enable all host channel interrupts */
 365                 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK,
 366                     (1U << sc->sc_host_ch_max) - 1U);
 367
 368                 /* enable proper host channel interrupts */
 369                 sc->sc_irq_mask |= GINTMSK_HCHINTMSK;
 370                 sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK;
 371                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 372         }
 373
 374         if (mode == DWC_MODE_DEVICE) {
 375
 376             DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ,
 377                 (0x10 << 16) | (tx_start / 4));
 378             fifo_size -= 0x40;
 379             tx_start += 0x40;
 380
 381             /* setup control endpoint profile */
 382             sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0];
 383
 384             /* reset active endpoints */
 385             sc->sc_active_rx_ep = 1;
 386
 387             for (x = 1; x != sc->sc_dev_ep_max; x++) {
 388
 389                 pf = sc->sc_hw_ep_profile + x;
 390
 391                 pf->usb.max_out_frame_size = 1024 * 3;
 392                 pf->usb.is_simplex = 0; /* assume duplex */
 393                 pf->usb.support_bulk = 1;
 394                 pf->usb.support_interrupt = 1;
 395                 pf->usb.support_isochronous = 1;
 396                 pf->usb.support_out = 1;
 397
 398                 if (x < sc->sc_dev_in_ep_max) {
 399                         uint32_t limit;
 400
 401                         limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE,
 402                             DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2,
 403                             DWC_OTG_TX_MAX_FIFO_SIZE);
 404
 405                         /* see if there is enough FIFO space */
 406                         if (limit <= fifo_size) {
 407                                 pf->max_buffer = limit;
 408                                 pf->usb.support_in = 1;
 409                         } else {
 410                                 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40);
 411                                 if (limit <= fifo_size) {
 412                                         pf->usb.support_in = 1;
 413                                 } else {
 414                                         pf->usb.is_simplex = 1;
 415                                         limit = 0;
 416                                 }
 417                         }
 418                         /* set FIFO size */
 419                         DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x),
 420                             ((limit / 4) << 16) | (tx_start / 4));
 421                         tx_start += limit;
 422                         fifo_size -= limit;
 423                         pf->usb.max_in_frame_size = limit;
 424                 } else {
 425                         pf->usb.is_simplex = 1;
 426                 }
 427
 428                 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x,
 429                     pf->usb.max_in_frame_size,
 430                     pf->usb.max_out_frame_size);
 431             }
 432
 433             /* enable proper device channel interrupts */
 434             sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK;
 435             sc->sc_irq_mask |= GINTMSK_IEPINTMSK;
 436             DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 437         }
 438
 439         /* reset RX FIFO */
 440         dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH);
 441
 442         if (mode != DWC_MODE_OTG) {
 443                 /* reset all TX FIFOs */
 444                 dwc_otg_tx_fifo_reset(sc,
 445                     GRSTCTL_TXFIFO(0x10) |
 446                     GRSTCTL_TXFFLSH);
 447         } else {
 448                 /* reset active endpoints */
 449                 sc->sc_active_rx_ep = 0;
 450
 451                 /* reset host channel state */
 452                 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
 453         }
 454         return (0);
 455 }
 456
 457 static uint8_t
 458 dwc_otg_uses_split(struct usb_device *udev)
 459 {
 460         /*
 461          * When a LOW or FULL speed device is connected directly to
 462          * the USB port we don't use split transactions:
 463          */
 464         return (udev->speed != USB_SPEED_HIGH &&
 465             udev->parent_hs_hub != NULL &&
 466             udev->parent_hs_hub->parent_hub != NULL);
 467 }
 468
 469 static void
 470 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc)
 471 {
 472
 473   /*
 474    * Disabled until further. Assuming that the register is already
 475    * programmed correctly by the boot loader.
 476    */
 477 #if 0
 478         uint32_t temp;
 479
 480         /* setup HOST frame interval register, based on existing value */
 481         temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK;
 482         if (temp >= 10000)
 483                 temp /= 1000;
 484         else
 485                 temp /= 125;
 486
 487         /* figure out nearest X-tal value */
 488         if (temp >= 54)
 489                 temp = 60;      /* MHz */
 490         else if (temp >= 39)
 491                 temp = 48;      /* MHz */
 492         else
 493                 temp = 30;      /* MHz */
 494
 495         if (sc->sc_flags.status_high_speed)
 496                 temp *= 125;
 497         else
 498                 temp *= 1000;
 499
 500         DPRINTF("HFIR=0x%08x\n", temp);
 501
 502         DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp);
 503 #endif
 504 }
 505
 506 static void
 507 dwc_otg_clocks_on(struct dwc_otg_softc *sc)
 508 {
 509         if (sc->sc_flags.clocks_off &&
 510             sc->sc_flags.port_powered) {
 511
 512                 DPRINTFN(5, "\n");
 513
 514                 /* TODO - platform specific */
 515
 516                 sc->sc_flags.clocks_off = 0;
 517         }
 518 }
 519
 520 static void
 521 dwc_otg_clocks_off(struct dwc_otg_softc *sc)
 522 {
 523         if (!sc->sc_flags.clocks_off) {
 524
 525                 DPRINTFN(5, "\n");
 526
 527                 /* TODO - platform specific */
 528
 529                 sc->sc_flags.clocks_off = 1;
 530         }
 531 }
 532
 533 static void
 534 dwc_otg_pull_up(struct dwc_otg_softc *sc)
 535 {
 536         uint32_t temp;
 537
 538         /* pullup D+, if possible */
 539
 540         if (!sc->sc_flags.d_pulled_up &&
 541             sc->sc_flags.port_powered) {
 542                 sc->sc_flags.d_pulled_up = 1;
 543
 544                 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
 545                 temp &= ~DCTL_SFTDISCON;
 546                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 547         }
 548 }
 549
 550 static void
 551 dwc_otg_pull_down(struct dwc_otg_softc *sc)
 552 {
 553         uint32_t temp;
 554
 555         /* pulldown D+, if possible */
 556
 557         if (sc->sc_flags.d_pulled_up) {
 558                 sc->sc_flags.d_pulled_up = 0;
 559
 560                 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
 561                 temp |= DCTL_SFTDISCON;
 562                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 563         }
 564 }
 565
 566 static void
 567 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc)
 568 {
 569         /* In device mode we don't use the SOF interrupt */
 570         if (sc->sc_flags.status_device_mode != 0)
 571                 return;
 572         /* Ensure the SOF interrupt is not disabled */
 573         sc->sc_needsof = 1;
 574         /* Check if the SOF interrupt is already enabled */
 575         if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0)
 576                 return;
 577         sc->sc_irq_mask |= GINTMSK_SOFMSK;
 578         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 579 }
 580
 581 static void
 582 dwc_otg_resume_irq(struct dwc_otg_softc *sc)
 583 {
 584         if (sc->sc_flags.status_suspend) {
 585                 /* update status bits */
 586                 sc->sc_flags.status_suspend = 0;
 587                 sc->sc_flags.change_suspend = 1;
 588
 589                 if (sc->sc_flags.status_device_mode) {
 590                         /*
 591                          * Disable resume interrupt and enable suspend
 592                          * interrupt:
 593                          */
 594                         sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK;
 595                         sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
 596                         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 597                 }
 598
 599                 /* complete root HUB interrupt endpoint */
 600                 dwc_otg_root_intr(sc);
 601         }
 602 }
 603
 604 static void
 605 dwc_otg_suspend_irq(struct dwc_otg_softc *sc)
 606 {
 607         if (!sc->sc_flags.status_suspend) {
 608                 /* update status bits */
 609                 sc->sc_flags.status_suspend = 1;
 610                 sc->sc_flags.change_suspend = 1;
 611
 612                 if (sc->sc_flags.status_device_mode) {
 613                         /*
 614                          * Disable suspend interrupt and enable resume
 615                          * interrupt:
 616                          */
 617                         sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK;
 618                         sc->sc_irq_mask |= GINTMSK_WKUPINTMSK;
 619                         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 620                 }
 621
 622                 /* complete root HUB interrupt endpoint */
 623                 dwc_otg_root_intr(sc);
 624         }
 625 }
 626
 627 static void
 628 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc)
 629 {
 630         if (!sc->sc_flags.status_suspend)
 631                 return;
 632
 633         DPRINTFN(5, "Remote wakeup\n");
 634
 635         if (sc->sc_flags.status_device_mode) {
 636                 uint32_t temp;
 637
 638                 /* enable remote wakeup signalling */
 639                 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
 640                 temp |= DCTL_RMTWKUPSIG;
 641                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 642
 643                 /* Wait 8ms for remote wakeup to complete. */
 644                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 645
 646                 temp &= ~DCTL_RMTWKUPSIG;
 647                 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
 648         } else {
 649                 /* enable USB port */
 650                 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0);
 651
 652                 /* wait 10ms */
 653                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
 654
 655                 /* resume port */
 656                 sc->sc_hprt_val |= HPRT_PRTRES;
 657                 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
 658
 659                 /* Wait 100ms for resume signalling to complete. */
 660                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
 661
 662                 /* clear suspend and resume */
 663                 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES);
 664                 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
 665
 666                 /* Wait 4ms */
 667                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
 668         }
 669
 670         /* need to fake resume IRQ */
 671         dwc_otg_resume_irq(sc);
 672 }
 673
 674 static void
 675 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr)
 676 {
 677         uint32_t temp;
 678
 679         DPRINTFN(5, "addr=%d\n", addr);
 680
 681         temp = DWC_OTG_READ_4(sc, DOTG_DCFG);
 682         temp &= ~DCFG_DEVADDR_SET(0x7F);
 683         temp |= DCFG_DEVADDR_SET(addr);
 684         DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp);
 685 }
 686
 687 static void
 688 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc)
 689 {
 690         DPRINTFN(5, "RX status clear\n");
 691
 692         /* enable RX FIFO level interrupt */
 693         sc->sc_irq_mask |= GINTMSK_RXFLVLMSK;
 694         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 695
 696         if (sc->sc_current_rx_bytes != 0) {
 697                 /* need to dump remaining data */
 698                 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
 699                     sc->sc_current_rx_fifo, sc->sc_bounce_buffer,
 700                     sc->sc_current_rx_bytes / 4);
 701                 /* clear number of active bytes to receive */
 702                 sc->sc_current_rx_bytes = 0;
 703         }
 704         /* clear cached status */
 705         sc->sc_last_rx_status = 0;
 706 }
 707
 708 static void
 709 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x)
 710 {
 711         uint32_t hcint;
 712
 713         /* clear all pending interrupts */
 714         hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
 715         DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint);
 716
 717         /* clear buffered interrupts */
 718         sc->sc_chan_state[x].hcint = 0;
 719 }
 720
 721 static uint8_t
 722 dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 723 {
 724         uint32_t temp;
 725
 726         temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
 727
 728         if (td->ep_type == UE_ISOCHRONOUS) {
 729                 /*
 730                  * NOTE: USB INTERRUPT transactions are executed like
 731                  * USB CONTROL transactions! See the setup standard
 732                  * chain function for more information.
 733                  */
 734                 if (!(temp & GINTSTS_PTXFEMP)) {
 735                         DPRINTF("Periodic TX FIFO is not empty\n");
 736                         if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) {
 737                                 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK;
 738                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 739                         }
 740                         return (1);     /* busy */
 741                 }
 742         } else {
 743                 if (!(temp & GINTSTS_NPTXFEMP)) {
 744                         DPRINTF("Non-periodic TX FIFO is not empty\n");
 745                         if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) {
 746                                 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK;
 747                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
 748                         }
 749                         return (1);     /* busy */
 750                 }
 751         }
 752         return (0);     /* ready for transmit */
 753 }
 754
 755 static uint8_t
 756 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc,
 757     struct dwc_otg_td *td, uint8_t is_out)
 758 {
 759         uint8_t x;
 760         uint8_t y;
 761         uint8_t z;
 762
 763         if (td->channel[0] < DWC_OTG_MAX_CHANNELS)
 764                 return (0);             /* already allocated */
 765
 766         /* check if device is suspended */
 767         if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
 768                 return (1);             /* busy - cannot transfer data */
 769
 770         /* compute needed TX FIFO size */
 771         if (is_out != 0) {
 772                 if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0)
 773                         return (1);     /* busy - cannot transfer data */
 774         }
 775         z = td->max_packet_count;
 776         for (x = y = 0; x != sc->sc_host_ch_max; x++) {
 777                 /* check if channel is allocated */
 778                 if (sc->sc_chan_state[x].allocated != 0)
 779                         continue;
 780                 /* check if channel is still enabled */
 781                 if (sc->sc_chan_state[x].wait_halted != 0)
 782                         continue;
 783                 /* store channel number */
 784                 td->channel[y++] = x;
 785                 /* check if we got all channels */
 786                 if (y == z)
 787                         break;
 788         }
 789         if (y != z) {
 790                 /* reset channel variable */
 791                 td->channel[0] = DWC_OTG_MAX_CHANNELS;
 792                 td->channel[1] = DWC_OTG_MAX_CHANNELS;
 793                 td->channel[2] = DWC_OTG_MAX_CHANNELS;
 794                 /* wait a bit */
 795                 dwc_otg_enable_sof_irq(sc);
 796                 return (1);     /* busy - not enough channels */
 797         }
 798
 799         for (y = 0; y != z; y++) {
 800                 x = td->channel[y];
 801
 802                 /* set allocated */
 803                 sc->sc_chan_state[x].allocated = 1;
 804
 805                 /* set wait halted */
 806                 sc->sc_chan_state[x].wait_halted = 1;
 807
 808                 /* clear interrupts */
 809                 dwc_otg_clear_hcint(sc, x);
 810
 811                 DPRINTF("CH=%d HCCHAR=0x%08x "
 812                     "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt);
 813
 814                 /* set active channel */
 815                 sc->sc_active_rx_ep |= (1 << x);
 816         }
 817         return (0);     /* allocated */
 818 }
 819
 820 static void
 821 dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index)
 822 {
 823         uint32_t hcchar;
 824         uint8_t x;
 825
 826         if (td->channel[index] >= DWC_OTG_MAX_CHANNELS)
 827                 return;         /* already freed */
 828
 829         /* free channel */
 830         x = td->channel[index];
 831         td->channel[index] = DWC_OTG_MAX_CHANNELS;
 832
 833         DPRINTF("CH=%d\n", x);
 834
 835         /*
 836          * We need to let programmed host channels run till complete
 837          * else the host channel will stop functioning.
 838          */
 839         sc->sc_chan_state[x].allocated = 0;
 840
 841         /* ack any pending messages */
 842         if (sc->sc_last_rx_status != 0 &&
 843             GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) {
 844                 dwc_otg_common_rx_ack(sc);
 845         }
 846
 847         /* clear active channel */
 848         sc->sc_active_rx_ep &= ~(1 << x);
 849
 850         /* check if already halted */
 851         if (sc->sc_chan_state[x].wait_halted == 0)
 852                 return;
 853
 854         /* disable host channel */
 855         hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x));
 856         if (hcchar & HCCHAR_CHENA) {
 857                 DPRINTF("Halting channel %d\n", x);
 858                 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x),
 859                     hcchar | HCCHAR_CHDIS);
 860                 /* don't write HCCHAR until the channel is halted */
 861         } else {
 862                 sc->sc_chan_state[x].wait_halted = 0;
 863         }
 864 }
 865
 866 static void
 867 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 868 {
 869         uint8_t x;
 870         for (x = 0; x != td->max_packet_count; x++)
 871                 dwc_otg_host_channel_free_sub(sc, td, x);
 872 }
 873
 874 static void
 875 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 876 {
 877         uint8_t x;
 878         /* dump any pending messages */
 879         if (sc->sc_last_rx_status == 0)
 880                 return;
 881         for (x = 0; x != td->max_packet_count; x++) {
 882                 if (td->channel[x] >= DWC_OTG_MAX_CHANNELS ||
 883                     td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status))
 884                         continue;
 885                 dwc_otg_common_rx_ack(sc);
 886                 break;
 887         }
 888 }
 889
 890 static uint8_t
 891 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
 892 {
 893         struct usb_device_request req __aligned(4);
 894         uint32_t hcint;
 895         uint32_t hcchar;
 896         uint8_t delta;
 897
 898         dwc_otg_host_dump_rx(sc, td);
 899
 900         if (td->channel[0] < DWC_OTG_MAX_CHANNELS) {
 901                 hcint = sc->sc_chan_state[td->channel[0]].hcint;
 902
 903                 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
 904                     td->channel[0], td->state, hcint,
 905                     DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])),
 906                     DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0])));
 907         } else {
 908                 hcint = 0;
 909                 goto check_state;
 910         }
 911
 912         if (hcint & (HCINT_RETRY |
 913             HCINT_ACK | HCINT_NYET)) {
 914                 /* give success bits priority over failure bits */
 915         } else if (hcint & HCINT_STALL) {
 916                 DPRINTF("CH=%d STALL\n", td->channel[0]);
 917                 td->error_stall = 1;
 918                 td->error_any = 1;
 919                 goto complete;
 920         } else if (hcint & HCINT_ERRORS) {
 921                 DPRINTF("CH=%d ERROR\n", td->channel[0]);
 922                 td->errcnt++;
 923                 if (td->hcsplt != 0 || td->errcnt >= 3) {
 924                         td->error_any = 1;
 925                         goto complete;
 926                 }
 927         }
 928
 929         if (hcint & (HCINT_ERRORS | HCINT_RETRY |
 930             HCINT_ACK | HCINT_NYET)) {
 931                 if (!(hcint & HCINT_ERRORS))
 932                         td->errcnt = 0;
 933         }
 934
 935 check_state:
 936         switch (td->state) {
 937         case DWC_CHAN_ST_START:
 938                 goto send_pkt;
 939
 940         case DWC_CHAN_ST_WAIT_ANE:
 941                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
 942                         td->did_nak = 1;
 943                         td->tt_scheduled = 0;
 944                         goto send_pkt;
 945                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
 946                         td->offset += td->tx_bytes;
 947                         td->remainder -= td->tx_bytes;
 948                         td->toggle = 1;
 949                         td->tt_scheduled = 0;
 950                         goto complete;
 951                 }
 952                 break;
 953
 954         case DWC_CHAN_ST_WAIT_S_ANE:
 955                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
 956                         td->did_nak = 1;
 957                         td->tt_scheduled = 0;
 958                         goto send_pkt;
 959                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
 960                         goto send_cpkt;
 961                 }
 962                 break;
 963
 964         case DWC_CHAN_ST_WAIT_C_ANE:
 965                 if (hcint & HCINT_NYET) {
 966                         goto send_cpkt;
 967                 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
 968                         td->did_nak = 1;
 969                         td->tt_scheduled = 0;
 970                         goto send_pkt;
 971                 } else if (hcint & HCINT_ACK) {
 972                         td->offset += td->tx_bytes;
 973                         td->remainder -= td->tx_bytes;
 974                         td->toggle = 1;
 975                         goto complete;
 976                 }
 977                 break;
 978
 979         case DWC_CHAN_ST_WAIT_C_PKT:
 980                 goto send_cpkt;
 981
 982         default:
 983                 break;
 984         }
 985         goto busy;
 986
 987 send_pkt:
 988         /* free existing channel, if any */
 989         dwc_otg_host_channel_free(sc, td);
 990
 991         if (sizeof(req) != td->remainder) {
 992                 td->error_any = 1;
 993                 goto complete;
 994         }
 995
 996         if (td->hcsplt != 0) {
 997                 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
 998                 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
 999                         td->state = DWC_CHAN_ST_START;
1000                         goto busy;
1001                 }
1002                 delta = sc->sc_last_frame_num - td->tt_start_slot;
1003                 if (delta > 5) {
1004                         /* missed it */
1005                         td->tt_scheduled = 0;
1006                         td->state = DWC_CHAN_ST_START;
1007                         goto busy;
1008                 }
1009         }
1010
1011         /* allocate a new channel */
1012         if (dwc_otg_host_channel_alloc(sc, td, 1)) {
1013                 td->state = DWC_CHAN_ST_START;
1014                 goto busy;
1015         }
1016
1017         if (td->hcsplt != 0) {
1018                 td->hcsplt &= ~HCSPLT_COMPSPLT;
1019                 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1020         } else {
1021                 td->state = DWC_CHAN_ST_WAIT_ANE;
1022         }
1023
1024         /* copy out control request */
1025         usbd_copy_out(td->pc, 0, &req, sizeof(req));
1026
1027         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1028             (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) |
1029             (1 << HCTSIZ_PKTCNT_SHIFT) |
1030             (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT));
1031
1032         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1033
1034         hcchar = td->hcchar;
1035         hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK);
1036         hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT;
1037
1038         /* must enable channel before writing data to FIFO */
1039         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1040
1041         /* transfer data into FIFO */
1042         bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
1043             DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4);
1044
1045         /* wait until next slot before trying complete split */
1046         td->tt_complete_slot = sc->sc_last_frame_num + 1;
1047
1048         /* store number of bytes transmitted */
1049         td->tx_bytes = sizeof(req);
1050         goto busy;
1051
1052 send_cpkt:
1053         /* free existing channel, if any */
1054         dwc_otg_host_channel_free(sc, td);
1055
1056         delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1057         if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1058                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1059                 goto busy;
1060         }
1061         delta = sc->sc_last_frame_num - td->tt_start_slot;
1062         if (delta > DWC_OTG_TT_SLOT_MAX) {
1063                 /* we missed the service interval */
1064                 if (td->ep_type != UE_ISOCHRONOUS)
1065                         td->error_any = 1;
1066                 goto complete;
1067         }
1068         /* allocate a new channel */
1069         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1070                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1071                 goto busy;
1072         }
1073
1074         /* wait until next slot before trying complete split */
1075         td->tt_complete_slot = sc->sc_last_frame_num + 1;
1076
1077         td->hcsplt |= HCSPLT_COMPSPLT;
1078         td->state = DWC_CHAN_ST_WAIT_C_ANE;
1079
1080         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1081             (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT));
1082
1083         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1084
1085         hcchar = td->hcchar;
1086         hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK);
1087         hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT;
1088
1089         /* must enable channel before writing data to FIFO */
1090         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1091
1092 busy:
1093         return (1);     /* busy */
1094
1095 complete:
1096         dwc_otg_host_channel_free(sc, td);
1097         return (0);     /* complete */
1098 }
1099
1100 static uint8_t
1101 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1102 {
1103         struct usb_device_request req __aligned(4);
1104         uint32_t temp;
1105         uint16_t count;
1106
1107         /* check endpoint status */
1108
1109         if (sc->sc_last_rx_status == 0)
1110                 goto not_complete;
1111
1112         if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0)
1113                 goto not_complete;
1114
1115         if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1116             GRXSTSRD_STP_DATA) {
1117                 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1118                     GRXSTSRD_STP_COMPLETE || td->remainder != 0) {
1119                         /* release FIFO */
1120                         dwc_otg_common_rx_ack(sc);
1121                         goto not_complete;
1122                 }
1123                 /* release FIFO */
1124                 dwc_otg_common_rx_ack(sc);
1125                 return (0);     /* complete */
1126         }
1127
1128         if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
1129             GRXSTSRD_DPID_DATA0) {
1130                 /* release FIFO */
1131                 dwc_otg_common_rx_ack(sc);
1132                 goto not_complete;
1133         }
1134
1135         DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status);
1136
1137         /* clear did stall */
1138         td->did_stall = 0;
1139
1140         /* get the packet byte count */
1141         count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1142
1143         if (count != sizeof(req)) {
1144                 DPRINTFN(0, "Unsupported SETUP packet "
1145                     "length, %d bytes\n", count);
1146                 /* release FIFO */
1147                 dwc_otg_common_rx_ack(sc);
1148                 goto not_complete;
1149         }
1150
1151         /* read FIFO */
1152         dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req));
1153
1154         /* copy out control request */
1155         usbd_copy_out(td->pc, 0, &req, sizeof(req));
1156
1157         td->offset = sizeof(req);
1158         td->remainder = 0;
1159
1160         /* sneak peek the set address */
1161         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1162             (req.bRequest == UR_SET_ADDRESS)) {
1163                 /* must write address before ZLP */
1164                 dwc_otg_set_address(sc, req.wValue[0] & 0x7F);
1165         }
1166
1167         /* don't send any data by default */
1168         DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS);
1169         DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS);
1170
1171         /* reset IN endpoint buffer */
1172         dwc_otg_tx_fifo_reset(sc,
1173             GRSTCTL_TXFIFO(0) |
1174             GRSTCTL_TXFFLSH);
1175
1176         /* acknowledge RX status */
1177         dwc_otg_common_rx_ack(sc);
1178         td->did_stall = 1;
1179
1180 not_complete:
1181         /* abort any ongoing transfer, before enabling again */
1182         if (!td->did_stall) {
1183                 td->did_stall = 1;
1184
1185                 DPRINTFN(5, "stalling IN and OUT direction\n");
1186
1187                 temp = sc->sc_out_ctl[0];
1188
1189                 /* set stall after enabling endpoint */
1190                 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0),
1191                     temp | DOEPCTL_STALL);
1192
1193                 temp = sc->sc_in_ctl[0];
1194
1195                 /* set stall assuming endpoint is enabled */
1196                 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0),
1197                     temp | DIEPCTL_STALL);
1198         }
1199         return (1);                     /* not complete */
1200 }
1201
1202 static uint8_t
1203 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1204 {
1205         uint8_t delta;
1206
1207         delta = sc->sc_tmr_val - td->tmr_val;
1208         if (delta >= 128)
1209                 return (1);     /* busy */
1210
1211         td->tmr_val = sc->sc_tmr_val + td->tmr_res;
1212
1213         /* set toggle, if any */
1214         if (td->set_toggle) {
1215                 td->set_toggle = 0;
1216                 td->toggle = 1;
1217         }
1218         return (0);
1219 }
1220
1221 static uint8_t
1222 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1223 {
1224         uint8_t frame_num = (uint8_t)sc->sc_last_frame_num;
1225
1226         if (td->ep_type == UE_ISOCHRONOUS) {
1227                 /* non TT isochronous traffic */
1228                 if (frame_num & (td->tmr_res - 1))
1229                         goto busy;
1230                 if ((frame_num ^ td->tmr_val) & td->tmr_res)
1231                         goto busy;
1232                 td->tmr_val = td->tmr_res + sc->sc_last_frame_num;
1233                 td->toggle = 0;
1234                 return (0);
1235         } else if (td->ep_type == UE_INTERRUPT) {
1236                 if (!td->tt_scheduled)
1237                         goto busy;
1238                 td->tt_scheduled = 0;
1239                 return (0);
1240         } else if (td->did_nak != 0) {
1241                 /* check if we should pause sending queries for 125us */
1242                 if (td->tmr_res == frame_num) {
1243                         /* wait a bit */
1244                         dwc_otg_enable_sof_irq(sc);
1245                         goto busy;
1246                 }
1247         } else if (td->set_toggle) {
1248                 td->set_toggle = 0;
1249                 td->toggle = 1;
1250         }
1251         /* query for data one more time */
1252         td->tmr_res = frame_num;
1253         td->did_nak = 0;
1254         return (0);
1255 busy:
1256         return (1);
1257 }
1258
1259 static uint8_t
1260 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td,
1261     uint8_t channel)
1262 {
1263         uint32_t count;
1264
1265         /* check endpoint status */
1266         if (sc->sc_last_rx_status == 0)
1267                 goto busy;
1268
1269         if (channel >= DWC_OTG_MAX_CHANNELS)
1270                 goto busy;
1271
1272         if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel)
1273                 goto busy;
1274
1275         switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) {
1276         case GRXSTSRH_IN_DATA:
1277
1278                 DPRINTF("DATA ST=%d STATUS=0x%08x\n",
1279                     (int)td->state, (int)sc->sc_last_rx_status);
1280
1281                 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) {
1282                         /*
1283                          * When using SPLIT transactions on interrupt
1284                          * endpoints, sometimes data occurs twice.
1285                          */
1286                         DPRINTF("Data already received\n");
1287                         break;
1288                 }
1289
1290                 /* get the packet byte count */
1291                 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1292
1293                 /* check for ISOCHRONOUS endpoint */
1294                 if (td->ep_type == UE_ISOCHRONOUS) {
1295                         if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
1296                             GRXSTSRD_DPID_DATA0) {
1297                                 /* more data to be received */
1298                                 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE;
1299                         } else {
1300                                 /* all data received */
1301                                 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
1302                                 /* verify the packet byte count */
1303                                 if (count != td->remainder) {
1304                                         /* we have a short packet */
1305                                         td->short_pkt = 1;
1306                                         td->got_short = 1;
1307                                 }
1308                         }
1309                 } else {
1310                         /* verify the packet byte count */
1311                         if (count != td->max_packet_size) {
1312                                 if (count < td->max_packet_size) {
1313                                         /* we have a short packet */
1314                                         td->short_pkt = 1;
1315                                         td->got_short = 1;
1316                                 } else {
1317                                         /* invalid USB packet */
1318                                         td->error_any = 1;
1319
1320                                         /* release FIFO */
1321                                         dwc_otg_common_rx_ack(sc);
1322                                         goto complete;
1323                                 }
1324                         }
1325                         td->toggle ^= 1;
1326                         td->tt_scheduled = 0;
1327                 }
1328
1329                 /* verify the packet byte count */
1330                 if (count > td->remainder) {
1331                         /* invalid USB packet */
1332                         td->error_any = 1;
1333
1334                         /* release FIFO */
1335                         dwc_otg_common_rx_ack(sc);
1336                         goto complete;
1337                 }
1338
1339                 /* read data from FIFO */
1340                 dwc_otg_read_fifo(sc, td->pc, td->offset, count);
1341
1342                 td->remainder -= count;
1343                 td->offset += count;
1344                 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY;
1345                 break;
1346         default:
1347                 break;
1348         }
1349         /* release FIFO */
1350         dwc_otg_common_rx_ack(sc);
1351 busy:
1352         return (0);
1353 complete:
1354         return (1);
1355 }
1356
1357 static uint8_t
1358 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1359 {
1360         uint32_t hcint = 0;
1361         uint32_t hcchar;
1362         uint8_t delta;
1363         uint8_t channel;
1364         uint8_t x;
1365
1366         for (x = 0; x != td->max_packet_count; x++) {
1367                 channel = td->channel[x];
1368                 if (channel >= DWC_OTG_MAX_CHANNELS)
1369                         continue;
1370                 hcint |= sc->sc_chan_state[channel].hcint;
1371
1372                 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
1373                     channel, td->state, hcint,
1374                     DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1375                     DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1376
1377                 /* check interrupt bits */
1378                 if (hcint & (HCINT_RETRY |
1379                     HCINT_ACK | HCINT_NYET)) {
1380                         /* give success bits priority over failure bits */
1381                 } else if (hcint & HCINT_STALL) {
1382                         DPRINTF("CH=%d STALL\n", channel);
1383                         td->error_stall = 1;
1384                         td->error_any = 1;
1385                         goto complete;
1386                 } else if (hcint & HCINT_ERRORS) {
1387                         DPRINTF("CH=%d ERROR\n", channel);
1388                         td->errcnt++;
1389                         if (td->hcsplt != 0 || td->errcnt >= 3) {
1390                                 if (td->ep_type != UE_ISOCHRONOUS) {
1391                                         td->error_any = 1;
1392                                         goto complete;
1393                                 }
1394                         }
1395                 }
1396
1397                 /* check channels for data, if any */
1398                 if (dwc_otg_host_data_rx_sub(sc, td, channel))
1399                         goto complete;
1400
1401                 /* refresh interrupt status */
1402                 hcint |= sc->sc_chan_state[channel].hcint;
1403
1404                 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
1405                     HCINT_ACK | HCINT_NYET)) {
1406                         if (!(hcint & HCINT_ERRORS))
1407                                 td->errcnt = 0;
1408                 }
1409         }
1410
1411         switch (td->state) {
1412         case DWC_CHAN_ST_START:
1413                 if (td->hcsplt != 0)
1414                         goto receive_spkt;
1415                 else
1416                         goto receive_pkt;
1417
1418         case DWC_CHAN_ST_WAIT_ANE:
1419                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1420                         if (td->ep_type == UE_INTERRUPT) {
1421                                 /*
1422                                  * The USB specification does not
1423                                  * mandate a particular data toggle
1424                                  * value for USB INTERRUPT
1425                                  * transfers. Switch the data toggle
1426                                  * value to receive the packet
1427                                  * correctly:
1428                                  */
1429                                 if (hcint & HCINT_DATATGLERR) {
1430                                         DPRINTF("Retrying packet due to "
1431                                             "data toggle error\n");
1432                                         td->toggle ^= 1;
1433                                         goto receive_pkt;
1434                                 }
1435                         } else if (td->ep_type == UE_ISOCHRONOUS) {
1436                                 if (td->hcsplt != 0) {
1437                                         /*
1438                                          * Sometimes the complete
1439                                          * split packet may be queued
1440                                          * too early and the
1441                                          * transaction translator will
1442                                          * return a NAK. Ignore
1443                                          * this message and retry the
1444                                          * complete split instead.
1445                                          */
1446                                         DPRINTF("Retrying complete split\n");
1447                                         goto receive_pkt;
1448                                 }
1449                                 goto complete;
1450                         }
1451                         td->did_nak = 1;
1452                         td->tt_scheduled = 0;
1453                         if (td->hcsplt != 0)
1454                                 goto receive_spkt;
1455                         else
1456                                 goto receive_pkt;
1457                 } else if (hcint & HCINT_NYET) {
1458                         if (td->hcsplt != 0) {
1459                                 /* try again */
1460                                 goto receive_pkt;
1461                         } else {
1462                                 /* not a valid token for IN endpoints */
1463                                 td->error_any = 1;
1464                                 goto complete;
1465                         }
1466                 } else if (hcint & HCINT_ACK) {
1467                         /* wait for data - ACK arrived first */
1468                         if (!(hcint & HCINT_SOFTWARE_ONLY))
1469                                 goto busy;
1470
1471                         if (td->ep_type == UE_ISOCHRONOUS) {
1472                                 /* check if we are complete */
1473                                 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) {
1474                                         goto complete;
1475                                 } else if (td->hcsplt != 0) {
1476                                         goto receive_pkt;
1477                                 } else {
1478                                         /* get more packets */
1479                                         goto busy;
1480                                 }
1481                         } else {
1482                                 /* check if we are complete */
1483                                 if ((td->remainder == 0) || (td->got_short != 0)) {
1484                                         if (td->short_pkt)
1485                                                 goto complete;
1486
1487                                         /*
1488                                          * Else need to receive a zero length
1489                                          * packet.
1490                                          */
1491                                 }
1492                                 td->tt_scheduled = 0;
1493                                 td->did_nak = 0;
1494                                 if (td->hcsplt != 0)
1495                                         goto receive_spkt;
1496                                 else
1497                                         goto receive_pkt;
1498                         }
1499                 }
1500                 break;
1501
1502         case DWC_CHAN_ST_WAIT_S_ANE:
1503                 /*
1504                  * NOTE: The DWC OTG hardware provides a fake ACK in
1505                  * case of interrupt and isochronous transfers:
1506                  */
1507                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1508                         td->did_nak = 1;
1509                         td->tt_scheduled = 0;
1510                         goto receive_spkt;
1511                 } else if (hcint & HCINT_NYET) {
1512                         td->tt_scheduled = 0;
1513                         goto receive_spkt;
1514                 } else if (hcint & HCINT_ACK) {
1515                         td->did_nak = 0;
1516                         goto receive_pkt;
1517                 }
1518                 break;
1519
1520         case DWC_CHAN_ST_WAIT_C_PKT:
1521                 goto receive_pkt;
1522
1523         default:
1524                 break;
1525         }
1526         goto busy;
1527
1528 receive_pkt:
1529         /* free existing channel, if any */
1530         dwc_otg_host_channel_free(sc, td);
1531
1532         if (td->hcsplt != 0) {
1533                 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1534                 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1535                         if (td->ep_type != UE_ISOCHRONOUS) {
1536                                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1537                                 goto busy;
1538                         }
1539                 }
1540                 delta = sc->sc_last_frame_num - td->tt_start_slot;
1541                 if (delta > DWC_OTG_TT_SLOT_MAX) {
1542                         if (td->ep_type != UE_ISOCHRONOUS) {
1543                                 /* we missed the service interval */
1544                                 td->error_any = 1;
1545                         }
1546                         goto complete;
1547                 }
1548                 /* complete split */
1549                 td->hcsplt |= HCSPLT_COMPSPLT;
1550         } else if (dwc_otg_host_rate_check(sc, td)) {
1551                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1552                 goto busy;
1553         }
1554
1555         /* allocate a new channel */
1556         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1557                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1558                 goto busy;
1559         }
1560
1561         /* set toggle, if any */
1562         if (td->set_toggle) {
1563                 td->set_toggle = 0;
1564                 td->toggle = 1;
1565         }
1566
1567         td->state = DWC_CHAN_ST_WAIT_ANE;
1568
1569         for (x = 0; x != td->max_packet_count; x++) {
1570                 channel = td->channel[x];
1571
1572                 /* receive one packet */
1573                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1574                     (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) |
1575                     (1 << HCTSIZ_PKTCNT_SHIFT) |
1576                     (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
1577                     (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
1578
1579                 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1580
1581                 hcchar = td->hcchar;
1582                 hcchar |= HCCHAR_EPDIR_IN;
1583
1584                 if (td->ep_type == UE_ISOCHRONOUS) {
1585                         if (td->hcsplt != 0) {
1586                                 /* continously buffer */
1587                                 if (sc->sc_last_frame_num & 1)
1588                                         hcchar &= ~HCCHAR_ODDFRM;
1589                                 else
1590                                         hcchar |= HCCHAR_ODDFRM;
1591                         } else {
1592                                 /* multi buffer, if any */
1593                                 if (sc->sc_last_frame_num & 1)
1594                                         hcchar |= HCCHAR_ODDFRM;
1595                                 else
1596                                         hcchar &= ~HCCHAR_ODDFRM;
1597                         }
1598                 } else {
1599                         hcchar &= ~HCCHAR_ODDFRM;
1600                 }
1601
1602                 /* must enable channel before data can be received */
1603                 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1604         }
1605         /* wait until next slot before trying complete split */
1606         td->tt_complete_slot = sc->sc_last_frame_num + 1;
1607
1608         goto busy;
1609
1610 receive_spkt:
1611         /* free existing channel(s), if any */
1612         dwc_otg_host_channel_free(sc, td);
1613
1614         delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1615         if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1616                 td->state = DWC_CHAN_ST_START;
1617                 goto busy;
1618         }
1619         delta = sc->sc_last_frame_num - td->tt_start_slot;
1620         if (delta > 5) {
1621                 /* missed it */
1622                 td->tt_scheduled = 0;
1623                 td->state = DWC_CHAN_ST_START;
1624                 goto busy;
1625         }
1626
1627         /* allocate a new channel */
1628         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1629                 td->state = DWC_CHAN_ST_START;
1630                 goto busy;
1631         }
1632
1633         channel = td->channel[0];
1634
1635         td->hcsplt &= ~HCSPLT_COMPSPLT;
1636         td->state = DWC_CHAN_ST_WAIT_S_ANE;
1637
1638         /* receive one packet */
1639         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1640             (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT));
1641
1642         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1643
1644         /* send after next SOF event */
1645         if ((sc->sc_last_frame_num & 1) == 0 &&
1646             td->ep_type == UE_ISOCHRONOUS)
1647                 td->hcchar |= HCCHAR_ODDFRM;
1648         else
1649                 td->hcchar &= ~HCCHAR_ODDFRM;
1650
1651         hcchar = td->hcchar;
1652         hcchar |= HCCHAR_EPDIR_IN;
1653
1654         /* wait until next slot before trying complete split */
1655         td->tt_complete_slot = sc->sc_last_frame_num + 1;
1656
1657         /* must enable channel before data can be received */
1658         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1659 busy:
1660         return (1);     /* busy */
1661
1662 complete:
1663         dwc_otg_host_channel_free(sc, td);
1664         return (0);     /* complete */
1665 }
1666
1667 static uint8_t
1668 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1669 {
1670         uint32_t temp;
1671         uint16_t count;
1672         uint8_t got_short;
1673
1674         got_short = 0;
1675
1676         /* check endpoint status */
1677         if (sc->sc_last_rx_status == 0)
1678                 goto not_complete;
1679
1680         if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no)
1681                 goto not_complete;
1682
1683         /* check for SETUP packet */
1684         if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1685             GRXSTSRD_STP_DATA ||
1686             (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1687             GRXSTSRD_STP_COMPLETE) {
1688                 if (td->remainder == 0) {
1689                         /*
1690                          * We are actually complete and have
1691                          * received the next SETUP
1692                          */
1693                         DPRINTFN(5, "faking complete\n");
1694                         return (0);     /* complete */
1695                 }
1696                 /*
1697                  * USB Host Aborted the transfer.
1698                  */
1699                 td->error_any = 1;
1700                 return (0);             /* complete */
1701         }
1702
1703         if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1704             GRXSTSRD_OUT_DATA) {
1705                 /* release FIFO */
1706                 dwc_otg_common_rx_ack(sc);
1707                 goto not_complete;
1708         }
1709
1710         /* get the packet byte count */
1711         count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1712
1713         /* verify the packet byte count */
1714         if (count != td->max_packet_size) {
1715                 if (count < td->max_packet_size) {
1716                         /* we have a short packet */
1717                         td->short_pkt = 1;
1718                         got_short = 1;
1719                 } else {
1720                         /* invalid USB packet */
1721                         td->error_any = 1;
1722
1723                         /* release FIFO */
1724                         dwc_otg_common_rx_ack(sc);
1725                         return (0);     /* we are complete */
1726                 }
1727         }
1728         /* verify the packet byte count */
1729         if (count > td->remainder) {
1730                 /* invalid USB packet */
1731                 td->error_any = 1;
1732
1733                 /* release FIFO */
1734                 dwc_otg_common_rx_ack(sc);
1735                 return (0);             /* we are complete */
1736         }
1737
1738         /* read data from FIFO */
1739         dwc_otg_read_fifo(sc, td->pc, td->offset, count);
1740
1741         td->remainder -= count;
1742         td->offset += count;
1743
1744         /* release FIFO */
1745         dwc_otg_common_rx_ack(sc);
1746
1747         temp = sc->sc_out_ctl[td->ep_no];
1748
1749         /* check for isochronous mode */
1750         if ((temp & DIEPCTL_EPTYPE_MASK) ==
1751             (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) {
1752                 /* toggle odd or even frame bit */
1753                 if (temp & DIEPCTL_SETD1PID) {
1754                         temp &= ~DIEPCTL_SETD1PID;
1755                         temp |= DIEPCTL_SETD0PID;
1756                 } else {
1757                         temp &= ~DIEPCTL_SETD0PID;
1758                         temp |= DIEPCTL_SETD1PID;
1759                 }
1760                 sc->sc_out_ctl[td->ep_no] = temp;
1761         }
1762
1763         /* check if we are complete */
1764         if ((td->remainder == 0) || got_short) {
1765                 if (td->short_pkt) {
1766                         /* we are complete */
1767                         return (0);
1768                 }
1769                 /* else need to receive a zero length packet */
1770         }
1771
1772 not_complete:
1773
1774         /* enable SETUP and transfer complete interrupt */
1775         if (td->ep_no == 0) {
1776                 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0),
1777                     DXEPTSIZ_SET_MULTI(3) |
1778                     DXEPTSIZ_SET_NPKT(1) |
1779                     DXEPTSIZ_SET_NBYTES(td->max_packet_size));
1780         } else {
1781                 /* allow reception of multiple packets */
1782                 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no),
1783                     DXEPTSIZ_SET_MULTI(1) |
1784                     DXEPTSIZ_SET_NPKT(4) |
1785                     DXEPTSIZ_SET_NBYTES(4 *
1786                         ((td->max_packet_size + 3) & ~3)));
1787         }
1788         temp = sc->sc_out_ctl[td->ep_no];
1789         DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp |
1790             DOEPCTL_EPENA | DOEPCTL_CNAK);
1791
1792         return (1);                     /* not complete */
1793 }
1794
1795 static uint8_t
1796 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1797 {
1798         uint32_t count;
1799         uint32_t hcint;
1800         uint32_t hcchar;
1801         uint8_t delta;
1802         uint8_t channel;
1803         uint8_t x;
1804
1805         dwc_otg_host_dump_rx(sc, td);
1806
1807         /* check that last channel is complete */
1808         channel = td->channel[td->npkt];
1809
1810         if (channel < DWC_OTG_MAX_CHANNELS) {
1811                 hcint = sc->sc_chan_state[channel].hcint;
1812
1813                 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
1814                     channel, td->state, hcint,
1815                     DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1816                     DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1817
1818                 if (hcint & (HCINT_RETRY |
1819                     HCINT_ACK | HCINT_NYET)) {
1820                         /* give success bits priority over failure bits */
1821                 } else if (hcint & HCINT_STALL) {
1822                         DPRINTF("CH=%d STALL\n", channel);
1823                         td->error_stall = 1;
1824                         td->error_any = 1;
1825                         goto complete;
1826                 } else if (hcint & HCINT_ERRORS) {
1827                         DPRINTF("CH=%d ERROR\n", channel);
1828                         td->errcnt++;
1829                         if (td->hcsplt != 0 || td->errcnt >= 3) {
1830                                 td->error_any = 1;
1831                                 goto complete;
1832                         }
1833                 }
1834
1835                 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
1836                     HCINT_ACK | HCINT_NYET)) {
1837
1838                         if (!(hcint & HCINT_ERRORS))
1839                                 td->errcnt = 0;
1840                 }
1841         } else {
1842                 hcint = 0;
1843         }
1844
1845         switch (td->state) {
1846         case DWC_CHAN_ST_START:
1847                 goto send_pkt;
1848
1849         case DWC_CHAN_ST_WAIT_ANE:
1850                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1851                         td->did_nak = 1;
1852                         td->tt_scheduled = 0;
1853                         goto send_pkt;
1854                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
1855                         td->offset += td->tx_bytes;
1856                         td->remainder -= td->tx_bytes;
1857                         td->toggle ^= 1;
1858                         /* check if next response will be a NAK */
1859                         if (hcint & HCINT_NYET)
1860                                 td->did_nak = 1;
1861                         else
1862                                 td->did_nak = 0;
1863                         td->tt_scheduled = 0;
1864
1865                         /* check remainder */
1866                         if (td->remainder == 0) {
1867                                 if (td->short_pkt)
1868                                         goto complete;
1869
1870                                 /*
1871                                  * Else we need to transmit a short
1872                                  * packet:
1873                                  */
1874                         }
1875                         goto send_pkt;
1876                 }
1877                 break;
1878
1879         case DWC_CHAN_ST_WAIT_S_ANE:
1880                 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1881                         td->did_nak = 1;
1882                         td->tt_scheduled = 0;
1883                         goto send_pkt;
1884                 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
1885                         td->did_nak = 0;
1886                         goto send_cpkt;
1887                 }
1888                 break;
1889
1890         case DWC_CHAN_ST_WAIT_C_ANE:
1891                 if (hcint & HCINT_NYET) {
1892                         goto send_cpkt;
1893                 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1894                         td->did_nak = 1;
1895                         td->tt_scheduled = 0;
1896                         goto send_pkt;
1897                 } else if (hcint & HCINT_ACK) {
1898                         td->offset += td->tx_bytes;
1899                         td->remainder -= td->tx_bytes;
1900                         td->toggle ^= 1;
1901                         td->did_nak = 0;
1902                         td->tt_scheduled = 0;
1903
1904                         /* check remainder */
1905                         if (td->remainder == 0) {
1906                                 if (td->short_pkt)
1907                                         goto complete;
1908
1909                                 /* else we need to transmit a short packet */
1910                         }
1911                         goto send_pkt;
1912                 }
1913                 break;
1914
1915         case DWC_CHAN_ST_WAIT_C_PKT:
1916                 goto send_cpkt;
1917
1918         case DWC_CHAN_ST_TX_WAIT_ISOC:
1919                 /* Check if ISOCHRONOUS OUT traffic is complete */
1920                 if ((hcint & HCINT_HCH_DONE_MASK) == 0)
1921                         break;
1922
1923                 td->offset += td->tx_bytes;
1924                 td->remainder -= td->tx_bytes;
1925                 goto complete;
1926         default:
1927                 break;
1928         }
1929         goto busy;
1930
1931 send_pkt:
1932         /* free existing channel(s), if any */
1933         dwc_otg_host_channel_free(sc, td);
1934
1935         if (td->hcsplt != 0) {
1936                 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1937                 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1938                         td->state = DWC_CHAN_ST_START;
1939                         goto busy;
1940                 }
1941                 delta = sc->sc_last_frame_num - td->tt_start_slot;
1942                 if (delta > 5) {
1943                         /* missed it */
1944                         td->tt_scheduled = 0;
1945                         td->state = DWC_CHAN_ST_START;
1946                         goto busy;
1947                 }
1948         } else if (dwc_otg_host_rate_check(sc, td)) {
1949                 td->state = DWC_CHAN_ST_START;
1950                 goto busy;
1951         }
1952
1953         /* allocate a new channel */
1954         if (dwc_otg_host_channel_alloc(sc, td, 1)) {
1955                 td->state = DWC_CHAN_ST_START;
1956                 goto busy;
1957         }
1958
1959         /* set toggle, if any */
1960         if (td->set_toggle) {
1961                 td->set_toggle = 0;
1962                 td->toggle = 1;
1963         }
1964
1965         if (td->ep_type == UE_ISOCHRONOUS) {
1966                 /* ISOCHRONOUS OUT transfers don't have any ACKs */
1967                 td->state = DWC_CHAN_ST_TX_WAIT_ISOC;
1968                 td->hcsplt &= ~HCSPLT_COMPSPLT;
1969                 if (td->hcsplt != 0) {
1970                         /* get maximum transfer length */
1971                         count = td->remainder;
1972                         if (count > HCSPLT_XACTLEN_BURST) {
1973                                 DPRINTF("TT overflow\n");
1974                                 td->error_any = 1;
1975                                 goto complete;
1976                         }
1977                         /* Update transaction position */
1978                         td->hcsplt &= ~HCSPLT_XACTPOS_MASK;
1979                         td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT);
1980                 }
1981         } else if (td->hcsplt != 0) {
1982                 td->hcsplt &= ~HCSPLT_COMPSPLT;
1983                 /* Wait for ACK/NAK/ERR from TT */
1984                 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1985         } else {
1986                 /* Wait for ACK/NAK/STALL from device */
1987                 td->state = DWC_CHAN_ST_WAIT_ANE;
1988         }
1989
1990         td->tx_bytes = 0;
1991
1992         for (x = 0; x != td->max_packet_count; x++) {
1993                 uint32_t rem_bytes;
1994
1995                 channel = td->channel[x];
1996
1997                 /* send one packet at a time */
1998                 count = td->max_packet_size;
1999                 rem_bytes = td->remainder - td->tx_bytes;
2000                 if (rem_bytes < count) {
2001                         /* we have a short packet */
2002                         td->short_pkt = 1;
2003                         count = rem_bytes;
2004                 }
2005                 if (count == rem_bytes) {
2006                         /* last packet */
2007                         switch (x) {
2008                         case 0:
2009                                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2010                                     (count << HCTSIZ_XFERSIZE_SHIFT) |
2011                                     (1 << HCTSIZ_PKTCNT_SHIFT) |
2012                                     (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
2013                                     (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
2014                                 break;
2015                         case 1:
2016                                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2017                                     (count << HCTSIZ_XFERSIZE_SHIFT) |
2018                                     (1 << HCTSIZ_PKTCNT_SHIFT) |
2019                                     (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT));
2020                                 break;
2021                         default:
2022                                 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2023                                     (count << HCTSIZ_XFERSIZE_SHIFT) |
2024                                     (1 << HCTSIZ_PKTCNT_SHIFT) |
2025                                     (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT));
2026                                 break;
2027                         }
2028                 } else if (td->ep_type == UE_ISOCHRONOUS &&
2029                            td->max_packet_count > 1) {
2030                         /* ISOCHRONOUS multi packet */
2031                         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2032                             (count << HCTSIZ_XFERSIZE_SHIFT) |
2033                             (1 << HCTSIZ_PKTCNT_SHIFT) |
2034                             (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT));
2035                 } else {
2036                         /* TODO: HCTSIZ_DOPNG */
2037                         /* standard BULK/INTERRUPT/CONTROL packet */
2038                         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2039                             (count << HCTSIZ_XFERSIZE_SHIFT) |
2040                             (1 << HCTSIZ_PKTCNT_SHIFT) |
2041                             (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
2042                             (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
2043                 }
2044
2045                 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2046
2047                 hcchar = td->hcchar;
2048                 hcchar &= ~HCCHAR_EPDIR_IN;
2049
2050                 /* send after next SOF event */
2051                 if ((sc->sc_last_frame_num & 1) == 0 &&
2052                     td->ep_type == UE_ISOCHRONOUS)
2053                         hcchar |= HCCHAR_ODDFRM;
2054                 else
2055                         hcchar &= ~HCCHAR_ODDFRM;
2056
2057                 /* must enable before writing data to FIFO */
2058                 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
2059
2060                 if (count != 0) {
2061                         /* write data into FIFO */
2062                         dwc_otg_write_fifo(sc, td->pc, td->offset +
2063                             td->tx_bytes, DOTG_DFIFO(channel), count);
2064                 }
2065
2066                 /* store number of bytes transmitted */
2067                 td->tx_bytes += count;
2068
2069                 /* store last packet index */
2070                 td->npkt = x;
2071
2072                 /* check for last packet */
2073                 if (count == rem_bytes)
2074                         break;
2075         }
2076         goto busy;
2077
2078 send_cpkt:
2079         /* free existing channel, if any */
2080         dwc_otg_host_channel_free(sc, td);
2081
2082         delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
2083         if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
2084                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
2085                 goto busy;
2086         }
2087         delta = sc->sc_last_frame_num - td->tt_start_slot;
2088         if (delta > DWC_OTG_TT_SLOT_MAX) {
2089                 /* we missed the service interval */
2090                 if (td->ep_type != UE_ISOCHRONOUS)
2091                         td->error_any = 1;
2092                 goto complete;
2093         }
2094
2095         /* allocate a new channel */
2096         if (dwc_otg_host_channel_alloc(sc, td, 0)) {
2097                 td->state = DWC_CHAN_ST_WAIT_C_PKT;
2098                 goto busy;
2099         }
2100
2101         channel = td->channel[0];
2102
2103         td->hcsplt |= HCSPLT_COMPSPLT;
2104         td->state = DWC_CHAN_ST_WAIT_C_ANE;
2105
2106         DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2107             (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT));
2108
2109         DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2110
2111         hcchar = td->hcchar;
2112         hcchar &= ~HCCHAR_EPDIR_IN;
2113
2114         /* receive complete split ASAP */
2115         if ((sc->sc_last_frame_num & 1) != 0 &&
2116             td->ep_type == UE_ISOCHRONOUS)
2117                 hcchar |= HCCHAR_ODDFRM;
2118         else
2119                 hcchar &= ~HCCHAR_ODDFRM;
2120
2121         /* must enable channel before data can be received */
2122         DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
2123
2124         /* wait until next slot before trying complete split */
2125         td->tt_complete_slot = sc->sc_last_frame_num + 1;
2126 busy:
2127         return (1);     /* busy */
2128
2129 complete:
2130         dwc_otg_host_channel_free(sc, td);
2131         return (0);     /* complete */
2132 }
2133
2134 static uint8_t
2135 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
2136 {
2137         uint32_t max_buffer;
2138         uint32_t count;
2139         uint32_t fifo_left;
2140         uint32_t mpkt;
2141         uint32_t temp;
2142         uint8_t to;
2143
2144         to = 3;                         /* don't loop forever! */
2145
2146         max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer;
2147
2148 repeat:
2149         /* check for for endpoint 0 data */
2150
2151         temp = sc->sc_last_rx_status;
2152
2153         if ((td->ep_no == 0) && (temp != 0) &&
2154             (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2155
2156                 if ((temp & GRXSTSRD_PKTSTS_MASK) !=
2157                     GRXSTSRD_STP_DATA &&
2158                     (temp & GRXSTSRD_PKTSTS_MASK) !=
2159                     GRXSTSRD_STP_COMPLETE) {
2160
2161                         /* dump data - wrong direction */
2162                         dwc_otg_common_rx_ack(sc);
2163                 } else {
2164                         /*
2165                          * The current transfer was cancelled
2166                          * by the USB Host:
2167                          */
2168                         td->error_any = 1;
2169                         return (0);             /* complete */
2170                 }
2171         }
2172
2173         /* fill in more TX data, if possible */
2174         if (td->tx_bytes != 0) {
2175
2176                 uint16_t cpkt;
2177
2178                 /* check if packets have been transferred */
2179                 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2180
2181                 /* get current packet number */
2182                 cpkt = DXEPTSIZ_GET_NPKT(temp);
2183
2184                 if (cpkt >= td->npkt) {
2185                         fifo_left = 0;
2186                 } else {
2187                         if (max_buffer != 0) {
2188                                 fifo_left = (td->npkt - cpkt) *
2189                                     td->max_packet_size;
2190
2191                                 if (fifo_left > max_buffer)
2192                                         fifo_left = max_buffer;
2193                         } else {
2194                                 fifo_left = td->max_packet_size;
2195                         }
2196                 }
2197
2198                 count = td->tx_bytes;
2199                 if (count > fifo_left)
2200                         count = fifo_left;
2201
2202                 if (count != 0) {
2203                         /* write data into FIFO */
2204                         dwc_otg_write_fifo(sc, td->pc, td->offset,
2205                             DOTG_DFIFO(td->ep_no), count);
2206
2207                         td->tx_bytes -= count;
2208                         td->remainder -= count;
2209                         td->offset += count;
2210                         td->npkt = cpkt;
2211                 }
2212                 if (td->tx_bytes != 0)
2213                         goto not_complete;
2214
2215                 /* check remainder */
2216                 if (td->remainder == 0) {
2217                         if (td->short_pkt)
2218                                 return (0);     /* complete */
2219
2220                         /* else we need to transmit a short packet */
2221                 }
2222         }
2223
2224         if (!to--)
2225                 goto not_complete;
2226
2227         /* check if not all packets have been transferred */
2228         temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2229
2230         if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2231
2232                 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x "
2233                     "DIEPCTL=0x%08x\n", td->ep_no,
2234                     DXEPTSIZ_GET_NPKT(temp),
2235                     temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no)));
2236
2237                 goto not_complete;
2238         }
2239
2240         DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no);
2241
2242         /* try to optimise by sending more data */
2243         if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) {
2244
2245                 /* send multiple packets at the same time */
2246                 mpkt = max_buffer / td->max_packet_size;
2247
2248                 if (mpkt > 0x3FE)
2249                         mpkt = 0x3FE;
2250
2251                 count = td->remainder;
2252                 if (count > 0x7FFFFF)
2253                         count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size);
2254
2255                 td->npkt = count / td->max_packet_size;
2256
2257                 /*
2258                  * NOTE: We could use 0x3FE instead of "mpkt" in the
2259                  * check below to get more throughput, but then we
2260                  * have a dependency towards non-generic chip features
2261                  * to disable the TX-FIFO-EMPTY interrupts on a per
2262                  * endpoint basis. Increase the maximum buffer size of
2263                  * the IN endpoint to increase the performance.
2264                  */
2265                 if (td->npkt > mpkt) {
2266                         td->npkt = mpkt;
2267                         count = td->max_packet_size * mpkt;
2268                 } else if ((count == 0) || (count % td->max_packet_size)) {
2269                         /* we are transmitting a short packet */
2270                         td->npkt++;
2271                         td->short_pkt = 1;
2272                 }
2273         } else {
2274                 /* send one packet at a time */
2275                 mpkt = 1;
2276                 count = td->max_packet_size;
2277                 if (td->remainder < count) {
2278                         /* we have a short packet */
2279                         td->short_pkt = 1;
2280                         count = td->remainder;
2281                 }
2282                 td->npkt = 1;
2283         }
2284         DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no),
2285             DXEPTSIZ_SET_MULTI(1) |
2286             DXEPTSIZ_SET_NPKT(td->npkt) |
2287             DXEPTSIZ_SET_NBYTES(count));
2288
2289         /* make room for buffering */
2290         td->npkt += mpkt;
2291
2292         temp = sc->sc_in_ctl[td->ep_no];
2293
2294         /* check for isochronous mode */
2295         if ((temp & DIEPCTL_EPTYPE_MASK) ==
2296             (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) {
2297                 /* toggle odd or even frame bit */
2298                 if (temp & DIEPCTL_SETD1PID) {
2299                         temp &= ~DIEPCTL_SETD1PID;
2300                         temp |= DIEPCTL_SETD0PID;
2301                 } else {
2302                         temp &= ~DIEPCTL_SETD0PID;
2303                         temp |= DIEPCTL_SETD1PID;
2304                 }
2305                 sc->sc_in_ctl[td->ep_no] = temp;
2306         }
2307
2308         /* must enable before writing data to FIFO */
2309         DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp |
2310             DIEPCTL_EPENA | DIEPCTL_CNAK);
2311
2312         td->tx_bytes = count;
2313
2314         /* check remainder */
2315         if (td->tx_bytes == 0 &&
2316             td->remainder == 0) {
2317                 if (td->short_pkt)
2318                         return (0);     /* complete */
2319
2320                 /* else we need to transmit a short packet */
2321         }
2322         goto repeat;
2323
2324 not_complete:
2325         return (1);                     /* not complete */
2326 }
2327
2328 static uint8_t
2329 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
2330 {
2331         uint32_t temp;
2332
2333         /*
2334          * If all packets are transferred we are complete:
2335          */
2336         temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2337
2338         /* check that all packets have been transferred */
2339         if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2340                 DPRINTFN(5, "busy ep=%d\n", td->ep_no);
2341                 goto not_complete;
2342         }
2343         return (0);
2344
2345 not_complete:
2346
2347         /* we only want to know if there is a SETUP packet or free IN packet */
2348
2349         temp = sc->sc_last_rx_status;
2350
2351         if ((td->ep_no == 0) && (temp != 0) &&
2352             (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2353
2354                 if ((temp & GRXSTSRD_PKTSTS_MASK) ==
2355                     GRXSTSRD_STP_DATA ||
2356                     (temp & GRXSTSRD_PKTSTS_MASK) ==
2357                     GRXSTSRD_STP_COMPLETE) {
2358                         DPRINTFN(5, "faking complete\n");
2359                         /*
2360                          * Race condition: We are complete!
2361                          */
2362                         return (0);
2363                 } else {
2364                         /* dump data - wrong direction */
2365                         dwc_otg_common_rx_ack(sc);
2366                 }
2367         }
2368         return (1);                     /* not complete */
2369 }
2370
2371 static void
2372 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer)
2373 {
2374         struct dwc_otg_td *td;
2375         uint8_t toggle;
2376         uint8_t tmr_val;
2377         uint8_t tmr_res;
2378
2379         DPRINTFN(9, "\n");
2380
2381         td = xfer->td_transfer_cache;
2382         if (td == NULL)
2383                 return;
2384
2385         while (1) {
2386                 if ((td->func) (sc, td)) {
2387                         /* operation in progress */
2388                         break;
2389                 }
2390                 if (((void *)td) == xfer->td_transfer_last) {
2391                         goto done;
2392                 }
2393                 if (td->error_any) {
2394                         goto done;
2395                 } else if (td->remainder > 0) {
2396                         /*
2397                          * We had a short transfer. If there is no alternate
2398                          * next, stop processing !
2399                          */
2400                         if (!td->alt_next)
2401                                 goto done;
2402                 }
2403
2404                 /*
2405                  * Fetch the next transfer descriptor and transfer
2406                  * some flags to the next transfer descriptor
2407                  */
2408                 tmr_res = td->tmr_res;
2409                 tmr_val = td->tmr_val;
2410                 toggle = td->toggle;
2411                 td = td->obj_next;
2412                 xfer->td_transfer_cache = td;
2413                 td->toggle = toggle;    /* transfer toggle */
2414                 td->tmr_res = tmr_res;
2415                 td->tmr_val = tmr_val;
2416         }
2417         return;
2418
2419 done:
2420         xfer->td_transfer_cache = NULL;
2421         sc->sc_xfer_complete = 1;
2422 }
2423
2424 static uint8_t
2425 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer)
2426 {
2427         struct dwc_otg_td *td;
2428
2429         DPRINTFN(9, "\n");
2430
2431         td = xfer->td_transfer_cache;
2432         if (td == NULL) {
2433                 /* compute all actual lengths */
2434                 dwc_otg_standard_done(xfer);
2435                 return (1);
2436         }
2437         return (0);
2438 }
2439
2440 static void
2441 dwc_otg_timer(void *_sc)
2442 {
2443         struct dwc_otg_softc *sc = _sc;
2444
2445         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2446
2447         DPRINTF("\n");
2448
2449         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2450
2451         /* increment timer value */
2452         sc->sc_tmr_val++;
2453
2454         /* enable SOF interrupt, which will poll jobs */
2455         dwc_otg_enable_sof_irq(sc);
2456
2457         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2458
2459         if (sc->sc_timer_active) {
2460                 /* restart timer */
2461                 usb_callout_reset(&sc->sc_timer,
2462                     hz / (1000 / DWC_OTG_HOST_TIMER_RATE),
2463                     &dwc_otg_timer, sc);
2464         }
2465 }
2466
2467 static void
2468 dwc_otg_timer_start(struct dwc_otg_softc *sc)
2469 {
2470         if (sc->sc_timer_active != 0)
2471                 return;
2472
2473         sc->sc_timer_active = 1;
2474
2475         /* restart timer */
2476         usb_callout_reset(&sc->sc_timer,
2477             hz / (1000 / DWC_OTG_HOST_TIMER_RATE),
2478             &dwc_otg_timer, sc);
2479 }
2480
2481 static void
2482 dwc_otg_timer_stop(struct dwc_otg_softc *sc)
2483 {
2484         if (sc->sc_timer_active == 0)
2485                 return;
2486
2487         sc->sc_timer_active = 0;
2488
2489         /* stop timer */
2490         usb_callout_stop(&sc->sc_timer);
2491 }
2492
2493 static uint16_t
2494 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo)
2495 {
2496         if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX)
2497                 pinfo->slot_index++;
2498         return (pinfo->slot_index);
2499 }
2500
2501 static uint8_t
2502 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc)
2503 {
2504         TAILQ_HEAD(, usb_xfer) head;
2505         struct usb_xfer *xfer;
2506         struct usb_xfer *xfer_next;
2507         struct dwc_otg_td *td;
2508         uint16_t temp;
2509         uint16_t slot;
2510
2511         temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK;
2512
2513         if (sc->sc_last_frame_num == temp)
2514                 return (0);
2515
2516         sc->sc_last_frame_num = temp;
2517
2518         TAILQ_INIT(&head);
2519
2520         if ((temp & 7) == 0) {
2521
2522                 /* reset the schedule */
2523                 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info));
2524
2525                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2526                         td = xfer->td_transfer_cache;
2527                         if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2528                                 continue;
2529
2530                         /* check for IN direction */
2531                         if ((td->hcchar & HCCHAR_EPDIR_IN) != 0)
2532                                 continue;
2533
2534                         sc->sc_needsof = 1;
2535
2536                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2537                                 continue;
2538
2539                         /* compute slot */
2540                         slot = dwc_otg_compute_isoc_rx_tt_slot(
2541                             sc->sc_tt_info + td->tt_index);
2542                         if (slot > 3) {
2543                                 /*
2544                                  * Not enough time to get complete
2545                                  * split executed.
2546                                  */
2547                                 continue;
2548                         }
2549                         /* Delayed start */
2550                         td->tt_start_slot = temp + slot;
2551                         td->tt_scheduled = 1;
2552                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2553                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2554                 }
2555
2556                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2557                         td = xfer->td_transfer_cache;
2558                         if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2559                                 continue;
2560
2561                         /* check for OUT direction */
2562                         if ((td->hcchar & HCCHAR_EPDIR_IN) == 0)
2563                                 continue;
2564
2565                         sc->sc_needsof = 1;
2566
2567                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2568                                 continue;
2569
2570                         /* Start ASAP */
2571                         td->tt_start_slot = temp;
2572                         td->tt_scheduled = 1;
2573                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2574                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2575                 }
2576
2577                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2578                         td = xfer->td_transfer_cache;
2579                         if (td == NULL || td->ep_type != UE_INTERRUPT)
2580                                 continue;
2581
2582                         if (td->tt_scheduled != 0) {
2583                                 sc->sc_needsof = 1;
2584                                 continue;
2585                         }
2586
2587                         if (dwc_otg_host_rate_check_interrupt(sc, td))
2588                                 continue;
2589
2590                         if (td->hcsplt == 0) {
2591                                 sc->sc_needsof = 1;
2592                                 td->tt_scheduled = 1;
2593                                 continue;
2594                         }
2595
2596                         /* start ASAP */
2597                         td->tt_start_slot = temp;
2598                         sc->sc_needsof = 1;
2599                         td->tt_scheduled = 1;
2600                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2601                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2602                 }
2603
2604                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2605                         td = xfer->td_transfer_cache;
2606                         if (td == NULL ||
2607                             td->ep_type != UE_CONTROL) {
2608                                 continue;
2609                         }
2610
2611                         sc->sc_needsof = 1;
2612
2613                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2614                                 continue;
2615
2616                         /* start ASAP */
2617                         td->tt_start_slot = temp;
2618                         td->tt_scheduled = 1;
2619                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2620                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2621                 }
2622         }
2623         if ((temp & 7) < 6) {
2624                 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2625                         td = xfer->td_transfer_cache;
2626                         if (td == NULL ||
2627                             td->ep_type != UE_BULK) {
2628                                 continue;
2629                         }
2630
2631                         sc->sc_needsof = 1;
2632
2633                         if (td->hcsplt == 0 || td->tt_scheduled != 0)
2634                                 continue;
2635
2636                         /* start ASAP */
2637                         td->tt_start_slot = temp;
2638                         td->tt_scheduled = 1;
2639                         TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2640                         TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2641                 }
2642         }
2643
2644         /* Put TT transfers in execution order at the end */
2645         TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2646
2647         /* move all TT transfers in front, keeping the current order */
2648         TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2649                 td = xfer->td_transfer_cache;
2650                 if (td == NULL || td->hcsplt == 0)
2651                         continue;
2652                 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2653                 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2654         }
2655         TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry);
2656         TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2657
2658         /* put non-TT non-ISOCHRONOUS transfers last */
2659         TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2660                 td = xfer->td_transfer_cache;
2661                 if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS)
2662                         continue;
2663                 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2664                 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2665         }
2666         TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2667
2668         if ((temp & 7) == 0) {
2669
2670                 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n",
2671                     (int)temp, (int)sc->sc_needsof);
2672
2673                 /* update SOF IRQ mask */
2674                 if (sc->sc_irq_mask & GINTMSK_SOFMSK) {
2675                         if (sc->sc_needsof == 0) {
2676                                 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2677                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2678                         }
2679                 } else {
2680                         if (sc->sc_needsof != 0) {
2681                                 sc->sc_irq_mask |= GINTMSK_SOFMSK;
2682                                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2683                         }
2684                 }
2685
2686                 /* clear need SOF flag */
2687                 sc->sc_needsof = 0;
2688         }
2689         return (1);
2690 }
2691
2692 static void
2693 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc)
2694 {
2695         struct usb_xfer *xfer;
2696         uint32_t count;
2697         uint32_t temp;
2698         uint32_t haint;
2699         uint8_t got_rx_status;
2700         uint8_t x;
2701
2702         if (sc->sc_flags.status_device_mode == 0) {
2703                 /*
2704                  * Update host transfer schedule, so that new
2705                  * transfers can be issued:
2706                  */
2707                 dwc_otg_update_host_transfer_schedule_locked(sc);
2708         }
2709         count = 0;
2710 repeat:
2711         if (++count == 16) {
2712                 /* give other interrupts a chance */
2713                 DPRINTF("Yield\n");
2714                 return;
2715         }
2716
2717         /* get all host channel interrupts */
2718         haint = DWC_OTG_READ_4(sc, DOTG_HAINT);
2719         while (1) {
2720                 x = ffs(haint) - 1;
2721                 if (x >= sc->sc_host_ch_max)
2722                         break;
2723                 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
2724                 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp);
2725                 temp &= ~HCINT_SOFTWARE_ONLY;
2726                 sc->sc_chan_state[x].hcint |= temp;
2727                 haint &= ~(1U << x);
2728         }
2729
2730         if (sc->sc_last_rx_status == 0) {
2731
2732                 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2733                 if (temp & GINTSTS_RXFLVL) {
2734                         /* pop current status */
2735                         sc->sc_last_rx_status =
2736                             DWC_OTG_READ_4(sc, DOTG_GRXSTSPD);
2737                 }
2738
2739                 if (sc->sc_last_rx_status != 0) {
2740
2741                         uint8_t ep_no;
2742
2743                         temp = sc->sc_last_rx_status &
2744                             GRXSTSRD_PKTSTS_MASK;
2745
2746                         /* non-data messages we simply skip */
2747                         if (temp != GRXSTSRD_STP_DATA &&
2748                             temp != GRXSTSRD_STP_COMPLETE &&
2749                             temp != GRXSTSRD_OUT_DATA) {
2750                                 /* check for halted channel */
2751                                 if (temp == GRXSTSRH_HALTED) {
2752                                         ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status);
2753                                         sc->sc_chan_state[ep_no].wait_halted = 0;
2754                                         DPRINTFN(5, "channel halt complete ch=%u\n", ep_no);
2755                                 }
2756                                 /* store bytes and FIFO offset */
2757                                 sc->sc_current_rx_bytes = 0;
2758                                 sc->sc_current_rx_fifo = 0;
2759
2760                                 /* acknowledge status */
2761                                 dwc_otg_common_rx_ack(sc);
2762                                 goto repeat;
2763                         }
2764
2765                         temp = GRXSTSRD_BCNT_GET(
2766                             sc->sc_last_rx_status);
2767                         ep_no = GRXSTSRD_CHNUM_GET(
2768                             sc->sc_last_rx_status);
2769
2770                         /* store bytes and FIFO offset */
2771                         sc->sc_current_rx_bytes = (temp + 3) & ~3;
2772                         sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no);
2773
2774                         DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no);
2775
2776                         /* check if we should dump the data */
2777                         if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2778                                 dwc_otg_common_rx_ack(sc);
2779                                 goto repeat;
2780                         }
2781
2782                         got_rx_status = 1;
2783
2784                         DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n",
2785                             sc->sc_last_rx_status, ep_no,
2786                             (sc->sc_last_rx_status >> 15) & 3,
2787                             GRXSTSRD_BCNT_GET(sc->sc_last_rx_status),
2788                             (sc->sc_last_rx_status >> 17) & 15);
2789                 } else {
2790                         got_rx_status = 0;
2791                 }
2792         } else {
2793                 uint8_t ep_no;
2794
2795                 ep_no = GRXSTSRD_CHNUM_GET(
2796                     sc->sc_last_rx_status);
2797
2798                 /* check if we should dump the data */
2799                 if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2800                         dwc_otg_common_rx_ack(sc);
2801                         goto repeat;
2802                 }
2803
2804                 got_rx_status = 1;
2805         }
2806
2807         /* execute FIFOs */
2808         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
2809                 dwc_otg_xfer_do_fifo(sc, xfer);
2810
2811         if (got_rx_status) {
2812                 /* check if data was consumed */
2813                 if (sc->sc_last_rx_status == 0)
2814                         goto repeat;
2815
2816                 /* disable RX FIFO level interrupt */
2817                 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK;
2818                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2819         }
2820 }
2821
2822 static void
2823 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc)
2824 {
2825         struct usb_xfer *xfer;
2826 repeat:
2827         /* scan for completion events */
2828         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2829                 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
2830                         goto repeat;
2831         }
2832 }
2833
2834 static void
2835 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on)
2836 {
2837         DPRINTFN(5, "vbus = %u\n", is_on);
2838
2839         /*
2840          * If the USB host mode is forced, then assume VBUS is always
2841          * present else rely on the input to this function:
2842          */
2843         if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) {
2844
2845                 if (!sc->sc_flags.status_vbus) {
2846                         sc->sc_flags.status_vbus = 1;
2847
2848                         /* complete root HUB interrupt endpoint */
2849
2850                         dwc_otg_root_intr(sc);
2851                 }
2852         } else {
2853                 if (sc->sc_flags.status_vbus) {
2854                         sc->sc_flags.status_vbus = 0;
2855                         sc->sc_flags.status_bus_reset = 0;
2856                         sc->sc_flags.status_suspend = 0;
2857                         sc->sc_flags.change_suspend = 0;
2858                         sc->sc_flags.change_connect = 1;
2859
2860                         /* complete root HUB interrupt endpoint */
2861
2862                         dwc_otg_root_intr(sc);
2863                 }
2864         }
2865 }
2866
2867 int
2868 dwc_otg_filter_interrupt(void *arg)
2869 {
2870         struct dwc_otg_softc *sc = arg;
2871         int retval = FILTER_HANDLED;
2872         uint32_t status;
2873
2874         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2875
2876         /* read and clear interrupt status */
2877         status = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2878
2879         /* clear interrupts we are handling here */
2880         DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ);
2881
2882         /* check for USB state change interrupts */
2883         if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0)
2884                 retval = FILTER_SCHEDULE_THREAD;
2885
2886         /* clear FIFO empty interrupts */
2887         if (status & sc->sc_irq_mask &
2888             (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) {
2889                 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
2890                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2891         }
2892         /* clear all IN endpoint interrupts */
2893         if (status & GINTSTS_IEPINT) {
2894                 uint32_t temp;
2895                 uint8_t x;
2896
2897                 for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
2898                         temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x));
2899                         /*
2900                          * NOTE: Need to clear all interrupt bits,
2901                          * because some appears to be unmaskable and
2902                          * can cause an interrupt loop:
2903                          */
2904                         if (temp != 0)
2905                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp);
2906                 }
2907         }
2908
2909         /* poll FIFOs, if any */
2910         dwc_otg_interrupt_poll_locked(sc);
2911
2912         if (sc->sc_xfer_complete != 0)
2913                 retval = FILTER_SCHEDULE_THREAD;
2914
2915         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2916
2917         return (retval);
2918 }
2919
2920 void
2921 dwc_otg_interrupt(void *arg)
2922 {
2923         struct dwc_otg_softc *sc = arg;
2924         uint32_t status;
2925
2926         USB_BUS_LOCK(&sc->sc_bus);
2927         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2928
2929         /* read and clear interrupt status */
2930         status = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2931
2932         /* clear interrupts we are handling here */
2933         DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ);
2934
2935         DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n",
2936             status, DWC_OTG_READ_4(sc, DOTG_HAINT),
2937             DWC_OTG_READ_4(sc, DOTG_HFNUM));
2938
2939         if (status & GINTSTS_USBRST) {
2940
2941                 /* set correct state */
2942                 sc->sc_flags.status_device_mode = 1;
2943                 sc->sc_flags.status_bus_reset = 0;
2944                 sc->sc_flags.status_suspend = 0;
2945                 sc->sc_flags.change_suspend = 0;
2946                 sc->sc_flags.change_connect = 1;
2947
2948                 /* Disable SOF interrupt */
2949                 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2950                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2951
2952                 /* complete root HUB interrupt endpoint */
2953                 dwc_otg_root_intr(sc);
2954         }
2955
2956         /* check for any bus state change interrupts */
2957         if (status & GINTSTS_ENUMDONE) {
2958
2959                 uint32_t temp;
2960
2961                 DPRINTFN(5, "end of reset\n");
2962
2963                 /* set correct state */
2964                 sc->sc_flags.status_device_mode = 1;
2965                 sc->sc_flags.status_bus_reset = 1;
2966                 sc->sc_flags.status_suspend = 0;
2967                 sc->sc_flags.change_suspend = 0;
2968                 sc->sc_flags.change_connect = 1;
2969                 sc->sc_flags.status_low_speed = 0;
2970                 sc->sc_flags.port_enabled = 1;
2971
2972                 /* reset FIFOs */
2973                 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE);
2974
2975                 /* reset function address */
2976                 dwc_otg_set_address(sc, 0);
2977
2978                 /* figure out enumeration speed */
2979                 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
2980                 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI)
2981                         sc->sc_flags.status_high_speed = 1;
2982                 else
2983                         sc->sc_flags.status_high_speed = 0;
2984
2985                 /*
2986                  * Disable resume and SOF interrupt, and enable
2987                  * suspend and RX frame interrupt:
2988                  */
2989                 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK);
2990                 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
2991                 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2992
2993                 /* complete root HUB interrupt endpoint */
2994                 dwc_otg_root_intr(sc);
2995         }
2996
2997         if (status & GINTSTS_PRTINT) {
2998                 uint32_t hprt;
2999
3000                 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT);
3001
3002                 /* clear change bits */
3003                 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & (
3004                     HPRT_PRTPWR | HPRT_PRTENCHNG |
3005                     HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) |
3006                     sc->sc_hprt_val);
3007
3008                 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt);
3009
3010                 sc->sc_flags.status_device_mode = 0;
3011
3012                 if (hprt & HPRT_PRTCONNSTS)
3013                         sc->sc_flags.status_bus_reset = 1;
3014                 else
3015                         sc->sc_flags.status_bus_reset = 0;
3016
3017                 if ((hprt & HPRT_PRTENCHNG) &&
3018                     (hprt & HPRT_PRTENA) == 0)
3019                         sc->sc_flags.change_enabled = 1;
3020
3021                 if (hprt & HPRT_PRTENA)
3022                         sc->sc_flags.port_enabled = 1;
3023                 else
3024                         sc->sc_flags.port_enabled = 0;
3025
3026                 if (hprt & HPRT_PRTOVRCURRCHNG)
3027                         sc->sc_flags.change_over_current = 1;
3028
3029                 if (hprt & HPRT_PRTOVRCURRACT)
3030                         sc->sc_flags.port_over_current = 1;
3031                 else
3032                         sc->sc_flags.port_over_current = 0;
3033
3034                 if (hprt & HPRT_PRTPWR)
3035                         sc->sc_flags.port_powered = 1;
3036                 else
3037                         sc->sc_flags.port_powered = 0;
3038
3039                 if (((hprt & HPRT_PRTSPD_MASK)
3040                     >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW)
3041                         sc->sc_flags.status_low_speed = 1;
3042                 else
3043                         sc->sc_flags.status_low_speed = 0;
3044
3045                 if (((hprt & HPRT_PRTSPD_MASK)
3046                     >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH)
3047                         sc->sc_flags.status_high_speed = 1;
3048                 else
3049                         sc->sc_flags.status_high_speed = 0;
3050
3051                 if (hprt & HPRT_PRTCONNDET)
3052                         sc->sc_flags.change_connect = 1;
3053
3054                 if (hprt & HPRT_PRTSUSP)
3055                         dwc_otg_suspend_irq(sc);
3056                 else
3057                         dwc_otg_resume_irq(sc);
3058
3059                 /* complete root HUB interrupt endpoint */
3060                 dwc_otg_root_intr(sc);
3061
3062                 /* update host frame interval */
3063                 dwc_otg_update_host_frame_interval(sc);
3064         }
3065
3066         /*
3067          * If resume and suspend is set at the same time we interpret
3068          * that like RESUME. Resume is set when there is at least 3
3069          * milliseconds of inactivity on the USB BUS.
3070          */
3071         if (status & GINTSTS_WKUPINT) {
3072
3073                 DPRINTFN(5, "resume interrupt\n");
3074
3075                 dwc_otg_resume_irq(sc);
3076
3077         } else if (status & GINTSTS_USBSUSP) {
3078
3079                 DPRINTFN(5, "suspend interrupt\n");
3080
3081                 dwc_otg_suspend_irq(sc);
3082         }
3083         /* check VBUS */
3084         if (status & (GINTSTS_USBSUSP |
3085             GINTSTS_USBRST |
3086             GINTMSK_OTGINTMSK |
3087             GINTSTS_SESSREQINT)) {
3088                 uint32_t temp;
3089
3090                 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
3091
3092                 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp);
3093
3094                 dwc_otg_vbus_interrupt(sc,
3095                     (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
3096         }
3097
3098         if (sc->sc_xfer_complete != 0) {
3099                 sc->sc_xfer_complete = 0;
3100
3101                 /* complete FIFOs, if any */
3102                 dwc_otg_interrupt_complete_locked(sc);
3103         }
3104         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3105         USB_BUS_UNLOCK(&sc->sc_bus);
3106 }
3107
3108 static void
3109 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp)
3110 {
3111         struct dwc_otg_td *td;
3112
3113         /* get current Transfer Descriptor */
3114         td = temp->td_next;
3115         temp->td = td;
3116
3117         /* prepare for next TD */
3118         temp->td_next = td->obj_next;
3119
3120         /* fill out the Transfer Descriptor */
3121         td->func = temp->func;
3122         td->pc = temp->pc;
3123         td->offset = temp->offset;
3124         td->remainder = temp->len;
3125         td->tx_bytes = 0;
3126         td->error_any = 0;
3127         td->error_stall = 0;
3128         td->npkt = 0;
3129         td->did_stall = temp->did_stall;
3130         td->short_pkt = temp->short_pkt;
3131         td->alt_next = temp->setup_alt_next;
3132         td->set_toggle = 0;
3133         td->got_short = 0;
3134         td->did_nak = 0;
3135         td->channel[0] = DWC_OTG_MAX_CHANNELS;
3136         td->channel[1] = DWC_OTG_MAX_CHANNELS;
3137         td->channel[2] = DWC_OTG_MAX_CHANNELS;
3138         td->state = 0;
3139         td->errcnt = 0;
3140         td->tt_scheduled = 0;
3141         td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
3142 }
3143
3144 static void
3145 dwc_otg_setup_standard_chain(struct usb_xfer *xfer)
3146 {
3147         struct dwc_otg_std_temp temp;
3148         struct dwc_otg_td *td;
3149         uint32_t x;
3150         uint8_t need_sync;
3151         uint8_t is_host;
3152
3153         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
3154             xfer->address, UE_GET_ADDR(xfer->endpointno),
3155             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
3156
3157         temp.max_frame_size = xfer->max_frame_size;
3158
3159         td = xfer->td_start[0];
3160         xfer->td_transfer_first = td;
3161         xfer->td_transfer_cache = td;
3162
3163         /* setup temp */
3164
3165         temp.pc = NULL;
3166         temp.td = NULL;
3167         temp.td_next = xfer->td_start[0];
3168         temp.offset = 0;
3169         temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
3170             xfer->flags_int.isochronous_xfr;
3171         temp.did_stall = !xfer->flags_int.control_stall;
3172
3173         is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
3174
3175         /* check if we should prepend a setup message */
3176
3177         if (xfer->flags_int.control_xfr) {
3178                 if (xfer->flags_int.control_hdr) {
3179
3180                         if (is_host)
3181                                 temp.func = &dwc_otg_host_setup_tx;
3182                         else
3183                                 temp.func = &dwc_otg_setup_rx;
3184
3185                         temp.len = xfer->frlengths[0];
3186                         temp.pc = xfer->frbuffers + 0;
3187                         temp.short_pkt = temp.len ? 1 : 0;
3188
3189                         /* check for last frame */
3190                         if (xfer->nframes == 1) {
3191                                 /* no STATUS stage yet, SETUP is last */
3192                                 if (xfer->flags_int.control_act)
3193                                         temp.setup_alt_next = 0;
3194                         }
3195
3196                         dwc_otg_setup_standard_chain_sub(&temp);
3197                 }
3198                 x = 1;
3199         } else {
3200                 x = 0;
3201         }
3202
3203         if (x != xfer->nframes) {
3204                 if (xfer->endpointno & UE_DIR_IN) {
3205                         if (is_host) {
3206                                 temp.func = &dwc_otg_host_data_rx;
3207                                 need_sync = 0;
3208                         } else {
3209                                 temp.func = &dwc_otg_data_tx;
3210                                 need_sync = 1;
3211                         }
3212                 } else {
3213                         if (is_host) {
3214                                 temp.func = &dwc_otg_host_data_tx;
3215                                 need_sync = 0;
3216                         } else {
3217                                 temp.func = &dwc_otg_data_rx;
3218                                 need_sync = 0;
3219                         }
3220                 }
3221
3222                 /* setup "pc" pointer */
3223                 temp.pc = xfer->frbuffers + x;
3224         } else {
3225                 need_sync = 0;
3226         }
3227         while (x != xfer->nframes) {
3228
3229                 /* DATA0 / DATA1 message */
3230
3231                 temp.len = xfer->frlengths[x];
3232
3233                 x++;
3234
3235                 if (x == xfer->nframes) {
3236                         if (xfer->flags_int.control_xfr) {
3237                                 if (xfer->flags_int.control_act) {
3238                                         temp.setup_alt_next = 0;
3239                                 }
3240                         } else {
3241                                 temp.setup_alt_next = 0;
3242                         }
3243                 }
3244                 if (temp.len == 0) {
3245
3246                         /* make sure that we send an USB packet */
3247
3248                         temp.short_pkt = 0;
3249
3250                 } else {
3251
3252                         /* regular data transfer */
3253
3254                         temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
3255                 }
3256
3257                 dwc_otg_setup_standard_chain_sub(&temp);
3258
3259                 if (xfer->flags_int.isochronous_xfr) {
3260                         temp.offset += temp.len;
3261                 } else {
3262                         /* get next Page Cache pointer */
3263                         temp.pc = xfer->frbuffers + x;
3264                 }
3265         }
3266
3267         if (xfer->flags_int.control_xfr) {
3268
3269                 /* always setup a valid "pc" pointer for status and sync */
3270                 temp.pc = xfer->frbuffers + 0;
3271                 temp.len = 0;
3272                 temp.short_pkt = 0;
3273                 temp.setup_alt_next = 0;
3274
3275                 /* check if we need to sync */
3276                 if (need_sync) {
3277                         /* we need a SYNC point after TX */
3278                         temp.func = &dwc_otg_data_tx_sync;
3279                         dwc_otg_setup_standard_chain_sub(&temp);
3280                 }
3281
3282                 /* check if we should append a status stage */
3283                 if (!xfer->flags_int.control_act) {
3284
3285                         /*
3286                          * Send a DATA1 message and invert the current
3287                          * endpoint direction.
3288                          */
3289                         if (xfer->endpointno & UE_DIR_IN) {
3290                                 if (is_host) {
3291                                         temp.func = &dwc_otg_host_data_tx;
3292                                         need_sync = 0;
3293                                 } else {
3294                                         temp.func = &dwc_otg_data_rx;
3295                                         need_sync = 0;
3296                                 }
3297                         } else {
3298                                 if (is_host) {
3299                                         temp.func = &dwc_otg_host_data_rx;
3300                                         need_sync = 0;
3301                                 } else {
3302                                         temp.func = &dwc_otg_data_tx;
3303                                         need_sync = 1;
3304                                 }
3305                         }
3306
3307                         dwc_otg_setup_standard_chain_sub(&temp);
3308
3309                         /* data toggle should be DATA1 */
3310                         td = temp.td;
3311                         td->set_toggle = 1;
3312
3313                         if (need_sync) {
3314                                 /* we need a SYNC point after TX */
3315                                 temp.func = &dwc_otg_data_tx_sync;
3316                                 dwc_otg_setup_standard_chain_sub(&temp);
3317                         }
3318                 }
3319         } else {
3320                 /* check if we need to sync */
3321                 if (need_sync) {
3322
3323                         temp.pc = xfer->frbuffers + 0;
3324                         temp.len = 0;
3325                         temp.short_pkt = 0;
3326                         temp.setup_alt_next = 0;
3327
3328                         /* we need a SYNC point after TX */
3329                         temp.func = &dwc_otg_data_tx_sync;
3330                         dwc_otg_setup_standard_chain_sub(&temp);
3331                 }
3332         }
3333
3334         /* must have at least one frame! */
3335         td = temp.td;
3336         xfer->td_transfer_last = td;
3337
3338         if (is_host) {
3339
3340                 struct dwc_otg_softc *sc;
3341                 uint32_t hcchar;
3342                 uint32_t hcsplt;
3343
3344                 sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3345
3346                 /* get first again */
3347                 td = xfer->td_transfer_first;
3348                 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
3349
3350                 hcchar =
3351                         (xfer->address << HCCHAR_DEVADDR_SHIFT) |
3352                         ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) |
3353                         (xfer->max_packet_size << HCCHAR_MPS_SHIFT) |
3354                         HCCHAR_CHENA;
3355
3356                 /*
3357                  * We are not always able to meet the timing
3358                  * requirements of the USB interrupt endpoint's
3359                  * complete split token, when doing transfers going
3360                  * via a transaction translator. Use the CONTROL
3361                  * transfer type instead of the INTERRUPT transfer
3362                  * type in general, as a means to workaround
3363                  * that. This trick should work for both FULL and LOW
3364                  * speed USB traffic going through a TT. For non-TT
3365                  * traffic it works as well. The reason for using
3366                  * CONTROL type instead of BULK is that some TTs might
3367                  * reject LOW speed BULK traffic.
3368                  */
3369                 if (td->ep_type == UE_INTERRUPT)
3370                         hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT);
3371                 else
3372                         hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT);
3373
3374                 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
3375                         hcchar |= HCCHAR_EPDIR_IN;
3376
3377                 switch (xfer->xroot->udev->speed) {
3378                 case USB_SPEED_LOW:
3379                         hcchar |= HCCHAR_LSPDDEV;
3380                         /* FALLTHROUGH */
3381                 case USB_SPEED_FULL:
3382                         /* check if root HUB port is running High Speed */
3383                         if (dwc_otg_uses_split(xfer->xroot->udev)) {
3384                                 hcsplt = HCSPLT_SPLTENA |
3385                                     (xfer->xroot->udev->hs_port_no <<
3386                                     HCSPLT_PRTADDR_SHIFT) |
3387                                     (xfer->xroot->udev->hs_hub_addr <<
3388                                     HCSPLT_HUBADDR_SHIFT);
3389                         } else {
3390                                 hcsplt = 0;
3391                         }
3392                         if (td->ep_type == UE_INTERRUPT) {
3393                                 uint32_t ival;
3394                                 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3395                                 if (ival == 0)
3396                                         ival = 1;
3397                                 else if (ival > 127)
3398                                         ival = 127;
3399                                 td->tmr_val = sc->sc_tmr_val + ival;
3400                                 td->tmr_res = ival;
3401                         } else if (td->ep_type == UE_ISOCHRONOUS) {
3402                                 td->tmr_res = 1;
3403                                 td->tmr_val = sc->sc_last_frame_num;
3404                                 if (td->hcchar & HCCHAR_EPDIR_IN)
3405                                         td->tmr_val++;
3406                         } else {
3407                                 td->tmr_val = 0;
3408                                 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3409                         }
3410                         break;
3411                 case USB_SPEED_HIGH:
3412                         hcsplt = 0;
3413                         if (td->ep_type == UE_INTERRUPT) {
3414                                 uint32_t ival;
3415                                 hcchar |= ((xfer->max_packet_count & 3)
3416                                     << HCCHAR_MC_SHIFT);
3417                                 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3418                                 if (ival == 0)
3419                                         ival = 1;
3420                                 else if (ival > 127)
3421                                         ival = 127;
3422                                 td->tmr_val = sc->sc_tmr_val + ival;
3423                                 td->tmr_res = ival;
3424                         } else if (td->ep_type == UE_ISOCHRONOUS) {
3425                                 hcchar |= ((xfer->max_packet_count & 3)
3426                                     << HCCHAR_MC_SHIFT);
3427                                 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer);
3428                                 td->tmr_val = sc->sc_last_frame_num;
3429                                 if (td->hcchar & HCCHAR_EPDIR_IN)
3430                                         td->tmr_val += td->tmr_res;
3431
3432                         } else {
3433                                 td->tmr_val = 0;
3434                                 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3435                         }
3436                         break;
3437                 default:
3438                         hcsplt = 0;
3439                         td->tmr_val = 0;
3440                         td->tmr_res = 0;
3441                         break;
3442                 }
3443
3444                 /* store configuration in all TD's */
3445                 while (1) {
3446                         td->hcchar = hcchar;
3447                         td->hcsplt = hcsplt;
3448
3449                         if (((void *)td) == xfer->td_transfer_last)
3450                                 break;
3451
3452                         td = td->obj_next;
3453                 }
3454         }
3455 }
3456
3457 static void
3458 dwc_otg_timeout(void *arg)
3459 {
3460         struct usb_xfer *xfer = arg;
3461
3462         DPRINTF("xfer=%p\n", xfer);
3463
3464         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
3465
3466         /* transfer is transferred */
3467         dwc_otg_device_done(xfer, USB_ERR_TIMEOUT);
3468 }
3469
3470 static void
3471 dwc_otg_start_standard_chain(struct usb_xfer *xfer)
3472 {
3473         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3474
3475         DPRINTFN(9, "\n");
3476
3477         /*
3478          * Poll one time in device mode, which will turn on the
3479          * endpoint interrupts. Else wait for SOF interrupt in host
3480          * mode.
3481          */
3482         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3483
3484         if (sc->sc_flags.status_device_mode != 0) {
3485                 dwc_otg_xfer_do_fifo(sc, xfer);
3486                 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
3487                         goto done;
3488         } else {
3489                 struct dwc_otg_td *td = xfer->td_transfer_cache;
3490                 if (td->ep_type == UE_ISOCHRONOUS &&
3491                     (td->hcchar & HCCHAR_EPDIR_IN) == 0) {
3492                         /*
3493                          * Need to start ISOCHRONOUS OUT transfer ASAP
3494                          * because execution is delayed by one 125us
3495                          * microframe:
3496                          */
3497                         dwc_otg_xfer_do_fifo(sc, xfer);
3498                         if (dwc_otg_xfer_do_complete_locked(sc, xfer))
3499                                 goto done;
3500                 }
3501         }
3502
3503         /* put transfer on interrupt queue */
3504         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3505
3506         /* start timeout, if any */
3507         if (xfer->timeout != 0) {
3508                 usbd_transfer_timeout_ms(xfer,
3509                     &dwc_otg_timeout, xfer->timeout);
3510         }
3511
3512         if (sc->sc_flags.status_device_mode != 0)
3513                 goto done;
3514
3515         /* enable SOF interrupt, if any */
3516         dwc_otg_enable_sof_irq(sc);
3517 done:
3518         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3519 }
3520
3521 static void
3522 dwc_otg_root_intr(struct dwc_otg_softc *sc)
3523 {
3524         DPRINTFN(9, "\n");
3525
3526         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3527
3528         /* set port bit */
3529         sc->sc_hub_idata[0] = 0x02;     /* we only have one port */
3530
3531         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3532             sizeof(sc->sc_hub_idata));
3533 }
3534
3535 static usb_error_t
3536 dwc_otg_standard_done_sub(struct usb_xfer *xfer)
3537 {
3538         struct dwc_otg_td *td;
3539         uint32_t len;
3540         usb_error_t error;
3541
3542         DPRINTFN(9, "\n");
3543
3544         td = xfer->td_transfer_cache;
3545
3546         do {
3547                 len = td->remainder;
3548
3549                 /* store last data toggle */
3550                 xfer->endpoint->toggle_next = td->toggle;
3551
3552                 if (xfer->aframes != xfer->nframes) {
3553                         /*
3554                          * Verify the length and subtract
3555                          * the remainder from "frlengths[]":
3556                          */
3557                         if (len > xfer->frlengths[xfer->aframes]) {
3558                                 td->error_any = 1;
3559                         } else {
3560                                 xfer->frlengths[xfer->aframes] -= len;
3561                         }
3562                 }
3563                 /* Check for transfer error */
3564                 if (td->error_any) {
3565                         /* the transfer is finished */
3566                         error = (td->error_stall ?
3567                             USB_ERR_STALLED : USB_ERR_IOERROR);
3568                         td = NULL;
3569                         break;
3570                 }
3571                 /* Check for short transfer */
3572                 if (len > 0) {
3573                         if (xfer->flags_int.short_frames_ok ||
3574                             xfer->flags_int.isochronous_xfr) {
3575                                 /* follow alt next */
3576                                 if (td->alt_next) {
3577                                         td = td->obj_next;
3578                                 } else {
3579                                         td = NULL;
3580                                 }
3581                         } else {
3582                                 /* the transfer is finished */
3583                                 td = NULL;
3584                         }
3585                         error = 0;
3586                         break;
3587                 }
3588                 td = td->obj_next;
3589
3590                 /* this USB frame is complete */
3591                 error = 0;
3592                 break;
3593
3594         } while (0);
3595
3596         /* update transfer cache */
3597
3598         xfer->td_transfer_cache = td;
3599
3600         return (error);
3601 }
3602
3603 static void
3604 dwc_otg_standard_done(struct usb_xfer *xfer)
3605 {
3606         usb_error_t err = 0;
3607
3608         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
3609             xfer, xfer->endpoint);
3610
3611         /* reset scanner */
3612
3613         xfer->td_transfer_cache = xfer->td_transfer_first;
3614
3615         if (xfer->flags_int.control_xfr) {
3616
3617                 if (xfer->flags_int.control_hdr) {
3618
3619                         err = dwc_otg_standard_done_sub(xfer);
3620                 }
3621                 xfer->aframes = 1;
3622
3623                 if (xfer->td_transfer_cache == NULL) {
3624                         goto done;
3625                 }
3626         }
3627         while (xfer->aframes != xfer->nframes) {
3628
3629                 err = dwc_otg_standard_done_sub(xfer);
3630                 xfer->aframes++;
3631
3632                 if (xfer->td_transfer_cache == NULL) {
3633                         goto done;
3634                 }
3635         }
3636
3637         if (xfer->flags_int.control_xfr &&
3638             !xfer->flags_int.control_act) {
3639
3640                 err = dwc_otg_standard_done_sub(xfer);
3641         }
3642 done:
3643         dwc_otg_device_done(xfer, err);
3644 }
3645
3646 /*------------------------------------------------------------------------*
3647  *      dwc_otg_device_done
3648  *
3649  * NOTE: this function can be called more than one time on the
3650  * same USB transfer!
3651  *------------------------------------------------------------------------*/
3652 static void
3653 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
3654 {
3655         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3656
3657         DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
3658             xfer, xfer->endpoint, error);
3659
3660         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3661
3662         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
3663                 /* Interrupts are cleared by the interrupt handler */
3664         } else {
3665                 struct dwc_otg_td *td;
3666
3667                 td = xfer->td_transfer_cache;
3668                 if (td != NULL)
3669                         dwc_otg_host_channel_free(sc, td);
3670         }
3671         /* dequeue transfer and start next transfer */
3672         usbd_transfer_done(xfer, error);
3673
3674         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3675 }
3676
3677 static void
3678 dwc_otg_xfer_stall(struct usb_xfer *xfer)
3679 {
3680         dwc_otg_device_done(xfer, USB_ERR_STALLED);
3681 }
3682
3683 static void
3684 dwc_otg_set_stall(struct usb_device *udev,
3685     struct usb_endpoint *ep, uint8_t *did_stall)
3686 {
3687         struct dwc_otg_softc *sc;
3688         uint32_t temp;
3689         uint32_t reg;
3690         uint8_t ep_no;
3691
3692         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3693
3694         /* check mode */
3695         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3696                 /* not supported */
3697                 return;
3698         }
3699
3700         sc = DWC_OTG_BUS2SC(udev->bus);
3701
3702         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3703
3704         /* get endpoint address */
3705         ep_no = ep->edesc->bEndpointAddress;
3706
3707         DPRINTFN(5, "endpoint=0x%x\n", ep_no);
3708
3709         if (ep_no & UE_DIR_IN) {
3710                 reg = DOTG_DIEPCTL(ep_no & UE_ADDR);
3711                 temp = sc->sc_in_ctl[ep_no & UE_ADDR];
3712         } else {
3713                 reg = DOTG_DOEPCTL(ep_no & UE_ADDR);
3714                 temp = sc->sc_out_ctl[ep_no & UE_ADDR];
3715         }
3716
3717         /* disable and stall endpoint */
3718         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3719         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL);
3720
3721         /* clear active OUT ep */
3722         if (!(ep_no & UE_DIR_IN)) {
3723
3724                 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR));
3725
3726                 if (sc->sc_last_rx_status != 0 &&
3727                     (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET(
3728                     sc->sc_last_rx_status)) {
3729                         /* dump data */
3730                         dwc_otg_common_rx_ack(sc);
3731                         /* poll interrupt */
3732                         dwc_otg_interrupt_poll_locked(sc);
3733                         dwc_otg_interrupt_complete_locked(sc);
3734                 }
3735         }
3736         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3737 }
3738
3739 static void
3740 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps,
3741     uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
3742 {
3743         uint32_t reg;
3744         uint32_t temp;
3745
3746         if (ep_type == UE_CONTROL) {
3747                 /* clearing stall is not needed */
3748                 return;
3749         }
3750
3751         if (ep_dir) {
3752                 reg = DOTG_DIEPCTL(ep_no);
3753         } else {
3754                 reg = DOTG_DOEPCTL(ep_no);
3755                 sc->sc_active_rx_ep |= (1U << ep_no);
3756         }
3757
3758         /* round up and mask away the multiplier count */
3759         mps = (mps + 3) & 0x7FC;
3760
3761         if (ep_type == UE_BULK) {
3762                 temp = DIEPCTL_EPTYPE_SET(
3763                     DIEPCTL_EPTYPE_BULK) |
3764                     DIEPCTL_USBACTEP;
3765         } else if (ep_type == UE_INTERRUPT) {
3766                 temp = DIEPCTL_EPTYPE_SET(
3767                     DIEPCTL_EPTYPE_INTERRUPT) |
3768                     DIEPCTL_USBACTEP;
3769         } else {
3770                 temp = DIEPCTL_EPTYPE_SET(
3771                     DIEPCTL_EPTYPE_ISOC) |
3772                     DIEPCTL_USBACTEP;
3773         }
3774
3775         temp |= DIEPCTL_MPS_SET(mps);
3776         temp |= DIEPCTL_TXFNUM_SET(ep_no);
3777
3778         if (ep_dir)
3779                 sc->sc_in_ctl[ep_no] = temp;
3780         else
3781                 sc->sc_out_ctl[ep_no] = temp;
3782
3783         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3784         DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID);
3785         DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK);
3786
3787         /* we only reset the transmit FIFO */
3788         if (ep_dir) {
3789                 dwc_otg_tx_fifo_reset(sc,
3790                     GRSTCTL_TXFIFO(ep_no) |
3791                     GRSTCTL_TXFFLSH);
3792
3793                 DWC_OTG_WRITE_4(sc,
3794                     DOTG_DIEPTSIZ(ep_no), 0);
3795         }
3796
3797         /* poll interrupt */
3798         dwc_otg_interrupt_poll_locked(sc);
3799         dwc_otg_interrupt_complete_locked(sc);
3800 }
3801
3802 static void
3803 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3804 {
3805         struct dwc_otg_softc *sc;
3806         struct usb_endpoint_descriptor *ed;
3807
3808         DPRINTFN(5, "endpoint=%p\n", ep);
3809
3810         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3811
3812         /* check mode */
3813         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3814                 /* not supported */
3815                 return;
3816         }
3817         /* get softc */
3818         sc = DWC_OTG_BUS2SC(udev->bus);
3819
3820         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3821
3822         /* get endpoint descriptor */
3823         ed = ep->edesc;
3824
3825         /* reset endpoint */
3826         dwc_otg_clear_stall_sub_locked(sc,
3827             UGETW(ed->wMaxPacketSize),
3828             (ed->bEndpointAddress & UE_ADDR),
3829             (ed->bmAttributes & UE_XFERTYPE),
3830             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3831
3832         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3833 }
3834
3835 static void
3836 dwc_otg_device_state_change(struct usb_device *udev)
3837 {
3838         struct dwc_otg_softc *sc;
3839         uint8_t x;
3840
3841         /* check mode */
3842         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3843                 /* not supported */
3844                 return;
3845         }
3846
3847         /* get softc */
3848         sc = DWC_OTG_BUS2SC(udev->bus);
3849
3850         /* deactivate all other endpoint but the control endpoint */
3851         if (udev->state == USB_STATE_CONFIGURED ||
3852             udev->state == USB_STATE_ADDRESSED) {
3853
3854                 USB_BUS_LOCK(&sc->sc_bus);
3855
3856                 for (x = 1; x != sc->sc_dev_ep_max; x++) {
3857
3858                         if (x < sc->sc_dev_in_ep_max) {
3859                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x),
3860                                     DIEPCTL_EPDIS);
3861                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0);
3862                         }
3863
3864                         DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x),
3865                             DOEPCTL_EPDIS);
3866                         DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0);
3867                 }
3868                 USB_BUS_UNLOCK(&sc->sc_bus);
3869         }
3870 }
3871
3872 int
3873 dwc_otg_init(struct dwc_otg_softc *sc)
3874 {
3875         uint32_t temp;
3876
3877         DPRINTF("start\n");
3878
3879         /* set up the bus structure */
3880         sc->sc_bus.usbrev = USB_REV_2_0;
3881         sc->sc_bus.methods = &dwc_otg_bus_methods;
3882
3883         usb_callout_init_mtx(&sc->sc_timer,
3884             &sc->sc_bus.bus_mtx, 0);
3885
3886         USB_BUS_LOCK(&sc->sc_bus);
3887
3888         /* turn on clocks */
3889         dwc_otg_clocks_on(sc);
3890
3891         temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID);
3892         DPRINTF("Version = 0x%08x\n", temp);
3893
3894         /* disconnect */
3895         DWC_OTG_WRITE_4(sc, DOTG_DCTL,
3896             DCTL_SFTDISCON);
3897
3898         /* wait for host to detect disconnect */
3899         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32);
3900
3901         DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
3902             GRSTCTL_CSFTRST);
3903
3904         /* wait a little bit for block to reset */
3905         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128);
3906
3907         switch (sc->sc_mode) {
3908         case DWC_MODE_DEVICE:
3909                 temp = GUSBCFG_FORCEDEVMODE;
3910                 break;
3911         case DWC_MODE_HOST:
3912                 temp = GUSBCFG_FORCEHOSTMODE;
3913                 break;
3914         default:
3915                 temp = 0;
3916                 break;
3917         }
3918
3919         if (sc->sc_phy_type == 0)
3920                 sc->sc_phy_type = dwc_otg_phy_type + 1;
3921         if (sc->sc_phy_bits == 0)
3922                 sc->sc_phy_bits = 16;
3923
3924         /* select HSIC, ULPI, UTMI+ or internal PHY mode */
3925         switch (sc->sc_phy_type) {
3926         case DWC_OTG_PHY_HSIC:
3927                 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3928                     GUSBCFG_PHYIF |
3929                     GUSBCFG_TRD_TIM_SET(5) | temp);
3930                 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL,
3931                     0x000000EC);
3932
3933                 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3934                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3935                     temp & ~GLPMCFG_HSIC_CONN);
3936                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3937                     temp | GLPMCFG_HSIC_CONN);
3938                 break;
3939         case DWC_OTG_PHY_ULPI:
3940                 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3941                     GUSBCFG_ULPI_UTMI_SEL |
3942                     GUSBCFG_TRD_TIM_SET(5) | temp);
3943                 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3944
3945                 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3946                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3947                     temp & ~GLPMCFG_HSIC_CONN);
3948                 break;
3949         case DWC_OTG_PHY_UTMI:
3950                 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3951                     (sc->sc_phy_bits == 16 ? GUSBCFG_PHYIF : 0) |
3952                     GUSBCFG_TRD_TIM_SET(5) | temp);
3953                 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3954
3955                 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3956                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3957                     temp & ~GLPMCFG_HSIC_CONN);
3958                 break;
3959         case DWC_OTG_PHY_INTERNAL:
3960                 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3961                     GUSBCFG_PHYSEL |
3962                     GUSBCFG_TRD_TIM_SET(5) | temp);
3963                 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3964
3965                 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3966                 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3967                     temp & ~GLPMCFG_HSIC_CONN);
3968
3969                 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO);
3970                 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN);
3971                 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN |
3972                     DOTG_GGPIO_PWRDWN);
3973                 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp);
3974                 break;
3975         default:
3976                 break;
3977         }
3978
3979         /* clear global nak */
3980         DWC_OTG_WRITE_4(sc, DOTG_DCTL,
3981             DCTL_CGOUTNAK |
3982             DCTL_CGNPINNAK);
3983
3984         /* disable USB port */
3985         DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF);
3986
3987         /* wait 10ms */
3988         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3989
3990         /* enable USB port */
3991         DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0);
3992
3993         /* wait 10ms */
3994         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3995
3996         temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3);
3997
3998         sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp);
3999
4000         temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
4001
4002         sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp);
4003
4004         if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS)
4005                 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS;
4006
4007         sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp);
4008
4009         if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS)
4010                 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS;
4011
4012         temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4);
4013
4014         sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp);
4015
4016         DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n",
4017             sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max,
4018             sc->sc_host_ch_max);
4019
4020         /* setup FIFO */
4021         if (dwc_otg_init_fifo(sc, sc->sc_mode)) {
4022                 USB_BUS_UNLOCK(&sc->sc_bus);
4023                 return (EINVAL);
4024         }
4025
4026         /* enable interrupts */
4027         sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ;
4028         DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
4029
4030         if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) {
4031
4032                 /* enable all endpoint interrupts */
4033                 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
4034                 if (temp & GHWCFG2_MPI) {
4035                         uint8_t x;
4036
4037                         DPRINTF("Disable Multi Process Interrupts\n");
4038
4039                         for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
4040                                 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0);
4041                                 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0);
4042                         }
4043                         DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0);
4044                 }
4045                 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK,
4046                     DIEPMSK_XFERCOMPLMSK);
4047                 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0);
4048                 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF);
4049         }
4050
4051         if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) {
4052                 /* setup clocks */
4053                 temp = DWC_OTG_READ_4(sc, DOTG_HCFG);
4054                 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK);
4055                 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT);
4056                 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp);
4057         }
4058
4059         /* only enable global IRQ */
4060         DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG,
4061             GAHBCFG_GLBLINTRMSK);
4062
4063         /* turn off clocks */
4064         dwc_otg_clocks_off(sc);
4065
4066         /* read initial VBUS state */
4067
4068         temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
4069
4070         DPRINTFN(5, "GOTCTL=0x%08x\n", temp);
4071
4072         dwc_otg_vbus_interrupt(sc,
4073             (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
4074
4075         USB_BUS_UNLOCK(&sc->sc_bus);
4076
4077         /* catch any lost interrupts */
4078
4079         dwc_otg_do_poll(&sc->sc_bus);
4080
4081         return (0);                     /* success */
4082 }
4083
4084 void
4085 dwc_otg_uninit(struct dwc_otg_softc *sc)
4086 {
4087         USB_BUS_LOCK(&sc->sc_bus);
4088
4089         /* stop host timer */
4090         dwc_otg_timer_stop(sc);
4091
4092         /* set disconnect */
4093         DWC_OTG_WRITE_4(sc, DOTG_DCTL,
4094             DCTL_SFTDISCON);
4095
4096         /* turn off global IRQ */
4097         DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0);
4098
4099         sc->sc_flags.port_enabled = 0;
4100         sc->sc_flags.port_powered = 0;
4101         sc->sc_flags.status_vbus = 0;
4102         sc->sc_flags.status_bus_reset = 0;
4103         sc->sc_flags.status_suspend = 0;
4104         sc->sc_flags.change_suspend = 0;
4105         sc->sc_flags.change_connect = 1;
4106
4107         dwc_otg_pull_down(sc);
4108         dwc_otg_clocks_off(sc);
4109
4110         USB_BUS_UNLOCK(&sc->sc_bus);
4111
4112         usb_callout_drain(&sc->sc_timer);
4113 }
4114
4115 static void
4116 dwc_otg_suspend(struct dwc_otg_softc *sc)
4117 {
4118         return;
4119 }
4120
4121 static void
4122 dwc_otg_resume(struct dwc_otg_softc *sc)
4123 {
4124         return;
4125 }
4126
4127 static void
4128 dwc_otg_do_poll(struct usb_bus *bus)
4129 {
4130         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus);
4131
4132         USB_BUS_LOCK(&sc->sc_bus);
4133         USB_BUS_SPIN_LOCK(&sc->sc_bus);
4134         dwc_otg_interrupt_poll_locked(sc);
4135         dwc_otg_interrupt_complete_locked(sc);
4136         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
4137         USB_BUS_UNLOCK(&sc->sc_bus);
4138 }
4139
4140 /*------------------------------------------------------------------------*
4141  * DWC OTG bulk support
4142  * DWC OTG control support
4143  * DWC OTG interrupt support
4144  *------------------------------------------------------------------------*/
4145 static void
4146 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer)
4147 {
4148 }
4149
4150 static void
4151 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer)
4152 {
4153         dwc_otg_device_done(xfer, USB_ERR_CANCELLED);
4154 }
4155
4156 static void
4157 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer)
4158 {
4159 }
4160
4161 static void
4162 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer)
4163 {
4164         /* setup TDs */
4165         dwc_otg_setup_standard_chain(xfer);
4166         dwc_otg_start_standard_chain(xfer);
4167 }
4168
4169 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods =
4170 {
4171         .open = dwc_otg_device_non_isoc_open,
4172         .close = dwc_otg_device_non_isoc_close,
4173         .enter = dwc_otg_device_non_isoc_enter,
4174         .start = dwc_otg_device_non_isoc_start,
4175 };
4176
4177 /*------------------------------------------------------------------------*
4178  * DWC OTG full speed isochronous support
4179  *------------------------------------------------------------------------*/
4180 static void
4181 dwc_otg_device_isoc_open(struct usb_xfer *xfer)
4182 {
4183 }
4184
4185 static void
4186 dwc_otg_device_isoc_close(struct usb_xfer *xfer)
4187 {
4188         dwc_otg_device_done(xfer, USB_ERR_CANCELLED);
4189 }
4190
4191 static void
4192 dwc_otg_device_isoc_enter(struct usb_xfer *xfer)
4193 {
4194 }
4195
4196 static void
4197 dwc_otg_device_isoc_start(struct usb_xfer *xfer)
4198 {
4199         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
4200         uint32_t temp;
4201         uint32_t msframes;
4202         uint32_t framenum;
4203         uint8_t shift = usbd_xfer_get_fps_shift(xfer);
4204
4205         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
4206             xfer, xfer->endpoint->isoc_next, xfer->nframes);
4207
4208         if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) {
4209                 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM);
4210
4211                 /* get the current frame index */
4212                 framenum = (temp & HFNUM_FRNUM_MASK);
4213         } else {
4214                 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
4215
4216                 /* get the current frame index */
4217                 framenum = DSTS_SOFFN_GET(temp);
4218         }
4219
4220         /*
4221          * Check if port is doing 8000 or 1000 frames per second:
4222          */
4223         if (sc->sc_flags.status_high_speed)
4224                 framenum /= 8;
4225
4226         framenum &= DWC_OTG_FRAME_MASK;
4227
4228         /*
4229          * Compute number of milliseconds worth of data traffic for
4230          * this USB transfer:
4231          */
4232         if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
4233                 msframes = ((xfer->nframes << shift) + 7) / 8;
4234         else
4235                 msframes = xfer->nframes;
4236
4237         /*
4238          * check if the frame index is within the window where the frames
4239          * will be inserted
4240          */
4241         temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK;
4242
4243         if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) {
4244                 /*
4245                  * If there is data underflow or the pipe queue is
4246                  * empty we schedule the transfer a few frames ahead
4247                  * of the current frame position. Else two isochronous
4248                  * transfers might overlap.
4249                  */
4250                 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK;
4251                 xfer->endpoint->is_synced = 1;
4252                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
4253         }
4254         /*
4255          * compute how many milliseconds the insertion is ahead of the
4256          * current frame position:
4257          */
4258         temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK;
4259
4260         /*
4261          * pre-compute when the isochronous transfer will be finished:
4262          */
4263         xfer->isoc_time_complete =
4264                 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes;
4265
4266         /* setup TDs */
4267         dwc_otg_setup_standard_chain(xfer);
4268
4269         /* compute frame number for next insertion */
4270         xfer->endpoint->isoc_next += msframes;
4271
4272         /* start TD chain */
4273         dwc_otg_start_standard_chain(xfer);
4274 }
4275
4276 static const struct usb_pipe_methods dwc_otg_device_isoc_methods =
4277 {
4278         .open = dwc_otg_device_isoc_open,
4279         .close = dwc_otg_device_isoc_close,
4280         .enter = dwc_otg_device_isoc_enter,
4281         .start = dwc_otg_device_isoc_start,
4282 };
4283
4284 /*------------------------------------------------------------------------*
4285  * DWC OTG root control support
4286  *------------------------------------------------------------------------*
4287  * Simulate a hardware HUB by handling all the necessary requests.
4288  *------------------------------------------------------------------------*/
4289
4290 static const struct usb_device_descriptor dwc_otg_devd = {
4291         .bLength = sizeof(struct usb_device_descriptor),
4292         .bDescriptorType = UDESC_DEVICE,
4293         .bcdUSB = {0x00, 0x02},
4294         .bDeviceClass = UDCLASS_HUB,
4295         .bDeviceSubClass = UDSUBCLASS_HUB,
4296         .bDeviceProtocol = UDPROTO_HSHUBSTT,
4297         .bMaxPacketSize = 64,
4298         .bcdDevice = {0x00, 0x01},
4299         .iManufacturer = 1,
4300         .iProduct = 2,
4301         .bNumConfigurations = 1,
4302 };
4303
4304 static const struct dwc_otg_config_desc dwc_otg_confd = {
4305         .confd = {
4306                 .bLength = sizeof(struct usb_config_descriptor),
4307                 .bDescriptorType = UDESC_CONFIG,
4308                 .wTotalLength[0] = sizeof(dwc_otg_confd),
4309                 .bNumInterface = 1,
4310                 .bConfigurationValue = 1,
4311                 .iConfiguration = 0,
4312                 .bmAttributes = UC_SELF_POWERED,
4313                 .bMaxPower = 0,
4314         },
4315         .ifcd = {
4316                 .bLength = sizeof(struct usb_interface_descriptor),
4317                 .bDescriptorType = UDESC_INTERFACE,
4318                 .bNumEndpoints = 1,
4319                 .bInterfaceClass = UICLASS_HUB,
4320                 .bInterfaceSubClass = UISUBCLASS_HUB,
4321                 .bInterfaceProtocol = 0,
4322         },
4323         .endpd = {
4324                 .bLength = sizeof(struct usb_endpoint_descriptor),
4325                 .bDescriptorType = UDESC_ENDPOINT,
4326                 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT),
4327                 .bmAttributes = UE_INTERRUPT,
4328                 .wMaxPacketSize[0] = 8,
4329                 .bInterval = 255,
4330         },
4331 };
4332
4333 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
4334
4335 static const struct usb_hub_descriptor_min dwc_otg_hubd = {
4336         .bDescLength = sizeof(dwc_otg_hubd),
4337         .bDescriptorType = UDESC_HUB,
4338         .bNbrPorts = 1,
4339         HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
4340         .bPwrOn2PwrGood = 50,
4341         .bHubContrCurrent = 0,
4342         .DeviceRemovable = {0},         /* port is removable */
4343 };
4344
4345 #define STRING_VENDOR \
4346   "D\0W\0C\0O\0T\0G"
4347
4348 #define STRING_PRODUCT \
4349   "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
4350
4351 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor);
4352 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product);
4353
4354 static usb_error_t
4355 dwc_otg_roothub_exec(struct usb_device *udev,
4356     struct usb_device_request *req, const void **pptr, uint16_t *plength)
4357 {
4358         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4359         const void *ptr;
4360         uint16_t len;
4361         uint16_t value;
4362         uint16_t index;
4363         usb_error_t err;
4364
4365         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
4366
4367         /* buffer reset */
4368         ptr = (const void *)&sc->sc_hub_temp;
4369         len = 0;
4370         err = 0;
4371
4372         value = UGETW(req->wValue);
4373         index = UGETW(req->wIndex);
4374
4375         /* demultiplex the control request */
4376
4377         switch (req->bmRequestType) {
4378         case UT_READ_DEVICE:
4379                 switch (req->bRequest) {
4380                 case UR_GET_DESCRIPTOR:
4381                         goto tr_handle_get_descriptor;
4382                 case UR_GET_CONFIG:
4383                         goto tr_handle_get_config;
4384                 case UR_GET_STATUS:
4385                         goto tr_handle_get_status;
4386                 default:
4387                         goto tr_stalled;
4388                 }
4389                 break;
4390
4391         case UT_WRITE_DEVICE:
4392                 switch (req->bRequest) {
4393                 case UR_SET_ADDRESS:
4394                         goto tr_handle_set_address;
4395                 case UR_SET_CONFIG:
4396                         goto tr_handle_set_config;
4397                 case UR_CLEAR_FEATURE:
4398                         goto tr_valid;  /* nop */
4399                 case UR_SET_DESCRIPTOR:
4400                         goto tr_valid;  /* nop */
4401                 case UR_SET_FEATURE:
4402                 default:
4403                         goto tr_stalled;
4404                 }
4405                 break;
4406
4407         case UT_WRITE_ENDPOINT:
4408                 switch (req->bRequest) {
4409                 case UR_CLEAR_FEATURE:
4410                         switch (UGETW(req->wValue)) {
4411                         case UF_ENDPOINT_HALT:
4412                                 goto tr_handle_clear_halt;
4413                         case UF_DEVICE_REMOTE_WAKEUP:
4414                                 goto tr_handle_clear_wakeup;
4415                         default:
4416                                 goto tr_stalled;
4417                         }
4418                         break;
4419                 case UR_SET_FEATURE:
4420                         switch (UGETW(req->wValue)) {
4421                         case UF_ENDPOINT_HALT:
4422                                 goto tr_handle_set_halt;
4423                         case UF_DEVICE_REMOTE_WAKEUP:
4424                                 goto tr_handle_set_wakeup;
4425                         default:
4426                                 goto tr_stalled;
4427                         }
4428                         break;
4429                 case UR_SYNCH_FRAME:
4430                         goto tr_valid;  /* nop */
4431                 default:
4432                         goto tr_stalled;
4433                 }
4434                 break;
4435
4436         case UT_READ_ENDPOINT:
4437                 switch (req->bRequest) {
4438                 case UR_GET_STATUS:
4439                         goto tr_handle_get_ep_status;
4440                 default:
4441                         goto tr_stalled;
4442                 }
4443                 break;
4444
4445         case UT_WRITE_INTERFACE:
4446                 switch (req->bRequest) {
4447                 case UR_SET_INTERFACE:
4448                         goto tr_handle_set_interface;
4449                 case UR_CLEAR_FEATURE:
4450                         goto tr_valid;  /* nop */
4451                 case UR_SET_FEATURE:
4452                 default:
4453                         goto tr_stalled;
4454                 }
4455                 break;
4456
4457         case UT_READ_INTERFACE:
4458                 switch (req->bRequest) {
4459                 case UR_GET_INTERFACE:
4460                         goto tr_handle_get_interface;
4461                 case UR_GET_STATUS:
4462                         goto tr_handle_get_iface_status;
4463                 default:
4464                         goto tr_stalled;
4465                 }
4466                 break;
4467
4468         case UT_WRITE_CLASS_INTERFACE:
4469         case UT_WRITE_VENDOR_INTERFACE:
4470                 /* XXX forward */
4471                 break;
4472
4473         case UT_READ_CLASS_INTERFACE:
4474         case UT_READ_VENDOR_INTERFACE:
4475                 /* XXX forward */
4476                 break;
4477
4478         case UT_WRITE_CLASS_DEVICE:
4479                 switch (req->bRequest) {
4480                 case UR_CLEAR_FEATURE:
4481                         goto tr_valid;
4482                 case UR_SET_DESCRIPTOR:
4483                 case UR_SET_FEATURE:
4484                         break;
4485                 default:
4486                         goto tr_stalled;
4487                 }
4488                 break;
4489
4490         case UT_WRITE_CLASS_OTHER:
4491                 switch (req->bRequest) {
4492                 case UR_CLEAR_FEATURE:
4493                         goto tr_handle_clear_port_feature;
4494                 case UR_SET_FEATURE:
4495                         goto tr_handle_set_port_feature;
4496                 case UR_CLEAR_TT_BUFFER:
4497                 case UR_RESET_TT:
4498                 case UR_STOP_TT:
4499                         goto tr_valid;
4500
4501                 default:
4502                         goto tr_stalled;
4503                 }
4504                 break;
4505
4506         case UT_READ_CLASS_OTHER:
4507                 switch (req->bRequest) {
4508                 case UR_GET_TT_STATE:
4509                         goto tr_handle_get_tt_state;
4510                 case UR_GET_STATUS:
4511                         goto tr_handle_get_port_status;
4512                 default:
4513                         goto tr_stalled;
4514                 }
4515                 break;
4516
4517         case UT_READ_CLASS_DEVICE:
4518                 switch (req->bRequest) {
4519                 case UR_GET_DESCRIPTOR:
4520                         goto tr_handle_get_class_descriptor;
4521                 case UR_GET_STATUS:
4522                         goto tr_handle_get_class_status;
4523
4524                 default:
4525                         goto tr_stalled;
4526                 }
4527                 break;
4528         default:
4529                 goto tr_stalled;
4530         }
4531         goto tr_valid;
4532
4533 tr_handle_get_descriptor:
4534         switch (value >> 8) {
4535         case UDESC_DEVICE:
4536                 if (value & 0xff) {
4537                         goto tr_stalled;
4538                 }
4539                 len = sizeof(dwc_otg_devd);
4540                 ptr = (const void *)&dwc_otg_devd;
4541                 goto tr_valid;
4542         case UDESC_CONFIG:
4543                 if (value & 0xff) {
4544                         goto tr_stalled;
4545                 }
4546                 len = sizeof(dwc_otg_confd);
4547                 ptr = (const void *)&dwc_otg_confd;
4548                 goto tr_valid;
4549         case UDESC_STRING:
4550                 switch (value & 0xff) {
4551                 case 0:         /* Language table */
4552                         len = sizeof(usb_string_lang_en);
4553                         ptr = (const void *)&usb_string_lang_en;
4554                         goto tr_valid;
4555
4556                 case 1:         /* Vendor */
4557                         len = sizeof(dwc_otg_vendor);
4558                         ptr = (const void *)&dwc_otg_vendor;
4559                         goto tr_valid;
4560
4561                 case 2:         /* Product */
4562                         len = sizeof(dwc_otg_product);
4563                         ptr = (const void *)&dwc_otg_product;
4564                         goto tr_valid;
4565                 default:
4566                         break;
4567                 }
4568                 break;
4569         default:
4570                 goto tr_stalled;
4571         }
4572         goto tr_stalled;
4573
4574 tr_handle_get_config:
4575         len = 1;
4576         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
4577         goto tr_valid;
4578
4579 tr_handle_get_status:
4580         len = 2;
4581         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
4582         goto tr_valid;
4583
4584 tr_handle_set_address:
4585         if (value & 0xFF00) {
4586                 goto tr_stalled;
4587         }
4588         sc->sc_rt_addr = value;
4589         goto tr_valid;
4590
4591 tr_handle_set_config:
4592         if (value >= 2) {
4593                 goto tr_stalled;
4594         }
4595         sc->sc_conf = value;
4596         goto tr_valid;
4597
4598 tr_handle_get_interface:
4599         len = 1;
4600         sc->sc_hub_temp.wValue[0] = 0;
4601         goto tr_valid;
4602
4603 tr_handle_get_tt_state:
4604 tr_handle_get_class_status:
4605 tr_handle_get_iface_status:
4606 tr_handle_get_ep_status:
4607         len = 2;
4608         USETW(sc->sc_hub_temp.wValue, 0);
4609         goto tr_valid;
4610
4611 tr_handle_set_halt:
4612 tr_handle_set_interface:
4613 tr_handle_set_wakeup:
4614 tr_handle_clear_wakeup:
4615 tr_handle_clear_halt:
4616         goto tr_valid;
4617
4618 tr_handle_clear_port_feature:
4619         if (index != 1)
4620                 goto tr_stalled;
4621
4622         DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
4623
4624         switch (value) {
4625         case UHF_PORT_SUSPEND:
4626                 dwc_otg_wakeup_peer(sc);
4627                 break;
4628
4629         case UHF_PORT_ENABLE:
4630                 if (sc->sc_flags.status_device_mode == 0) {
4631                         DWC_OTG_WRITE_4(sc, DOTG_HPRT,
4632                             sc->sc_hprt_val | HPRT_PRTENA);
4633                 }
4634                 sc->sc_flags.port_enabled = 0;
4635                 break;
4636
4637         case UHF_C_PORT_RESET:
4638                 sc->sc_flags.change_reset = 0;
4639                 break;
4640
4641         case UHF_C_PORT_ENABLE:
4642                 sc->sc_flags.change_enabled = 0;
4643                 break;
4644
4645         case UHF_C_PORT_OVER_CURRENT:
4646                 sc->sc_flags.change_over_current = 0;
4647                 break;
4648
4649         case UHF_PORT_TEST:
4650         case UHF_PORT_INDICATOR:
4651                 /* nops */
4652                 break;
4653
4654         case UHF_PORT_POWER:
4655                 sc->sc_flags.port_powered = 0;
4656                 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4657                         sc->sc_hprt_val = 0;
4658                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA);
4659                 }
4660                 dwc_otg_pull_down(sc);
4661                 dwc_otg_clocks_off(sc);
4662                 break;
4663
4664         case UHF_C_PORT_CONNECTION:
4665                 /* clear connect change flag */
4666                 sc->sc_flags.change_connect = 0;
4667                 break;
4668
4669         case UHF_C_PORT_SUSPEND:
4670                 sc->sc_flags.change_suspend = 0;
4671                 break;
4672
4673         default:
4674                 err = USB_ERR_IOERROR;
4675                 goto done;
4676         }
4677         goto tr_valid;
4678
4679 tr_handle_set_port_feature:
4680         if (index != 1) {
4681                 goto tr_stalled;
4682         }
4683         DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
4684
4685         switch (value) {
4686         case UHF_PORT_ENABLE:
4687                 break;
4688
4689         case UHF_PORT_SUSPEND:
4690                 if (sc->sc_flags.status_device_mode == 0) {
4691                         /* set suspend BIT */
4692                         sc->sc_hprt_val |= HPRT_PRTSUSP;
4693                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4694
4695                         /* generate HUB suspend event */
4696                         dwc_otg_suspend_irq(sc);
4697                 }
4698                 break;
4699
4700         case UHF_PORT_RESET:
4701                 if (sc->sc_flags.status_device_mode == 0) {
4702
4703                         DPRINTF("PORT RESET\n");
4704
4705                         /* enable PORT reset */
4706                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST);
4707
4708                         /* Wait 62.5ms for reset to complete */
4709                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4710
4711                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4712
4713                         /* Wait 62.5ms for reset to complete */
4714                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4715
4716                         /* reset FIFOs */
4717                         (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST);
4718
4719                         sc->sc_flags.change_reset = 1;
4720                 } else {
4721                         err = USB_ERR_IOERROR;
4722                 }
4723                 break;
4724
4725         case UHF_PORT_TEST:
4726         case UHF_PORT_INDICATOR:
4727                 /* nops */
4728                 break;
4729         case UHF_PORT_POWER:
4730                 sc->sc_flags.port_powered = 1;
4731                 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4732                         sc->sc_hprt_val |= HPRT_PRTPWR;
4733                         DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4734                 }
4735                 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) {
4736                         /* pull up D+, if any */
4737                         dwc_otg_pull_up(sc);
4738                 }
4739                 break;
4740         default:
4741                 err = USB_ERR_IOERROR;
4742                 goto done;
4743         }
4744         goto tr_valid;
4745
4746 tr_handle_get_port_status:
4747
4748         DPRINTFN(9, "UR_GET_PORT_STATUS\n");
4749
4750         if (index != 1)
4751                 goto tr_stalled;
4752
4753         if (sc->sc_flags.status_vbus)
4754                 dwc_otg_clocks_on(sc);
4755         else
4756                 dwc_otg_clocks_off(sc);
4757
4758         /* Select Device Side Mode */
4759
4760         if (sc->sc_flags.status_device_mode) {
4761                 value = UPS_PORT_MODE_DEVICE;
4762                 dwc_otg_timer_stop(sc);
4763         } else {
4764                 value = 0;
4765                 dwc_otg_timer_start(sc);
4766         }
4767
4768         if (sc->sc_flags.status_high_speed)
4769                 value |= UPS_HIGH_SPEED;
4770         else if (sc->sc_flags.status_low_speed)
4771                 value |= UPS_LOW_SPEED;
4772
4773         if (sc->sc_flags.port_powered)
4774                 value |= UPS_PORT_POWER;
4775
4776         if (sc->sc_flags.port_enabled)
4777                 value |= UPS_PORT_ENABLED;
4778
4779         if (sc->sc_flags.port_over_current)
4780                 value |= UPS_OVERCURRENT_INDICATOR;
4781
4782         if (sc->sc_flags.status_vbus &&
4783             sc->sc_flags.status_bus_reset)
4784                 value |= UPS_CURRENT_CONNECT_STATUS;
4785
4786         if (sc->sc_flags.status_suspend)
4787                 value |= UPS_SUSPEND;
4788
4789         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4790
4791         value = 0;
4792
4793         if (sc->sc_flags.change_enabled)
4794                 value |= UPS_C_PORT_ENABLED;
4795         if (sc->sc_flags.change_connect)
4796                 value |= UPS_C_CONNECT_STATUS;
4797         if (sc->sc_flags.change_suspend)
4798                 value |= UPS_C_SUSPEND;
4799         if (sc->sc_flags.change_reset)
4800                 value |= UPS_C_PORT_RESET;
4801         if (sc->sc_flags.change_over_current)
4802                 value |= UPS_C_OVERCURRENT_INDICATOR;
4803
4804         USETW(sc->sc_hub_temp.ps.wPortChange, value);
4805         len = sizeof(sc->sc_hub_temp.ps);
4806         goto tr_valid;
4807
4808 tr_handle_get_class_descriptor:
4809         if (value & 0xFF) {
4810                 goto tr_stalled;
4811         }
4812         ptr = (const void *)&dwc_otg_hubd;
4813         len = sizeof(dwc_otg_hubd);
4814         goto tr_valid;
4815
4816 tr_stalled:
4817         err = USB_ERR_STALLED;
4818 tr_valid:
4819 done:
4820         *plength = len;
4821         *pptr = ptr;
4822         return (err);
4823 }
4824
4825 static void
4826 dwc_otg_xfer_setup(struct usb_setup_params *parm)
4827 {
4828         struct usb_xfer *xfer;
4829         void *last_obj;
4830         uint32_t ntd;
4831         uint32_t n;
4832         uint8_t ep_no;
4833         uint8_t ep_type;
4834
4835         xfer = parm->curr_xfer;
4836
4837         /*
4838          * NOTE: This driver does not use any of the parameters that
4839          * are computed from the following values. Just set some
4840          * reasonable dummies:
4841          */
4842         parm->hc_max_packet_size = 0x500;
4843         parm->hc_max_packet_count = 3;
4844         parm->hc_max_frame_size = 3 * 0x500;
4845
4846         usbd_transfer_setup_sub(parm);
4847
4848         /*
4849          * compute maximum number of TDs
4850          */
4851         ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
4852
4853         if (ep_type == UE_CONTROL) {
4854
4855                 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
4856                     + 1 /* SYNC 2 */ + 1 /* SYNC 3 */;
4857         } else {
4858
4859                 ntd = xfer->nframes + 1 /* SYNC */ ;
4860         }
4861
4862         /*
4863          * check if "usbd_transfer_setup_sub" set an error
4864          */
4865         if (parm->err)
4866                 return;
4867
4868         /*
4869          * allocate transfer descriptors
4870          */
4871         last_obj = NULL;
4872
4873         ep_no = xfer->endpointno & UE_ADDR;
4874
4875         /*
4876          * Check for a valid endpoint profile in USB device mode:
4877          */
4878         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4879                 const struct usb_hw_ep_profile *pf;
4880
4881                 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4882
4883                 if (pf == NULL) {
4884                         /* should not happen */
4885                         parm->err = USB_ERR_INVAL;
4886                         return;
4887                 }
4888         }
4889
4890         /* align data */
4891         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4892
4893         for (n = 0; n != ntd; n++) {
4894
4895                 struct dwc_otg_td *td;
4896
4897                 if (parm->buf) {
4898
4899                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4900
4901                         /* compute shared bandwidth resource index for TT */
4902                         if (dwc_otg_uses_split(parm->udev)) {
4903                                 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT)
4904                                         td->tt_index = parm->udev->device_index;
4905                                 else
4906                                         td->tt_index = parm->udev->parent_hs_hub->device_index;
4907                         } else {
4908                                 td->tt_index = parm->udev->device_index;
4909                         }
4910
4911                         /* init TD */
4912                         td->max_packet_size = xfer->max_packet_size;
4913                         td->max_packet_count = xfer->max_packet_count;
4914                         /* range check */
4915                         if (td->max_packet_count == 0 || td->max_packet_count > 3)
4916                                 td->max_packet_count = 1;
4917                         td->ep_no = ep_no;
4918                         td->ep_type = ep_type;
4919                         td->obj_next = last_obj;
4920
4921                         last_obj = td;
4922                 }
4923                 parm->size[0] += sizeof(*td);
4924         }
4925
4926         xfer->td_start[0] = last_obj;
4927 }
4928
4929 static void
4930 dwc_otg_xfer_unsetup(struct usb_xfer *xfer)
4931 {
4932         return;
4933 }
4934
4935 static void
4936 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4937     struct usb_endpoint *ep)
4938 {
4939         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4940
4941         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
4942             ep, udev->address,
4943             edesc->bEndpointAddress, udev->flags.usb_mode,
4944             sc->sc_rt_addr, udev->device_index);
4945
4946         if (udev->device_index != sc->sc_rt_addr) {
4947
4948                 if (udev->flags.usb_mode == USB_MODE_DEVICE) {
4949                         if (udev->speed != USB_SPEED_FULL &&
4950                             udev->speed != USB_SPEED_HIGH) {
4951                                 /* not supported */
4952                                 return;
4953                         }
4954                 } else {
4955                         if (udev->speed == USB_SPEED_HIGH &&
4956                             (edesc->wMaxPacketSize[1] & 0x18) != 0 &&
4957                             (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) {
4958                                 /* not supported */
4959                                 DPRINTFN(-1, "Non-isochronous high bandwidth "
4960                                     "endpoint not supported\n");
4961                                 return;
4962                         }
4963                 }
4964                 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
4965                         ep->methods = &dwc_otg_device_isoc_methods;
4966                 else
4967                         ep->methods = &dwc_otg_device_non_isoc_methods;
4968         }
4969 }
4970
4971 static void
4972 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4973 {
4974         struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus);
4975
4976         switch (state) {
4977         case USB_HW_POWER_SUSPEND:
4978                 dwc_otg_suspend(sc);
4979                 break;
4980         case USB_HW_POWER_SHUTDOWN:
4981                 dwc_otg_uninit(sc);
4982                 break;
4983         case USB_HW_POWER_RESUME:
4984                 dwc_otg_resume(sc);
4985                 break;
4986         default:
4987                 break;
4988         }
4989 }
4990
4991 static void
4992 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4993 {
4994         /* DMA delay - wait until any use of memory is finished */
4995         *pus = (2125);                  /* microseconds */
4996 }
4997
4998 static void
4999 dwc_otg_device_resume(struct usb_device *udev)
5000 {
5001         DPRINTF("\n");
5002
5003         /* poll all transfers again to restart resumed ones */
5004         dwc_otg_do_poll(udev->bus);
5005 }
5006
5007 static void
5008 dwc_otg_device_suspend(struct usb_device *udev)
5009 {
5010         DPRINTF("\n");
5011 }
5012
5013 static const struct usb_bus_methods dwc_otg_bus_methods =
5014 {
5015         .endpoint_init = &dwc_otg_ep_init,
5016         .xfer_setup = &dwc_otg_xfer_setup,
5017         .xfer_unsetup = &dwc_otg_xfer_unsetup,
5018         .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile,
5019         .xfer_stall = &dwc_otg_xfer_stall,
5020         .set_stall = &dwc_otg_set_stall,
5021         .clear_stall = &dwc_otg_clear_stall,
5022         .roothub_exec = &dwc_otg_roothub_exec,
5023         .xfer_poll = &dwc_otg_do_poll,
5024         .device_state_change = &dwc_otg_device_state_change,
5025         .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep,
5026         .get_dma_delay = &dwc_otg_get_dma_delay,
5027         .device_resume = &dwc_otg_device_resume,
5028         .device_suspend = &dwc_otg_device_suspend,
5029 };