3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2015 Daisuke Aoyama. All rights reserved.
6 * Copyright (c) 2012-2015 Hans Petter Selasky. All rights reserved.
7 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * This file contains the driver for the DesignWare series USB 2.0 OTG
37 * LIMITATION: Drivers must be bound to all OUT endpoints in the
38 * active configuration for this driver to work properly. Blocking any
39 * OUT endpoint will block all OUT endpoints including the control
40 * endpoint. Usually this is not a problem.
44 * NOTE: Writing to non-existing registers appears to cause an
48 #ifdef USB_GLOBAL_INCLUDE_FILE
49 #include USB_GLOBAL_INCLUDE_FILE
51 #include <sys/stdint.h>
52 #include <sys/stddef.h>
53 #include <sys/param.h>
54 #include <sys/queue.h>
55 #include <sys/types.h>
56 #include <sys/systm.h>
57 #include <sys/kernel.h>
59 #include <sys/module.h>
61 #include <sys/mutex.h>
62 #include <sys/condvar.h>
63 #include <sys/sysctl.h>
65 #include <sys/unistd.h>
66 #include <sys/callout.h>
67 #include <sys/malloc.h>
70 #include <dev/usb/usb.h>
71 #include <dev/usb/usbdi.h>
73 #define USB_DEBUG_VAR dwc_otg_debug
75 #include <dev/usb/usb_core.h>
76 #include <dev/usb/usb_debug.h>
77 #include <dev/usb/usb_busdma.h>
78 #include <dev/usb/usb_process.h>
79 #include <dev/usb/usb_transfer.h>
80 #include <dev/usb/usb_device.h>
81 #include <dev/usb/usb_hub.h>
82 #include <dev/usb/usb_util.h>
84 #include <dev/usb/usb_controller.h>
85 #include <dev/usb/usb_bus.h>
86 #endif /* USB_GLOBAL_INCLUDE_FILE */
88 #include <dev/usb/controller/dwc_otg.h>
89 #include <dev/usb/controller/dwc_otgreg.h>
91 #define DWC_OTG_BUS2SC(bus) \
92 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \
93 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus))))
95 #define DWC_OTG_PC2UDEV(pc) \
96 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
98 #define DWC_OTG_MSK_GINT_THREAD_IRQ \
99 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \
100 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \
103 #ifndef DWC_OTG_PHY_DEFAULT
104 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI
107 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT;
109 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG");
110 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN,
111 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2/3 - ULPI/HSIC/INTERNAL/UTMI+");
114 static int dwc_otg_debug = 0;
116 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN,
117 &dwc_otg_debug, 0, "DWC OTG debug level");
120 #define DWC_OTG_INTR_ENDPT 1
124 static const struct usb_bus_methods dwc_otg_bus_methods;
125 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods;
126 static const struct usb_pipe_methods dwc_otg_device_isoc_methods;
128 static dwc_otg_cmd_t dwc_otg_setup_rx;
129 static dwc_otg_cmd_t dwc_otg_data_rx;
130 static dwc_otg_cmd_t dwc_otg_data_tx;
131 static dwc_otg_cmd_t dwc_otg_data_tx_sync;
133 static dwc_otg_cmd_t dwc_otg_host_setup_tx;
134 static dwc_otg_cmd_t dwc_otg_host_data_tx;
135 static dwc_otg_cmd_t dwc_otg_host_data_rx;
137 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t);
138 static void dwc_otg_do_poll(struct usb_bus *);
139 static void dwc_otg_standard_done(struct usb_xfer *);
140 static void dwc_otg_root_intr(struct dwc_otg_softc *);
141 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *);
144 * Here is a configuration that the chip supports.
146 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = {
149 .max_in_frame_size = 64,/* fixed */
150 .max_out_frame_size = 64, /* fixed */
152 .support_control = 1,
157 dwc_otg_get_hw_ep_profile(struct usb_device *udev,
158 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
160 struct dwc_otg_softc *sc;
162 sc = DWC_OTG_BUS2SC(udev->bus);
164 if (ep_addr < sc->sc_dev_ep_max)
165 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb;
171 dwc_otg_write_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc,
172 uint32_t offset, uint32_t fifo, uint32_t count)
176 /* round down length to nearest 4-bytes */
179 /* check if we can write the data directly */
180 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
181 struct usb_page_search buf_res;
183 /* pre-subtract length */
186 /* iterate buffer list */
188 /* get current buffer pointer */
189 usbd_get_page(pc, offset, &buf_res);
191 if (buf_res.length > temp)
192 buf_res.length = temp;
194 /* transfer data into FIFO */
195 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
196 fifo, buf_res.buffer, buf_res.length / 4);
198 offset += buf_res.length;
199 fifo += buf_res.length;
200 temp -= buf_res.length;
204 /* check for remainder */
206 /* clear topmost word before copy */
207 sc->sc_bounce_buffer[(count - 1) / 4] = 0;
210 usbd_copy_out(pc, offset,
211 sc->sc_bounce_buffer, count);
213 /* transfer data into FIFO */
214 bus_space_write_region_4(sc->sc_io_tag,
215 sc->sc_io_hdl, fifo, sc->sc_bounce_buffer,
221 dwc_otg_read_fifo(struct dwc_otg_softc *sc, struct usb_page_cache *pc,
222 uint32_t offset, uint32_t count)
226 /* round down length to nearest 4-bytes */
229 /* check if we can read the data directly */
230 if (temp != 0 && usb_pc_buffer_is_aligned(pc, offset, temp, 3)) {
231 struct usb_page_search buf_res;
233 /* pre-subtract length */
236 /* iterate buffer list */
238 /* get current buffer pointer */
239 usbd_get_page(pc, offset, &buf_res);
241 if (buf_res.length > temp)
242 buf_res.length = temp;
244 /* transfer data from FIFO */
245 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
246 sc->sc_current_rx_fifo, buf_res.buffer, buf_res.length / 4);
248 offset += buf_res.length;
249 sc->sc_current_rx_fifo += buf_res.length;
250 sc->sc_current_rx_bytes -= buf_res.length;
251 temp -= buf_res.length;
255 /* check for remainder */
257 /* read data into bounce buffer */
258 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
259 sc->sc_current_rx_fifo,
260 sc->sc_bounce_buffer, (count + 3) / 4);
262 /* store data into proper buffer */
263 usbd_copy_in(pc, offset, sc->sc_bounce_buffer, count);
265 /* round length up to nearest 4 bytes */
266 count = (count + 3) & ~3;
268 /* update counters */
269 sc->sc_current_rx_bytes -= count;
270 sc->sc_current_rx_fifo += count;
275 dwc_otg_tx_fifo_reset(struct dwc_otg_softc *sc, uint32_t value)
280 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, value);
282 /* wait for reset to complete */
283 for (temp = 0; temp != 16; temp++) {
284 value = DWC_OTG_READ_4(sc, DOTG_GRSTCTL);
285 if (!(value & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)))
291 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode)
293 struct dwc_otg_profile *pf;
299 fifo_size = sc->sc_fifo_size;
302 * NOTE: Reserved fixed size area at end of RAM, which must
303 * not be allocated to the FIFOs:
307 if (fifo_size < fifo_regs) {
308 DPRINTF("Too little FIFO\n");
312 /* subtract FIFO regs from total once */
313 fifo_size -= fifo_regs;
315 /* split equally for IN and OUT */
318 /* Align to 4 bytes boundary (refer to PGM) */
321 /* set global receive FIFO size */
322 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4);
324 tx_start = fifo_size;
326 if (fifo_size < 64) {
327 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n");
331 if (mode == DWC_MODE_HOST) {
333 /* reset active endpoints */
334 sc->sc_active_rx_ep = 0;
336 /* split equally for periodic and non-periodic */
339 DPRINTF("PTX/NPTX FIFO=%u\n", fifo_size);
341 /* align to 4 bytes boundary */
344 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ,
345 ((fifo_size / 4) << 16) |
348 tx_start += fifo_size;
350 for (x = 0; x != sc->sc_host_ch_max; x++) {
351 /* enable all host interrupts */
352 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x),
356 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ,
357 ((fifo_size / 4) << 16) |
360 /* reset host channel state */
361 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
363 /* enable all host channel interrupts */
364 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK,
365 (1U << sc->sc_host_ch_max) - 1U);
367 /* enable proper host channel interrupts */
368 sc->sc_irq_mask |= GINTMSK_HCHINTMSK;
369 sc->sc_irq_mask &= ~GINTMSK_IEPINTMSK;
370 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
373 if (mode == DWC_MODE_DEVICE) {
375 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ,
376 (0x10 << 16) | (tx_start / 4));
380 /* setup control endpoint profile */
381 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0];
383 /* reset active endpoints */
384 sc->sc_active_rx_ep = 1;
386 for (x = 1; x != sc->sc_dev_ep_max; x++) {
388 pf = sc->sc_hw_ep_profile + x;
390 pf->usb.max_out_frame_size = 1024 * 3;
391 pf->usb.is_simplex = 0; /* assume duplex */
392 pf->usb.support_bulk = 1;
393 pf->usb.support_interrupt = 1;
394 pf->usb.support_isochronous = 1;
395 pf->usb.support_out = 1;
397 if (x < sc->sc_dev_in_ep_max) {
400 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE,
401 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2,
402 DWC_OTG_TX_MAX_FIFO_SIZE);
404 /* see if there is enough FIFO space */
405 if (limit <= fifo_size) {
406 pf->max_buffer = limit;
407 pf->usb.support_in = 1;
409 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40);
410 if (limit <= fifo_size) {
411 pf->usb.support_in = 1;
413 pf->usb.is_simplex = 1;
418 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x),
419 ((limit / 4) << 16) | (tx_start / 4));
422 pf->usb.max_in_frame_size = limit;
424 pf->usb.is_simplex = 1;
427 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x,
428 pf->usb.max_in_frame_size,
429 pf->usb.max_out_frame_size);
432 /* enable proper device channel interrupts */
433 sc->sc_irq_mask &= ~GINTMSK_HCHINTMSK;
434 sc->sc_irq_mask |= GINTMSK_IEPINTMSK;
435 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
439 dwc_otg_tx_fifo_reset(sc, GRSTCTL_RXFFLSH);
441 if (mode != DWC_MODE_OTG) {
442 /* reset all TX FIFOs */
443 dwc_otg_tx_fifo_reset(sc,
444 GRSTCTL_TXFIFO(0x10) |
447 /* reset active endpoints */
448 sc->sc_active_rx_ep = 0;
450 /* reset host channel state */
451 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state));
457 dwc_otg_uses_split(struct usb_device *udev)
460 * When a LOW or FULL speed device is connected directly to
461 * the USB port we don't use split transactions:
463 return (udev->speed != USB_SPEED_HIGH &&
464 udev->parent_hs_hub != NULL &&
465 udev->parent_hs_hub->parent_hub != NULL);
469 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc)
473 * Disabled until further. Assuming that the register is already
474 * programmed correctly by the boot loader.
479 /* setup HOST frame interval register, based on existing value */
480 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK;
486 /* figure out nearest X-tal value */
494 if (sc->sc_flags.status_high_speed)
499 DPRINTF("HFIR=0x%08x\n", temp);
501 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp);
506 dwc_otg_clocks_on(struct dwc_otg_softc *sc)
508 if (sc->sc_flags.clocks_off &&
509 sc->sc_flags.port_powered) {
513 /* TODO - platform specific */
515 sc->sc_flags.clocks_off = 0;
520 dwc_otg_clocks_off(struct dwc_otg_softc *sc)
522 if (!sc->sc_flags.clocks_off) {
526 /* TODO - platform specific */
528 sc->sc_flags.clocks_off = 1;
533 dwc_otg_pull_up(struct dwc_otg_softc *sc)
537 /* pullup D+, if possible */
539 if (!sc->sc_flags.d_pulled_up &&
540 sc->sc_flags.port_powered) {
541 sc->sc_flags.d_pulled_up = 1;
543 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
544 temp &= ~DCTL_SFTDISCON;
545 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
550 dwc_otg_pull_down(struct dwc_otg_softc *sc)
554 /* pulldown D+, if possible */
556 if (sc->sc_flags.d_pulled_up) {
557 sc->sc_flags.d_pulled_up = 0;
559 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
560 temp |= DCTL_SFTDISCON;
561 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
566 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc)
568 /* In device mode we don't use the SOF interrupt */
569 if (sc->sc_flags.status_device_mode != 0)
571 /* Ensure the SOF interrupt is not disabled */
573 /* Check if the SOF interrupt is already enabled */
574 if ((sc->sc_irq_mask & GINTMSK_SOFMSK) != 0)
576 sc->sc_irq_mask |= GINTMSK_SOFMSK;
577 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
581 dwc_otg_resume_irq(struct dwc_otg_softc *sc)
583 if (sc->sc_flags.status_suspend) {
584 /* update status bits */
585 sc->sc_flags.status_suspend = 0;
586 sc->sc_flags.change_suspend = 1;
588 if (sc->sc_flags.status_device_mode) {
590 * Disable resume interrupt and enable suspend
593 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK;
594 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
595 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
598 /* complete root HUB interrupt endpoint */
599 dwc_otg_root_intr(sc);
604 dwc_otg_suspend_irq(struct dwc_otg_softc *sc)
606 if (!sc->sc_flags.status_suspend) {
607 /* update status bits */
608 sc->sc_flags.status_suspend = 1;
609 sc->sc_flags.change_suspend = 1;
611 if (sc->sc_flags.status_device_mode) {
613 * Disable suspend interrupt and enable resume
616 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK;
617 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK;
618 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
621 /* complete root HUB interrupt endpoint */
622 dwc_otg_root_intr(sc);
627 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc)
629 if (!sc->sc_flags.status_suspend)
632 DPRINTFN(5, "Remote wakeup\n");
634 if (sc->sc_flags.status_device_mode) {
637 /* enable remote wakeup signalling */
638 temp = DWC_OTG_READ_4(sc, DOTG_DCTL);
639 temp |= DCTL_RMTWKUPSIG;
640 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
642 /* Wait 8ms for remote wakeup to complete. */
643 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
645 temp &= ~DCTL_RMTWKUPSIG;
646 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp);
648 /* enable USB port */
649 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0);
652 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
655 sc->sc_hprt_val |= HPRT_PRTRES;
656 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
658 /* Wait 100ms for resume signalling to complete. */
659 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
661 /* clear suspend and resume */
662 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES);
663 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
666 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
669 /* need to fake resume IRQ */
670 dwc_otg_resume_irq(sc);
674 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr)
678 DPRINTFN(5, "addr=%d\n", addr);
680 temp = DWC_OTG_READ_4(sc, DOTG_DCFG);
681 temp &= ~DCFG_DEVADDR_SET(0x7F);
682 temp |= DCFG_DEVADDR_SET(addr);
683 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp);
687 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc)
689 DPRINTFN(5, "RX status clear\n");
691 /* enable RX FIFO level interrupt */
692 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK;
693 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
695 if (sc->sc_current_rx_bytes != 0) {
696 /* need to dump remaining data */
697 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl,
698 sc->sc_current_rx_fifo, sc->sc_bounce_buffer,
699 sc->sc_current_rx_bytes / 4);
700 /* clear number of active bytes to receive */
701 sc->sc_current_rx_bytes = 0;
703 /* clear cached status */
704 sc->sc_last_rx_status = 0;
708 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x)
712 /* clear all pending interrupts */
713 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
714 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint);
716 /* clear buffered interrupts */
717 sc->sc_chan_state[x].hcint = 0;
721 dwc_otg_host_check_tx_fifo_empty(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
725 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
727 if (td->ep_type == UE_ISOCHRONOUS) {
729 * NOTE: USB INTERRUPT transactions are executed like
730 * USB CONTROL transactions! See the setup standard
731 * chain function for more information.
733 if (!(temp & GINTSTS_PTXFEMP)) {
734 DPRINTF("Periodic TX FIFO is not empty\n");
735 if (!(sc->sc_irq_mask & GINTMSK_PTXFEMPMSK)) {
736 sc->sc_irq_mask |= GINTMSK_PTXFEMPMSK;
737 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
739 return (1); /* busy */
742 if (!(temp & GINTSTS_NPTXFEMP)) {
743 DPRINTF("Non-periodic TX FIFO is not empty\n");
744 if (!(sc->sc_irq_mask & GINTMSK_NPTXFEMPMSK)) {
745 sc->sc_irq_mask |= GINTMSK_NPTXFEMPMSK;
746 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
748 return (1); /* busy */
751 return (0); /* ready for transmit */
755 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc,
756 struct dwc_otg_td *td, uint8_t is_out)
762 if (td->channel[0] < DWC_OTG_MAX_CHANNELS)
763 return (0); /* already allocated */
765 /* check if device is suspended */
766 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
767 return (1); /* busy - cannot transfer data */
769 /* compute needed TX FIFO size */
771 if (dwc_otg_host_check_tx_fifo_empty(sc, td) != 0)
772 return (1); /* busy - cannot transfer data */
774 z = td->max_packet_count;
775 for (x = y = 0; x != sc->sc_host_ch_max; x++) {
776 /* check if channel is allocated */
777 if (sc->sc_chan_state[x].allocated != 0)
779 /* check if channel is still enabled */
780 if (sc->sc_chan_state[x].wait_halted != 0)
782 /* store channel number */
783 td->channel[y++] = x;
784 /* check if we got all channels */
789 /* reset channel variable */
790 td->channel[0] = DWC_OTG_MAX_CHANNELS;
791 td->channel[1] = DWC_OTG_MAX_CHANNELS;
792 td->channel[2] = DWC_OTG_MAX_CHANNELS;
794 dwc_otg_enable_sof_irq(sc);
795 return (1); /* busy - not enough channels */
798 for (y = 0; y != z; y++) {
802 sc->sc_chan_state[x].allocated = 1;
804 /* set wait halted */
805 sc->sc_chan_state[x].wait_halted = 1;
807 /* clear interrupts */
808 dwc_otg_clear_hcint(sc, x);
810 DPRINTF("CH=%d HCCHAR=0x%08x "
811 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt);
813 /* set active channel */
814 sc->sc_active_rx_ep |= (1 << x);
816 return (0); /* allocated */
820 dwc_otg_host_channel_free_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t index)
825 if (td->channel[index] >= DWC_OTG_MAX_CHANNELS)
826 return; /* already freed */
829 x = td->channel[index];
830 td->channel[index] = DWC_OTG_MAX_CHANNELS;
832 DPRINTF("CH=%d\n", x);
835 * We need to let programmed host channels run till complete
836 * else the host channel will stop functioning.
838 sc->sc_chan_state[x].allocated = 0;
840 /* ack any pending messages */
841 if (sc->sc_last_rx_status != 0 &&
842 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) {
843 dwc_otg_common_rx_ack(sc);
846 /* clear active channel */
847 sc->sc_active_rx_ep &= ~(1 << x);
849 /* check if already halted */
850 if (sc->sc_chan_state[x].wait_halted == 0)
853 /* disable host channel */
854 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x));
855 if (hcchar & HCCHAR_CHENA) {
856 DPRINTF("Halting channel %d\n", x);
857 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x),
858 hcchar | HCCHAR_CHDIS);
859 /* don't write HCCHAR until the channel is halted */
861 sc->sc_chan_state[x].wait_halted = 0;
866 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
869 for (x = 0; x != td->max_packet_count; x++)
870 dwc_otg_host_channel_free_sub(sc, td, x);
874 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
877 /* dump any pending messages */
878 if (sc->sc_last_rx_status == 0)
880 for (x = 0; x != td->max_packet_count; x++) {
881 if (td->channel[x] >= DWC_OTG_MAX_CHANNELS ||
882 td->channel[x] != GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status))
884 dwc_otg_common_rx_ack(sc);
890 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
892 struct usb_device_request req __aligned(4);
897 dwc_otg_host_dump_rx(sc, td);
899 if (td->channel[0] < DWC_OTG_MAX_CHANNELS) {
900 hcint = sc->sc_chan_state[td->channel[0]].hcint;
902 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
903 td->channel[0], td->state, hcint,
904 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel[0])),
905 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel[0])));
911 if (hcint & (HCINT_RETRY |
912 HCINT_ACK | HCINT_NYET)) {
913 /* give success bits priority over failure bits */
914 } else if (hcint & HCINT_STALL) {
915 DPRINTF("CH=%d STALL\n", td->channel[0]);
919 } else if (hcint & HCINT_ERRORS) {
920 DPRINTF("CH=%d ERROR\n", td->channel[0]);
922 if (td->hcsplt != 0 || td->errcnt >= 3) {
928 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
929 HCINT_ACK | HCINT_NYET)) {
930 if (!(hcint & HCINT_ERRORS))
936 case DWC_CHAN_ST_START:
939 case DWC_CHAN_ST_WAIT_ANE:
940 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
942 td->tt_scheduled = 0;
944 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
945 td->offset += td->tx_bytes;
946 td->remainder -= td->tx_bytes;
948 td->tt_scheduled = 0;
953 case DWC_CHAN_ST_WAIT_S_ANE:
954 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
956 td->tt_scheduled = 0;
958 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
963 case DWC_CHAN_ST_WAIT_C_ANE:
964 if (hcint & HCINT_NYET) {
966 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
968 td->tt_scheduled = 0;
970 } else if (hcint & HCINT_ACK) {
971 td->offset += td->tx_bytes;
972 td->remainder -= td->tx_bytes;
978 case DWC_CHAN_ST_WAIT_C_PKT:
987 /* free existing channel, if any */
988 dwc_otg_host_channel_free(sc, td);
990 if (sizeof(req) != td->remainder) {
995 if (td->hcsplt != 0) {
996 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
997 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
998 td->state = DWC_CHAN_ST_START;
1001 delta = sc->sc_last_frame_num - td->tt_start_slot;
1004 td->tt_scheduled = 0;
1005 td->state = DWC_CHAN_ST_START;
1010 /* allocate a new channel */
1011 if (dwc_otg_host_channel_alloc(sc, td, 1)) {
1012 td->state = DWC_CHAN_ST_START;
1016 if (td->hcsplt != 0) {
1017 td->hcsplt &= ~HCSPLT_COMPSPLT;
1018 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1020 td->state = DWC_CHAN_ST_WAIT_ANE;
1023 /* copy out control request */
1024 usbd_copy_out(td->pc, 0, &req, sizeof(req));
1026 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1027 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) |
1028 (1 << HCTSIZ_PKTCNT_SHIFT) |
1029 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT));
1031 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1033 hcchar = td->hcchar;
1034 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK);
1035 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT;
1037 /* must enable channel before writing data to FIFO */
1038 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1040 /* transfer data into FIFO */
1041 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl,
1042 DOTG_DFIFO(td->channel[0]), (uint32_t *)&req, sizeof(req) / 4);
1044 /* wait until next slot before trying complete split */
1045 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1047 /* store number of bytes transmitted */
1048 td->tx_bytes = sizeof(req);
1052 /* free existing channel, if any */
1053 dwc_otg_host_channel_free(sc, td);
1055 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1056 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1057 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1060 delta = sc->sc_last_frame_num - td->tt_start_slot;
1061 if (delta > DWC_OTG_TT_SLOT_MAX) {
1062 /* we missed the service interval */
1063 if (td->ep_type != UE_ISOCHRONOUS)
1067 /* allocate a new channel */
1068 if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1069 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1073 /* wait until next slot before trying complete split */
1074 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1076 td->hcsplt |= HCSPLT_COMPSPLT;
1077 td->state = DWC_CHAN_ST_WAIT_C_ANE;
1079 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel[0]),
1080 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT));
1082 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel[0]), td->hcsplt);
1084 hcchar = td->hcchar;
1085 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK);
1086 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT;
1088 /* must enable channel before writing data to FIFO */
1089 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel[0]), hcchar);
1092 return (1); /* busy */
1095 dwc_otg_host_channel_free(sc, td);
1096 return (0); /* complete */
1100 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1102 struct usb_device_request req __aligned(4);
1106 /* check endpoint status */
1108 if (sc->sc_last_rx_status == 0)
1111 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0)
1114 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1115 GRXSTSRD_STP_DATA) {
1116 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1117 GRXSTSRD_STP_COMPLETE || td->remainder != 0) {
1119 dwc_otg_common_rx_ack(sc);
1123 dwc_otg_common_rx_ack(sc);
1124 return (0); /* complete */
1127 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
1128 GRXSTSRD_DPID_DATA0) {
1130 dwc_otg_common_rx_ack(sc);
1134 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status);
1136 /* clear did stall */
1139 /* get the packet byte count */
1140 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1142 if (count != sizeof(req)) {
1143 DPRINTFN(0, "Unsupported SETUP packet "
1144 "length, %d bytes\n", count);
1146 dwc_otg_common_rx_ack(sc);
1151 dwc_otg_read_fifo(sc, td->pc, 0, sizeof(req));
1153 /* copy out control request */
1154 usbd_copy_out(td->pc, 0, &req, sizeof(req));
1156 td->offset = sizeof(req);
1159 /* sneak peek the set address */
1160 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1161 (req.bRequest == UR_SET_ADDRESS)) {
1162 /* must write address before ZLP */
1163 dwc_otg_set_address(sc, req.wValue[0] & 0x7F);
1166 /* don't send any data by default */
1167 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), DIEPCTL_EPDIS);
1168 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), DOEPCTL_EPDIS);
1170 /* reset IN endpoint buffer */
1171 dwc_otg_tx_fifo_reset(sc,
1175 /* acknowledge RX status */
1176 dwc_otg_common_rx_ack(sc);
1180 /* abort any ongoing transfer, before enabling again */
1181 if (!td->did_stall) {
1184 DPRINTFN(5, "stalling IN and OUT direction\n");
1186 temp = sc->sc_out_ctl[0];
1188 /* set stall after enabling endpoint */
1189 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0),
1190 temp | DOEPCTL_STALL);
1192 temp = sc->sc_in_ctl[0];
1194 /* set stall assuming endpoint is enabled */
1195 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0),
1196 temp | DIEPCTL_STALL);
1198 return (1); /* not complete */
1202 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1206 delta = sc->sc_tmr_val - td->tmr_val;
1208 return (1); /* busy */
1210 td->tmr_val = sc->sc_tmr_val + td->tmr_res;
1212 /* set toggle, if any */
1213 if (td->set_toggle) {
1221 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1223 uint8_t frame_num = (uint8_t)sc->sc_last_frame_num;
1225 if (td->ep_type == UE_ISOCHRONOUS) {
1226 /* non TT isochronous traffic */
1227 if (frame_num & (td->tmr_res - 1))
1229 if ((frame_num ^ td->tmr_val) & td->tmr_res)
1231 td->tmr_val = td->tmr_res + sc->sc_last_frame_num;
1234 } else if (td->ep_type == UE_INTERRUPT) {
1235 if (!td->tt_scheduled)
1237 td->tt_scheduled = 0;
1239 } else if (td->did_nak != 0) {
1240 /* check if we should pause sending queries for 125us */
1241 if (td->tmr_res == frame_num) {
1243 dwc_otg_enable_sof_irq(sc);
1246 } else if (td->set_toggle) {
1250 /* query for data one more time */
1251 td->tmr_res = frame_num;
1259 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td,
1264 /* check endpoint status */
1265 if (sc->sc_last_rx_status == 0)
1268 if (channel >= DWC_OTG_MAX_CHANNELS)
1271 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel)
1274 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) {
1275 case GRXSTSRH_IN_DATA:
1277 DPRINTF("DATA ST=%d STATUS=0x%08x\n",
1278 (int)td->state, (int)sc->sc_last_rx_status);
1280 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) {
1282 * When using SPLIT transactions on interrupt
1283 * endpoints, sometimes data occurs twice.
1285 DPRINTF("Data already received\n");
1289 /* get the packet byte count */
1290 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1292 /* check for ISOCHRONOUS endpoint */
1293 if (td->ep_type == UE_ISOCHRONOUS) {
1294 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) !=
1295 GRXSTSRD_DPID_DATA0) {
1296 /* more data to be received */
1297 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE;
1299 /* all data received */
1300 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
1301 /* verify the packet byte count */
1302 if (count != td->remainder) {
1303 /* we have a short packet */
1309 /* verify the packet byte count */
1310 if (count != td->max_packet_size) {
1311 if (count < td->max_packet_size) {
1312 /* we have a short packet */
1316 /* invalid USB packet */
1320 dwc_otg_common_rx_ack(sc);
1325 td->tt_scheduled = 0;
1328 /* verify the packet byte count */
1329 if (count > td->remainder) {
1330 /* invalid USB packet */
1334 dwc_otg_common_rx_ack(sc);
1338 /* read data from FIFO */
1339 dwc_otg_read_fifo(sc, td->pc, td->offset, count);
1341 td->remainder -= count;
1342 td->offset += count;
1343 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY;
1349 dwc_otg_common_rx_ack(sc);
1357 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1365 for (x = 0; x != td->max_packet_count; x++) {
1366 channel = td->channel[x];
1367 if (channel >= DWC_OTG_MAX_CHANNELS)
1369 hcint |= sc->sc_chan_state[channel].hcint;
1371 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
1372 channel, td->state, hcint,
1373 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1374 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1376 /* check interrupt bits */
1377 if (hcint & (HCINT_RETRY |
1378 HCINT_ACK | HCINT_NYET)) {
1379 /* give success bits priority over failure bits */
1380 } else if (hcint & HCINT_STALL) {
1381 DPRINTF("CH=%d STALL\n", channel);
1382 td->error_stall = 1;
1385 } else if (hcint & HCINT_ERRORS) {
1386 DPRINTF("CH=%d ERROR\n", channel);
1388 if (td->hcsplt != 0 || td->errcnt >= 3) {
1389 if (td->ep_type != UE_ISOCHRONOUS) {
1396 /* check channels for data, if any */
1397 if (dwc_otg_host_data_rx_sub(sc, td, channel))
1400 /* refresh interrupt status */
1401 hcint |= sc->sc_chan_state[channel].hcint;
1403 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
1404 HCINT_ACK | HCINT_NYET)) {
1405 if (!(hcint & HCINT_ERRORS))
1410 switch (td->state) {
1411 case DWC_CHAN_ST_START:
1412 if (td->hcsplt != 0)
1417 case DWC_CHAN_ST_WAIT_ANE:
1418 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1419 if (td->ep_type == UE_INTERRUPT) {
1421 * The USB specification does not
1422 * mandate a particular data toggle
1423 * value for USB INTERRUPT
1424 * transfers. Switch the data toggle
1425 * value to receive the packet
1428 if (hcint & HCINT_DATATGLERR) {
1429 DPRINTF("Retrying packet due to "
1430 "data toggle error\n");
1434 } else if (td->ep_type == UE_ISOCHRONOUS) {
1438 td->tt_scheduled = 0;
1439 if (td->hcsplt != 0)
1443 } else if (hcint & HCINT_NYET) {
1444 if (td->hcsplt != 0) {
1448 /* not a valid token for IN endpoints */
1452 } else if (hcint & HCINT_ACK) {
1453 /* wait for data - ACK arrived first */
1454 if (!(hcint & HCINT_SOFTWARE_ONLY))
1457 if (td->ep_type == UE_ISOCHRONOUS) {
1458 /* check if we are complete */
1459 if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN) {
1462 /* get more packets */
1466 /* check if we are complete */
1467 if ((td->remainder == 0) || (td->got_short != 0)) {
1472 * Else need to receive a zero length
1476 td->tt_scheduled = 0;
1478 if (td->hcsplt != 0)
1486 case DWC_CHAN_ST_WAIT_S_ANE:
1488 * NOTE: The DWC OTG hardware provides a fake ACK in
1489 * case of interrupt and isochronous transfers:
1491 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1493 td->tt_scheduled = 0;
1495 } else if (hcint & HCINT_NYET) {
1496 td->tt_scheduled = 0;
1498 } else if (hcint & HCINT_ACK) {
1504 case DWC_CHAN_ST_WAIT_C_PKT:
1513 /* free existing channel, if any */
1514 dwc_otg_host_channel_free(sc, td);
1516 if (td->hcsplt != 0) {
1517 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
1518 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1519 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1522 delta = sc->sc_last_frame_num - td->tt_start_slot;
1523 if (delta > DWC_OTG_TT_SLOT_MAX) {
1524 if (td->ep_type != UE_ISOCHRONOUS) {
1525 /* we missed the service interval */
1530 /* complete split */
1531 td->hcsplt |= HCSPLT_COMPSPLT;
1532 } else if (dwc_otg_host_rate_check(sc, td)) {
1533 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1537 /* allocate a new channel */
1538 if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1539 td->state = DWC_CHAN_ST_WAIT_C_PKT;
1543 /* set toggle, if any */
1544 if (td->set_toggle) {
1549 td->state = DWC_CHAN_ST_WAIT_ANE;
1551 for (x = 0; x != td->max_packet_count; x++) {
1552 channel = td->channel[x];
1554 /* receive one packet */
1555 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1556 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) |
1557 (1 << HCTSIZ_PKTCNT_SHIFT) |
1558 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
1559 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
1561 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1563 hcchar = td->hcchar;
1564 hcchar |= HCCHAR_EPDIR_IN;
1566 /* receive complete split ASAP */
1567 if ((sc->sc_last_frame_num & 1) != 0 &&
1568 td->ep_type == UE_ISOCHRONOUS)
1569 hcchar |= HCCHAR_ODDFRM;
1571 hcchar &= ~HCCHAR_ODDFRM;
1573 /* must enable channel before data can be received */
1574 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1576 /* wait until next slot before trying complete split */
1577 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1582 /* free existing channel(s), if any */
1583 dwc_otg_host_channel_free(sc, td);
1585 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1586 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1587 td->state = DWC_CHAN_ST_START;
1590 delta = sc->sc_last_frame_num - td->tt_start_slot;
1593 td->tt_scheduled = 0;
1594 td->state = DWC_CHAN_ST_START;
1598 /* allocate a new channel */
1599 if (dwc_otg_host_channel_alloc(sc, td, 0)) {
1600 td->state = DWC_CHAN_ST_START;
1604 channel = td->channel[0];
1606 td->hcsplt &= ~HCSPLT_COMPSPLT;
1607 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1609 /* receive one packet */
1610 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1611 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT));
1613 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
1615 /* send after next SOF event */
1616 if ((sc->sc_last_frame_num & 1) == 0 &&
1617 td->ep_type == UE_ISOCHRONOUS)
1618 td->hcchar |= HCCHAR_ODDFRM;
1620 td->hcchar &= ~HCCHAR_ODDFRM;
1622 hcchar = td->hcchar;
1623 hcchar |= HCCHAR_EPDIR_IN;
1625 /* wait until next slot before trying complete split */
1626 td->tt_complete_slot = sc->sc_last_frame_num + 1;
1628 /* must enable channel before data can be received */
1629 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
1631 return (1); /* busy */
1634 dwc_otg_host_channel_free(sc, td);
1635 return (0); /* complete */
1639 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1647 /* check endpoint status */
1648 if (sc->sc_last_rx_status == 0)
1651 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no)
1654 /* check for SETUP packet */
1655 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1656 GRXSTSRD_STP_DATA ||
1657 (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) ==
1658 GRXSTSRD_STP_COMPLETE) {
1659 if (td->remainder == 0) {
1661 * We are actually complete and have
1662 * received the next SETUP
1664 DPRINTFN(5, "faking complete\n");
1665 return (0); /* complete */
1668 * USB Host Aborted the transfer.
1671 return (0); /* complete */
1674 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) !=
1675 GRXSTSRD_OUT_DATA) {
1677 dwc_otg_common_rx_ack(sc);
1681 /* get the packet byte count */
1682 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status);
1684 /* verify the packet byte count */
1685 if (count != td->max_packet_size) {
1686 if (count < td->max_packet_size) {
1687 /* we have a short packet */
1691 /* invalid USB packet */
1695 dwc_otg_common_rx_ack(sc);
1696 return (0); /* we are complete */
1699 /* verify the packet byte count */
1700 if (count > td->remainder) {
1701 /* invalid USB packet */
1705 dwc_otg_common_rx_ack(sc);
1706 return (0); /* we are complete */
1709 /* read data from FIFO */
1710 dwc_otg_read_fifo(sc, td->pc, td->offset, count);
1712 td->remainder -= count;
1713 td->offset += count;
1716 dwc_otg_common_rx_ack(sc);
1718 temp = sc->sc_out_ctl[td->ep_no];
1720 /* check for isochronous mode */
1721 if ((temp & DIEPCTL_EPTYPE_MASK) ==
1722 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) {
1723 /* toggle odd or even frame bit */
1724 if (temp & DIEPCTL_SETD1PID) {
1725 temp &= ~DIEPCTL_SETD1PID;
1726 temp |= DIEPCTL_SETD0PID;
1728 temp &= ~DIEPCTL_SETD0PID;
1729 temp |= DIEPCTL_SETD1PID;
1731 sc->sc_out_ctl[td->ep_no] = temp;
1734 /* check if we are complete */
1735 if ((td->remainder == 0) || got_short) {
1736 if (td->short_pkt) {
1737 /* we are complete */
1740 /* else need to receive a zero length packet */
1745 /* enable SETUP and transfer complete interrupt */
1746 if (td->ep_no == 0) {
1747 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0),
1748 DXEPTSIZ_SET_MULTI(3) |
1749 DXEPTSIZ_SET_NPKT(1) |
1750 DXEPTSIZ_SET_NBYTES(td->max_packet_size));
1752 /* allow reception of multiple packets */
1753 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no),
1754 DXEPTSIZ_SET_MULTI(1) |
1755 DXEPTSIZ_SET_NPKT(4) |
1756 DXEPTSIZ_SET_NBYTES(4 *
1757 ((td->max_packet_size + 3) & ~3)));
1759 temp = sc->sc_out_ctl[td->ep_no];
1760 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp |
1761 DOEPCTL_EPENA | DOEPCTL_CNAK);
1763 return (1); /* not complete */
1767 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
1776 dwc_otg_host_dump_rx(sc, td);
1778 /* check that last channel is complete */
1779 channel = td->channel[td->npkt];
1781 if (channel < DWC_OTG_MAX_CHANNELS) {
1782 hcint = sc->sc_chan_state[channel].hcint;
1784 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n",
1785 channel, td->state, hcint,
1786 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)),
1787 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel)));
1789 if (hcint & (HCINT_RETRY |
1790 HCINT_ACK | HCINT_NYET)) {
1791 /* give success bits priority over failure bits */
1792 } else if (hcint & HCINT_STALL) {
1793 DPRINTF("CH=%d STALL\n", channel);
1794 td->error_stall = 1;
1797 } else if (hcint & HCINT_ERRORS) {
1798 DPRINTF("CH=%d ERROR\n", channel);
1800 if (td->hcsplt != 0 || td->errcnt >= 3) {
1806 if (hcint & (HCINT_ERRORS | HCINT_RETRY |
1807 HCINT_ACK | HCINT_NYET)) {
1809 if (!(hcint & HCINT_ERRORS))
1816 switch (td->state) {
1817 case DWC_CHAN_ST_START:
1820 case DWC_CHAN_ST_WAIT_ANE:
1821 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1823 td->tt_scheduled = 0;
1825 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
1826 td->offset += td->tx_bytes;
1827 td->remainder -= td->tx_bytes;
1829 /* check if next response will be a NAK */
1830 if (hcint & HCINT_NYET)
1834 td->tt_scheduled = 0;
1836 /* check remainder */
1837 if (td->remainder == 0) {
1842 * Else we need to transmit a short
1850 case DWC_CHAN_ST_WAIT_S_ANE:
1851 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1853 td->tt_scheduled = 0;
1855 } else if (hcint & (HCINT_ACK | HCINT_NYET)) {
1861 case DWC_CHAN_ST_WAIT_C_ANE:
1862 if (hcint & HCINT_NYET) {
1864 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) {
1866 td->tt_scheduled = 0;
1868 } else if (hcint & HCINT_ACK) {
1869 td->offset += td->tx_bytes;
1870 td->remainder -= td->tx_bytes;
1873 td->tt_scheduled = 0;
1875 /* check remainder */
1876 if (td->remainder == 0) {
1880 /* else we need to transmit a short packet */
1886 case DWC_CHAN_ST_WAIT_C_PKT:
1889 case DWC_CHAN_ST_TX_WAIT_ISOC:
1890 /* Check if ISOCHRONOUS OUT traffic is complete */
1891 if ((hcint & HCINT_HCH_DONE_MASK) == 0)
1894 td->offset += td->tx_bytes;
1895 td->remainder -= td->tx_bytes;
1903 /* free existing channel(s), if any */
1904 dwc_otg_host_channel_free(sc, td);
1906 if (td->hcsplt != 0) {
1907 delta = td->tt_start_slot - sc->sc_last_frame_num - 1;
1908 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
1909 td->state = DWC_CHAN_ST_START;
1912 delta = sc->sc_last_frame_num - td->tt_start_slot;
1915 td->tt_scheduled = 0;
1916 td->state = DWC_CHAN_ST_START;
1919 } else if (dwc_otg_host_rate_check(sc, td)) {
1920 td->state = DWC_CHAN_ST_START;
1924 /* allocate a new channel */
1925 if (dwc_otg_host_channel_alloc(sc, td, 1)) {
1926 td->state = DWC_CHAN_ST_START;
1930 /* set toggle, if any */
1931 if (td->set_toggle) {
1936 if (td->ep_type == UE_ISOCHRONOUS) {
1937 /* ISOCHRONOUS OUT transfers don't have any ACKs */
1938 td->state = DWC_CHAN_ST_TX_WAIT_ISOC;
1939 td->hcsplt &= ~HCSPLT_COMPSPLT;
1940 if (td->hcsplt != 0) {
1941 /* get maximum transfer length */
1942 count = td->remainder;
1943 if (count > HCSPLT_XACTLEN_BURST) {
1944 DPRINTF("TT overflow\n");
1948 /* Update transaction position */
1949 td->hcsplt &= ~HCSPLT_XACTPOS_MASK;
1950 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT);
1952 } else if (td->hcsplt != 0) {
1953 td->hcsplt &= ~HCSPLT_COMPSPLT;
1954 /* Wait for ACK/NAK/ERR from TT */
1955 td->state = DWC_CHAN_ST_WAIT_S_ANE;
1957 /* Wait for ACK/NAK/STALL from device */
1958 td->state = DWC_CHAN_ST_WAIT_ANE;
1963 for (x = 0; x != td->max_packet_count; x++) {
1966 channel = td->channel[x];
1968 /* send one packet at a time */
1969 count = td->max_packet_size;
1970 rem_bytes = td->remainder - td->tx_bytes;
1971 if (rem_bytes < count) {
1972 /* we have a short packet */
1976 if (count == rem_bytes) {
1980 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1981 (count << HCTSIZ_XFERSIZE_SHIFT) |
1982 (1 << HCTSIZ_PKTCNT_SHIFT) |
1983 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
1984 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
1987 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1988 (count << HCTSIZ_XFERSIZE_SHIFT) |
1989 (1 << HCTSIZ_PKTCNT_SHIFT) |
1990 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT));
1993 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
1994 (count << HCTSIZ_XFERSIZE_SHIFT) |
1995 (1 << HCTSIZ_PKTCNT_SHIFT) |
1996 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT));
1999 } else if (td->ep_type == UE_ISOCHRONOUS &&
2000 td->max_packet_count > 1) {
2001 /* ISOCHRONOUS multi packet */
2002 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2003 (count << HCTSIZ_XFERSIZE_SHIFT) |
2004 (1 << HCTSIZ_PKTCNT_SHIFT) |
2005 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT));
2007 /* TODO: HCTSIZ_DOPNG */
2008 /* standard BULK/INTERRUPT/CONTROL packet */
2009 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2010 (count << HCTSIZ_XFERSIZE_SHIFT) |
2011 (1 << HCTSIZ_PKTCNT_SHIFT) |
2012 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) :
2013 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)));
2016 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2018 hcchar = td->hcchar;
2019 hcchar &= ~HCCHAR_EPDIR_IN;
2021 /* send after next SOF event */
2022 if ((sc->sc_last_frame_num & 1) == 0 &&
2023 td->ep_type == UE_ISOCHRONOUS)
2024 hcchar |= HCCHAR_ODDFRM;
2026 hcchar &= ~HCCHAR_ODDFRM;
2028 /* must enable before writing data to FIFO */
2029 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
2032 /* write data into FIFO */
2033 dwc_otg_write_fifo(sc, td->pc, td->offset +
2034 td->tx_bytes, DOTG_DFIFO(channel), count);
2037 /* store number of bytes transmitted */
2038 td->tx_bytes += count;
2040 /* store last packet index */
2043 /* check for last packet */
2044 if (count == rem_bytes)
2050 /* free existing channel, if any */
2051 dwc_otg_host_channel_free(sc, td);
2053 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1;
2054 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) {
2055 td->state = DWC_CHAN_ST_WAIT_C_PKT;
2058 delta = sc->sc_last_frame_num - td->tt_start_slot;
2059 if (delta > DWC_OTG_TT_SLOT_MAX) {
2060 /* we missed the service interval */
2061 if (td->ep_type != UE_ISOCHRONOUS)
2066 /* allocate a new channel */
2067 if (dwc_otg_host_channel_alloc(sc, td, 0)) {
2068 td->state = DWC_CHAN_ST_WAIT_C_PKT;
2072 channel = td->channel[0];
2074 td->hcsplt |= HCSPLT_COMPSPLT;
2075 td->state = DWC_CHAN_ST_WAIT_C_ANE;
2077 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel),
2078 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT));
2080 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt);
2082 hcchar = td->hcchar;
2083 hcchar &= ~HCCHAR_EPDIR_IN;
2085 /* receive complete split ASAP */
2086 if ((sc->sc_last_frame_num & 1) != 0 &&
2087 td->ep_type == UE_ISOCHRONOUS)
2088 hcchar |= HCCHAR_ODDFRM;
2090 hcchar &= ~HCCHAR_ODDFRM;
2092 /* must enable channel before data can be received */
2093 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar);
2095 /* wait until next slot before trying complete split */
2096 td->tt_complete_slot = sc->sc_last_frame_num + 1;
2098 return (1); /* busy */
2101 dwc_otg_host_channel_free(sc, td);
2102 return (0); /* complete */
2106 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
2108 uint32_t max_buffer;
2115 to = 3; /* don't loop forever! */
2117 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer;
2120 /* check for for endpoint 0 data */
2122 temp = sc->sc_last_rx_status;
2124 if ((td->ep_no == 0) && (temp != 0) &&
2125 (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2127 if ((temp & GRXSTSRD_PKTSTS_MASK) !=
2128 GRXSTSRD_STP_DATA &&
2129 (temp & GRXSTSRD_PKTSTS_MASK) !=
2130 GRXSTSRD_STP_COMPLETE) {
2132 /* dump data - wrong direction */
2133 dwc_otg_common_rx_ack(sc);
2136 * The current transfer was cancelled
2140 return (0); /* complete */
2144 /* fill in more TX data, if possible */
2145 if (td->tx_bytes != 0) {
2149 /* check if packets have been transferred */
2150 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2152 /* get current packet number */
2153 cpkt = DXEPTSIZ_GET_NPKT(temp);
2155 if (cpkt >= td->npkt) {
2158 if (max_buffer != 0) {
2159 fifo_left = (td->npkt - cpkt) *
2160 td->max_packet_size;
2162 if (fifo_left > max_buffer)
2163 fifo_left = max_buffer;
2165 fifo_left = td->max_packet_size;
2169 count = td->tx_bytes;
2170 if (count > fifo_left)
2174 /* write data into FIFO */
2175 dwc_otg_write_fifo(sc, td->pc, td->offset,
2176 DOTG_DFIFO(td->ep_no), count);
2178 td->tx_bytes -= count;
2179 td->remainder -= count;
2180 td->offset += count;
2183 if (td->tx_bytes != 0)
2186 /* check remainder */
2187 if (td->remainder == 0) {
2189 return (0); /* complete */
2191 /* else we need to transmit a short packet */
2198 /* check if not all packets have been transferred */
2199 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2201 if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2203 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x "
2204 "DIEPCTL=0x%08x\n", td->ep_no,
2205 DXEPTSIZ_GET_NPKT(temp),
2206 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no)));
2211 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no);
2213 /* try to optimise by sending more data */
2214 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) {
2216 /* send multiple packets at the same time */
2217 mpkt = max_buffer / td->max_packet_size;
2222 count = td->remainder;
2223 if (count > 0x7FFFFF)
2224 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size);
2226 td->npkt = count / td->max_packet_size;
2229 * NOTE: We could use 0x3FE instead of "mpkt" in the
2230 * check below to get more throughput, but then we
2231 * have a dependency towards non-generic chip features
2232 * to disable the TX-FIFO-EMPTY interrupts on a per
2233 * endpoint basis. Increase the maximum buffer size of
2234 * the IN endpoint to increase the performance.
2236 if (td->npkt > mpkt) {
2238 count = td->max_packet_size * mpkt;
2239 } else if ((count == 0) || (count % td->max_packet_size)) {
2240 /* we are transmitting a short packet */
2245 /* send one packet at a time */
2247 count = td->max_packet_size;
2248 if (td->remainder < count) {
2249 /* we have a short packet */
2251 count = td->remainder;
2255 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no),
2256 DXEPTSIZ_SET_MULTI(1) |
2257 DXEPTSIZ_SET_NPKT(td->npkt) |
2258 DXEPTSIZ_SET_NBYTES(count));
2260 /* make room for buffering */
2263 temp = sc->sc_in_ctl[td->ep_no];
2265 /* check for isochronous mode */
2266 if ((temp & DIEPCTL_EPTYPE_MASK) ==
2267 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) {
2268 /* toggle odd or even frame bit */
2269 if (temp & DIEPCTL_SETD1PID) {
2270 temp &= ~DIEPCTL_SETD1PID;
2271 temp |= DIEPCTL_SETD0PID;
2273 temp &= ~DIEPCTL_SETD0PID;
2274 temp |= DIEPCTL_SETD1PID;
2276 sc->sc_in_ctl[td->ep_no] = temp;
2279 /* must enable before writing data to FIFO */
2280 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp |
2281 DIEPCTL_EPENA | DIEPCTL_CNAK);
2283 td->tx_bytes = count;
2285 /* check remainder */
2286 if (td->tx_bytes == 0 &&
2287 td->remainder == 0) {
2289 return (0); /* complete */
2291 /* else we need to transmit a short packet */
2296 return (1); /* not complete */
2300 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td)
2305 * If all packets are transferred we are complete:
2307 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no));
2309 /* check that all packets have been transferred */
2310 if (DXEPTSIZ_GET_NPKT(temp) != 0) {
2311 DPRINTFN(5, "busy ep=%d\n", td->ep_no);
2318 /* we only want to know if there is a SETUP packet or free IN packet */
2320 temp = sc->sc_last_rx_status;
2322 if ((td->ep_no == 0) && (temp != 0) &&
2323 (GRXSTSRD_CHNUM_GET(temp) == 0)) {
2325 if ((temp & GRXSTSRD_PKTSTS_MASK) ==
2326 GRXSTSRD_STP_DATA ||
2327 (temp & GRXSTSRD_PKTSTS_MASK) ==
2328 GRXSTSRD_STP_COMPLETE) {
2329 DPRINTFN(5, "faking complete\n");
2331 * Race condition: We are complete!
2335 /* dump data - wrong direction */
2336 dwc_otg_common_rx_ack(sc);
2339 return (1); /* not complete */
2343 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer)
2345 struct dwc_otg_td *td;
2352 td = xfer->td_transfer_cache;
2357 if ((td->func) (sc, td)) {
2358 /* operation in progress */
2361 if (((void *)td) == xfer->td_transfer_last) {
2364 if (td->error_any) {
2366 } else if (td->remainder > 0) {
2368 * We had a short transfer. If there is no alternate
2369 * next, stop processing !
2376 * Fetch the next transfer descriptor and transfer
2377 * some flags to the next transfer descriptor
2379 tmr_res = td->tmr_res;
2380 tmr_val = td->tmr_val;
2381 toggle = td->toggle;
2383 xfer->td_transfer_cache = td;
2384 td->toggle = toggle; /* transfer toggle */
2385 td->tmr_res = tmr_res;
2386 td->tmr_val = tmr_val;
2391 xfer->td_transfer_cache = NULL;
2392 sc->sc_xfer_complete = 1;
2396 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer)
2398 struct dwc_otg_td *td;
2402 td = xfer->td_transfer_cache;
2404 /* compute all actual lengths */
2405 dwc_otg_standard_done(xfer);
2412 dwc_otg_timer(void *_sc)
2414 struct dwc_otg_softc *sc = _sc;
2416 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2420 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2422 /* increment timer value */
2425 /* enable SOF interrupt, which will poll jobs */
2426 dwc_otg_enable_sof_irq(sc);
2428 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2430 if (sc->sc_timer_active) {
2432 usb_callout_reset(&sc->sc_timer,
2433 hz / (1000 / DWC_OTG_HOST_TIMER_RATE),
2434 &dwc_otg_timer, sc);
2439 dwc_otg_timer_start(struct dwc_otg_softc *sc)
2441 if (sc->sc_timer_active != 0)
2444 sc->sc_timer_active = 1;
2447 usb_callout_reset(&sc->sc_timer,
2448 hz / (1000 / DWC_OTG_HOST_TIMER_RATE),
2449 &dwc_otg_timer, sc);
2453 dwc_otg_timer_stop(struct dwc_otg_softc *sc)
2455 if (sc->sc_timer_active == 0)
2458 sc->sc_timer_active = 0;
2461 usb_callout_stop(&sc->sc_timer);
2465 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo)
2467 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX)
2468 pinfo->slot_index++;
2469 return (pinfo->slot_index);
2473 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc)
2475 TAILQ_HEAD(, usb_xfer) head;
2476 struct usb_xfer *xfer;
2477 struct usb_xfer *xfer_next;
2478 struct dwc_otg_td *td;
2482 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK;
2484 if (sc->sc_last_frame_num == temp)
2487 sc->sc_last_frame_num = temp;
2491 if ((temp & 7) == 0) {
2493 /* reset the schedule */
2494 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info));
2496 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2497 td = xfer->td_transfer_cache;
2498 if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2501 /* check for IN direction */
2502 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0)
2507 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2511 slot = dwc_otg_compute_isoc_rx_tt_slot(
2512 sc->sc_tt_info + td->tt_index);
2515 * Not enough time to get complete
2521 td->tt_start_slot = temp + slot;
2522 td->tt_scheduled = 1;
2523 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2524 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2527 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2528 td = xfer->td_transfer_cache;
2529 if (td == NULL || td->ep_type != UE_ISOCHRONOUS)
2532 /* check for OUT direction */
2533 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0)
2538 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2542 td->tt_start_slot = temp;
2543 td->tt_scheduled = 1;
2544 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2545 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2548 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2549 td = xfer->td_transfer_cache;
2550 if (td == NULL || td->ep_type != UE_INTERRUPT)
2553 if (td->tt_scheduled != 0) {
2558 if (dwc_otg_host_rate_check_interrupt(sc, td))
2561 if (td->hcsplt == 0) {
2563 td->tt_scheduled = 1;
2568 td->tt_start_slot = temp;
2570 td->tt_scheduled = 1;
2571 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2572 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2575 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2576 td = xfer->td_transfer_cache;
2578 td->ep_type != UE_CONTROL) {
2584 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2588 td->tt_start_slot = temp;
2589 td->tt_scheduled = 1;
2590 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2591 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2594 if ((temp & 7) < 6) {
2595 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2596 td = xfer->td_transfer_cache;
2598 td->ep_type != UE_BULK) {
2604 if (td->hcsplt == 0 || td->tt_scheduled != 0)
2608 td->tt_start_slot = temp;
2609 td->tt_scheduled = 1;
2610 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2611 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2615 /* Put TT transfers in execution order at the end */
2616 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2618 /* move all TT transfers in front, keeping the current order */
2619 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2620 td = xfer->td_transfer_cache;
2621 if (td == NULL || td->hcsplt == 0)
2623 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2624 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2626 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry);
2627 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2629 /* put non-TT non-ISOCHRONOUS transfers last */
2630 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) {
2631 td = xfer->td_transfer_cache;
2632 if (td == NULL || td->hcsplt != 0 || td->ep_type == UE_ISOCHRONOUS)
2634 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry);
2635 TAILQ_INSERT_TAIL(&head, xfer, wait_entry);
2637 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry);
2639 if ((temp & 7) == 0) {
2641 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n",
2642 (int)temp, (int)sc->sc_needsof);
2644 /* update SOF IRQ mask */
2645 if (sc->sc_irq_mask & GINTMSK_SOFMSK) {
2646 if (sc->sc_needsof == 0) {
2647 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2648 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2651 if (sc->sc_needsof != 0) {
2652 sc->sc_irq_mask |= GINTMSK_SOFMSK;
2653 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2657 /* clear need SOF flag */
2664 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc)
2666 struct usb_xfer *xfer;
2670 uint8_t got_rx_status;
2673 if (sc->sc_flags.status_device_mode == 0) {
2675 * Update host transfer schedule, so that new
2676 * transfers can be issued:
2678 dwc_otg_update_host_transfer_schedule_locked(sc);
2682 if (++count == 16) {
2683 /* give other interrupts a chance */
2688 /* get all host channel interrupts */
2689 haint = DWC_OTG_READ_4(sc, DOTG_HAINT);
2692 if (x >= sc->sc_host_ch_max)
2694 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x));
2695 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp);
2696 temp &= ~HCINT_SOFTWARE_ONLY;
2697 sc->sc_chan_state[x].hcint |= temp;
2698 haint &= ~(1U << x);
2701 if (sc->sc_last_rx_status == 0) {
2703 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2704 if (temp & GINTSTS_RXFLVL) {
2705 /* pop current status */
2706 sc->sc_last_rx_status =
2707 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD);
2710 if (sc->sc_last_rx_status != 0) {
2714 temp = sc->sc_last_rx_status &
2715 GRXSTSRD_PKTSTS_MASK;
2717 /* non-data messages we simply skip */
2718 if (temp != GRXSTSRD_STP_DATA &&
2719 temp != GRXSTSRD_STP_COMPLETE &&
2720 temp != GRXSTSRD_OUT_DATA) {
2721 /* check for halted channel */
2722 if (temp == GRXSTSRH_HALTED) {
2723 ep_no = GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status);
2724 sc->sc_chan_state[ep_no].wait_halted = 0;
2725 DPRINTFN(5, "channel halt complete ch=%u\n", ep_no);
2727 /* store bytes and FIFO offset */
2728 sc->sc_current_rx_bytes = 0;
2729 sc->sc_current_rx_fifo = 0;
2731 /* acknowledge status */
2732 dwc_otg_common_rx_ack(sc);
2736 temp = GRXSTSRD_BCNT_GET(
2737 sc->sc_last_rx_status);
2738 ep_no = GRXSTSRD_CHNUM_GET(
2739 sc->sc_last_rx_status);
2741 /* store bytes and FIFO offset */
2742 sc->sc_current_rx_bytes = (temp + 3) & ~3;
2743 sc->sc_current_rx_fifo = DOTG_DFIFO(ep_no);
2745 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no);
2747 /* check if we should dump the data */
2748 if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2749 dwc_otg_common_rx_ack(sc);
2755 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n",
2756 sc->sc_last_rx_status, ep_no,
2757 (sc->sc_last_rx_status >> 15) & 3,
2758 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status),
2759 (sc->sc_last_rx_status >> 17) & 15);
2766 ep_no = GRXSTSRD_CHNUM_GET(
2767 sc->sc_last_rx_status);
2769 /* check if we should dump the data */
2770 if (!(sc->sc_active_rx_ep & (1U << ep_no))) {
2771 dwc_otg_common_rx_ack(sc);
2779 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
2780 dwc_otg_xfer_do_fifo(sc, xfer);
2782 if (got_rx_status) {
2783 /* check if data was consumed */
2784 if (sc->sc_last_rx_status == 0)
2787 /* disable RX FIFO level interrupt */
2788 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK;
2789 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2794 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc)
2796 struct usb_xfer *xfer;
2798 /* scan for completion events */
2799 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2800 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
2806 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on)
2808 DPRINTFN(5, "vbus = %u\n", is_on);
2811 * If the USB host mode is forced, then assume VBUS is always
2812 * present else rely on the input to this function:
2814 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) {
2816 if (!sc->sc_flags.status_vbus) {
2817 sc->sc_flags.status_vbus = 1;
2819 /* complete root HUB interrupt endpoint */
2821 dwc_otg_root_intr(sc);
2824 if (sc->sc_flags.status_vbus) {
2825 sc->sc_flags.status_vbus = 0;
2826 sc->sc_flags.status_bus_reset = 0;
2827 sc->sc_flags.status_suspend = 0;
2828 sc->sc_flags.change_suspend = 0;
2829 sc->sc_flags.change_connect = 1;
2831 /* complete root HUB interrupt endpoint */
2833 dwc_otg_root_intr(sc);
2839 dwc_otg_filter_interrupt(void *arg)
2841 struct dwc_otg_softc *sc = arg;
2842 int retval = FILTER_HANDLED;
2845 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2847 /* read and clear interrupt status */
2848 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2850 /* clear interrupts we are handling here */
2851 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ);
2853 /* check for USB state change interrupts */
2854 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0)
2855 retval = FILTER_SCHEDULE_THREAD;
2857 /* clear FIFO empty interrupts */
2858 if (status & sc->sc_irq_mask &
2859 (GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP)) {
2860 sc->sc_irq_mask &= ~(GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
2861 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2863 /* clear all IN endpoint interrupts */
2864 if (status & GINTSTS_IEPINT) {
2868 for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
2869 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x));
2871 * NOTE: Need to clear all interrupt bits,
2872 * because some appears to be unmaskable and
2873 * can cause an interrupt loop:
2876 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), temp);
2880 /* poll FIFOs, if any */
2881 dwc_otg_interrupt_poll_locked(sc);
2883 if (sc->sc_xfer_complete != 0)
2884 retval = FILTER_SCHEDULE_THREAD;
2886 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2892 dwc_otg_interrupt(void *arg)
2894 struct dwc_otg_softc *sc = arg;
2897 USB_BUS_LOCK(&sc->sc_bus);
2898 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2900 /* read and clear interrupt status */
2901 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS);
2903 /* clear interrupts we are handling here */
2904 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ);
2906 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n",
2907 status, DWC_OTG_READ_4(sc, DOTG_HAINT),
2908 DWC_OTG_READ_4(sc, DOTG_HFNUM));
2910 if (status & GINTSTS_USBRST) {
2912 /* set correct state */
2913 sc->sc_flags.status_device_mode = 1;
2914 sc->sc_flags.status_bus_reset = 0;
2915 sc->sc_flags.status_suspend = 0;
2916 sc->sc_flags.change_suspend = 0;
2917 sc->sc_flags.change_connect = 1;
2919 /* Disable SOF interrupt */
2920 sc->sc_irq_mask &= ~GINTMSK_SOFMSK;
2921 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2923 /* complete root HUB interrupt endpoint */
2924 dwc_otg_root_intr(sc);
2927 /* check for any bus state change interrupts */
2928 if (status & GINTSTS_ENUMDONE) {
2932 DPRINTFN(5, "end of reset\n");
2934 /* set correct state */
2935 sc->sc_flags.status_device_mode = 1;
2936 sc->sc_flags.status_bus_reset = 1;
2937 sc->sc_flags.status_suspend = 0;
2938 sc->sc_flags.change_suspend = 0;
2939 sc->sc_flags.change_connect = 1;
2940 sc->sc_flags.status_low_speed = 0;
2941 sc->sc_flags.port_enabled = 1;
2944 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE);
2946 /* reset function address */
2947 dwc_otg_set_address(sc, 0);
2949 /* figure out enumeration speed */
2950 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
2951 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI)
2952 sc->sc_flags.status_high_speed = 1;
2954 sc->sc_flags.status_high_speed = 0;
2957 * Disable resume and SOF interrupt, and enable
2958 * suspend and RX frame interrupt:
2960 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK);
2961 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK;
2962 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
2964 /* complete root HUB interrupt endpoint */
2965 dwc_otg_root_intr(sc);
2968 if (status & GINTSTS_PRTINT) {
2971 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT);
2973 /* clear change bits */
2974 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & (
2975 HPRT_PRTPWR | HPRT_PRTENCHNG |
2976 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) |
2979 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt);
2981 sc->sc_flags.status_device_mode = 0;
2983 if (hprt & HPRT_PRTCONNSTS)
2984 sc->sc_flags.status_bus_reset = 1;
2986 sc->sc_flags.status_bus_reset = 0;
2988 if ((hprt & HPRT_PRTENCHNG) &&
2989 (hprt & HPRT_PRTENA) == 0)
2990 sc->sc_flags.change_enabled = 1;
2992 if (hprt & HPRT_PRTENA)
2993 sc->sc_flags.port_enabled = 1;
2995 sc->sc_flags.port_enabled = 0;
2997 if (hprt & HPRT_PRTOVRCURRCHNG)
2998 sc->sc_flags.change_over_current = 1;
3000 if (hprt & HPRT_PRTOVRCURRACT)
3001 sc->sc_flags.port_over_current = 1;
3003 sc->sc_flags.port_over_current = 0;
3005 if (hprt & HPRT_PRTPWR)
3006 sc->sc_flags.port_powered = 1;
3008 sc->sc_flags.port_powered = 0;
3010 if (((hprt & HPRT_PRTSPD_MASK)
3011 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW)
3012 sc->sc_flags.status_low_speed = 1;
3014 sc->sc_flags.status_low_speed = 0;
3016 if (((hprt & HPRT_PRTSPD_MASK)
3017 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH)
3018 sc->sc_flags.status_high_speed = 1;
3020 sc->sc_flags.status_high_speed = 0;
3022 if (hprt & HPRT_PRTCONNDET)
3023 sc->sc_flags.change_connect = 1;
3025 if (hprt & HPRT_PRTSUSP)
3026 dwc_otg_suspend_irq(sc);
3028 dwc_otg_resume_irq(sc);
3030 /* complete root HUB interrupt endpoint */
3031 dwc_otg_root_intr(sc);
3033 /* update host frame interval */
3034 dwc_otg_update_host_frame_interval(sc);
3038 * If resume and suspend is set at the same time we interpret
3039 * that like RESUME. Resume is set when there is at least 3
3040 * milliseconds of inactivity on the USB BUS.
3042 if (status & GINTSTS_WKUPINT) {
3044 DPRINTFN(5, "resume interrupt\n");
3046 dwc_otg_resume_irq(sc);
3048 } else if (status & GINTSTS_USBSUSP) {
3050 DPRINTFN(5, "suspend interrupt\n");
3052 dwc_otg_suspend_irq(sc);
3055 if (status & (GINTSTS_USBSUSP |
3058 GINTSTS_SESSREQINT)) {
3061 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
3063 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp);
3065 dwc_otg_vbus_interrupt(sc,
3066 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
3069 if (sc->sc_xfer_complete != 0) {
3070 sc->sc_xfer_complete = 0;
3072 /* complete FIFOs, if any */
3073 dwc_otg_interrupt_complete_locked(sc);
3075 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3076 USB_BUS_UNLOCK(&sc->sc_bus);
3080 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp)
3082 struct dwc_otg_td *td;
3084 /* get current Transfer Descriptor */
3088 /* prepare for next TD */
3089 temp->td_next = td->obj_next;
3091 /* fill out the Transfer Descriptor */
3092 td->func = temp->func;
3094 td->offset = temp->offset;
3095 td->remainder = temp->len;
3098 td->error_stall = 0;
3100 td->did_stall = temp->did_stall;
3101 td->short_pkt = temp->short_pkt;
3102 td->alt_next = temp->setup_alt_next;
3106 td->channel[0] = DWC_OTG_MAX_CHANNELS;
3107 td->channel[1] = DWC_OTG_MAX_CHANNELS;
3108 td->channel[2] = DWC_OTG_MAX_CHANNELS;
3111 td->tt_scheduled = 0;
3112 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN;
3116 dwc_otg_setup_standard_chain(struct usb_xfer *xfer)
3118 struct dwc_otg_std_temp temp;
3119 struct dwc_otg_td *td;
3124 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
3125 xfer->address, UE_GET_ADDR(xfer->endpointno),
3126 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
3128 temp.max_frame_size = xfer->max_frame_size;
3130 td = xfer->td_start[0];
3131 xfer->td_transfer_first = td;
3132 xfer->td_transfer_cache = td;
3138 temp.td_next = xfer->td_start[0];
3140 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
3141 xfer->flags_int.isochronous_xfr;
3142 temp.did_stall = !xfer->flags_int.control_stall;
3144 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
3146 /* check if we should prepend a setup message */
3148 if (xfer->flags_int.control_xfr) {
3149 if (xfer->flags_int.control_hdr) {
3152 temp.func = &dwc_otg_host_setup_tx;
3154 temp.func = &dwc_otg_setup_rx;
3156 temp.len = xfer->frlengths[0];
3157 temp.pc = xfer->frbuffers + 0;
3158 temp.short_pkt = temp.len ? 1 : 0;
3160 /* check for last frame */
3161 if (xfer->nframes == 1) {
3162 /* no STATUS stage yet, SETUP is last */
3163 if (xfer->flags_int.control_act)
3164 temp.setup_alt_next = 0;
3167 dwc_otg_setup_standard_chain_sub(&temp);
3174 if (x != xfer->nframes) {
3175 if (xfer->endpointno & UE_DIR_IN) {
3177 temp.func = &dwc_otg_host_data_rx;
3180 temp.func = &dwc_otg_data_tx;
3185 temp.func = &dwc_otg_host_data_tx;
3188 temp.func = &dwc_otg_data_rx;
3193 /* setup "pc" pointer */
3194 temp.pc = xfer->frbuffers + x;
3198 while (x != xfer->nframes) {
3200 /* DATA0 / DATA1 message */
3202 temp.len = xfer->frlengths[x];
3206 if (x == xfer->nframes) {
3207 if (xfer->flags_int.control_xfr) {
3208 if (xfer->flags_int.control_act) {
3209 temp.setup_alt_next = 0;
3212 temp.setup_alt_next = 0;
3215 if (temp.len == 0) {
3217 /* make sure that we send an USB packet */
3223 /* regular data transfer */
3225 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
3228 dwc_otg_setup_standard_chain_sub(&temp);
3230 if (xfer->flags_int.isochronous_xfr) {
3231 temp.offset += temp.len;
3233 /* get next Page Cache pointer */
3234 temp.pc = xfer->frbuffers + x;
3238 if (xfer->flags_int.control_xfr) {
3240 /* always setup a valid "pc" pointer for status and sync */
3241 temp.pc = xfer->frbuffers + 0;
3244 temp.setup_alt_next = 0;
3246 /* check if we need to sync */
3248 /* we need a SYNC point after TX */
3249 temp.func = &dwc_otg_data_tx_sync;
3250 dwc_otg_setup_standard_chain_sub(&temp);
3253 /* check if we should append a status stage */
3254 if (!xfer->flags_int.control_act) {
3257 * Send a DATA1 message and invert the current
3258 * endpoint direction.
3260 if (xfer->endpointno & UE_DIR_IN) {
3262 temp.func = &dwc_otg_host_data_tx;
3265 temp.func = &dwc_otg_data_rx;
3270 temp.func = &dwc_otg_host_data_rx;
3273 temp.func = &dwc_otg_data_tx;
3278 dwc_otg_setup_standard_chain_sub(&temp);
3280 /* data toggle should be DATA1 */
3285 /* we need a SYNC point after TX */
3286 temp.func = &dwc_otg_data_tx_sync;
3287 dwc_otg_setup_standard_chain_sub(&temp);
3291 /* check if we need to sync */
3294 temp.pc = xfer->frbuffers + 0;
3297 temp.setup_alt_next = 0;
3299 /* we need a SYNC point after TX */
3300 temp.func = &dwc_otg_data_tx_sync;
3301 dwc_otg_setup_standard_chain_sub(&temp);
3305 /* must have at least one frame! */
3307 xfer->td_transfer_last = td;
3311 struct dwc_otg_softc *sc;
3315 sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3317 /* get first again */
3318 td = xfer->td_transfer_first;
3319 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
3322 (xfer->address << HCCHAR_DEVADDR_SHIFT) |
3323 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) |
3324 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) |
3328 * We are not always able to meet the timing
3329 * requirements of the USB interrupt endpoint's
3330 * complete split token, when doing transfers going
3331 * via a transaction translator. Use the CONTROL
3332 * transfer type instead of the INTERRUPT transfer
3333 * type in general, as a means to workaround
3334 * that. This trick should work for both FULL and LOW
3335 * speed USB traffic going through a TT. For non-TT
3336 * traffic it works as well. The reason for using
3337 * CONTROL type instead of BULK is that some TTs might
3338 * reject LOW speed BULK traffic.
3340 if (td->ep_type == UE_INTERRUPT)
3341 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT);
3343 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT);
3345 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN)
3346 hcchar |= HCCHAR_EPDIR_IN;
3348 switch (xfer->xroot->udev->speed) {
3350 hcchar |= HCCHAR_LSPDDEV;
3352 case USB_SPEED_FULL:
3353 /* check if root HUB port is running High Speed */
3354 if (dwc_otg_uses_split(xfer->xroot->udev)) {
3355 hcsplt = HCSPLT_SPLTENA |
3356 (xfer->xroot->udev->hs_port_no <<
3357 HCSPLT_PRTADDR_SHIFT) |
3358 (xfer->xroot->udev->hs_hub_addr <<
3359 HCSPLT_HUBADDR_SHIFT);
3363 if (td->ep_type == UE_INTERRUPT) {
3365 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3368 else if (ival > 127)
3370 td->tmr_val = sc->sc_tmr_val + ival;
3372 } else if (td->ep_type == UE_ISOCHRONOUS) {
3374 td->tmr_val = sc->sc_last_frame_num;
3375 if (td->hcchar & HCCHAR_EPDIR_IN)
3379 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3382 case USB_SPEED_HIGH:
3384 if (td->ep_type == UE_INTERRUPT) {
3386 hcchar |= ((xfer->max_packet_count & 3)
3387 << HCCHAR_MC_SHIFT);
3388 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE;
3391 else if (ival > 127)
3393 td->tmr_val = sc->sc_tmr_val + ival;
3395 } else if (td->ep_type == UE_ISOCHRONOUS) {
3396 hcchar |= ((xfer->max_packet_count & 3)
3397 << HCCHAR_MC_SHIFT);
3398 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer);
3399 td->tmr_val = sc->sc_last_frame_num;
3400 if (td->hcchar & HCCHAR_EPDIR_IN)
3401 td->tmr_val += td->tmr_res;
3405 td->tmr_res = (uint8_t)sc->sc_last_frame_num;
3415 /* store configuration in all TD's */
3417 td->hcchar = hcchar;
3418 td->hcsplt = hcsplt;
3420 if (((void *)td) == xfer->td_transfer_last)
3429 dwc_otg_timeout(void *arg)
3431 struct usb_xfer *xfer = arg;
3433 DPRINTF("xfer=%p\n", xfer);
3435 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
3437 /* transfer is transferred */
3438 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT);
3442 dwc_otg_start_standard_chain(struct usb_xfer *xfer)
3444 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3449 * Poll one time in device mode, which will turn on the
3450 * endpoint interrupts. Else wait for SOF interrupt in host
3453 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3455 if (sc->sc_flags.status_device_mode != 0) {
3456 dwc_otg_xfer_do_fifo(sc, xfer);
3457 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
3460 struct dwc_otg_td *td = xfer->td_transfer_cache;
3461 if (td->ep_type == UE_ISOCHRONOUS &&
3462 (td->hcchar & HCCHAR_EPDIR_IN) == 0) {
3464 * Need to start ISOCHRONOUS OUT transfer ASAP
3465 * because execution is delayed by one 125us
3468 dwc_otg_xfer_do_fifo(sc, xfer);
3469 if (dwc_otg_xfer_do_complete_locked(sc, xfer))
3474 /* put transfer on interrupt queue */
3475 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3477 /* start timeout, if any */
3478 if (xfer->timeout != 0) {
3479 usbd_transfer_timeout_ms(xfer,
3480 &dwc_otg_timeout, xfer->timeout);
3483 if (sc->sc_flags.status_device_mode != 0)
3486 /* enable SOF interrupt, if any */
3487 dwc_otg_enable_sof_irq(sc);
3489 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3493 dwc_otg_root_intr(struct dwc_otg_softc *sc)
3497 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3500 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
3502 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3503 sizeof(sc->sc_hub_idata));
3507 dwc_otg_standard_done_sub(struct usb_xfer *xfer)
3509 struct dwc_otg_td *td;
3515 td = xfer->td_transfer_cache;
3518 len = td->remainder;
3520 /* store last data toggle */
3521 xfer->endpoint->toggle_next = td->toggle;
3523 if (xfer->aframes != xfer->nframes) {
3525 * Verify the length and subtract
3526 * the remainder from "frlengths[]":
3528 if (len > xfer->frlengths[xfer->aframes]) {
3531 xfer->frlengths[xfer->aframes] -= len;
3534 /* Check for transfer error */
3535 if (td->error_any) {
3536 /* the transfer is finished */
3537 error = (td->error_stall ?
3538 USB_ERR_STALLED : USB_ERR_IOERROR);
3542 /* Check for short transfer */
3544 if (xfer->flags_int.short_frames_ok ||
3545 xfer->flags_int.isochronous_xfr) {
3546 /* follow alt next */
3553 /* the transfer is finished */
3561 /* this USB frame is complete */
3567 /* update transfer cache */
3569 xfer->td_transfer_cache = td;
3575 dwc_otg_standard_done(struct usb_xfer *xfer)
3577 usb_error_t err = 0;
3579 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
3580 xfer, xfer->endpoint);
3584 xfer->td_transfer_cache = xfer->td_transfer_first;
3586 if (xfer->flags_int.control_xfr) {
3588 if (xfer->flags_int.control_hdr) {
3590 err = dwc_otg_standard_done_sub(xfer);
3594 if (xfer->td_transfer_cache == NULL) {
3598 while (xfer->aframes != xfer->nframes) {
3600 err = dwc_otg_standard_done_sub(xfer);
3603 if (xfer->td_transfer_cache == NULL) {
3608 if (xfer->flags_int.control_xfr &&
3609 !xfer->flags_int.control_act) {
3611 err = dwc_otg_standard_done_sub(xfer);
3614 dwc_otg_device_done(xfer, err);
3617 /*------------------------------------------------------------------------*
3618 * dwc_otg_device_done
3620 * NOTE: this function can be called more than one time on the
3621 * same USB transfer!
3622 *------------------------------------------------------------------------*/
3624 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
3626 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
3628 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n",
3629 xfer, xfer->endpoint, error);
3631 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3633 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
3634 /* Interrupts are cleared by the interrupt handler */
3636 struct dwc_otg_td *td;
3638 td = xfer->td_transfer_cache;
3640 dwc_otg_host_channel_free(sc, td);
3642 /* dequeue transfer and start next transfer */
3643 usbd_transfer_done(xfer, error);
3645 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3649 dwc_otg_xfer_stall(struct usb_xfer *xfer)
3651 dwc_otg_device_done(xfer, USB_ERR_STALLED);
3655 dwc_otg_set_stall(struct usb_device *udev,
3656 struct usb_endpoint *ep, uint8_t *did_stall)
3658 struct dwc_otg_softc *sc;
3663 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3666 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3671 sc = DWC_OTG_BUS2SC(udev->bus);
3673 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3675 /* get endpoint address */
3676 ep_no = ep->edesc->bEndpointAddress;
3678 DPRINTFN(5, "endpoint=0x%x\n", ep_no);
3680 if (ep_no & UE_DIR_IN) {
3681 reg = DOTG_DIEPCTL(ep_no & UE_ADDR);
3682 temp = sc->sc_in_ctl[ep_no & UE_ADDR];
3684 reg = DOTG_DOEPCTL(ep_no & UE_ADDR);
3685 temp = sc->sc_out_ctl[ep_no & UE_ADDR];
3688 /* disable and stall endpoint */
3689 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3690 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL);
3692 /* clear active OUT ep */
3693 if (!(ep_no & UE_DIR_IN)) {
3695 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR));
3697 if (sc->sc_last_rx_status != 0 &&
3698 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET(
3699 sc->sc_last_rx_status)) {
3701 dwc_otg_common_rx_ack(sc);
3702 /* poll interrupt */
3703 dwc_otg_interrupt_poll_locked(sc);
3704 dwc_otg_interrupt_complete_locked(sc);
3707 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3711 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps,
3712 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
3717 if (ep_type == UE_CONTROL) {
3718 /* clearing stall is not needed */
3723 reg = DOTG_DIEPCTL(ep_no);
3725 reg = DOTG_DOEPCTL(ep_no);
3726 sc->sc_active_rx_ep |= (1U << ep_no);
3729 /* round up and mask away the multiplier count */
3730 mps = (mps + 3) & 0x7FC;
3732 if (ep_type == UE_BULK) {
3733 temp = DIEPCTL_EPTYPE_SET(
3734 DIEPCTL_EPTYPE_BULK) |
3736 } else if (ep_type == UE_INTERRUPT) {
3737 temp = DIEPCTL_EPTYPE_SET(
3738 DIEPCTL_EPTYPE_INTERRUPT) |
3741 temp = DIEPCTL_EPTYPE_SET(
3742 DIEPCTL_EPTYPE_ISOC) |
3746 temp |= DIEPCTL_MPS_SET(mps);
3747 temp |= DIEPCTL_TXFNUM_SET(ep_no);
3750 sc->sc_in_ctl[ep_no] = temp;
3752 sc->sc_out_ctl[ep_no] = temp;
3754 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS);
3755 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID);
3756 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK);
3758 /* we only reset the transmit FIFO */
3760 dwc_otg_tx_fifo_reset(sc,
3761 GRSTCTL_TXFIFO(ep_no) |
3765 DOTG_DIEPTSIZ(ep_no), 0);
3768 /* poll interrupt */
3769 dwc_otg_interrupt_poll_locked(sc);
3770 dwc_otg_interrupt_complete_locked(sc);
3774 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3776 struct dwc_otg_softc *sc;
3777 struct usb_endpoint_descriptor *ed;
3779 DPRINTFN(5, "endpoint=%p\n", ep);
3781 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3784 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3789 sc = DWC_OTG_BUS2SC(udev->bus);
3791 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3793 /* get endpoint descriptor */
3796 /* reset endpoint */
3797 dwc_otg_clear_stall_sub_locked(sc,
3798 UGETW(ed->wMaxPacketSize),
3799 (ed->bEndpointAddress & UE_ADDR),
3800 (ed->bmAttributes & UE_XFERTYPE),
3801 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3803 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3807 dwc_otg_device_state_change(struct usb_device *udev)
3809 struct dwc_otg_softc *sc;
3813 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3819 sc = DWC_OTG_BUS2SC(udev->bus);
3821 /* deactivate all other endpoint but the control endpoint */
3822 if (udev->state == USB_STATE_CONFIGURED ||
3823 udev->state == USB_STATE_ADDRESSED) {
3825 USB_BUS_LOCK(&sc->sc_bus);
3827 for (x = 1; x != sc->sc_dev_ep_max; x++) {
3829 if (x < sc->sc_dev_in_ep_max) {
3830 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x),
3832 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0);
3835 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x),
3837 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0);
3839 USB_BUS_UNLOCK(&sc->sc_bus);
3844 dwc_otg_init(struct dwc_otg_softc *sc)
3850 /* set up the bus structure */
3851 sc->sc_bus.usbrev = USB_REV_2_0;
3852 sc->sc_bus.methods = &dwc_otg_bus_methods;
3854 usb_callout_init_mtx(&sc->sc_timer,
3855 &sc->sc_bus.bus_mtx, 0);
3857 USB_BUS_LOCK(&sc->sc_bus);
3859 /* turn on clocks */
3860 dwc_otg_clocks_on(sc);
3862 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID);
3863 DPRINTF("Version = 0x%08x\n", temp);
3866 DWC_OTG_WRITE_4(sc, DOTG_DCTL,
3869 /* wait for host to detect disconnect */
3870 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32);
3872 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL,
3875 /* wait a little bit for block to reset */
3876 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128);
3878 switch (sc->sc_mode) {
3879 case DWC_MODE_DEVICE:
3880 temp = GUSBCFG_FORCEDEVMODE;
3883 temp = GUSBCFG_FORCEHOSTMODE;
3890 if (sc->sc_phy_type == 0)
3891 sc->sc_phy_type = dwc_otg_phy_type + 1;
3892 if (sc->sc_phy_bits == 0)
3893 sc->sc_phy_bits = 16;
3895 /* select HSIC, ULPI, UTMI+ or internal PHY mode */
3896 switch (sc->sc_phy_type) {
3897 case DWC_OTG_PHY_HSIC:
3898 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3900 GUSBCFG_TRD_TIM_SET(5) | temp);
3901 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL,
3904 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3905 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3906 temp & ~GLPMCFG_HSIC_CONN);
3907 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3908 temp | GLPMCFG_HSIC_CONN);
3910 case DWC_OTG_PHY_ULPI:
3911 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3912 GUSBCFG_ULPI_UTMI_SEL |
3913 GUSBCFG_TRD_TIM_SET(5) | temp);
3914 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3916 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3917 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3918 temp & ~GLPMCFG_HSIC_CONN);
3920 case DWC_OTG_PHY_UTMI:
3921 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3922 (sc->sc_phy_bits == 16 ? GUSBCFG_PHYIF : 0) |
3923 GUSBCFG_TRD_TIM_SET(5) | temp);
3924 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3926 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3927 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3928 temp & ~GLPMCFG_HSIC_CONN);
3930 case DWC_OTG_PHY_INTERNAL:
3931 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG,
3933 GUSBCFG_TRD_TIM_SET(5) | temp);
3934 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0);
3936 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG);
3937 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG,
3938 temp & ~GLPMCFG_HSIC_CONN);
3940 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO);
3941 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN);
3942 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN |
3944 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp);
3950 /* clear global nak */
3951 DWC_OTG_WRITE_4(sc, DOTG_DCTL,
3955 /* disable USB port */
3956 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF);
3959 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3961 /* enable USB port */
3962 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0);
3965 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3967 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3);
3969 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp);
3971 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
3973 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp);
3975 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS)
3976 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS;
3978 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp);
3980 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS)
3981 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS;
3983 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4);
3985 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp);
3987 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n",
3988 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max,
3989 sc->sc_host_ch_max);
3992 if (dwc_otg_init_fifo(sc, sc->sc_mode)) {
3993 USB_BUS_UNLOCK(&sc->sc_bus);
3997 /* enable interrupts */
3998 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_THREAD_IRQ;
3999 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask);
4001 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) {
4003 /* enable all endpoint interrupts */
4004 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2);
4005 if (temp & GHWCFG2_MPI) {
4008 DPRINTF("Disable Multi Process Interrupts\n");
4010 for (x = 0; x != sc->sc_dev_in_ep_max; x++) {
4011 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0);
4012 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0);
4014 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0);
4016 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK,
4017 DIEPMSK_XFERCOMPLMSK);
4018 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0);
4019 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF);
4022 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) {
4024 temp = DWC_OTG_READ_4(sc, DOTG_HCFG);
4025 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK);
4026 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT);
4027 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp);
4030 /* only enable global IRQ */
4031 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG,
4032 GAHBCFG_GLBLINTRMSK);
4034 /* turn off clocks */
4035 dwc_otg_clocks_off(sc);
4037 /* read initial VBUS state */
4039 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL);
4041 DPRINTFN(5, "GOTCTL=0x%08x\n", temp);
4043 dwc_otg_vbus_interrupt(sc,
4044 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0);
4046 USB_BUS_UNLOCK(&sc->sc_bus);
4048 /* catch any lost interrupts */
4050 dwc_otg_do_poll(&sc->sc_bus);
4052 return (0); /* success */
4056 dwc_otg_uninit(struct dwc_otg_softc *sc)
4058 USB_BUS_LOCK(&sc->sc_bus);
4060 /* stop host timer */
4061 dwc_otg_timer_stop(sc);
4063 /* set disconnect */
4064 DWC_OTG_WRITE_4(sc, DOTG_DCTL,
4067 /* turn off global IRQ */
4068 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0);
4070 sc->sc_flags.port_enabled = 0;
4071 sc->sc_flags.port_powered = 0;
4072 sc->sc_flags.status_vbus = 0;
4073 sc->sc_flags.status_bus_reset = 0;
4074 sc->sc_flags.status_suspend = 0;
4075 sc->sc_flags.change_suspend = 0;
4076 sc->sc_flags.change_connect = 1;
4078 dwc_otg_pull_down(sc);
4079 dwc_otg_clocks_off(sc);
4081 USB_BUS_UNLOCK(&sc->sc_bus);
4083 usb_callout_drain(&sc->sc_timer);
4087 dwc_otg_suspend(struct dwc_otg_softc *sc)
4093 dwc_otg_resume(struct dwc_otg_softc *sc)
4099 dwc_otg_do_poll(struct usb_bus *bus)
4101 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus);
4103 USB_BUS_LOCK(&sc->sc_bus);
4104 USB_BUS_SPIN_LOCK(&sc->sc_bus);
4105 dwc_otg_interrupt_poll_locked(sc);
4106 dwc_otg_interrupt_complete_locked(sc);
4107 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
4108 USB_BUS_UNLOCK(&sc->sc_bus);
4111 /*------------------------------------------------------------------------*
4112 * DWC OTG bulk support
4113 * DWC OTG control support
4114 * DWC OTG interrupt support
4115 *------------------------------------------------------------------------*/
4117 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer)
4122 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer)
4124 dwc_otg_device_done(xfer, USB_ERR_CANCELLED);
4128 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer)
4133 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer)
4136 dwc_otg_setup_standard_chain(xfer);
4137 dwc_otg_start_standard_chain(xfer);
4140 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods =
4142 .open = dwc_otg_device_non_isoc_open,
4143 .close = dwc_otg_device_non_isoc_close,
4144 .enter = dwc_otg_device_non_isoc_enter,
4145 .start = dwc_otg_device_non_isoc_start,
4148 /*------------------------------------------------------------------------*
4149 * DWC OTG full speed isochronous support
4150 *------------------------------------------------------------------------*/
4152 dwc_otg_device_isoc_open(struct usb_xfer *xfer)
4157 dwc_otg_device_isoc_close(struct usb_xfer *xfer)
4159 dwc_otg_device_done(xfer, USB_ERR_CANCELLED);
4163 dwc_otg_device_isoc_enter(struct usb_xfer *xfer)
4168 dwc_otg_device_isoc_start(struct usb_xfer *xfer)
4170 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus);
4174 uint8_t shift = usbd_xfer_get_fps_shift(xfer);
4176 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
4177 xfer, xfer->endpoint->isoc_next, xfer->nframes);
4179 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) {
4180 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM);
4182 /* get the current frame index */
4183 framenum = (temp & HFNUM_FRNUM_MASK);
4185 temp = DWC_OTG_READ_4(sc, DOTG_DSTS);
4187 /* get the current frame index */
4188 framenum = DSTS_SOFFN_GET(temp);
4192 * Check if port is doing 8000 or 1000 frames per second:
4194 if (sc->sc_flags.status_high_speed)
4197 framenum &= DWC_OTG_FRAME_MASK;
4200 * Compute number of milliseconds worth of data traffic for
4201 * this USB transfer:
4203 if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
4204 msframes = ((xfer->nframes << shift) + 7) / 8;
4206 msframes = xfer->nframes;
4209 * check if the frame index is within the window where the frames
4212 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK;
4214 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) {
4216 * If there is data underflow or the pipe queue is
4217 * empty we schedule the transfer a few frames ahead
4218 * of the current frame position. Else two isochronous
4219 * transfers might overlap.
4221 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK;
4222 xfer->endpoint->is_synced = 1;
4223 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
4226 * compute how many milliseconds the insertion is ahead of the
4227 * current frame position:
4229 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK;
4232 * pre-compute when the isochronous transfer will be finished:
4234 xfer->isoc_time_complete =
4235 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes;
4238 dwc_otg_setup_standard_chain(xfer);
4240 /* compute frame number for next insertion */
4241 xfer->endpoint->isoc_next += msframes;
4243 /* start TD chain */
4244 dwc_otg_start_standard_chain(xfer);
4247 static const struct usb_pipe_methods dwc_otg_device_isoc_methods =
4249 .open = dwc_otg_device_isoc_open,
4250 .close = dwc_otg_device_isoc_close,
4251 .enter = dwc_otg_device_isoc_enter,
4252 .start = dwc_otg_device_isoc_start,
4255 /*------------------------------------------------------------------------*
4256 * DWC OTG root control support
4257 *------------------------------------------------------------------------*
4258 * Simulate a hardware HUB by handling all the necessary requests.
4259 *------------------------------------------------------------------------*/
4261 static const struct usb_device_descriptor dwc_otg_devd = {
4262 .bLength = sizeof(struct usb_device_descriptor),
4263 .bDescriptorType = UDESC_DEVICE,
4264 .bcdUSB = {0x00, 0x02},
4265 .bDeviceClass = UDCLASS_HUB,
4266 .bDeviceSubClass = UDSUBCLASS_HUB,
4267 .bDeviceProtocol = UDPROTO_HSHUBSTT,
4268 .bMaxPacketSize = 64,
4269 .bcdDevice = {0x00, 0x01},
4272 .bNumConfigurations = 1,
4275 static const struct dwc_otg_config_desc dwc_otg_confd = {
4277 .bLength = sizeof(struct usb_config_descriptor),
4278 .bDescriptorType = UDESC_CONFIG,
4279 .wTotalLength[0] = sizeof(dwc_otg_confd),
4281 .bConfigurationValue = 1,
4282 .iConfiguration = 0,
4283 .bmAttributes = UC_SELF_POWERED,
4287 .bLength = sizeof(struct usb_interface_descriptor),
4288 .bDescriptorType = UDESC_INTERFACE,
4290 .bInterfaceClass = UICLASS_HUB,
4291 .bInterfaceSubClass = UISUBCLASS_HUB,
4292 .bInterfaceProtocol = 0,
4295 .bLength = sizeof(struct usb_endpoint_descriptor),
4296 .bDescriptorType = UDESC_ENDPOINT,
4297 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT),
4298 .bmAttributes = UE_INTERRUPT,
4299 .wMaxPacketSize[0] = 8,
4304 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
4306 static const struct usb_hub_descriptor_min dwc_otg_hubd = {
4307 .bDescLength = sizeof(dwc_otg_hubd),
4308 .bDescriptorType = UDESC_HUB,
4310 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
4311 .bPwrOn2PwrGood = 50,
4312 .bHubContrCurrent = 0,
4313 .DeviceRemovable = {0}, /* port is removable */
4316 #define STRING_VENDOR \
4319 #define STRING_PRODUCT \
4320 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
4322 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor);
4323 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product);
4326 dwc_otg_roothub_exec(struct usb_device *udev,
4327 struct usb_device_request *req, const void **pptr, uint16_t *plength)
4329 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4336 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
4339 ptr = (const void *)&sc->sc_hub_temp;
4343 value = UGETW(req->wValue);
4344 index = UGETW(req->wIndex);
4346 /* demultiplex the control request */
4348 switch (req->bmRequestType) {
4349 case UT_READ_DEVICE:
4350 switch (req->bRequest) {
4351 case UR_GET_DESCRIPTOR:
4352 goto tr_handle_get_descriptor;
4354 goto tr_handle_get_config;
4356 goto tr_handle_get_status;
4362 case UT_WRITE_DEVICE:
4363 switch (req->bRequest) {
4364 case UR_SET_ADDRESS:
4365 goto tr_handle_set_address;
4367 goto tr_handle_set_config;
4368 case UR_CLEAR_FEATURE:
4369 goto tr_valid; /* nop */
4370 case UR_SET_DESCRIPTOR:
4371 goto tr_valid; /* nop */
4372 case UR_SET_FEATURE:
4378 case UT_WRITE_ENDPOINT:
4379 switch (req->bRequest) {
4380 case UR_CLEAR_FEATURE:
4381 switch (UGETW(req->wValue)) {
4382 case UF_ENDPOINT_HALT:
4383 goto tr_handle_clear_halt;
4384 case UF_DEVICE_REMOTE_WAKEUP:
4385 goto tr_handle_clear_wakeup;
4390 case UR_SET_FEATURE:
4391 switch (UGETW(req->wValue)) {
4392 case UF_ENDPOINT_HALT:
4393 goto tr_handle_set_halt;
4394 case UF_DEVICE_REMOTE_WAKEUP:
4395 goto tr_handle_set_wakeup;
4400 case UR_SYNCH_FRAME:
4401 goto tr_valid; /* nop */
4407 case UT_READ_ENDPOINT:
4408 switch (req->bRequest) {
4410 goto tr_handle_get_ep_status;
4416 case UT_WRITE_INTERFACE:
4417 switch (req->bRequest) {
4418 case UR_SET_INTERFACE:
4419 goto tr_handle_set_interface;
4420 case UR_CLEAR_FEATURE:
4421 goto tr_valid; /* nop */
4422 case UR_SET_FEATURE:
4428 case UT_READ_INTERFACE:
4429 switch (req->bRequest) {
4430 case UR_GET_INTERFACE:
4431 goto tr_handle_get_interface;
4433 goto tr_handle_get_iface_status;
4439 case UT_WRITE_CLASS_INTERFACE:
4440 case UT_WRITE_VENDOR_INTERFACE:
4444 case UT_READ_CLASS_INTERFACE:
4445 case UT_READ_VENDOR_INTERFACE:
4449 case UT_WRITE_CLASS_DEVICE:
4450 switch (req->bRequest) {
4451 case UR_CLEAR_FEATURE:
4453 case UR_SET_DESCRIPTOR:
4454 case UR_SET_FEATURE:
4461 case UT_WRITE_CLASS_OTHER:
4462 switch (req->bRequest) {
4463 case UR_CLEAR_FEATURE:
4464 goto tr_handle_clear_port_feature;
4465 case UR_SET_FEATURE:
4466 goto tr_handle_set_port_feature;
4467 case UR_CLEAR_TT_BUFFER:
4477 case UT_READ_CLASS_OTHER:
4478 switch (req->bRequest) {
4479 case UR_GET_TT_STATE:
4480 goto tr_handle_get_tt_state;
4482 goto tr_handle_get_port_status;
4488 case UT_READ_CLASS_DEVICE:
4489 switch (req->bRequest) {
4490 case UR_GET_DESCRIPTOR:
4491 goto tr_handle_get_class_descriptor;
4493 goto tr_handle_get_class_status;
4504 tr_handle_get_descriptor:
4505 switch (value >> 8) {
4510 len = sizeof(dwc_otg_devd);
4511 ptr = (const void *)&dwc_otg_devd;
4517 len = sizeof(dwc_otg_confd);
4518 ptr = (const void *)&dwc_otg_confd;
4521 switch (value & 0xff) {
4522 case 0: /* Language table */
4523 len = sizeof(usb_string_lang_en);
4524 ptr = (const void *)&usb_string_lang_en;
4527 case 1: /* Vendor */
4528 len = sizeof(dwc_otg_vendor);
4529 ptr = (const void *)&dwc_otg_vendor;
4532 case 2: /* Product */
4533 len = sizeof(dwc_otg_product);
4534 ptr = (const void *)&dwc_otg_product;
4545 tr_handle_get_config:
4547 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
4550 tr_handle_get_status:
4552 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
4555 tr_handle_set_address:
4556 if (value & 0xFF00) {
4559 sc->sc_rt_addr = value;
4562 tr_handle_set_config:
4566 sc->sc_conf = value;
4569 tr_handle_get_interface:
4571 sc->sc_hub_temp.wValue[0] = 0;
4574 tr_handle_get_tt_state:
4575 tr_handle_get_class_status:
4576 tr_handle_get_iface_status:
4577 tr_handle_get_ep_status:
4579 USETW(sc->sc_hub_temp.wValue, 0);
4583 tr_handle_set_interface:
4584 tr_handle_set_wakeup:
4585 tr_handle_clear_wakeup:
4586 tr_handle_clear_halt:
4589 tr_handle_clear_port_feature:
4593 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
4596 case UHF_PORT_SUSPEND:
4597 dwc_otg_wakeup_peer(sc);
4600 case UHF_PORT_ENABLE:
4601 if (sc->sc_flags.status_device_mode == 0) {
4602 DWC_OTG_WRITE_4(sc, DOTG_HPRT,
4603 sc->sc_hprt_val | HPRT_PRTENA);
4605 sc->sc_flags.port_enabled = 0;
4608 case UHF_C_PORT_RESET:
4609 sc->sc_flags.change_reset = 0;
4612 case UHF_C_PORT_ENABLE:
4613 sc->sc_flags.change_enabled = 0;
4616 case UHF_C_PORT_OVER_CURRENT:
4617 sc->sc_flags.change_over_current = 0;
4621 case UHF_PORT_INDICATOR:
4625 case UHF_PORT_POWER:
4626 sc->sc_flags.port_powered = 0;
4627 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4628 sc->sc_hprt_val = 0;
4629 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA);
4631 dwc_otg_pull_down(sc);
4632 dwc_otg_clocks_off(sc);
4635 case UHF_C_PORT_CONNECTION:
4636 /* clear connect change flag */
4637 sc->sc_flags.change_connect = 0;
4640 case UHF_C_PORT_SUSPEND:
4641 sc->sc_flags.change_suspend = 0;
4645 err = USB_ERR_IOERROR;
4650 tr_handle_set_port_feature:
4654 DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
4657 case UHF_PORT_ENABLE:
4660 case UHF_PORT_SUSPEND:
4661 if (sc->sc_flags.status_device_mode == 0) {
4662 /* set suspend BIT */
4663 sc->sc_hprt_val |= HPRT_PRTSUSP;
4664 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4666 /* generate HUB suspend event */
4667 dwc_otg_suspend_irq(sc);
4671 case UHF_PORT_RESET:
4672 if (sc->sc_flags.status_device_mode == 0) {
4674 DPRINTF("PORT RESET\n");
4676 /* enable PORT reset */
4677 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST);
4679 /* Wait 62.5ms for reset to complete */
4680 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4682 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4684 /* Wait 62.5ms for reset to complete */
4685 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16);
4688 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST);
4690 sc->sc_flags.change_reset = 1;
4692 err = USB_ERR_IOERROR;
4697 case UHF_PORT_INDICATOR:
4700 case UHF_PORT_POWER:
4701 sc->sc_flags.port_powered = 1;
4702 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) {
4703 sc->sc_hprt_val |= HPRT_PRTPWR;
4704 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val);
4706 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) {
4707 /* pull up D+, if any */
4708 dwc_otg_pull_up(sc);
4712 err = USB_ERR_IOERROR;
4717 tr_handle_get_port_status:
4719 DPRINTFN(9, "UR_GET_PORT_STATUS\n");
4724 if (sc->sc_flags.status_vbus)
4725 dwc_otg_clocks_on(sc);
4727 dwc_otg_clocks_off(sc);
4729 /* Select Device Side Mode */
4731 if (sc->sc_flags.status_device_mode) {
4732 value = UPS_PORT_MODE_DEVICE;
4733 dwc_otg_timer_stop(sc);
4736 dwc_otg_timer_start(sc);
4739 if (sc->sc_flags.status_high_speed)
4740 value |= UPS_HIGH_SPEED;
4741 else if (sc->sc_flags.status_low_speed)
4742 value |= UPS_LOW_SPEED;
4744 if (sc->sc_flags.port_powered)
4745 value |= UPS_PORT_POWER;
4747 if (sc->sc_flags.port_enabled)
4748 value |= UPS_PORT_ENABLED;
4750 if (sc->sc_flags.port_over_current)
4751 value |= UPS_OVERCURRENT_INDICATOR;
4753 if (sc->sc_flags.status_vbus &&
4754 sc->sc_flags.status_bus_reset)
4755 value |= UPS_CURRENT_CONNECT_STATUS;
4757 if (sc->sc_flags.status_suspend)
4758 value |= UPS_SUSPEND;
4760 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4764 if (sc->sc_flags.change_enabled)
4765 value |= UPS_C_PORT_ENABLED;
4766 if (sc->sc_flags.change_connect)
4767 value |= UPS_C_CONNECT_STATUS;
4768 if (sc->sc_flags.change_suspend)
4769 value |= UPS_C_SUSPEND;
4770 if (sc->sc_flags.change_reset)
4771 value |= UPS_C_PORT_RESET;
4772 if (sc->sc_flags.change_over_current)
4773 value |= UPS_C_OVERCURRENT_INDICATOR;
4775 USETW(sc->sc_hub_temp.ps.wPortChange, value);
4776 len = sizeof(sc->sc_hub_temp.ps);
4779 tr_handle_get_class_descriptor:
4783 ptr = (const void *)&dwc_otg_hubd;
4784 len = sizeof(dwc_otg_hubd);
4788 err = USB_ERR_STALLED;
4797 dwc_otg_xfer_setup(struct usb_setup_params *parm)
4799 struct usb_xfer *xfer;
4806 xfer = parm->curr_xfer;
4809 * NOTE: This driver does not use any of the parameters that
4810 * are computed from the following values. Just set some
4811 * reasonable dummies:
4813 parm->hc_max_packet_size = 0x500;
4814 parm->hc_max_packet_count = 3;
4815 parm->hc_max_frame_size = 3 * 0x500;
4817 usbd_transfer_setup_sub(parm);
4820 * compute maximum number of TDs
4822 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
4824 if (ep_type == UE_CONTROL) {
4826 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */
4827 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */;
4830 ntd = xfer->nframes + 1 /* SYNC */ ;
4834 * check if "usbd_transfer_setup_sub" set an error
4840 * allocate transfer descriptors
4844 ep_no = xfer->endpointno & UE_ADDR;
4847 * Check for a valid endpoint profile in USB device mode:
4849 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4850 const struct usb_hw_ep_profile *pf;
4852 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4855 /* should not happen */
4856 parm->err = USB_ERR_INVAL;
4862 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4864 for (n = 0; n != ntd; n++) {
4866 struct dwc_otg_td *td;
4870 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4872 /* compute shared bandwidth resource index for TT */
4873 if (dwc_otg_uses_split(parm->udev)) {
4874 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT)
4875 td->tt_index = parm->udev->device_index;
4877 td->tt_index = parm->udev->parent_hs_hub->device_index;
4879 td->tt_index = parm->udev->device_index;
4883 td->max_packet_size = xfer->max_packet_size;
4884 td->max_packet_count = xfer->max_packet_count;
4886 if (td->max_packet_count == 0 || td->max_packet_count > 3)
4887 td->max_packet_count = 1;
4889 td->ep_type = ep_type;
4890 td->obj_next = last_obj;
4894 parm->size[0] += sizeof(*td);
4897 xfer->td_start[0] = last_obj;
4901 dwc_otg_xfer_unsetup(struct usb_xfer *xfer)
4907 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4908 struct usb_endpoint *ep)
4910 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus);
4912 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n",
4914 edesc->bEndpointAddress, udev->flags.usb_mode,
4915 sc->sc_rt_addr, udev->device_index);
4917 if (udev->device_index != sc->sc_rt_addr) {
4919 if (udev->flags.usb_mode == USB_MODE_DEVICE) {
4920 if (udev->speed != USB_SPEED_FULL &&
4921 udev->speed != USB_SPEED_HIGH) {
4926 if (udev->speed == USB_SPEED_HIGH &&
4927 (edesc->wMaxPacketSize[1] & 0x18) != 0 &&
4928 (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) {
4930 DPRINTFN(-1, "Non-isochronous high bandwidth "
4931 "endpoint not supported\n");
4935 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS)
4936 ep->methods = &dwc_otg_device_isoc_methods;
4938 ep->methods = &dwc_otg_device_non_isoc_methods;
4943 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4945 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus);
4948 case USB_HW_POWER_SUSPEND:
4949 dwc_otg_suspend(sc);
4951 case USB_HW_POWER_SHUTDOWN:
4954 case USB_HW_POWER_RESUME:
4963 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4965 /* DMA delay - wait until any use of memory is finished */
4966 *pus = (2125); /* microseconds */
4970 dwc_otg_device_resume(struct usb_device *udev)
4974 /* poll all transfers again to restart resumed ones */
4975 dwc_otg_do_poll(udev->bus);
4979 dwc_otg_device_suspend(struct usb_device *udev)
4984 static const struct usb_bus_methods dwc_otg_bus_methods =
4986 .endpoint_init = &dwc_otg_ep_init,
4987 .xfer_setup = &dwc_otg_xfer_setup,
4988 .xfer_unsetup = &dwc_otg_xfer_unsetup,
4989 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile,
4990 .xfer_stall = &dwc_otg_xfer_stall,
4991 .set_stall = &dwc_otg_set_stall,
4992 .clear_stall = &dwc_otg_clear_stall,
4993 .roothub_exec = &dwc_otg_roothub_exec,
4994 .xfer_poll = &dwc_otg_do_poll,
4995 .device_state_change = &dwc_otg_device_state_change,
4996 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep,
4997 .get_dma_delay = &dwc_otg_get_dma_delay,
4998 .device_resume = &dwc_otg_device_resume,
4999 .device_suspend = &dwc_otg_device_suspend,