3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Thanks to Mentor Graphics for providing a reference driver for this USB chip
35 * This file contains the driver for the Mentor Graphics Inventra USB
36 * 2.0 High Speed Dual-Role controller.
40 #ifdef USB_GLOBAL_INCLUDE_FILE
41 #include USB_GLOBAL_INCLUDE_FILE
43 #include <sys/stdint.h>
44 #include <sys/stddef.h>
45 #include <sys/param.h>
46 #include <sys/queue.h>
47 #include <sys/types.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
51 #include <sys/module.h>
53 #include <sys/mutex.h>
54 #include <sys/condvar.h>
55 #include <sys/sysctl.h>
57 #include <sys/unistd.h>
58 #include <sys/callout.h>
59 #include <sys/malloc.h>
62 #include <dev/usb/usb.h>
63 #include <dev/usb/usbdi.h>
65 #define USB_DEBUG_VAR musbotgdebug
67 #include <dev/usb/usb_core.h>
68 #include <dev/usb/usb_debug.h>
69 #include <dev/usb/usb_busdma.h>
70 #include <dev/usb/usb_process.h>
71 #include <dev/usb/usb_transfer.h>
72 #include <dev/usb/usb_device.h>
73 #include <dev/usb/usb_hub.h>
74 #include <dev/usb/usb_util.h>
76 #include <dev/usb/usb_controller.h>
77 #include <dev/usb/usb_bus.h>
78 #endif /* USB_GLOBAL_INCLUDE_FILE */
80 #include <dev/usb/controller/musb_otg.h>
82 #define MUSBOTG_INTR_ENDPT 1
84 #define MUSBOTG_BUS2SC(bus) \
85 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \
86 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
88 #define MUSBOTG_PC2SC(pc) \
89 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
92 static int musbotgdebug = 0;
94 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
96 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN,
97 &musbotgdebug, 0, "Debug level");
100 #define MAX_NAK_TO 16
104 static const struct usb_bus_methods musbotg_bus_methods;
105 static const struct usb_pipe_methods musbotg_device_bulk_methods;
106 static const struct usb_pipe_methods musbotg_device_ctrl_methods;
107 static const struct usb_pipe_methods musbotg_device_intr_methods;
108 static const struct usb_pipe_methods musbotg_device_isoc_methods;
110 /* Control transfers: Device mode */
111 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
112 static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
113 static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
114 static musbotg_cmd_t musbotg_dev_ctrl_status;
116 /* Control transfers: Host mode */
117 static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
118 static musbotg_cmd_t musbotg_host_ctrl_data_rx;
119 static musbotg_cmd_t musbotg_host_ctrl_data_tx;
120 static musbotg_cmd_t musbotg_host_ctrl_status_rx;
121 static musbotg_cmd_t musbotg_host_ctrl_status_tx;
123 /* Bulk, Interrupt, Isochronous: Device mode */
124 static musbotg_cmd_t musbotg_dev_data_rx;
125 static musbotg_cmd_t musbotg_dev_data_tx;
127 /* Bulk, Interrupt, Isochronous: Host mode */
128 static musbotg_cmd_t musbotg_host_data_rx;
129 static musbotg_cmd_t musbotg_host_data_tx;
131 static void musbotg_device_done(struct usb_xfer *, usb_error_t);
132 static void musbotg_do_poll(struct usb_bus *);
133 static void musbotg_standard_done(struct usb_xfer *);
134 static void musbotg_interrupt_poll(struct musbotg_softc *);
135 static void musbotg_root_intr(struct musbotg_softc *);
136 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t);
137 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td);
138 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
141 * Here is a configuration that the chip supports.
143 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
145 .max_in_frame_size = 64,/* fixed */
146 .max_out_frame_size = 64, /* fixed */
148 .support_control = 1,
152 static const struct musb_otg_ep_cfg musbotg_ep_default[] = {
155 .ep_fifosz_shift = 12,
156 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_4096 | MUSB2_MASK_FIFODB,
160 .ep_fifosz_shift = 10,
161 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_512 | MUSB2_MASK_FIFODB,
165 .ep_fifosz_shift = 7,
166 .ep_fifosz_reg = MUSB2_VAL_FIFOSZ_128,
174 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx)
181 /* In device mode each EP got its own channel */
182 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
183 musbotg_ep_int_set(sc, ep, 1);
188 * All control transactions go through EP0
191 if (sc->sc_channel_mask & (1 << 0))
193 sc->sc_channel_mask |= (1 << 0);
194 musbotg_ep_int_set(sc, ep, 1);
198 for (ch = sc->sc_ep_max; ch != 0; ch--) {
199 if (sc->sc_channel_mask & (1 << ch))
202 /* check FIFO size requirement */
204 if (td->max_frame_size >
205 sc->sc_hw_ep_profile[ch].max_in_frame_size)
208 if (td->max_frame_size >
209 sc->sc_hw_ep_profile[ch].max_out_frame_size)
212 sc->sc_channel_mask |= (1 << ch);
213 musbotg_ep_int_set(sc, ch, 1);
217 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask);
223 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td)
226 DPRINTFN(1, "ep_no=%d\n", td->channel);
228 if (sc->sc_mode == MUSB2_DEVICE_MODE)
233 if (td->channel == -1)
236 musbotg_ep_int_set(sc, td->channel, 0);
237 sc->sc_channel_mask &= ~(1 << td->channel);
243 musbotg_get_hw_ep_profile(struct usb_device *udev,
244 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
246 struct musbotg_softc *sc;
248 sc = MUSBOTG_BUS2SC(udev->bus);
251 /* control endpoint */
252 *ppf = musbotg_ep_profile;
253 } else if (ep_addr <= sc->sc_ep_max) {
254 /* other endpoints */
255 *ppf = sc->sc_hw_ep_profile + ep_addr;
262 musbotg_clocks_on(struct musbotg_softc *sc)
264 if (sc->sc_flags.clocks_off &&
265 sc->sc_flags.port_powered) {
268 if (sc->sc_clocks_on) {
269 (sc->sc_clocks_on) (sc->sc_clocks_arg);
271 sc->sc_flags.clocks_off = 0;
273 /* XXX enable Transceiver */
278 musbotg_clocks_off(struct musbotg_softc *sc)
280 if (!sc->sc_flags.clocks_off) {
283 /* XXX disable Transceiver */
285 if (sc->sc_clocks_off) {
286 (sc->sc_clocks_off) (sc->sc_clocks_arg);
288 sc->sc_flags.clocks_off = 1;
293 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
297 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
299 temp |= MUSB2_MASK_SOFTC;
301 temp &= ~MUSB2_MASK_SOFTC;
303 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
307 musbotg_pull_up(struct musbotg_softc *sc)
309 /* pullup D+, if possible */
311 if (!sc->sc_flags.d_pulled_up &&
312 sc->sc_flags.port_powered) {
313 sc->sc_flags.d_pulled_up = 1;
314 musbotg_pull_common(sc, 1);
319 musbotg_pull_down(struct musbotg_softc *sc)
321 /* pulldown D+, if possible */
323 if (sc->sc_flags.d_pulled_up) {
324 sc->sc_flags.d_pulled_up = 0;
325 musbotg_pull_common(sc, 0);
330 musbotg_suspend_host(struct musbotg_softc *sc)
334 if (sc->sc_flags.status_suspend) {
338 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
339 temp |= MUSB2_MASK_SUSPMODE;
340 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
341 sc->sc_flags.status_suspend = 1;
345 musbotg_wakeup_host(struct musbotg_softc *sc)
349 if (!(sc->sc_flags.status_suspend)) {
353 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
354 temp &= ~MUSB2_MASK_SUSPMODE;
355 temp |= MUSB2_MASK_RESUME;
356 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
358 /* wait 20 milliseconds */
359 /* Wait for reset to complete. */
360 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
362 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
363 temp &= ~MUSB2_MASK_RESUME;
364 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
366 sc->sc_flags.status_suspend = 0;
370 musbotg_wakeup_peer(struct musbotg_softc *sc)
374 if (!(sc->sc_flags.status_suspend)) {
378 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
379 temp |= MUSB2_MASK_RESUME;
380 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
382 /* wait 8 milliseconds */
383 /* Wait for reset to complete. */
384 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
386 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
387 temp &= ~MUSB2_MASK_RESUME;
388 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
392 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
394 DPRINTFN(4, "addr=%d\n", addr);
396 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
400 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
402 struct musbotg_softc *sc;
403 struct usb_device_request req;
407 /* get pointer to softc */
408 sc = MUSBOTG_PC2SC(td->pc);
410 if (td->channel == -1)
411 td->channel = musbotg_channel_alloc(sc, td, 0);
413 /* EP0 is busy, wait */
414 if (td->channel == -1)
417 DPRINTFN(1, "ep_no=%d\n", td->channel);
419 /* select endpoint 0 */
420 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
422 /* read out FIFO status */
423 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
425 DPRINTFN(4, "csr=0x%02x\n", csr);
428 * NOTE: If DATAEND is set we should not call the
429 * callback, hence the status stage is not complete.
431 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
432 /* do not stall at this point */
434 /* wait for interrupt */
435 DPRINTFN(1, "CSR0 DATAEND\n");
439 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
440 /* clear SENTSTALL */
441 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
442 /* get latest status */
443 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
444 /* update EP0 state */
447 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
449 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
450 MUSB2_MASK_CSR0L_SETUPEND_CLR);
451 /* get latest status */
452 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
453 /* update EP0 state */
456 if (sc->sc_ep0_busy) {
457 DPRINTFN(1, "EP0 BUSY\n");
460 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
463 /* get the packet byte count */
464 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
466 /* verify data length */
467 if (count != td->remainder) {
468 DPRINTFN(1, "Invalid SETUP packet "
469 "length, %d bytes\n", count);
470 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
471 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
472 /* don't clear stall */
476 if (count != sizeof(req)) {
477 DPRINTFN(1, "Unsupported SETUP packet "
478 "length, %d bytes\n", count);
479 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
480 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
481 /* don't clear stall */
485 /* clear did stall flag */
489 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
490 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
492 /* copy data into real buffer */
493 usbd_copy_in(td->pc, 0, &req, sizeof(req));
495 td->offset = sizeof(req);
498 /* set pending command */
499 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
501 /* we need set stall or dataend after this */
504 /* sneak peek the set address */
505 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
506 (req.bRequest == UR_SET_ADDRESS)) {
507 sc->sc_dv_addr = req.wValue[0] & 0x7F;
509 sc->sc_dv_addr = 0xFF;
512 musbotg_channel_free(sc, td);
513 return (0); /* complete */
516 /* abort any ongoing transfer */
517 if (!td->did_stall) {
518 DPRINTFN(4, "stalling\n");
519 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
520 MUSB2_MASK_CSR0L_SENDSTALL);
523 return (1); /* not complete */
527 musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
529 struct musbotg_softc *sc;
530 struct usb_device_request req;
533 /* get pointer to softc */
534 sc = MUSBOTG_PC2SC(td->pc);
536 if (td->channel == -1)
537 td->channel = musbotg_channel_alloc(sc, td, 1);
539 /* EP0 is busy, wait */
540 if (td->channel == -1)
543 DPRINTFN(1, "ep_no=%d\n", td->channel);
545 /* select endpoint 0 */
546 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
548 /* read out FIFO status */
549 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
550 DPRINTFN(4, "csr=0x%02x\n", csr);
552 /* Not ready yet yet */
553 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
557 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
558 MUSB2_MASK_CSR0L_ERROR))
560 /* Clear status bit */
561 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
562 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
566 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
567 DPRINTFN(1, "NAK timeout\n");
569 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
570 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
571 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
572 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
573 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
574 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
575 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
576 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
577 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
578 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
582 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
583 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
589 musbotg_channel_free(sc, td);
593 /* Fifo is not empty and there is no NAK timeout */
594 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
597 /* check if we are complete */
598 if (td->remainder == 0) {
599 /* we are complete */
600 musbotg_channel_free(sc, td);
604 /* copy data into real buffer */
605 usbd_copy_out(td->pc, 0, &req, sizeof(req));
608 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
609 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
611 /* update offset and remainder */
612 td->offset += sizeof(req);
613 td->remainder -= sizeof(req);
615 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
616 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
617 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
618 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
619 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
622 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
623 MUSB2_MASK_CSR0L_TXPKTRDY |
624 MUSB2_MASK_CSR0L_SETUPPKT);
626 /* Just to be consistent, not used above */
627 td->transaction_started = 1;
629 return (1); /* in progress */
632 /* Control endpoint only data handling functions (RX/TX/SYNC) */
635 musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
637 struct usb_page_search buf_res;
638 struct musbotg_softc *sc;
643 /* get pointer to softc */
644 sc = MUSBOTG_PC2SC(td->pc);
646 /* select endpoint 0 */
647 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
649 /* check if a command is pending */
650 if (sc->sc_ep0_cmd) {
651 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
654 /* read out FIFO status */
655 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
657 DPRINTFN(4, "csr=0x%02x\n", csr);
661 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
662 MUSB2_MASK_CSR0L_SENTSTALL)) {
663 if (td->remainder == 0) {
665 * We are actually complete and have
666 * received the next SETUP
668 DPRINTFN(4, "faking complete\n");
669 return (0); /* complete */
672 * USB Host Aborted the transfer.
675 return (0); /* complete */
677 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
678 return (1); /* not complete */
680 /* get the packet byte count */
681 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
683 /* verify the packet byte count */
684 if (count != td->max_frame_size) {
685 if (count < td->max_frame_size) {
686 /* we have a short packet */
690 /* invalid USB packet */
692 return (0); /* we are complete */
695 /* verify the packet byte count */
696 if (count > td->remainder) {
697 /* invalid USB packet */
699 return (0); /* we are complete */
704 usbd_get_page(td->pc, td->offset, &buf_res);
706 /* get correct length */
707 if (buf_res.length > count) {
708 buf_res.length = count;
710 /* check for unaligned memory address */
711 if (USB_P2U(buf_res.buffer) & 3) {
715 /* receive data 4 bytes at a time */
716 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
717 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
722 /* receive data 1 byte at a time */
723 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
725 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
727 usbd_copy_in(td->pc, td->offset,
728 sc->sc_bounce_buf, count);
730 /* update offset and remainder */
732 td->remainder -= count;
735 /* check if we can optimise */
736 if (buf_res.length >= 4) {
737 /* receive data 4 bytes at a time */
738 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
739 MUSB2_REG_EPFIFO(0), buf_res.buffer,
742 temp = buf_res.length & ~3;
744 /* update counters */
747 td->remainder -= temp;
751 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
752 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
754 /* update counters */
755 count -= buf_res.length;
756 td->offset += buf_res.length;
757 td->remainder -= buf_res.length;
760 /* check if we are complete */
761 if ((td->remainder == 0) || got_short) {
763 /* we are complete */
764 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
767 /* else need to receive a zero length packet */
769 /* write command - need more data */
770 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
771 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
772 return (1); /* not complete */
776 musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
778 struct usb_page_search buf_res;
779 struct musbotg_softc *sc;
783 /* get pointer to softc */
784 sc = MUSBOTG_PC2SC(td->pc);
786 /* select endpoint 0 */
787 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
789 /* check if a command is pending */
790 if (sc->sc_ep0_cmd) {
791 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
794 /* read out FIFO status */
795 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
797 DPRINTFN(4, "csr=0x%02x\n", csr);
799 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
800 MUSB2_MASK_CSR0L_SENTSTALL)) {
802 * The current transfer was aborted
806 return (0); /* complete */
808 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
809 return (1); /* not complete */
811 count = td->max_frame_size;
812 if (td->remainder < count) {
813 /* we have a short packet */
815 count = td->remainder;
820 usbd_get_page(td->pc, td->offset, &buf_res);
822 /* get correct length */
823 if (buf_res.length > count) {
824 buf_res.length = count;
826 /* check for unaligned memory address */
827 if (USB_P2U(buf_res.buffer) & 3) {
828 usbd_copy_out(td->pc, td->offset,
829 sc->sc_bounce_buf, count);
834 /* transmit data 4 bytes at a time */
835 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
836 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
841 /* receive data 1 byte at a time */
842 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
844 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
846 /* update offset and remainder */
848 td->remainder -= count;
851 /* check if we can optimise */
852 if (buf_res.length >= 4) {
853 /* transmit data 4 bytes at a time */
854 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
855 MUSB2_REG_EPFIFO(0), buf_res.buffer,
858 temp = buf_res.length & ~3;
860 /* update counters */
863 td->remainder -= temp;
867 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
868 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
870 /* update counters */
871 count -= buf_res.length;
872 td->offset += buf_res.length;
873 td->remainder -= buf_res.length;
876 /* check remainder */
877 if (td->remainder == 0) {
879 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
880 return (0); /* complete */
882 /* else we need to transmit a short packet */
885 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
886 MUSB2_MASK_CSR0L_TXPKTRDY);
888 return (1); /* not complete */
892 musbotg_host_ctrl_data_rx(struct musbotg_td *td)
894 struct usb_page_search buf_res;
895 struct musbotg_softc *sc;
900 /* get pointer to softc */
901 sc = MUSBOTG_PC2SC(td->pc);
903 if (td->channel == -1)
904 td->channel = musbotg_channel_alloc(sc, td, 0);
906 /* EP0 is busy, wait */
907 if (td->channel == -1)
910 DPRINTFN(1, "ep_no=%d\n", td->channel);
912 /* select endpoint 0 */
913 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
915 /* read out FIFO status */
916 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
918 DPRINTFN(4, "csr=0x%02x\n", csr);
921 if (!td->transaction_started) {
922 td->transaction_started = 1;
924 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
926 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
928 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
929 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
930 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
932 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
933 MUSB2_MASK_CSR0L_REQPKT);
938 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
939 csr &= ~MUSB2_MASK_CSR0L_REQPKT;
940 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
942 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
943 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
949 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
950 MUSB2_MASK_CSR0L_ERROR))
952 /* Clear status bit */
953 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
954 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
959 musbotg_channel_free(sc, td);
960 return (0); /* we are complete */
963 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
964 return (1); /* not yet */
966 /* get the packet byte count */
967 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
969 /* verify the packet byte count */
970 if (count != td->max_frame_size) {
971 if (count < td->max_frame_size) {
972 /* we have a short packet */
976 /* invalid USB packet */
978 musbotg_channel_free(sc, td);
979 return (0); /* we are complete */
982 /* verify the packet byte count */
983 if (count > td->remainder) {
984 /* invalid USB packet */
986 musbotg_channel_free(sc, td);
987 return (0); /* we are complete */
992 usbd_get_page(td->pc, td->offset, &buf_res);
994 /* get correct length */
995 if (buf_res.length > count) {
996 buf_res.length = count;
998 /* check for unaligned memory address */
999 if (USB_P2U(buf_res.buffer) & 3) {
1003 /* receive data 4 bytes at a time */
1004 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1005 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
1010 /* receive data 1 byte at a time */
1011 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1012 MUSB2_REG_EPFIFO(0),
1013 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
1015 usbd_copy_in(td->pc, td->offset,
1016 sc->sc_bounce_buf, count);
1018 /* update offset and remainder */
1019 td->offset += count;
1020 td->remainder -= count;
1023 /* check if we can optimise */
1024 if (buf_res.length >= 4) {
1025 /* receive data 4 bytes at a time */
1026 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1027 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1028 buf_res.length / 4);
1030 temp = buf_res.length & ~3;
1032 /* update counters */
1035 td->remainder -= temp;
1039 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1040 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
1042 /* update counters */
1043 count -= buf_res.length;
1044 td->offset += buf_res.length;
1045 td->remainder -= buf_res.length;
1048 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
1049 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1051 /* check if we are complete */
1052 if ((td->remainder == 0) || got_short) {
1053 if (td->short_pkt) {
1054 /* we are complete */
1056 musbotg_channel_free(sc, td);
1059 /* else need to receive a zero length packet */
1062 td->transaction_started = 1;
1063 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1064 MUSB2_MASK_CSR0L_REQPKT);
1066 return (1); /* not complete */
1070 musbotg_host_ctrl_data_tx(struct musbotg_td *td)
1072 struct usb_page_search buf_res;
1073 struct musbotg_softc *sc;
1077 /* get pointer to softc */
1078 sc = MUSBOTG_PC2SC(td->pc);
1080 if (td->channel == -1)
1081 td->channel = musbotg_channel_alloc(sc, td, 1);
1084 if (td->channel == -1)
1087 DPRINTFN(1, "ep_no=%d\n", td->channel);
1089 /* select endpoint */
1090 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1092 /* read out FIFO status */
1093 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1094 DPRINTFN(4, "csr=0x%02x\n", csr);
1096 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1097 MUSB2_MASK_CSR0L_ERROR)) {
1098 /* clear status bits */
1099 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1103 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
1104 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1105 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1106 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1107 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1108 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1109 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1110 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1111 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1112 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1113 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1117 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1118 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1124 musbotg_channel_free(sc, td);
1125 return (0); /* complete */
1129 * Wait while FIFO is empty.
1130 * Do not flush it because it will cause transactions
1131 * with size more then packet size. It might upset
1134 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
1137 /* Packet still being processed */
1138 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1141 if (td->transaction_started) {
1142 /* check remainder */
1143 if (td->remainder == 0) {
1144 if (td->short_pkt) {
1145 musbotg_channel_free(sc, td);
1146 return (0); /* complete */
1148 /* else we need to transmit a short packet */
1151 /* We're not complete - more transactions required */
1152 td->transaction_started = 0;
1155 /* check for short packet */
1156 count = td->max_frame_size;
1157 if (td->remainder < count) {
1158 /* we have a short packet */
1160 count = td->remainder;
1166 usbd_get_page(td->pc, td->offset, &buf_res);
1168 /* get correct length */
1169 if (buf_res.length > count) {
1170 buf_res.length = count;
1172 /* check for unaligned memory address */
1173 if (USB_P2U(buf_res.buffer) & 3) {
1174 usbd_copy_out(td->pc, td->offset,
1175 sc->sc_bounce_buf, count);
1180 /* transmit data 4 bytes at a time */
1181 bus_space_write_multi_4(sc->sc_io_tag,
1182 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0),
1183 sc->sc_bounce_buf, temp / 4);
1187 /* receive data 1 byte at a time */
1188 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1189 MUSB2_REG_EPFIFO(0),
1190 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1192 /* update offset and remainder */
1193 td->offset += count;
1194 td->remainder -= count;
1197 /* check if we can optimise */
1198 if (buf_res.length >= 4) {
1199 /* transmit data 4 bytes at a time */
1200 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1201 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1202 buf_res.length / 4);
1204 temp = buf_res.length & ~3;
1206 /* update counters */
1209 td->remainder -= temp;
1213 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1214 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1217 /* update counters */
1218 count -= buf_res.length;
1219 td->offset += buf_res.length;
1220 td->remainder -= buf_res.length;
1223 /* Function address */
1224 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1225 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1226 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1227 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1229 /* TX NAK timeout */
1230 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1233 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1234 MUSB2_MASK_CSR0L_TXPKTRDY);
1236 td->transaction_started = 1;
1238 return (1); /* not complete */
1242 musbotg_dev_ctrl_status(struct musbotg_td *td)
1244 struct musbotg_softc *sc;
1247 /* get pointer to softc */
1248 sc = MUSBOTG_PC2SC(td->pc);
1250 /* select endpoint 0 */
1251 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1253 if (sc->sc_ep0_busy) {
1254 sc->sc_ep0_busy = 0;
1255 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
1256 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
1259 /* read out FIFO status */
1260 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1262 DPRINTFN(4, "csr=0x%02x\n", csr);
1264 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
1265 /* wait for interrupt */
1266 return (1); /* not complete */
1268 if (sc->sc_dv_addr != 0xFF) {
1269 /* write function address */
1270 musbotg_set_address(sc, sc->sc_dv_addr);
1273 musbotg_channel_free(sc, td);
1274 return (0); /* complete */
1278 musbotg_host_ctrl_status_rx(struct musbotg_td *td)
1280 struct musbotg_softc *sc;
1283 /* get pointer to softc */
1284 sc = MUSBOTG_PC2SC(td->pc);
1286 if (td->channel == -1)
1287 td->channel = musbotg_channel_alloc(sc, td, 0);
1289 /* EP0 is busy, wait */
1290 if (td->channel == -1)
1293 DPRINTFN(1, "ep_no=%d\n", td->channel);
1295 /* select endpoint 0 */
1296 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1298 if (!td->transaction_started) {
1299 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
1302 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
1303 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
1304 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1306 /* RX NAK timeout */
1307 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1309 td->transaction_started = 1;
1312 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1313 csrh |= MUSB2_MASK_CSR0H_PING_DIS;
1314 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1317 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1318 MUSB2_MASK_CSR0L_STATUSPKT |
1319 MUSB2_MASK_CSR0L_REQPKT);
1321 return (1); /* Just started */
1324 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1326 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
1328 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
1329 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1330 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
1331 musbotg_channel_free(sc, td);
1332 return (0); /* complete */
1335 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1336 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT |
1337 MUSB2_MASK_CSR0L_REQPKT);
1338 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1340 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1341 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1346 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1347 MUSB2_MASK_CSR0L_ERROR))
1349 /* Clear status bit */
1350 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1351 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1356 musbotg_channel_free(sc, td);
1360 return (1); /* Not ready yet */
1364 musbotg_host_ctrl_status_tx(struct musbotg_td *td)
1366 struct musbotg_softc *sc;
1369 /* get pointer to softc */
1370 sc = MUSBOTG_PC2SC(td->pc);
1372 if (td->channel == -1)
1373 td->channel = musbotg_channel_alloc(sc, td, 1);
1375 /* EP0 is busy, wait */
1376 if (td->channel == -1)
1379 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started,
1380 td->dev_addr,td->haddr,td->hport, td->transfer_type);
1382 /* select endpoint 0 */
1383 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1385 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1386 DPRINTFN(4, "csr=0x%02x\n", csr);
1389 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1393 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1394 MUSB2_MASK_CSR0L_ERROR))
1396 /* Clear status bit */
1397 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1398 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1400 musbotg_channel_free(sc, td);
1401 return (0); /* complete */
1404 if (td->transaction_started) {
1405 musbotg_channel_free(sc, td);
1406 return (0); /* complete */
1409 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS);
1411 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1412 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1413 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1414 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1416 /* TX NAK timeout */
1417 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1419 td->transaction_started = 1;
1422 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1423 MUSB2_MASK_CSR0L_STATUSPKT |
1424 MUSB2_MASK_CSR0L_TXPKTRDY);
1426 return (1); /* wait for interrupt */
1430 musbotg_dev_data_rx(struct musbotg_td *td)
1432 struct usb_page_search buf_res;
1433 struct musbotg_softc *sc;
1439 to = 8; /* don't loop forever! */
1442 /* get pointer to softc */
1443 sc = MUSBOTG_PC2SC(td->pc);
1445 if (td->channel == -1)
1446 td->channel = musbotg_channel_alloc(sc, td, 0);
1448 /* EP0 is busy, wait */
1449 if (td->channel == -1)
1452 /* select endpoint */
1453 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1456 /* read out FIFO status */
1457 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1459 DPRINTFN(4, "csr=0x%02x\n", csr);
1462 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
1463 /* make sure we don't clear "RXPKTRDY" */
1464 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1465 MUSB2_MASK_CSRL_RXPKTRDY);
1469 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
1470 return (1); /* not complete */
1472 /* get the packet byte count */
1473 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1475 DPRINTFN(4, "count=0x%04x\n", count);
1478 * Check for short or invalid packet:
1480 if (count != td->max_frame_size) {
1481 if (count < td->max_frame_size) {
1482 /* we have a short packet */
1486 /* invalid USB packet */
1488 musbotg_channel_free(sc, td);
1489 return (0); /* we are complete */
1492 /* verify the packet byte count */
1493 if (count > td->remainder) {
1494 /* invalid USB packet */
1496 musbotg_channel_free(sc, td);
1497 return (0); /* we are complete */
1502 usbd_get_page(td->pc, td->offset, &buf_res);
1504 /* get correct length */
1505 if (buf_res.length > count) {
1506 buf_res.length = count;
1508 /* check for unaligned memory address */
1509 if (USB_P2U(buf_res.buffer) & 3) {
1513 /* receive data 4 bytes at a time */
1514 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1515 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1520 /* receive data 1 byte at a time */
1521 bus_space_read_multi_1(sc->sc_io_tag,
1522 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1523 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1525 usbd_copy_in(td->pc, td->offset,
1526 sc->sc_bounce_buf, count);
1528 /* update offset and remainder */
1529 td->offset += count;
1530 td->remainder -= count;
1533 /* check if we can optimise */
1534 if (buf_res.length >= 4) {
1535 /* receive data 4 bytes at a time */
1536 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1537 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1538 buf_res.length / 4);
1540 temp = buf_res.length & ~3;
1542 /* update counters */
1545 td->remainder -= temp;
1549 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1550 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1553 /* update counters */
1554 count -= buf_res.length;
1555 td->offset += buf_res.length;
1556 td->remainder -= buf_res.length;
1559 /* clear status bits */
1560 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1562 /* check if we are complete */
1563 if ((td->remainder == 0) || got_short) {
1564 if (td->short_pkt) {
1565 /* we are complete */
1566 musbotg_channel_free(sc, td);
1569 /* else need to receive a zero length packet */
1574 return (1); /* not complete */
1578 musbotg_dev_data_tx(struct musbotg_td *td)
1580 struct usb_page_search buf_res;
1581 struct musbotg_softc *sc;
1586 to = 8; /* don't loop forever! */
1588 /* get pointer to softc */
1589 sc = MUSBOTG_PC2SC(td->pc);
1591 if (td->channel == -1)
1592 td->channel = musbotg_channel_alloc(sc, td, 1);
1594 /* EP0 is busy, wait */
1595 if (td->channel == -1)
1598 /* select endpoint */
1599 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1603 /* read out FIFO status */
1604 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1606 DPRINTFN(4, "csr=0x%02x\n", csr);
1608 if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
1609 MUSB2_MASK_CSRL_TXUNDERRUN)) {
1610 /* clear status bits */
1611 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1613 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
1614 return (1); /* not complete */
1616 /* check for short packet */
1617 count = td->max_frame_size;
1618 if (td->remainder < count) {
1619 /* we have a short packet */
1621 count = td->remainder;
1626 usbd_get_page(td->pc, td->offset, &buf_res);
1628 /* get correct length */
1629 if (buf_res.length > count) {
1630 buf_res.length = count;
1632 /* check for unaligned memory address */
1633 if (USB_P2U(buf_res.buffer) & 3) {
1634 usbd_copy_out(td->pc, td->offset,
1635 sc->sc_bounce_buf, count);
1640 /* transmit data 4 bytes at a time */
1641 bus_space_write_multi_4(sc->sc_io_tag,
1642 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1643 sc->sc_bounce_buf, temp / 4);
1647 /* receive data 1 byte at a time */
1648 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1649 MUSB2_REG_EPFIFO(td->channel),
1650 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1652 /* update offset and remainder */
1653 td->offset += count;
1654 td->remainder -= count;
1657 /* check if we can optimise */
1658 if (buf_res.length >= 4) {
1659 /* transmit data 4 bytes at a time */
1660 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1661 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1662 buf_res.length / 4);
1664 temp = buf_res.length & ~3;
1666 /* update counters */
1669 td->remainder -= temp;
1673 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1674 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1677 /* update counters */
1678 count -= buf_res.length;
1679 td->offset += buf_res.length;
1680 td->remainder -= buf_res.length;
1683 /* Max packet size */
1684 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
1687 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1688 MUSB2_MASK_CSRL_TXPKTRDY);
1690 /* check remainder */
1691 if (td->remainder == 0) {
1692 if (td->short_pkt) {
1693 musbotg_channel_free(sc, td);
1694 return (0); /* complete */
1696 /* else we need to transmit a short packet */
1701 return (1); /* not complete */
1705 musbotg_host_data_rx(struct musbotg_td *td)
1707 struct usb_page_search buf_res;
1708 struct musbotg_softc *sc;
1714 /* get pointer to softc */
1715 sc = MUSBOTG_PC2SC(td->pc);
1717 if (td->channel == -1)
1718 td->channel = musbotg_channel_alloc(sc, td, 0);
1721 if (td->channel == -1)
1724 DPRINTFN(1, "ep_no=%d\n", td->channel);
1726 to = 8; /* don't loop forever! */
1729 /* select endpoint */
1730 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1733 /* read out FIFO status */
1734 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1735 DPRINTFN(4, "csr=0x%02x\n", csr);
1737 if (!td->transaction_started) {
1738 /* Function address */
1739 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel),
1742 /* SPLIT transaction */
1743 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel),
1745 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel),
1748 /* RX NAK timeout */
1749 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
1750 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0);
1752 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1754 /* Protocol, speed, device endpoint */
1755 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1757 /* Max packet size */
1758 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet);
1761 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1762 DPRINTFN(4, "csrh=0x%02x\n", csrh);
1764 csrh |= MUSB2_MASK_CSRH_RXDT_WREN;
1766 csrh |= MUSB2_MASK_CSRH_RXDT_VAL;
1768 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1770 /* Set data toggle */
1771 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1774 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1775 MUSB2_MASK_CSRL_RXREQPKT);
1777 td->transaction_started = 1;
1781 /* clear NAK timeout */
1782 if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1783 DPRINTFN(4, "NAK Timeout\n");
1784 if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
1785 csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1786 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1788 csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1789 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1795 if (csr & MUSB2_MASK_CSRL_RXERROR) {
1796 DPRINTFN(4, "RXERROR\n");
1800 if (csr & MUSB2_MASK_CSRL_RXSTALL) {
1801 DPRINTFN(4, "RXSTALL\n");
1806 musbotg_channel_free(sc, td);
1807 return (0); /* we are complete */
1810 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
1811 /* No data available yet */
1816 /* get the packet byte count */
1817 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1818 DPRINTFN(4, "count=0x%04x\n", count);
1821 * Check for short or invalid packet:
1823 if (count != td->max_frame_size) {
1824 if (count < td->max_frame_size) {
1825 /* we have a short packet */
1829 /* invalid USB packet */
1831 musbotg_channel_free(sc, td);
1832 return (0); /* we are complete */
1836 /* verify the packet byte count */
1837 if (count > td->remainder) {
1838 /* invalid USB packet */
1840 musbotg_channel_free(sc, td);
1841 return (0); /* we are complete */
1847 usbd_get_page(td->pc, td->offset, &buf_res);
1849 /* get correct length */
1850 if (buf_res.length > count) {
1851 buf_res.length = count;
1853 /* check for unaligned memory address */
1854 if (USB_P2U(buf_res.buffer) & 3) {
1858 /* receive data 4 bytes at a time */
1859 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1860 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1865 /* receive data 1 byte at a time */
1866 bus_space_read_multi_1(sc->sc_io_tag,
1867 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1868 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1870 usbd_copy_in(td->pc, td->offset,
1871 sc->sc_bounce_buf, count);
1873 /* update offset and remainder */
1874 td->offset += count;
1875 td->remainder -= count;
1878 /* check if we can optimise */
1879 if (buf_res.length >= 4) {
1880 /* receive data 4 bytes at a time */
1881 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1882 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1883 buf_res.length / 4);
1885 temp = buf_res.length & ~3;
1887 /* update counters */
1890 td->remainder -= temp;
1894 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1895 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1898 /* update counters */
1899 count -= buf_res.length;
1900 td->offset += buf_res.length;
1901 td->remainder -= buf_res.length;
1904 /* clear status bits */
1905 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1907 /* check if we are complete */
1908 if ((td->remainder == 0) || got_short) {
1909 if (td->short_pkt) {
1910 /* we are complete */
1911 musbotg_channel_free(sc, td);
1914 /* else need to receive a zero length packet */
1917 /* Reset transaction state and restart */
1918 td->transaction_started = 0;
1923 return (1); /* not complete */
1927 musbotg_host_data_tx(struct musbotg_td *td)
1929 struct usb_page_search buf_res;
1930 struct musbotg_softc *sc;
1934 /* get pointer to softc */
1935 sc = MUSBOTG_PC2SC(td->pc);
1937 if (td->channel == -1)
1938 td->channel = musbotg_channel_alloc(sc, td, 1);
1941 if (td->channel == -1)
1944 DPRINTFN(1, "ep_no=%d\n", td->channel);
1946 /* select endpoint */
1947 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1949 /* read out FIFO status */
1950 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1951 DPRINTFN(4, "csr=0x%02x\n", csr);
1953 if (csr & (MUSB2_MASK_CSRL_TXSTALLED |
1954 MUSB2_MASK_CSRL_TXERROR)) {
1955 /* clear status bits */
1956 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1958 musbotg_channel_free(sc, td);
1959 return (0); /* complete */
1962 if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
1964 * Flush TX FIFO before clearing NAK TO
1966 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1967 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1968 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1969 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1970 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1971 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1972 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1973 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1977 csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
1978 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1981 musbotg_channel_free(sc, td);
1982 return (0); /* complete */
1986 * Wait while FIFO is empty.
1987 * Do not flush it because it will cause transactions
1988 * with size more then packet size. It might upset
1991 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
1994 /* Packet still being processed */
1995 if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
1998 if (td->transaction_started) {
1999 /* check remainder */
2000 if (td->remainder == 0) {
2001 if (td->short_pkt) {
2002 musbotg_channel_free(sc, td);
2003 return (0); /* complete */
2005 /* else we need to transmit a short packet */
2008 /* We're not complete - more transactions required */
2009 td->transaction_started = 0;
2012 /* check for short packet */
2013 count = td->max_frame_size;
2014 if (td->remainder < count) {
2015 /* we have a short packet */
2017 count = td->remainder;
2023 usbd_get_page(td->pc, td->offset, &buf_res);
2025 /* get correct length */
2026 if (buf_res.length > count) {
2027 buf_res.length = count;
2029 /* check for unaligned memory address */
2030 if (USB_P2U(buf_res.buffer) & 3) {
2031 usbd_copy_out(td->pc, td->offset,
2032 sc->sc_bounce_buf, count);
2037 /* transmit data 4 bytes at a time */
2038 bus_space_write_multi_4(sc->sc_io_tag,
2039 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
2040 sc->sc_bounce_buf, temp / 4);
2044 /* receive data 1 byte at a time */
2045 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2046 MUSB2_REG_EPFIFO(td->channel),
2047 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
2049 /* update offset and remainder */
2050 td->offset += count;
2051 td->remainder -= count;
2054 /* check if we can optimise */
2055 if (buf_res.length >= 4) {
2056 /* transmit data 4 bytes at a time */
2057 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
2058 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2059 buf_res.length / 4);
2061 temp = buf_res.length & ~3;
2063 /* update counters */
2066 td->remainder -= temp;
2070 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2071 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2074 /* update counters */
2075 count -= buf_res.length;
2076 td->offset += buf_res.length;
2077 td->remainder -= buf_res.length;
2080 /* Function address */
2081 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel),
2084 /* SPLIT transaction */
2085 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel),
2087 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel),
2090 /* TX NAK timeout */
2091 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
2092 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0);
2094 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
2096 /* Protocol, speed, device endpoint */
2097 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
2099 /* Max packet size */
2100 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
2102 if (!td->transaction_started) {
2103 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
2104 DPRINTFN(4, "csrh=0x%02x\n", csrh);
2106 csrh |= MUSB2_MASK_CSRH_TXDT_WREN;
2108 csrh |= MUSB2_MASK_CSRH_TXDT_VAL;
2110 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL;
2112 /* Set data toggle */
2113 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
2117 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2118 MUSB2_MASK_CSRL_TXPKTRDY);
2120 /* Update Data Toggle */
2122 td->transaction_started = 1;
2124 return (1); /* not complete */
2128 musbotg_xfer_do_fifo(struct usb_xfer *xfer)
2130 struct musbotg_softc *sc;
2131 struct musbotg_td *td;
2134 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2136 td = xfer->td_transfer_cache;
2138 if ((td->func) (td)) {
2139 /* operation in progress */
2143 if (((void *)td) == xfer->td_transfer_last) {
2148 } else if (td->remainder > 0) {
2150 * We had a short transfer. If there is no alternate
2151 * next, stop processing !
2153 if (!td->alt_next) {
2158 * Fetch the next transfer descriptor and transfer
2159 * some flags to the next transfer descriptor
2162 xfer->td_transfer_cache = td;
2165 return (1); /* not complete */
2167 /* compute all actual lengths */
2168 musbotg_standard_done(xfer);
2170 return (0); /* complete */
2174 musbotg_interrupt_poll(struct musbotg_softc *sc)
2176 struct usb_xfer *xfer;
2179 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2180 if (!musbotg_xfer_do_fifo(xfer)) {
2181 /* queue has been modified */
2188 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
2190 DPRINTFN(4, "vbus = %u\n", is_on);
2192 USB_BUS_LOCK(&sc->sc_bus);
2194 if (!sc->sc_flags.status_vbus) {
2195 sc->sc_flags.status_vbus = 1;
2197 /* complete root HUB interrupt endpoint */
2198 musbotg_root_intr(sc);
2201 if (sc->sc_flags.status_vbus) {
2202 sc->sc_flags.status_vbus = 0;
2203 sc->sc_flags.status_bus_reset = 0;
2204 sc->sc_flags.status_suspend = 0;
2205 sc->sc_flags.change_suspend = 0;
2206 sc->sc_flags.change_connect = 1;
2208 /* complete root HUB interrupt endpoint */
2209 musbotg_root_intr(sc);
2213 USB_BUS_UNLOCK(&sc->sc_bus);
2217 musbotg_connect_interrupt(struct musbotg_softc *sc)
2219 USB_BUS_LOCK(&sc->sc_bus);
2220 sc->sc_flags.change_connect = 1;
2222 /* complete root HUB interrupt endpoint */
2223 musbotg_root_intr(sc);
2224 USB_BUS_UNLOCK(&sc->sc_bus);
2228 musbotg_interrupt(struct musbotg_softc *sc,
2229 uint16_t rxstat, uint16_t txstat, uint8_t stat)
2237 USB_BUS_LOCK(&sc->sc_bus);
2241 /* read all interrupt registers */
2242 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
2244 /* read all FIFO interrupts */
2245 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
2246 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
2247 rx_status |= rxstat;
2248 tx_status |= txstat;
2251 /* Clear platform flags after first time */
2256 /* check for any bus state change interrupts */
2258 if (usb_status & (MUSB2_MASK_IRESET |
2259 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP |
2260 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC |
2261 MUSB2_MASK_IVBUSERR)) {
2262 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
2264 if (usb_status & MUSB2_MASK_IRESET) {
2265 /* set correct state */
2266 sc->sc_flags.status_bus_reset = 1;
2267 sc->sc_flags.status_suspend = 0;
2268 sc->sc_flags.change_suspend = 0;
2269 sc->sc_flags.change_connect = 1;
2271 /* determine line speed */
2272 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
2273 if (temp & MUSB2_MASK_HSMODE)
2274 sc->sc_flags.status_high_speed = 1;
2276 sc->sc_flags.status_high_speed = 0;
2279 * After reset all interrupts are on and we need to
2282 temp = MUSB2_MASK_IRESET;
2283 /* disable resume interrupt */
2284 temp &= ~MUSB2_MASK_IRESUME;
2285 /* enable suspend interrupt */
2286 temp |= MUSB2_MASK_ISUSP;
2287 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2288 /* disable TX and RX interrupts */
2289 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
2290 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
2293 * If RXRSM and RXSUSP is set at the same time we interpret
2294 * that like RESUME. Resume is set when there is at least 3
2295 * milliseconds of inactivity on the USB BUS.
2297 if (usb_status & MUSB2_MASK_IRESUME) {
2298 if (sc->sc_flags.status_suspend) {
2299 sc->sc_flags.status_suspend = 0;
2300 sc->sc_flags.change_suspend = 1;
2302 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2303 /* disable resume interrupt */
2304 temp &= ~MUSB2_MASK_IRESUME;
2305 /* enable suspend interrupt */
2306 temp |= MUSB2_MASK_ISUSP;
2307 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2309 } else if (usb_status & MUSB2_MASK_ISUSP) {
2310 if (!sc->sc_flags.status_suspend) {
2311 sc->sc_flags.status_suspend = 1;
2312 sc->sc_flags.change_suspend = 1;
2314 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2315 /* disable suspend interrupt */
2316 temp &= ~MUSB2_MASK_ISUSP;
2317 /* enable resume interrupt */
2318 temp |= MUSB2_MASK_IRESUME;
2319 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2323 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC))
2324 sc->sc_flags.change_connect = 1;
2327 * Host Mode: There is no IRESET so assume bus is
2328 * always in reset state once device is connected.
2330 if (sc->sc_mode == MUSB2_HOST_MODE) {
2331 /* check for VBUS error in USB host mode */
2332 if (usb_status & MUSB2_MASK_IVBUSERR) {
2333 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
2334 temp |= MUSB2_MASK_SESS;
2335 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
2337 if (usb_status & MUSB2_MASK_ICONN)
2338 sc->sc_flags.status_bus_reset = 1;
2339 if (usb_status & MUSB2_MASK_IDISC)
2340 sc->sc_flags.status_bus_reset = 0;
2343 /* complete root HUB interrupt endpoint */
2344 musbotg_root_intr(sc);
2346 /* check for any endpoint interrupts */
2348 if (rx_status || tx_status) {
2349 DPRINTFN(4, "real endpoint interrupt "
2350 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
2352 /* poll one time regardless of FIFO status */
2354 musbotg_interrupt_poll(sc);
2359 USB_BUS_UNLOCK(&sc->sc_bus);
2363 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
2365 struct musbotg_td *td;
2367 /* get current Transfer Descriptor */
2371 /* prepare for next TD */
2372 temp->td_next = td->obj_next;
2374 /* fill out the Transfer Descriptor */
2375 td->func = temp->func;
2377 td->offset = temp->offset;
2378 td->remainder = temp->len;
2380 td->transaction_started = 0;
2381 td->did_stall = temp->did_stall;
2382 td->short_pkt = temp->short_pkt;
2383 td->alt_next = temp->setup_alt_next;
2384 td->channel = temp->channel;
2385 td->dev_addr = temp->dev_addr;
2386 td->haddr = temp->haddr;
2387 td->hport = temp->hport;
2388 td->transfer_type = temp->transfer_type;
2392 musbotg_setup_standard_chain(struct usb_xfer *xfer)
2394 struct musbotg_std_temp temp;
2395 struct musbotg_softc *sc;
2396 struct musbotg_td *td;
2400 enum usb_dev_speed speed;
2404 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2405 xfer->address, UE_GET_ADDR(xfer->endpointno),
2406 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2408 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2409 ep_no = (xfer->endpointno & UE_ADDR);
2411 temp.max_frame_size = xfer->max_frame_size;
2413 td = xfer->td_start[0];
2414 xfer->td_transfer_first = td;
2415 xfer->td_transfer_cache = td;
2418 dev_addr = xfer->address;
2420 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE;
2424 temp.td_next = xfer->td_start[0];
2426 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
2427 xfer->flags_int.isochronous_xfr;
2428 temp.did_stall = !xfer->flags_int.control_stall;
2430 temp.dev_addr = dev_addr;
2431 temp.haddr = xfer->xroot->udev->hs_hub_addr;
2432 temp.hport = xfer->xroot->udev->hs_port_no;
2434 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2435 speed = usbd_get_speed(xfer->xroot->udev);
2439 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO;
2441 case USB_SPEED_FULL:
2442 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS;
2444 case USB_SPEED_HIGH:
2445 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS;
2448 temp.transfer_type = 0;
2449 DPRINTFN(-1, "Invalid USB speed: %d\n", speed);
2453 switch (xfer_type) {
2455 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL;
2457 case UE_ISOCHRONOUS:
2458 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC;
2461 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK;
2464 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR;
2467 DPRINTFN(-1, "Invalid USB transfer type: %d\n",
2472 temp.transfer_type |= ep_no;
2473 td->toggle = xfer->endpoint->toggle_next;
2476 /* check if we should prepend a setup message */
2478 if (xfer->flags_int.control_xfr) {
2479 if (xfer->flags_int.control_hdr) {
2480 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE)
2481 temp.func = &musbotg_dev_ctrl_setup_rx;
2483 temp.func = &musbotg_host_ctrl_setup_tx;
2485 temp.len = xfer->frlengths[0];
2486 temp.pc = xfer->frbuffers + 0;
2487 temp.short_pkt = temp.len ? 1 : 0;
2489 musbotg_setup_standard_chain_sub(&temp);
2498 if (x != xfer->nframes) {
2499 if (xfer->endpointno & UE_DIR_IN)
2502 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2506 if (xfer->flags_int.control_xfr)
2507 temp.func = &musbotg_host_ctrl_data_tx;
2509 temp.func = &musbotg_host_data_tx;
2511 if (xfer->flags_int.control_xfr)
2512 temp.func = &musbotg_host_ctrl_data_rx;
2514 temp.func = &musbotg_host_data_rx;
2519 if (xfer->flags_int.control_xfr)
2520 temp.func = &musbotg_dev_ctrl_data_tx;
2522 temp.func = &musbotg_dev_data_tx;
2524 if (xfer->flags_int.control_xfr)
2525 temp.func = &musbotg_dev_ctrl_data_rx;
2527 temp.func = &musbotg_dev_data_rx;
2531 /* setup "pc" pointer */
2532 temp.pc = xfer->frbuffers + x;
2534 while (x != xfer->nframes) {
2535 /* DATA0 / DATA1 message */
2537 temp.len = xfer->frlengths[x];
2541 if (x == xfer->nframes) {
2542 if (xfer->flags_int.control_xfr) {
2543 if (xfer->flags_int.control_act) {
2544 temp.setup_alt_next = 0;
2547 temp.setup_alt_next = 0;
2550 if (temp.len == 0) {
2551 /* make sure that we send an USB packet */
2556 if (xfer->flags_int.isochronous_xfr) {
2557 /* isochronous data transfer */
2558 /* don't force short */
2561 /* regular data transfer */
2562 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
2566 musbotg_setup_standard_chain_sub(&temp);
2568 if (xfer->flags_int.isochronous_xfr) {
2569 temp.offset += temp.len;
2571 /* get next Page Cache pointer */
2572 temp.pc = xfer->frbuffers + x;
2576 /* check for control transfer */
2577 if (xfer->flags_int.control_xfr) {
2578 /* always setup a valid "pc" pointer for status and sync */
2579 temp.pc = xfer->frbuffers + 0;
2582 temp.setup_alt_next = 0;
2584 /* check if we should append a status stage */
2585 if (!xfer->flags_int.control_act) {
2587 * Send a DATA1 message and invert the current
2588 * endpoint direction.
2590 if (sc->sc_mode == MUSB2_DEVICE_MODE)
2591 temp.func = &musbotg_dev_ctrl_status;
2593 if (xfer->endpointno & UE_DIR_IN)
2594 temp.func = musbotg_host_ctrl_status_tx;
2596 temp.func = musbotg_host_ctrl_status_rx;
2598 musbotg_setup_standard_chain_sub(&temp);
2601 /* must have at least one frame! */
2603 xfer->td_transfer_last = td;
2607 musbotg_timeout(void *arg)
2609 struct usb_xfer *xfer = arg;
2611 DPRINTFN(1, "xfer=%p\n", xfer);
2613 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2615 /* transfer is transferred */
2616 musbotg_device_done(xfer, USB_ERR_TIMEOUT);
2620 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
2625 * Only enable the endpoint interrupt when we are
2626 * actually waiting for data, hence we are dealing
2627 * with level triggered interrupts !
2629 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on);
2635 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2637 temp |= MUSB2_MASK_EPINT(0);
2639 temp &= ~MUSB2_MASK_EPINT(0);
2641 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2643 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
2645 temp |= MUSB2_MASK_EPINT(channel);
2647 temp &= ~MUSB2_MASK_EPINT(channel);
2648 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
2650 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2652 temp |= MUSB2_MASK_EPINT(channel);
2654 temp &= ~MUSB2_MASK_EPINT(channel);
2655 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2658 if (sc->sc_ep_int_set)
2659 sc->sc_ep_int_set(sc, channel, on);
2663 musbotg_start_standard_chain(struct usb_xfer *xfer)
2668 if (musbotg_xfer_do_fifo(xfer)) {
2669 DPRINTFN(14, "enabled interrupts on endpoint\n");
2671 /* put transfer on interrupt queue */
2672 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2674 /* start timeout, if any */
2675 if (xfer->timeout != 0) {
2676 usbd_transfer_timeout_ms(xfer,
2677 &musbotg_timeout, xfer->timeout);
2683 musbotg_root_intr(struct musbotg_softc *sc)
2687 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2690 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
2692 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2693 sizeof(sc->sc_hub_idata));
2697 musbotg_standard_done_sub(struct usb_xfer *xfer)
2699 struct musbotg_td *td;
2705 td = xfer->td_transfer_cache;
2708 len = td->remainder;
2710 xfer->endpoint->toggle_next = td->toggle;
2712 if (xfer->aframes != xfer->nframes) {
2714 * Verify the length and subtract
2715 * the remainder from "frlengths[]":
2717 if (len > xfer->frlengths[xfer->aframes]) {
2720 xfer->frlengths[xfer->aframes] -= len;
2723 /* Check for transfer error */
2725 /* the transfer is finished */
2730 /* Check for short transfer */
2732 if (xfer->flags_int.short_frames_ok ||
2733 xfer->flags_int.isochronous_xfr) {
2734 /* follow alt next */
2741 /* the transfer is finished */
2749 /* this USB frame is complete */
2755 /* update transfer cache */
2757 xfer->td_transfer_cache = td;
2760 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
2764 musbotg_standard_done(struct usb_xfer *xfer)
2766 usb_error_t err = 0;
2768 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
2769 xfer, xfer->endpoint);
2773 xfer->td_transfer_cache = xfer->td_transfer_first;
2775 if (xfer->flags_int.control_xfr) {
2776 if (xfer->flags_int.control_hdr) {
2777 err = musbotg_standard_done_sub(xfer);
2781 if (xfer->td_transfer_cache == NULL) {
2785 while (xfer->aframes != xfer->nframes) {
2786 err = musbotg_standard_done_sub(xfer);
2789 if (xfer->td_transfer_cache == NULL) {
2794 if (xfer->flags_int.control_xfr &&
2795 !xfer->flags_int.control_act) {
2796 err = musbotg_standard_done_sub(xfer);
2799 musbotg_device_done(xfer, err);
2802 /*------------------------------------------------------------------------*
2803 * musbotg_device_done
2805 * NOTE: this function can be called more than one time on the
2806 * same USB transfer!
2807 *------------------------------------------------------------------------*/
2809 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
2811 struct musbotg_td *td;
2812 struct musbotg_softc *sc;
2814 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2816 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n",
2817 xfer, xfer->endpoint, error);
2819 DPRINTFN(14, "disabled interrupts on endpoint\n");
2821 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2822 td = xfer->td_transfer_cache;
2824 if (td && (td->channel != -1))
2825 musbotg_channel_free(sc, td);
2827 /* dequeue transfer and start next transfer */
2828 usbd_transfer_done(xfer, error);
2832 musbotg_xfer_stall(struct usb_xfer *xfer)
2834 musbotg_device_done(xfer, USB_ERR_STALLED);
2838 musbotg_set_stall(struct usb_device *udev,
2839 struct usb_endpoint *ep, uint8_t *did_stall)
2841 struct musbotg_softc *sc;
2844 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2846 DPRINTFN(4, "endpoint=%p\n", ep);
2848 /* set FORCESTALL */
2849 sc = MUSBOTG_BUS2SC(udev->bus);
2851 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2853 /* select endpoint */
2854 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2856 if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
2857 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2858 MUSB2_MASK_CSRL_TXSENDSTALL);
2860 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2861 MUSB2_MASK_CSRL_RXSENDSTALL);
2866 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
2867 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2873 if (ep_type == UE_CONTROL) {
2874 /* clearing stall is not needed */
2877 /* select endpoint */
2878 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2880 /* compute max frame size */
2881 mps = wMaxPacket & 0x7FF;
2882 switch ((wMaxPacket >> 11) & 3) {
2893 if (ep_dir == UE_DIR_IN) {
2896 /* Configure endpoint */
2899 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2900 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2901 MUSB2_MASK_CSRH_TXMODE | temp);
2903 case UE_ISOCHRONOUS:
2904 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2905 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2906 MUSB2_MASK_CSRH_TXMODE |
2907 MUSB2_MASK_CSRH_TXISO | temp);
2910 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2911 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2912 MUSB2_MASK_CSRH_TXMODE | temp);
2918 /* Need to flush twice in case of double bufring */
2919 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2920 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2921 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2922 MUSB2_MASK_CSRL_TXFFLUSH);
2923 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2924 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2925 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2926 MUSB2_MASK_CSRL_TXFFLUSH);
2927 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2930 /* reset data toggle */
2931 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2932 MUSB2_MASK_CSRL_TXDT_CLR);
2933 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2934 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2936 /* set double/single buffering */
2937 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
2938 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2939 max_in_frame_size / 2)) {
2941 temp &= ~(1 << ep_no);
2944 temp |= (1 << ep_no);
2946 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
2948 /* clear sent stall */
2949 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
2950 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2951 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2956 /* Configure endpoint */
2959 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2960 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2961 MUSB2_MASK_CSRH_RXNYET | temp);
2963 case UE_ISOCHRONOUS:
2964 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2965 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2966 MUSB2_MASK_CSRH_RXNYET |
2967 MUSB2_MASK_CSRH_RXISO | temp);
2970 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2971 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
2977 /* Need to flush twice in case of double bufring */
2978 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2979 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2980 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2981 MUSB2_MASK_CSRL_RXFFLUSH);
2982 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2983 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2984 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2985 MUSB2_MASK_CSRL_RXFFLUSH);
2986 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2989 /* reset data toggle */
2990 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2991 MUSB2_MASK_CSRL_RXDT_CLR);
2992 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
2993 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2995 /* set double/single buffering */
2996 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
2997 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2998 max_out_frame_size / 2)) {
3000 temp &= ~(1 << ep_no);
3003 temp |= (1 << ep_no);
3005 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
3007 /* clear sent stall */
3008 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
3009 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3015 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3017 struct musbotg_softc *sc;
3018 struct usb_endpoint_descriptor *ed;
3020 DPRINTFN(4, "endpoint=%p\n", ep);
3022 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3025 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3030 sc = MUSBOTG_BUS2SC(udev->bus);
3032 /* get endpoint descriptor */
3035 /* reset endpoint */
3036 musbotg_clear_stall_sub(sc,
3037 UGETW(ed->wMaxPacketSize),
3038 (ed->bEndpointAddress & UE_ADDR),
3039 (ed->bmAttributes & UE_XFERTYPE),
3040 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3044 musbotg_init(struct musbotg_softc *sc)
3046 const struct musb_otg_ep_cfg *cfg;
3047 struct usb_hw_ep_profile *pf;
3058 DPRINTFN(1, "start\n");
3060 /* set up the bus structure */
3061 sc->sc_bus.usbrev = USB_REV_2_0;
3062 sc->sc_bus.methods = &musbotg_bus_methods;
3064 /* Set a default endpoint configuration */
3065 if (sc->sc_ep_cfg == NULL)
3066 sc->sc_ep_cfg = musbotg_ep_default;
3068 USB_BUS_LOCK(&sc->sc_bus);
3070 /* turn on clocks */
3072 if (sc->sc_clocks_on) {
3073 (sc->sc_clocks_on) (sc->sc_clocks_arg);
3076 /* wait a little for things to stabilise */
3077 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
3079 /* disable all interrupts */
3081 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3082 DPRINTF("pre-DEVCTL=0x%02x\n", temp);
3084 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3085 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3086 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3088 /* disable pullup */
3090 musbotg_pull_common(sc, 0);
3092 /* wait a little bit (10ms) */
3093 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3095 /* disable double packet buffering */
3096 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
3097 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
3099 /* enable HighSpeed and ISO Update flags */
3101 MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
3102 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
3104 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3105 /* clear Session bit, if set */
3106 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3107 temp &= ~MUSB2_MASK_SESS;
3108 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3110 /* Enter session for Host mode */
3111 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3112 temp |= MUSB2_MASK_SESS;
3113 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3116 /* wait a little for things to stabilise */
3117 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
3119 DPRINTF("DEVCTL=0x%02x\n", temp);
3121 /* disable testmode */
3123 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
3125 /* set default value */
3127 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
3129 /* select endpoint index 0 */
3131 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
3133 if (sc->sc_ep_max == 0) {
3134 /* read out number of endpoints */
3137 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
3140 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
3142 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
3144 nrx = ntx = sc->sc_ep_max;
3147 /* these numbers exclude the control endpoint */
3149 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
3151 if (sc->sc_ep_max == 0) {
3152 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
3154 /* read out configuration data */
3156 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
3158 DPRINTFN(2, "Config Data: 0x%02x\n",
3161 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
3164 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
3165 "assuming 16Kbytes of FIFO RAM\n");
3168 DPRINTFN(2, "HW version: 0x%04x\n",
3169 MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
3171 /* initialise endpoint profiles */
3175 for (temp = 1; temp <= sc->sc_ep_max; temp++) {
3176 pf = sc->sc_hw_ep_profile + temp;
3178 /* select endpoint */
3179 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
3181 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
3182 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
3183 ftx = (fsize & MUSB2_MASK_TX_FSIZE);
3185 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
3186 temp, ftx, frx, dynfifo);
3189 if (frx && (temp <= nrx)) {
3190 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) {
3191 cfg = &sc->sc_ep_cfg[i];
3192 if (temp <= cfg->ep_end) {
3193 frx = cfg->ep_fifosz_shift;
3196 cfg->ep_fifosz_reg);
3201 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
3204 offset += (1 << frx);
3206 if (ftx && (temp <= ntx)) {
3207 for (i = 0; sc->sc_ep_cfg[i].ep_end >= 0; i++) {
3208 cfg = &sc->sc_ep_cfg[i];
3209 if (temp <= cfg->ep_end) {
3210 ftx = cfg->ep_fifosz_shift;
3213 cfg->ep_fifosz_reg);
3218 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
3221 offset += (1 << ftx);
3225 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
3226 pf->max_in_frame_size = 1 << ftx;
3227 pf->max_out_frame_size = 1 << frx;
3228 pf->is_simplex = 0; /* duplex */
3229 pf->support_multi_buffer = 1;
3230 pf->support_bulk = 1;
3231 pf->support_interrupt = 1;
3232 pf->support_isochronous = 1;
3234 pf->support_out = 1;
3235 } else if (frx && (temp <= nrx)) {
3236 pf->max_out_frame_size = 1 << frx;
3237 pf->max_in_frame_size = 0;
3238 pf->is_simplex = 1; /* simplex */
3239 pf->support_multi_buffer = 1;
3240 pf->support_bulk = 1;
3241 pf->support_interrupt = 1;
3242 pf->support_isochronous = 1;
3243 pf->support_out = 1;
3244 } else if (ftx && (temp <= ntx)) {
3245 pf->max_in_frame_size = 1 << ftx;
3246 pf->max_out_frame_size = 0;
3247 pf->is_simplex = 1; /* simplex */
3248 pf->support_multi_buffer = 1;
3249 pf->support_bulk = 1;
3250 pf->support_interrupt = 1;
3251 pf->support_isochronous = 1;
3256 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
3258 /* turn on default interrupts */
3260 if (sc->sc_mode == MUSB2_HOST_MODE)
3261 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff);
3263 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
3266 musbotg_clocks_off(sc);
3268 USB_BUS_UNLOCK(&sc->sc_bus);
3270 /* catch any lost interrupts */
3272 musbotg_do_poll(&sc->sc_bus);
3274 return (0); /* success */
3278 musbotg_uninit(struct musbotg_softc *sc)
3280 USB_BUS_LOCK(&sc->sc_bus);
3282 /* disable all interrupts */
3283 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3284 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3285 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3287 sc->sc_flags.port_powered = 0;
3288 sc->sc_flags.status_vbus = 0;
3289 sc->sc_flags.status_bus_reset = 0;
3290 sc->sc_flags.status_suspend = 0;
3291 sc->sc_flags.change_suspend = 0;
3292 sc->sc_flags.change_connect = 1;
3294 musbotg_pull_down(sc);
3295 musbotg_clocks_off(sc);
3296 USB_BUS_UNLOCK(&sc->sc_bus);
3300 musbotg_do_poll(struct usb_bus *bus)
3302 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
3304 USB_BUS_LOCK(&sc->sc_bus);
3305 musbotg_interrupt_poll(sc);
3306 USB_BUS_UNLOCK(&sc->sc_bus);
3309 /*------------------------------------------------------------------------*
3310 * musbotg bulk support
3311 *------------------------------------------------------------------------*/
3313 musbotg_device_bulk_open(struct usb_xfer *xfer)
3319 musbotg_device_bulk_close(struct usb_xfer *xfer)
3321 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3325 musbotg_device_bulk_enter(struct usb_xfer *xfer)
3331 musbotg_device_bulk_start(struct usb_xfer *xfer)
3334 musbotg_setup_standard_chain(xfer);
3335 musbotg_start_standard_chain(xfer);
3338 static const struct usb_pipe_methods musbotg_device_bulk_methods =
3340 .open = musbotg_device_bulk_open,
3341 .close = musbotg_device_bulk_close,
3342 .enter = musbotg_device_bulk_enter,
3343 .start = musbotg_device_bulk_start,
3346 /*------------------------------------------------------------------------*
3347 * musbotg control support
3348 *------------------------------------------------------------------------*/
3350 musbotg_device_ctrl_open(struct usb_xfer *xfer)
3356 musbotg_device_ctrl_close(struct usb_xfer *xfer)
3358 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3362 musbotg_device_ctrl_enter(struct usb_xfer *xfer)
3368 musbotg_device_ctrl_start(struct usb_xfer *xfer)
3371 musbotg_setup_standard_chain(xfer);
3372 musbotg_start_standard_chain(xfer);
3375 static const struct usb_pipe_methods musbotg_device_ctrl_methods =
3377 .open = musbotg_device_ctrl_open,
3378 .close = musbotg_device_ctrl_close,
3379 .enter = musbotg_device_ctrl_enter,
3380 .start = musbotg_device_ctrl_start,
3383 /*------------------------------------------------------------------------*
3384 * musbotg interrupt support
3385 *------------------------------------------------------------------------*/
3387 musbotg_device_intr_open(struct usb_xfer *xfer)
3393 musbotg_device_intr_close(struct usb_xfer *xfer)
3395 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3399 musbotg_device_intr_enter(struct usb_xfer *xfer)
3405 musbotg_device_intr_start(struct usb_xfer *xfer)
3408 musbotg_setup_standard_chain(xfer);
3409 musbotg_start_standard_chain(xfer);
3412 static const struct usb_pipe_methods musbotg_device_intr_methods =
3414 .open = musbotg_device_intr_open,
3415 .close = musbotg_device_intr_close,
3416 .enter = musbotg_device_intr_enter,
3417 .start = musbotg_device_intr_start,
3420 /*------------------------------------------------------------------------*
3421 * musbotg full speed isochronous support
3422 *------------------------------------------------------------------------*/
3424 musbotg_device_isoc_open(struct usb_xfer *xfer)
3430 musbotg_device_isoc_close(struct usb_xfer *xfer)
3432 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3436 musbotg_device_isoc_enter(struct usb_xfer *xfer)
3438 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
3443 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
3444 xfer, xfer->endpoint->isoc_next, xfer->nframes);
3446 /* get the current frame index */
3448 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
3451 * check if the frame index is within the window where the frames
3454 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME;
3456 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
3457 fs_frames = (xfer->nframes + 7) / 8;
3459 fs_frames = xfer->nframes;
3462 if ((xfer->endpoint->is_synced == 0) ||
3463 (temp < fs_frames)) {
3465 * If there is data underflow or the pipe queue is
3466 * empty we schedule the transfer a few frames ahead
3467 * of the current frame position. Else two isochronous
3468 * transfers might overlap.
3470 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
3471 xfer->endpoint->is_synced = 1;
3472 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
3475 * compute how many milliseconds the insertion is ahead of the
3476 * current frame position:
3478 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME;
3481 * pre-compute when the isochronous transfer will be finished:
3483 xfer->isoc_time_complete =
3484 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
3487 /* compute frame number for next insertion */
3488 xfer->endpoint->isoc_next += fs_frames;
3491 musbotg_setup_standard_chain(xfer);
3495 musbotg_device_isoc_start(struct usb_xfer *xfer)
3497 /* start TD chain */
3498 musbotg_start_standard_chain(xfer);
3501 static const struct usb_pipe_methods musbotg_device_isoc_methods =
3503 .open = musbotg_device_isoc_open,
3504 .close = musbotg_device_isoc_close,
3505 .enter = musbotg_device_isoc_enter,
3506 .start = musbotg_device_isoc_start,
3509 /*------------------------------------------------------------------------*
3510 * musbotg root control support
3511 *------------------------------------------------------------------------*
3512 * Simulate a hardware HUB by handling all the necessary requests.
3513 *------------------------------------------------------------------------*/
3515 static const struct usb_device_descriptor musbotg_devd = {
3516 .bLength = sizeof(struct usb_device_descriptor),
3517 .bDescriptorType = UDESC_DEVICE,
3518 .bcdUSB = {0x00, 0x02},
3519 .bDeviceClass = UDCLASS_HUB,
3520 .bDeviceSubClass = UDSUBCLASS_HUB,
3521 .bDeviceProtocol = UDPROTO_HSHUBSTT,
3522 .bMaxPacketSize = 64,
3523 .bcdDevice = {0x00, 0x01},
3526 .bNumConfigurations = 1,
3529 static const struct usb_device_qualifier musbotg_odevd = {
3530 .bLength = sizeof(struct usb_device_qualifier),
3531 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
3532 .bcdUSB = {0x00, 0x02},
3533 .bDeviceClass = UDCLASS_HUB,
3534 .bDeviceSubClass = UDSUBCLASS_HUB,
3535 .bDeviceProtocol = UDPROTO_FSHUB,
3536 .bMaxPacketSize0 = 0,
3537 .bNumConfigurations = 0,
3540 static const struct musbotg_config_desc musbotg_confd = {
3542 .bLength = sizeof(struct usb_config_descriptor),
3543 .bDescriptorType = UDESC_CONFIG,
3544 .wTotalLength[0] = sizeof(musbotg_confd),
3546 .bConfigurationValue = 1,
3547 .iConfiguration = 0,
3548 .bmAttributes = UC_SELF_POWERED,
3552 .bLength = sizeof(struct usb_interface_descriptor),
3553 .bDescriptorType = UDESC_INTERFACE,
3555 .bInterfaceClass = UICLASS_HUB,
3556 .bInterfaceSubClass = UISUBCLASS_HUB,
3557 .bInterfaceProtocol = 0,
3560 .bLength = sizeof(struct usb_endpoint_descriptor),
3561 .bDescriptorType = UDESC_ENDPOINT,
3562 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
3563 .bmAttributes = UE_INTERRUPT,
3564 .wMaxPacketSize[0] = 8,
3568 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3570 static const struct usb_hub_descriptor_min musbotg_hubd = {
3571 .bDescLength = sizeof(musbotg_hubd),
3572 .bDescriptorType = UDESC_HUB,
3574 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
3575 .bPwrOn2PwrGood = 50,
3576 .bHubContrCurrent = 0,
3577 .DeviceRemovable = {0}, /* port is removable */
3580 #define STRING_VENDOR \
3581 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s"
3583 #define STRING_PRODUCT \
3584 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
3586 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
3587 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
3590 musbotg_roothub_exec(struct usb_device *udev,
3591 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3593 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
3601 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3604 ptr = (const void *)&sc->sc_hub_temp;
3608 value = UGETW(req->wValue);
3609 index = UGETW(req->wIndex);
3611 /* demultiplex the control request */
3613 switch (req->bmRequestType) {
3614 case UT_READ_DEVICE:
3615 switch (req->bRequest) {
3616 case UR_GET_DESCRIPTOR:
3617 goto tr_handle_get_descriptor;
3619 goto tr_handle_get_config;
3621 goto tr_handle_get_status;
3627 case UT_WRITE_DEVICE:
3628 switch (req->bRequest) {
3629 case UR_SET_ADDRESS:
3630 goto tr_handle_set_address;
3632 goto tr_handle_set_config;
3633 case UR_CLEAR_FEATURE:
3634 goto tr_valid; /* nop */
3635 case UR_SET_DESCRIPTOR:
3636 goto tr_valid; /* nop */
3637 case UR_SET_FEATURE:
3643 case UT_WRITE_ENDPOINT:
3644 switch (req->bRequest) {
3645 case UR_CLEAR_FEATURE:
3646 switch (UGETW(req->wValue)) {
3647 case UF_ENDPOINT_HALT:
3648 goto tr_handle_clear_halt;
3649 case UF_DEVICE_REMOTE_WAKEUP:
3650 goto tr_handle_clear_wakeup;
3655 case UR_SET_FEATURE:
3656 switch (UGETW(req->wValue)) {
3657 case UF_ENDPOINT_HALT:
3658 goto tr_handle_set_halt;
3659 case UF_DEVICE_REMOTE_WAKEUP:
3660 goto tr_handle_set_wakeup;
3665 case UR_SYNCH_FRAME:
3666 goto tr_valid; /* nop */
3672 case UT_READ_ENDPOINT:
3673 switch (req->bRequest) {
3675 goto tr_handle_get_ep_status;
3681 case UT_WRITE_INTERFACE:
3682 switch (req->bRequest) {
3683 case UR_SET_INTERFACE:
3684 goto tr_handle_set_interface;
3685 case UR_CLEAR_FEATURE:
3686 goto tr_valid; /* nop */
3687 case UR_SET_FEATURE:
3693 case UT_READ_INTERFACE:
3694 switch (req->bRequest) {
3695 case UR_GET_INTERFACE:
3696 goto tr_handle_get_interface;
3698 goto tr_handle_get_iface_status;
3704 case UT_WRITE_CLASS_INTERFACE:
3705 case UT_WRITE_VENDOR_INTERFACE:
3709 case UT_READ_CLASS_INTERFACE:
3710 case UT_READ_VENDOR_INTERFACE:
3714 case UT_WRITE_CLASS_DEVICE:
3715 switch (req->bRequest) {
3716 case UR_CLEAR_FEATURE:
3718 case UR_SET_DESCRIPTOR:
3719 case UR_SET_FEATURE:
3726 case UT_WRITE_CLASS_OTHER:
3727 switch (req->bRequest) {
3728 case UR_CLEAR_FEATURE:
3729 goto tr_handle_clear_port_feature;
3730 case UR_SET_FEATURE:
3731 goto tr_handle_set_port_feature;
3732 case UR_CLEAR_TT_BUFFER:
3742 case UT_READ_CLASS_OTHER:
3743 switch (req->bRequest) {
3744 case UR_GET_TT_STATE:
3745 goto tr_handle_get_tt_state;
3747 goto tr_handle_get_port_status;
3753 case UT_READ_CLASS_DEVICE:
3754 switch (req->bRequest) {
3755 case UR_GET_DESCRIPTOR:
3756 goto tr_handle_get_class_descriptor;
3758 goto tr_handle_get_class_status;
3769 tr_handle_get_descriptor:
3770 switch (value >> 8) {
3775 len = sizeof(musbotg_devd);
3776 ptr = (const void *)&musbotg_devd;
3778 case UDESC_DEVICE_QUALIFIER:
3782 len = sizeof(musbotg_odevd);
3783 ptr = (const void *)&musbotg_odevd;
3789 len = sizeof(musbotg_confd);
3790 ptr = (const void *)&musbotg_confd;
3793 switch (value & 0xff) {
3794 case 0: /* Language table */
3795 len = sizeof(usb_string_lang_en);
3796 ptr = (const void *)&usb_string_lang_en;
3799 case 1: /* Vendor */
3800 len = sizeof(musbotg_vendor);
3801 ptr = (const void *)&musbotg_vendor;
3804 case 2: /* Product */
3805 len = sizeof(musbotg_product);
3806 ptr = (const void *)&musbotg_product;
3817 tr_handle_get_config:
3819 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3822 tr_handle_get_status:
3824 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3827 tr_handle_set_address:
3828 if (value & 0xFF00) {
3831 sc->sc_rt_addr = value;
3834 tr_handle_set_config:
3838 sc->sc_conf = value;
3841 tr_handle_get_interface:
3843 sc->sc_hub_temp.wValue[0] = 0;
3846 tr_handle_get_tt_state:
3847 tr_handle_get_class_status:
3848 tr_handle_get_iface_status:
3849 tr_handle_get_ep_status:
3851 USETW(sc->sc_hub_temp.wValue, 0);
3855 tr_handle_set_interface:
3856 tr_handle_set_wakeup:
3857 tr_handle_clear_wakeup:
3858 tr_handle_clear_halt:
3861 tr_handle_clear_port_feature:
3865 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
3868 case UHF_PORT_SUSPEND:
3869 if (sc->sc_mode == MUSB2_HOST_MODE)
3870 musbotg_wakeup_host(sc);
3872 musbotg_wakeup_peer(sc);
3875 case UHF_PORT_ENABLE:
3876 sc->sc_flags.port_enabled = 0;
3879 case UHF_C_PORT_ENABLE:
3880 sc->sc_flags.change_enabled = 0;
3883 case UHF_C_PORT_OVER_CURRENT:
3884 sc->sc_flags.change_over_current = 0;
3887 case UHF_C_PORT_RESET:
3888 sc->sc_flags.change_reset = 0;
3892 case UHF_PORT_INDICATOR:
3896 case UHF_PORT_POWER:
3897 sc->sc_flags.port_powered = 0;
3898 musbotg_pull_down(sc);
3899 musbotg_clocks_off(sc);
3901 case UHF_C_PORT_CONNECTION:
3902 sc->sc_flags.change_connect = 0;
3904 case UHF_C_PORT_SUSPEND:
3905 sc->sc_flags.change_suspend = 0;
3908 err = USB_ERR_IOERROR;
3913 tr_handle_set_port_feature:
3917 DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
3920 case UHF_PORT_ENABLE:
3921 sc->sc_flags.port_enabled = 1;
3923 case UHF_PORT_SUSPEND:
3924 if (sc->sc_mode == MUSB2_HOST_MODE)
3925 musbotg_suspend_host(sc);
3928 case UHF_PORT_RESET:
3929 if (sc->sc_mode == MUSB2_HOST_MODE) {
3930 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3931 reg |= MUSB2_MASK_RESET;
3932 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3934 /* Wait for 20 msec */
3935 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5);
3937 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3938 reg &= ~MUSB2_MASK_RESET;
3939 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3941 /* determine line speed */
3942 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3943 if (reg & MUSB2_MASK_HSMODE)
3944 sc->sc_flags.status_high_speed = 1;
3946 sc->sc_flags.status_high_speed = 0;
3948 sc->sc_flags.change_reset = 1;
3950 err = USB_ERR_IOERROR;
3954 case UHF_PORT_INDICATOR:
3957 case UHF_PORT_POWER:
3958 sc->sc_flags.port_powered = 1;
3961 err = USB_ERR_IOERROR;
3966 tr_handle_get_port_status:
3968 DPRINTFN(8, "UR_GET_PORT_STATUS\n");
3973 if (sc->sc_flags.status_vbus) {
3974 musbotg_clocks_on(sc);
3975 musbotg_pull_up(sc);
3977 musbotg_pull_down(sc);
3978 musbotg_clocks_off(sc);
3981 /* Select Device Side Mode */
3982 if (sc->sc_mode == MUSB2_DEVICE_MODE)
3983 value = UPS_PORT_MODE_DEVICE;
3987 if (sc->sc_flags.status_high_speed) {
3988 value |= UPS_HIGH_SPEED;
3990 if (sc->sc_flags.port_powered) {
3991 value |= UPS_PORT_POWER;
3993 if (sc->sc_flags.port_enabled) {
3994 value |= UPS_PORT_ENABLED;
3997 if (sc->sc_flags.port_over_current)
3998 value |= UPS_OVERCURRENT_INDICATOR;
4000 if (sc->sc_flags.status_vbus &&
4001 sc->sc_flags.status_bus_reset) {
4002 value |= UPS_CURRENT_CONNECT_STATUS;
4004 if (sc->sc_flags.status_suspend) {
4005 value |= UPS_SUSPEND;
4007 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4011 if (sc->sc_flags.change_connect) {
4012 value |= UPS_C_CONNECT_STATUS;
4014 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
4015 if (sc->sc_flags.status_vbus &&
4016 sc->sc_flags.status_bus_reset) {
4017 /* reset EP0 state */
4018 sc->sc_ep0_busy = 0;
4023 if (sc->sc_flags.change_suspend)
4024 value |= UPS_C_SUSPEND;
4025 if (sc->sc_flags.change_reset)
4026 value |= UPS_C_PORT_RESET;
4027 if (sc->sc_flags.change_over_current)
4028 value |= UPS_C_OVERCURRENT_INDICATOR;
4030 USETW(sc->sc_hub_temp.ps.wPortChange, value);
4031 len = sizeof(sc->sc_hub_temp.ps);
4034 tr_handle_get_class_descriptor:
4038 ptr = (const void *)&musbotg_hubd;
4039 len = sizeof(musbotg_hubd);
4043 err = USB_ERR_STALLED;
4052 musbotg_xfer_setup(struct usb_setup_params *parm)
4054 struct musbotg_softc *sc;
4055 struct usb_xfer *xfer;
4061 sc = MUSBOTG_BUS2SC(parm->udev->bus);
4062 xfer = parm->curr_xfer;
4065 * NOTE: This driver does not use any of the parameters that
4066 * are computed from the following values. Just set some
4067 * reasonable dummies:
4069 parm->hc_max_packet_size = 0x400;
4070 parm->hc_max_frame_size = 0xc00;
4072 if ((parm->methods == &musbotg_device_isoc_methods) ||
4073 (parm->methods == &musbotg_device_intr_methods))
4074 parm->hc_max_packet_count = 3;
4076 parm->hc_max_packet_count = 1;
4078 usbd_transfer_setup_sub(parm);
4081 * compute maximum number of TDs
4083 if (parm->methods == &musbotg_device_ctrl_methods) {
4084 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
4086 } else if (parm->methods == &musbotg_device_bulk_methods) {
4087 ntd = xfer->nframes + 1 /* SYNC */ ;
4089 } else if (parm->methods == &musbotg_device_intr_methods) {
4090 ntd = xfer->nframes + 1 /* SYNC */ ;
4092 } else if (parm->methods == &musbotg_device_isoc_methods) {
4093 ntd = xfer->nframes + 1 /* SYNC */ ;
4100 * check if "usbd_transfer_setup_sub" set an error
4106 * allocate transfer descriptors
4110 ep_no = xfer->endpointno & UE_ADDR;
4113 * Check for a valid endpoint profile in USB device mode:
4115 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4116 const struct usb_hw_ep_profile *pf;
4118 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4121 /* should not happen */
4122 parm->err = USB_ERR_INVAL;
4128 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4130 for (n = 0; n != ntd; n++) {
4131 struct musbotg_td *td;
4134 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4137 td->max_frame_size = xfer->max_frame_size;
4138 td->reg_max_packet = xfer->max_packet_size |
4139 ((xfer->max_packet_count - 1) << 11);
4141 td->obj_next = last_obj;
4145 parm->size[0] += sizeof(*td);
4148 xfer->td_start[0] = last_obj;
4152 musbotg_xfer_unsetup(struct usb_xfer *xfer)
4158 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4160 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4162 if (sc->sc_mode == MUSB2_HOST_MODE)
4163 *pus = 2000; /* microseconds */
4169 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4170 struct usb_endpoint *ep)
4172 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4174 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
4176 edesc->bEndpointAddress, udev->flags.usb_mode,
4179 if (udev->device_index != sc->sc_rt_addr) {
4180 switch (edesc->bmAttributes & UE_XFERTYPE) {
4182 ep->methods = &musbotg_device_ctrl_methods;
4185 ep->methods = &musbotg_device_intr_methods;
4187 case UE_ISOCHRONOUS:
4188 ep->methods = &musbotg_device_isoc_methods;
4191 ep->methods = &musbotg_device_bulk_methods;
4201 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4203 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
4206 case USB_HW_POWER_SUSPEND:
4209 case USB_HW_POWER_SHUTDOWN:
4212 case USB_HW_POWER_RESUME:
4220 static const struct usb_bus_methods musbotg_bus_methods =
4222 .endpoint_init = &musbotg_ep_init,
4223 .get_dma_delay = &musbotg_get_dma_delay,
4224 .xfer_setup = &musbotg_xfer_setup,
4225 .xfer_unsetup = &musbotg_xfer_unsetup,
4226 .get_hw_ep_profile = &musbotg_get_hw_ep_profile,
4227 .xfer_stall = &musbotg_xfer_stall,
4228 .set_stall = &musbotg_set_stall,
4229 .clear_stall = &musbotg_clear_stall,
4230 .roothub_exec = &musbotg_roothub_exec,
4231 .xfer_poll = &musbotg_do_poll,
4232 .set_hw_power_sleep = &musbotg_set_hw_power_sleep,