3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Thanks to Mentor Graphics for providing a reference driver for this USB chip
35 * This file contains the driver for the Mentor Graphics Inventra USB
36 * 2.0 High Speed Dual-Role controller.
40 #ifdef USB_GLOBAL_INCLUDE_FILE
41 #include USB_GLOBAL_INCLUDE_FILE
43 #include <sys/stdint.h>
44 #include <sys/stddef.h>
45 #include <sys/param.h>
46 #include <sys/queue.h>
47 #include <sys/types.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
51 #include <sys/module.h>
53 #include <sys/mutex.h>
54 #include <sys/condvar.h>
55 #include <sys/sysctl.h>
57 #include <sys/unistd.h>
58 #include <sys/callout.h>
59 #include <sys/malloc.h>
62 #include <dev/usb/usb.h>
63 #include <dev/usb/usbdi.h>
65 #define USB_DEBUG_VAR musbotgdebug
67 #include <dev/usb/usb_core.h>
68 #include <dev/usb/usb_debug.h>
69 #include <dev/usb/usb_busdma.h>
70 #include <dev/usb/usb_process.h>
71 #include <dev/usb/usb_transfer.h>
72 #include <dev/usb/usb_device.h>
73 #include <dev/usb/usb_hub.h>
74 #include <dev/usb/usb_util.h>
76 #include <dev/usb/usb_controller.h>
77 #include <dev/usb/usb_bus.h>
78 #endif /* USB_GLOBAL_INCLUDE_FILE */
80 #include <dev/usb/controller/musb_otg.h>
82 #define MUSBOTG_INTR_ENDPT 1
84 #define MUSBOTG_BUS2SC(bus) \
85 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \
86 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
88 #define MUSBOTG_PC2SC(pc) \
89 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
92 static int musbotgdebug = 0;
94 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg");
95 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN,
96 &musbotgdebug, 0, "Debug level");
103 static const struct usb_bus_methods musbotg_bus_methods;
104 static const struct usb_pipe_methods musbotg_device_bulk_methods;
105 static const struct usb_pipe_methods musbotg_device_ctrl_methods;
106 static const struct usb_pipe_methods musbotg_device_intr_methods;
107 static const struct usb_pipe_methods musbotg_device_isoc_methods;
109 /* Control transfers: Device mode */
110 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
111 static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
112 static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
113 static musbotg_cmd_t musbotg_dev_ctrl_status;
115 /* Control transfers: Host mode */
116 static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
117 static musbotg_cmd_t musbotg_host_ctrl_data_rx;
118 static musbotg_cmd_t musbotg_host_ctrl_data_tx;
119 static musbotg_cmd_t musbotg_host_ctrl_status_rx;
120 static musbotg_cmd_t musbotg_host_ctrl_status_tx;
122 /* Bulk, Interrupt, Isochronous: Device mode */
123 static musbotg_cmd_t musbotg_dev_data_rx;
124 static musbotg_cmd_t musbotg_dev_data_tx;
126 /* Bulk, Interrupt, Isochronous: Host mode */
127 static musbotg_cmd_t musbotg_host_data_rx;
128 static musbotg_cmd_t musbotg_host_data_tx;
130 static void musbotg_device_done(struct usb_xfer *, usb_error_t);
131 static void musbotg_do_poll(struct usb_bus *);
132 static void musbotg_standard_done(struct usb_xfer *);
133 static void musbotg_interrupt_poll(struct musbotg_softc *);
134 static void musbotg_root_intr(struct musbotg_softc *);
135 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t);
136 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td);
137 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
140 * Here is a configuration that the chip supports.
142 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
145 .max_in_frame_size = 64,/* fixed */
146 .max_out_frame_size = 64, /* fixed */
148 .support_control = 1,
153 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx)
160 /* In device mode each EP got its own channel */
161 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
162 musbotg_ep_int_set(sc, ep, 1);
167 * All control transactions go through EP0
170 if (sc->sc_channel_mask & (1 << 0))
172 sc->sc_channel_mask |= (1 << 0);
173 musbotg_ep_int_set(sc, ep, 1);
177 for (ch = sc->sc_ep_max; ch != 0; ch--) {
178 if (sc->sc_channel_mask & (1 << ch))
181 /* check FIFO size requirement */
183 if (td->max_frame_size >
184 sc->sc_hw_ep_profile[ch].max_in_frame_size)
187 if (td->max_frame_size >
188 sc->sc_hw_ep_profile[ch].max_out_frame_size)
191 sc->sc_channel_mask |= (1 << ch);
192 musbotg_ep_int_set(sc, ch, 1);
196 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask);
202 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td)
205 DPRINTFN(1, "ep_no=%d\n", td->channel);
207 if (sc->sc_mode == MUSB2_DEVICE_MODE)
212 if (td->channel == -1)
215 musbotg_ep_int_set(sc, td->channel, 0);
216 sc->sc_channel_mask &= ~(1 << td->channel);
222 musbotg_get_hw_ep_profile(struct usb_device *udev,
223 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
225 struct musbotg_softc *sc;
227 sc = MUSBOTG_BUS2SC(udev->bus);
230 /* control endpoint */
231 *ppf = musbotg_ep_profile;
232 } else if (ep_addr <= sc->sc_ep_max) {
233 /* other endpoints */
234 *ppf = sc->sc_hw_ep_profile + ep_addr;
241 musbotg_clocks_on(struct musbotg_softc *sc)
243 if (sc->sc_flags.clocks_off &&
244 sc->sc_flags.port_powered) {
248 if (sc->sc_clocks_on) {
249 (sc->sc_clocks_on) (sc->sc_clocks_arg);
251 sc->sc_flags.clocks_off = 0;
253 /* XXX enable Transceiver */
258 musbotg_clocks_off(struct musbotg_softc *sc)
260 if (!sc->sc_flags.clocks_off) {
264 /* XXX disable Transceiver */
266 if (sc->sc_clocks_off) {
267 (sc->sc_clocks_off) (sc->sc_clocks_arg);
269 sc->sc_flags.clocks_off = 1;
274 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
278 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
280 temp |= MUSB2_MASK_SOFTC;
282 temp &= ~MUSB2_MASK_SOFTC;
284 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
288 musbotg_pull_up(struct musbotg_softc *sc)
290 /* pullup D+, if possible */
292 if (!sc->sc_flags.d_pulled_up &&
293 sc->sc_flags.port_powered) {
294 sc->sc_flags.d_pulled_up = 1;
295 musbotg_pull_common(sc, 1);
300 musbotg_pull_down(struct musbotg_softc *sc)
302 /* pulldown D+, if possible */
304 if (sc->sc_flags.d_pulled_up) {
305 sc->sc_flags.d_pulled_up = 0;
306 musbotg_pull_common(sc, 0);
311 musbotg_suspend_host(struct musbotg_softc *sc)
315 if (sc->sc_flags.status_suspend) {
319 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
320 temp |= MUSB2_MASK_SUSPMODE;
321 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
322 sc->sc_flags.status_suspend = 1;
326 musbotg_wakeup_host(struct musbotg_softc *sc)
330 if (!(sc->sc_flags.status_suspend)) {
334 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
335 temp &= ~MUSB2_MASK_SUSPMODE;
336 temp |= MUSB2_MASK_RESUME;
337 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
339 /* wait 20 milliseconds */
340 /* Wait for reset to complete. */
341 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
343 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
344 temp &= ~MUSB2_MASK_RESUME;
345 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
347 sc->sc_flags.status_suspend = 0;
351 musbotg_wakeup_peer(struct musbotg_softc *sc)
355 if (!(sc->sc_flags.status_suspend)) {
359 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
360 temp |= MUSB2_MASK_RESUME;
361 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
363 /* wait 8 milliseconds */
364 /* Wait for reset to complete. */
365 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
367 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
368 temp &= ~MUSB2_MASK_RESUME;
369 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
373 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
375 DPRINTFN(4, "addr=%d\n", addr);
377 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
381 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
383 struct musbotg_softc *sc;
384 struct usb_device_request req;
388 /* get pointer to softc */
389 sc = MUSBOTG_PC2SC(td->pc);
391 if (td->channel == -1)
392 td->channel = musbotg_channel_alloc(sc, td, 0);
394 /* EP0 is busy, wait */
395 if (td->channel == -1)
398 DPRINTFN(1, "ep_no=%d\n", td->channel);
400 /* select endpoint 0 */
401 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
403 /* read out FIFO status */
404 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
406 DPRINTFN(4, "csr=0x%02x\n", csr);
409 * NOTE: If DATAEND is set we should not call the
410 * callback, hence the status stage is not complete.
412 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
413 /* do not stall at this point */
415 /* wait for interrupt */
416 DPRINTFN(1, "CSR0 DATAEND\n");
420 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
421 /* clear SENTSTALL */
422 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
423 /* get latest status */
424 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
425 /* update EP0 state */
428 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
430 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
431 MUSB2_MASK_CSR0L_SETUPEND_CLR);
432 /* get latest status */
433 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
434 /* update EP0 state */
437 if (sc->sc_ep0_busy) {
438 DPRINTFN(1, "EP0 BUSY\n");
441 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
444 /* get the packet byte count */
445 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
447 /* verify data length */
448 if (count != td->remainder) {
449 DPRINTFN(1, "Invalid SETUP packet "
450 "length, %d bytes\n", count);
451 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
452 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
453 /* don't clear stall */
457 if (count != sizeof(req)) {
458 DPRINTFN(1, "Unsupported SETUP packet "
459 "length, %d bytes\n", count);
460 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
461 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
462 /* don't clear stall */
466 /* clear did stall flag */
470 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
471 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
473 /* copy data into real buffer */
474 usbd_copy_in(td->pc, 0, &req, sizeof(req));
476 td->offset = sizeof(req);
479 /* set pending command */
480 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
482 /* we need set stall or dataend after this */
485 /* sneak peek the set address */
486 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
487 (req.bRequest == UR_SET_ADDRESS)) {
488 sc->sc_dv_addr = req.wValue[0] & 0x7F;
490 sc->sc_dv_addr = 0xFF;
493 musbotg_channel_free(sc, td);
494 return (0); /* complete */
497 /* abort any ongoing transfer */
498 if (!td->did_stall) {
499 DPRINTFN(4, "stalling\n");
500 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
501 MUSB2_MASK_CSR0L_SENDSTALL);
504 return (1); /* not complete */
508 musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
510 struct musbotg_softc *sc;
511 struct usb_device_request req;
514 /* get pointer to softc */
515 sc = MUSBOTG_PC2SC(td->pc);
517 if (td->channel == -1)
518 td->channel = musbotg_channel_alloc(sc, td, 1);
520 /* EP0 is busy, wait */
521 if (td->channel == -1)
524 DPRINTFN(1, "ep_no=%d\n", td->channel);
526 /* select endpoint 0 */
527 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
529 /* read out FIFO status */
530 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
531 DPRINTFN(4, "csr=0x%02x\n", csr);
533 /* Not ready yet yet */
534 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
538 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
539 MUSB2_MASK_CSR0L_ERROR))
541 /* Clear status bit */
542 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
543 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
547 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
548 DPRINTFN(1, "NAK timeout\n");
550 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
551 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
552 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
553 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
554 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
555 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
556 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
557 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
558 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
559 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
563 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
564 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
570 musbotg_channel_free(sc, td);
574 /* Fifo is not empty and there is no NAK timeout */
575 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
578 /* check if we are complete */
579 if (td->remainder == 0) {
580 /* we are complete */
581 musbotg_channel_free(sc, td);
585 /* copy data into real buffer */
586 usbd_copy_out(td->pc, 0, &req, sizeof(req));
589 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
590 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
592 /* update offset and remainder */
593 td->offset += sizeof(req);
594 td->remainder -= sizeof(req);
597 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
598 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
599 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
600 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
601 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
604 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
605 MUSB2_MASK_CSR0L_TXPKTRDY |
606 MUSB2_MASK_CSR0L_SETUPPKT);
608 /* Just to be consistent, not used above */
609 td->transaction_started = 1;
611 return (1); /* in progress */
614 /* Control endpoint only data handling functions (RX/TX/SYNC) */
617 musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
619 struct usb_page_search buf_res;
620 struct musbotg_softc *sc;
625 /* get pointer to softc */
626 sc = MUSBOTG_PC2SC(td->pc);
628 /* select endpoint 0 */
629 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
631 /* check if a command is pending */
632 if (sc->sc_ep0_cmd) {
633 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
636 /* read out FIFO status */
637 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
639 DPRINTFN(4, "csr=0x%02x\n", csr);
643 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
644 MUSB2_MASK_CSR0L_SENTSTALL)) {
645 if (td->remainder == 0) {
647 * We are actually complete and have
648 * received the next SETUP
650 DPRINTFN(4, "faking complete\n");
651 return (0); /* complete */
654 * USB Host Aborted the transfer.
657 return (0); /* complete */
659 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
660 return (1); /* not complete */
662 /* get the packet byte count */
663 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
665 /* verify the packet byte count */
666 if (count != td->max_frame_size) {
667 if (count < td->max_frame_size) {
668 /* we have a short packet */
672 /* invalid USB packet */
674 return (0); /* we are complete */
677 /* verify the packet byte count */
678 if (count > td->remainder) {
679 /* invalid USB packet */
681 return (0); /* we are complete */
686 usbd_get_page(td->pc, td->offset, &buf_res);
688 /* get correct length */
689 if (buf_res.length > count) {
690 buf_res.length = count;
692 /* check for unaligned memory address */
693 if (USB_P2U(buf_res.buffer) & 3) {
698 /* receive data 4 bytes at a time */
699 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
700 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
705 /* receive data 1 byte at a time */
706 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
708 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
710 usbd_copy_in(td->pc, td->offset,
711 sc->sc_bounce_buf, count);
713 /* update offset and remainder */
715 td->remainder -= count;
718 /* check if we can optimise */
719 if (buf_res.length >= 4) {
721 /* receive data 4 bytes at a time */
722 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
723 MUSB2_REG_EPFIFO(0), buf_res.buffer,
726 temp = buf_res.length & ~3;
728 /* update counters */
731 td->remainder -= temp;
735 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
736 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
738 /* update counters */
739 count -= buf_res.length;
740 td->offset += buf_res.length;
741 td->remainder -= buf_res.length;
744 /* check if we are complete */
745 if ((td->remainder == 0) || got_short) {
747 /* we are complete */
748 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
751 /* else need to receive a zero length packet */
753 /* write command - need more data */
754 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
755 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
756 return (1); /* not complete */
760 musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
762 struct usb_page_search buf_res;
763 struct musbotg_softc *sc;
767 /* get pointer to softc */
768 sc = MUSBOTG_PC2SC(td->pc);
770 /* select endpoint 0 */
771 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
773 /* check if a command is pending */
774 if (sc->sc_ep0_cmd) {
775 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
778 /* read out FIFO status */
779 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
781 DPRINTFN(4, "csr=0x%02x\n", csr);
783 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
784 MUSB2_MASK_CSR0L_SENTSTALL)) {
786 * The current transfer was aborted
790 return (0); /* complete */
792 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
793 return (1); /* not complete */
795 count = td->max_frame_size;
796 if (td->remainder < count) {
797 /* we have a short packet */
799 count = td->remainder;
804 usbd_get_page(td->pc, td->offset, &buf_res);
806 /* get correct length */
807 if (buf_res.length > count) {
808 buf_res.length = count;
810 /* check for unaligned memory address */
811 if (USB_P2U(buf_res.buffer) & 3) {
813 usbd_copy_out(td->pc, td->offset,
814 sc->sc_bounce_buf, count);
819 /* transmit data 4 bytes at a time */
820 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
821 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
826 /* receive data 1 byte at a time */
827 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
829 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
831 /* update offset and remainder */
833 td->remainder -= count;
836 /* check if we can optimise */
837 if (buf_res.length >= 4) {
839 /* transmit data 4 bytes at a time */
840 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
841 MUSB2_REG_EPFIFO(0), buf_res.buffer,
844 temp = buf_res.length & ~3;
846 /* update counters */
849 td->remainder -= temp;
853 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
854 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
856 /* update counters */
857 count -= buf_res.length;
858 td->offset += buf_res.length;
859 td->remainder -= buf_res.length;
862 /* check remainder */
863 if (td->remainder == 0) {
865 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
866 return (0); /* complete */
868 /* else we need to transmit a short packet */
871 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
872 MUSB2_MASK_CSR0L_TXPKTRDY);
874 return (1); /* not complete */
878 musbotg_host_ctrl_data_rx(struct musbotg_td *td)
880 struct usb_page_search buf_res;
881 struct musbotg_softc *sc;
886 /* get pointer to softc */
887 sc = MUSBOTG_PC2SC(td->pc);
889 if (td->channel == -1)
890 td->channel = musbotg_channel_alloc(sc, td, 0);
892 /* EP0 is busy, wait */
893 if (td->channel == -1)
896 DPRINTFN(1, "ep_no=%d\n", td->channel);
898 /* select endpoint 0 */
899 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
901 /* read out FIFO status */
902 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
904 DPRINTFN(4, "csr=0x%02x\n", csr);
907 if (!td->transaction_started) {
908 td->transaction_started = 1;
910 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
912 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
914 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
915 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
916 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
918 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
919 MUSB2_MASK_CSR0L_REQPKT);
924 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
925 csr &= ~MUSB2_MASK_CSR0L_REQPKT;
926 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
928 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
929 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
935 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
936 MUSB2_MASK_CSR0L_ERROR))
938 /* Clear status bit */
939 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
940 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
945 musbotg_channel_free(sc, td);
946 return (0); /* we are complete */
949 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
950 return (1); /* not yet */
952 /* get the packet byte count */
953 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
955 /* verify the packet byte count */
956 if (count != td->max_frame_size) {
957 if (count < td->max_frame_size) {
958 /* we have a short packet */
962 /* invalid USB packet */
964 musbotg_channel_free(sc, td);
965 return (0); /* we are complete */
968 /* verify the packet byte count */
969 if (count > td->remainder) {
970 /* invalid USB packet */
972 musbotg_channel_free(sc, td);
973 return (0); /* we are complete */
978 usbd_get_page(td->pc, td->offset, &buf_res);
980 /* get correct length */
981 if (buf_res.length > count) {
982 buf_res.length = count;
984 /* check for unaligned memory address */
985 if (USB_P2U(buf_res.buffer) & 3) {
990 /* receive data 4 bytes at a time */
991 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
992 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
997 /* receive data 1 byte at a time */
998 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1000 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
1002 usbd_copy_in(td->pc, td->offset,
1003 sc->sc_bounce_buf, count);
1005 /* update offset and remainder */
1006 td->offset += count;
1007 td->remainder -= count;
1010 /* check if we can optimise */
1011 if (buf_res.length >= 4) {
1013 /* receive data 4 bytes at a time */
1014 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1015 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1016 buf_res.length / 4);
1018 temp = buf_res.length & ~3;
1020 /* update counters */
1023 td->remainder -= temp;
1027 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1028 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
1030 /* update counters */
1031 count -= buf_res.length;
1032 td->offset += buf_res.length;
1033 td->remainder -= buf_res.length;
1036 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
1037 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1039 /* check if we are complete */
1040 if ((td->remainder == 0) || got_short) {
1041 if (td->short_pkt) {
1042 /* we are complete */
1044 musbotg_channel_free(sc, td);
1047 /* else need to receive a zero length packet */
1050 td->transaction_started = 1;
1051 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1052 MUSB2_MASK_CSR0L_REQPKT);
1054 return (1); /* not complete */
1058 musbotg_host_ctrl_data_tx(struct musbotg_td *td)
1060 struct usb_page_search buf_res;
1061 struct musbotg_softc *sc;
1065 /* get pointer to softc */
1066 sc = MUSBOTG_PC2SC(td->pc);
1068 if (td->channel == -1)
1069 td->channel = musbotg_channel_alloc(sc, td, 1);
1072 if (td->channel == -1)
1075 DPRINTFN(1, "ep_no=%d\n", td->channel);
1077 /* select endpoint */
1078 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1080 /* read out FIFO status */
1081 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1082 DPRINTFN(4, "csr=0x%02x\n", csr);
1084 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1085 MUSB2_MASK_CSR0L_ERROR)) {
1086 /* clear status bits */
1087 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1091 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
1093 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1094 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1095 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1096 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1097 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1098 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1099 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1100 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1101 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1102 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1106 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1107 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1114 musbotg_channel_free(sc, td);
1115 return (0); /* complete */
1119 * Wait while FIFO is empty.
1120 * Do not flush it because it will cause transactions
1121 * with size more then packet size. It might upset
1124 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
1127 /* Packet still being processed */
1128 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1131 if (td->transaction_started) {
1132 /* check remainder */
1133 if (td->remainder == 0) {
1134 if (td->short_pkt) {
1135 musbotg_channel_free(sc, td);
1136 return (0); /* complete */
1138 /* else we need to transmit a short packet */
1141 /* We're not complete - more transactions required */
1142 td->transaction_started = 0;
1145 /* check for short packet */
1146 count = td->max_frame_size;
1147 if (td->remainder < count) {
1148 /* we have a short packet */
1150 count = td->remainder;
1156 usbd_get_page(td->pc, td->offset, &buf_res);
1158 /* get correct length */
1159 if (buf_res.length > count) {
1160 buf_res.length = count;
1162 /* check for unaligned memory address */
1163 if (USB_P2U(buf_res.buffer) & 3) {
1165 usbd_copy_out(td->pc, td->offset,
1166 sc->sc_bounce_buf, count);
1171 /* transmit data 4 bytes at a time */
1172 bus_space_write_multi_4(sc->sc_io_tag,
1173 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0),
1174 sc->sc_bounce_buf, temp / 4);
1178 /* receive data 1 byte at a time */
1179 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1180 MUSB2_REG_EPFIFO(0),
1181 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1183 /* update offset and remainder */
1184 td->offset += count;
1185 td->remainder -= count;
1188 /* check if we can optimise */
1189 if (buf_res.length >= 4) {
1191 /* transmit data 4 bytes at a time */
1192 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1193 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1194 buf_res.length / 4);
1196 temp = buf_res.length & ~3;
1198 /* update counters */
1201 td->remainder -= temp;
1205 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1206 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1209 /* update counters */
1210 count -= buf_res.length;
1211 td->offset += buf_res.length;
1212 td->remainder -= buf_res.length;
1215 /* Function address */
1216 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1217 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1218 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1219 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1221 /* TX NAK timeout */
1222 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1225 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1226 MUSB2_MASK_CSR0L_TXPKTRDY);
1228 td->transaction_started = 1;
1230 return (1); /* not complete */
1234 musbotg_dev_ctrl_status(struct musbotg_td *td)
1236 struct musbotg_softc *sc;
1239 /* get pointer to softc */
1240 sc = MUSBOTG_PC2SC(td->pc);
1242 /* select endpoint 0 */
1243 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1245 if (sc->sc_ep0_busy) {
1246 sc->sc_ep0_busy = 0;
1247 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
1248 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
1251 /* read out FIFO status */
1252 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1254 DPRINTFN(4, "csr=0x%02x\n", csr);
1256 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
1257 /* wait for interrupt */
1258 return (1); /* not complete */
1260 if (sc->sc_dv_addr != 0xFF) {
1261 /* write function address */
1262 musbotg_set_address(sc, sc->sc_dv_addr);
1265 musbotg_channel_free(sc, td);
1266 return (0); /* complete */
1270 musbotg_host_ctrl_status_rx(struct musbotg_td *td)
1272 struct musbotg_softc *sc;
1275 /* get pointer to softc */
1276 sc = MUSBOTG_PC2SC(td->pc);
1278 if (td->channel == -1)
1279 td->channel = musbotg_channel_alloc(sc, td, 0);
1281 /* EP0 is busy, wait */
1282 if (td->channel == -1)
1285 DPRINTFN(1, "ep_no=%d\n", td->channel);
1287 /* select endpoint 0 */
1288 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1290 if (!td->transaction_started) {
1291 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
1294 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
1295 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
1296 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1298 /* RX NAK timeout */
1299 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1301 td->transaction_started = 1;
1304 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1305 csrh |= MUSB2_MASK_CSR0H_PING_DIS;
1306 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1309 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1310 MUSB2_MASK_CSR0L_STATUSPKT |
1311 MUSB2_MASK_CSR0L_REQPKT);
1313 return (1); /* Just started */
1317 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1319 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
1321 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
1322 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1323 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
1324 musbotg_channel_free(sc, td);
1325 return (0); /* complete */
1328 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1329 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT |
1330 MUSB2_MASK_CSR0L_REQPKT);
1331 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1333 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1334 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1339 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1340 MUSB2_MASK_CSR0L_ERROR))
1342 /* Clear status bit */
1343 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1344 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1349 musbotg_channel_free(sc, td);
1353 return (1); /* Not ready yet */
1357 musbotg_host_ctrl_status_tx(struct musbotg_td *td)
1359 struct musbotg_softc *sc;
1362 /* get pointer to softc */
1363 sc = MUSBOTG_PC2SC(td->pc);
1365 if (td->channel == -1)
1366 td->channel = musbotg_channel_alloc(sc, td, 1);
1368 /* EP0 is busy, wait */
1369 if (td->channel == -1)
1372 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started,
1373 td->dev_addr,td->haddr,td->hport, td->transfer_type);
1375 /* select endpoint 0 */
1376 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1378 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1379 DPRINTFN(4, "csr=0x%02x\n", csr);
1382 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1386 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1387 MUSB2_MASK_CSR0L_ERROR))
1389 /* Clear status bit */
1390 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1391 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1393 musbotg_channel_free(sc, td);
1394 return (0); /* complete */
1397 if (td->transaction_started) {
1398 musbotg_channel_free(sc, td);
1399 return (0); /* complete */
1402 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS);
1404 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1405 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1406 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1407 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1409 /* TX NAK timeout */
1410 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1412 td->transaction_started = 1;
1415 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1416 MUSB2_MASK_CSR0L_STATUSPKT |
1417 MUSB2_MASK_CSR0L_TXPKTRDY);
1419 return (1); /* wait for interrupt */
1423 musbotg_dev_data_rx(struct musbotg_td *td)
1425 struct usb_page_search buf_res;
1426 struct musbotg_softc *sc;
1432 to = 8; /* don't loop forever! */
1435 /* get pointer to softc */
1436 sc = MUSBOTG_PC2SC(td->pc);
1438 if (td->channel == -1)
1439 td->channel = musbotg_channel_alloc(sc, td, 0);
1441 /* EP0 is busy, wait */
1442 if (td->channel == -1)
1445 /* select endpoint */
1446 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1449 /* read out FIFO status */
1450 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1452 DPRINTFN(4, "csr=0x%02x\n", csr);
1455 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
1456 /* make sure we don't clear "RXPKTRDY" */
1457 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1458 MUSB2_MASK_CSRL_RXPKTRDY);
1462 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
1463 return (1); /* not complete */
1465 /* get the packet byte count */
1466 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1468 DPRINTFN(4, "count=0x%04x\n", count);
1471 * Check for short or invalid packet:
1473 if (count != td->max_frame_size) {
1474 if (count < td->max_frame_size) {
1475 /* we have a short packet */
1479 /* invalid USB packet */
1481 musbotg_channel_free(sc, td);
1482 return (0); /* we are complete */
1485 /* verify the packet byte count */
1486 if (count > td->remainder) {
1487 /* invalid USB packet */
1489 musbotg_channel_free(sc, td);
1490 return (0); /* we are complete */
1495 usbd_get_page(td->pc, td->offset, &buf_res);
1497 /* get correct length */
1498 if (buf_res.length > count) {
1499 buf_res.length = count;
1501 /* check for unaligned memory address */
1502 if (USB_P2U(buf_res.buffer) & 3) {
1507 /* receive data 4 bytes at a time */
1508 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1509 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1514 /* receive data 1 byte at a time */
1515 bus_space_read_multi_1(sc->sc_io_tag,
1516 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1517 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1519 usbd_copy_in(td->pc, td->offset,
1520 sc->sc_bounce_buf, count);
1522 /* update offset and remainder */
1523 td->offset += count;
1524 td->remainder -= count;
1527 /* check if we can optimise */
1528 if (buf_res.length >= 4) {
1530 /* receive data 4 bytes at a time */
1531 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1532 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1533 buf_res.length / 4);
1535 temp = buf_res.length & ~3;
1537 /* update counters */
1540 td->remainder -= temp;
1544 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1545 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1548 /* update counters */
1549 count -= buf_res.length;
1550 td->offset += buf_res.length;
1551 td->remainder -= buf_res.length;
1554 /* clear status bits */
1555 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1557 /* check if we are complete */
1558 if ((td->remainder == 0) || got_short) {
1559 if (td->short_pkt) {
1560 /* we are complete */
1561 musbotg_channel_free(sc, td);
1564 /* else need to receive a zero length packet */
1569 return (1); /* not complete */
1573 musbotg_dev_data_tx(struct musbotg_td *td)
1575 struct usb_page_search buf_res;
1576 struct musbotg_softc *sc;
1581 to = 8; /* don't loop forever! */
1583 /* get pointer to softc */
1584 sc = MUSBOTG_PC2SC(td->pc);
1586 if (td->channel == -1)
1587 td->channel = musbotg_channel_alloc(sc, td, 1);
1589 /* EP0 is busy, wait */
1590 if (td->channel == -1)
1593 /* select endpoint */
1594 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1598 /* read out FIFO status */
1599 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1601 DPRINTFN(4, "csr=0x%02x\n", csr);
1603 if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
1604 MUSB2_MASK_CSRL_TXUNDERRUN)) {
1605 /* clear status bits */
1606 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1608 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
1609 return (1); /* not complete */
1611 /* check for short packet */
1612 count = td->max_frame_size;
1613 if (td->remainder < count) {
1614 /* we have a short packet */
1616 count = td->remainder;
1621 usbd_get_page(td->pc, td->offset, &buf_res);
1623 /* get correct length */
1624 if (buf_res.length > count) {
1625 buf_res.length = count;
1627 /* check for unaligned memory address */
1628 if (USB_P2U(buf_res.buffer) & 3) {
1630 usbd_copy_out(td->pc, td->offset,
1631 sc->sc_bounce_buf, count);
1636 /* transmit data 4 bytes at a time */
1637 bus_space_write_multi_4(sc->sc_io_tag,
1638 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1639 sc->sc_bounce_buf, temp / 4);
1643 /* receive data 1 byte at a time */
1644 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1645 MUSB2_REG_EPFIFO(td->channel),
1646 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1648 /* update offset and remainder */
1649 td->offset += count;
1650 td->remainder -= count;
1653 /* check if we can optimise */
1654 if (buf_res.length >= 4) {
1656 /* transmit data 4 bytes at a time */
1657 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1658 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1659 buf_res.length / 4);
1661 temp = buf_res.length & ~3;
1663 /* update counters */
1666 td->remainder -= temp;
1670 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1671 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1674 /* update counters */
1675 count -= buf_res.length;
1676 td->offset += buf_res.length;
1677 td->remainder -= buf_res.length;
1680 /* Max packet size */
1681 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
1684 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1685 MUSB2_MASK_CSRL_TXPKTRDY);
1687 /* check remainder */
1688 if (td->remainder == 0) {
1689 if (td->short_pkt) {
1690 musbotg_channel_free(sc, td);
1691 return (0); /* complete */
1693 /* else we need to transmit a short packet */
1698 return (1); /* not complete */
1702 musbotg_host_data_rx(struct musbotg_td *td)
1704 struct usb_page_search buf_res;
1705 struct musbotg_softc *sc;
1711 /* get pointer to softc */
1712 sc = MUSBOTG_PC2SC(td->pc);
1714 if (td->channel == -1)
1715 td->channel = musbotg_channel_alloc(sc, td, 0);
1718 if (td->channel == -1)
1721 DPRINTFN(1, "ep_no=%d\n", td->channel);
1723 to = 8; /* don't loop forever! */
1726 /* select endpoint */
1727 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1730 /* read out FIFO status */
1731 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1732 DPRINTFN(4, "csr=0x%02x\n", csr);
1734 if (!td->transaction_started) {
1735 /* Function address */
1736 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel),
1739 /* SPLIT transaction */
1740 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel),
1742 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel),
1745 /* RX NAK timeout */
1746 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
1747 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0);
1749 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1751 /* Protocol, speed, device endpoint */
1752 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1754 /* Max packet size */
1755 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet);
1758 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1759 DPRINTFN(4, "csrh=0x%02x\n", csrh);
1761 csrh |= MUSB2_MASK_CSRH_RXDT_WREN;
1763 csrh |= MUSB2_MASK_CSRH_RXDT_VAL;
1765 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1767 /* Set data toggle */
1768 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1771 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1772 MUSB2_MASK_CSRL_RXREQPKT);
1774 td->transaction_started = 1;
1778 /* clear NAK timeout */
1779 if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1780 DPRINTFN(4, "NAK Timeout\n");
1781 if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
1782 csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1783 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1785 csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1786 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1792 if (csr & MUSB2_MASK_CSRL_RXERROR) {
1793 DPRINTFN(4, "RXERROR\n");
1797 if (csr & MUSB2_MASK_CSRL_RXSTALL) {
1798 DPRINTFN(4, "RXSTALL\n");
1803 musbotg_channel_free(sc, td);
1804 return (0); /* we are complete */
1807 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
1808 /* No data available yet */
1813 /* get the packet byte count */
1814 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1815 DPRINTFN(4, "count=0x%04x\n", count);
1818 * Check for short or invalid packet:
1820 if (count != td->max_frame_size) {
1821 if (count < td->max_frame_size) {
1822 /* we have a short packet */
1826 /* invalid USB packet */
1828 musbotg_channel_free(sc, td);
1829 return (0); /* we are complete */
1833 /* verify the packet byte count */
1834 if (count > td->remainder) {
1835 /* invalid USB packet */
1837 musbotg_channel_free(sc, td);
1838 return (0); /* we are complete */
1844 usbd_get_page(td->pc, td->offset, &buf_res);
1846 /* get correct length */
1847 if (buf_res.length > count) {
1848 buf_res.length = count;
1850 /* check for unaligned memory address */
1851 if (USB_P2U(buf_res.buffer) & 3) {
1856 /* receive data 4 bytes at a time */
1857 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1858 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1863 /* receive data 1 byte at a time */
1864 bus_space_read_multi_1(sc->sc_io_tag,
1865 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1866 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1868 usbd_copy_in(td->pc, td->offset,
1869 sc->sc_bounce_buf, count);
1871 /* update offset and remainder */
1872 td->offset += count;
1873 td->remainder -= count;
1876 /* check if we can optimise */
1877 if (buf_res.length >= 4) {
1879 /* receive data 4 bytes at a time */
1880 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1881 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1882 buf_res.length / 4);
1884 temp = buf_res.length & ~3;
1886 /* update counters */
1889 td->remainder -= temp;
1893 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1894 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1897 /* update counters */
1898 count -= buf_res.length;
1899 td->offset += buf_res.length;
1900 td->remainder -= buf_res.length;
1903 /* clear status bits */
1904 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1906 /* check if we are complete */
1907 if ((td->remainder == 0) || got_short) {
1908 if (td->short_pkt) {
1909 /* we are complete */
1910 musbotg_channel_free(sc, td);
1913 /* else need to receive a zero length packet */
1916 /* Reset transaction state and restart */
1917 td->transaction_started = 0;
1922 return (1); /* not complete */
1926 musbotg_host_data_tx(struct musbotg_td *td)
1928 struct usb_page_search buf_res;
1929 struct musbotg_softc *sc;
1933 /* get pointer to softc */
1934 sc = MUSBOTG_PC2SC(td->pc);
1936 if (td->channel == -1)
1937 td->channel = musbotg_channel_alloc(sc, td, 1);
1940 if (td->channel == -1)
1943 DPRINTFN(1, "ep_no=%d\n", td->channel);
1945 /* select endpoint */
1946 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1948 /* read out FIFO status */
1949 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1950 DPRINTFN(4, "csr=0x%02x\n", csr);
1952 if (csr & (MUSB2_MASK_CSRL_TXSTALLED |
1953 MUSB2_MASK_CSRL_TXERROR)) {
1954 /* clear status bits */
1955 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1957 musbotg_channel_free(sc, td);
1958 return (0); /* complete */
1961 if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
1963 * Flush TX FIFO before clearing NAK TO
1965 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1966 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1967 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1968 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1969 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1970 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1971 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1972 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1976 csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
1977 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1980 musbotg_channel_free(sc, td);
1981 return (0); /* complete */
1985 * Wait while FIFO is empty.
1986 * Do not flush it because it will cause transactions
1987 * with size more then packet size. It might upset
1990 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
1993 /* Packet still being processed */
1994 if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
1997 if (td->transaction_started) {
1998 /* check remainder */
1999 if (td->remainder == 0) {
2000 if (td->short_pkt) {
2001 musbotg_channel_free(sc, td);
2002 return (0); /* complete */
2004 /* else we need to transmit a short packet */
2007 /* We're not complete - more transactions required */
2008 td->transaction_started = 0;
2011 /* check for short packet */
2012 count = td->max_frame_size;
2013 if (td->remainder < count) {
2014 /* we have a short packet */
2016 count = td->remainder;
2022 usbd_get_page(td->pc, td->offset, &buf_res);
2024 /* get correct length */
2025 if (buf_res.length > count) {
2026 buf_res.length = count;
2028 /* check for unaligned memory address */
2029 if (USB_P2U(buf_res.buffer) & 3) {
2031 usbd_copy_out(td->pc, td->offset,
2032 sc->sc_bounce_buf, count);
2037 /* transmit data 4 bytes at a time */
2038 bus_space_write_multi_4(sc->sc_io_tag,
2039 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
2040 sc->sc_bounce_buf, temp / 4);
2044 /* receive data 1 byte at a time */
2045 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2046 MUSB2_REG_EPFIFO(td->channel),
2047 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
2049 /* update offset and remainder */
2050 td->offset += count;
2051 td->remainder -= count;
2054 /* check if we can optimise */
2055 if (buf_res.length >= 4) {
2057 /* transmit data 4 bytes at a time */
2058 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
2059 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2060 buf_res.length / 4);
2062 temp = buf_res.length & ~3;
2064 /* update counters */
2067 td->remainder -= temp;
2071 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2072 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2075 /* update counters */
2076 count -= buf_res.length;
2077 td->offset += buf_res.length;
2078 td->remainder -= buf_res.length;
2081 /* Function address */
2082 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel),
2085 /* SPLIT transaction */
2086 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel),
2088 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel),
2091 /* TX NAK timeout */
2092 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
2093 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0);
2095 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
2097 /* Protocol, speed, device endpoint */
2098 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
2100 /* Max packet size */
2101 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
2103 if (!td->transaction_started) {
2104 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
2105 DPRINTFN(4, "csrh=0x%02x\n", csrh);
2107 csrh |= MUSB2_MASK_CSRH_TXDT_WREN;
2109 csrh |= MUSB2_MASK_CSRH_TXDT_VAL;
2111 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL;
2113 /* Set data toggle */
2114 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
2118 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2119 MUSB2_MASK_CSRL_TXPKTRDY);
2121 /* Update Data Toggle */
2123 td->transaction_started = 1;
2125 return (1); /* not complete */
2129 musbotg_xfer_do_fifo(struct usb_xfer *xfer)
2131 struct musbotg_softc *sc;
2132 struct musbotg_td *td;
2135 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2137 td = xfer->td_transfer_cache;
2140 if ((td->func) (td)) {
2141 /* operation in progress */
2145 if (((void *)td) == xfer->td_transfer_last) {
2150 } else if (td->remainder > 0) {
2152 * We had a short transfer. If there is no alternate
2153 * next, stop processing !
2155 if (!td->alt_next) {
2160 * Fetch the next transfer descriptor and transfer
2161 * some flags to the next transfer descriptor
2164 xfer->td_transfer_cache = td;
2167 return (1); /* not complete */
2169 /* compute all actual lengths */
2170 musbotg_standard_done(xfer);
2172 return (0); /* complete */
2176 musbotg_interrupt_poll(struct musbotg_softc *sc)
2178 struct usb_xfer *xfer;
2181 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2182 if (!musbotg_xfer_do_fifo(xfer)) {
2183 /* queue has been modified */
2190 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
2192 DPRINTFN(4, "vbus = %u\n", is_on);
2194 USB_BUS_LOCK(&sc->sc_bus);
2196 if (!sc->sc_flags.status_vbus) {
2197 sc->sc_flags.status_vbus = 1;
2199 /* complete root HUB interrupt endpoint */
2200 musbotg_root_intr(sc);
2203 if (sc->sc_flags.status_vbus) {
2204 sc->sc_flags.status_vbus = 0;
2205 sc->sc_flags.status_bus_reset = 0;
2206 sc->sc_flags.status_suspend = 0;
2207 sc->sc_flags.change_suspend = 0;
2208 sc->sc_flags.change_connect = 1;
2210 /* complete root HUB interrupt endpoint */
2211 musbotg_root_intr(sc);
2215 USB_BUS_UNLOCK(&sc->sc_bus);
2219 musbotg_connect_interrupt(struct musbotg_softc *sc)
2221 USB_BUS_LOCK(&sc->sc_bus);
2222 sc->sc_flags.change_connect = 1;
2224 /* complete root HUB interrupt endpoint */
2225 musbotg_root_intr(sc);
2226 USB_BUS_UNLOCK(&sc->sc_bus);
2230 musbotg_interrupt(struct musbotg_softc *sc,
2231 uint16_t rxstat, uint16_t txstat, uint8_t stat)
2239 USB_BUS_LOCK(&sc->sc_bus);
2243 /* read all interrupt registers */
2244 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
2246 /* read all FIFO interrupts */
2247 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
2248 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
2249 rx_status |= rxstat;
2250 tx_status |= txstat;
2253 /* Clear platform flags after first time */
2258 /* check for any bus state change interrupts */
2260 if (usb_status & (MUSB2_MASK_IRESET |
2261 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP |
2262 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC |
2263 MUSB2_MASK_IVBUSERR)) {
2265 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
2267 if (usb_status & MUSB2_MASK_IRESET) {
2269 /* set correct state */
2270 sc->sc_flags.status_bus_reset = 1;
2271 sc->sc_flags.status_suspend = 0;
2272 sc->sc_flags.change_suspend = 0;
2273 sc->sc_flags.change_connect = 1;
2275 /* determine line speed */
2276 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
2277 if (temp & MUSB2_MASK_HSMODE)
2278 sc->sc_flags.status_high_speed = 1;
2280 sc->sc_flags.status_high_speed = 0;
2283 * After reset all interrupts are on and we need to
2286 temp = MUSB2_MASK_IRESET;
2287 /* disable resume interrupt */
2288 temp &= ~MUSB2_MASK_IRESUME;
2289 /* enable suspend interrupt */
2290 temp |= MUSB2_MASK_ISUSP;
2291 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2292 /* disable TX and RX interrupts */
2293 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
2294 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
2297 * If RXRSM and RXSUSP is set at the same time we interpret
2298 * that like RESUME. Resume is set when there is at least 3
2299 * milliseconds of inactivity on the USB BUS.
2301 if (usb_status & MUSB2_MASK_IRESUME) {
2302 if (sc->sc_flags.status_suspend) {
2303 sc->sc_flags.status_suspend = 0;
2304 sc->sc_flags.change_suspend = 1;
2306 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2307 /* disable resume interrupt */
2308 temp &= ~MUSB2_MASK_IRESUME;
2309 /* enable suspend interrupt */
2310 temp |= MUSB2_MASK_ISUSP;
2311 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2313 } else if (usb_status & MUSB2_MASK_ISUSP) {
2314 if (!sc->sc_flags.status_suspend) {
2315 sc->sc_flags.status_suspend = 1;
2316 sc->sc_flags.change_suspend = 1;
2318 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2319 /* disable suspend interrupt */
2320 temp &= ~MUSB2_MASK_ISUSP;
2321 /* enable resume interrupt */
2322 temp |= MUSB2_MASK_IRESUME;
2323 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2327 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC))
2328 sc->sc_flags.change_connect = 1;
2331 * Host Mode: There is no IRESET so assume bus is
2332 * always in reset state once device is connected.
2334 if (sc->sc_mode == MUSB2_HOST_MODE) {
2335 /* check for VBUS error in USB host mode */
2336 if (usb_status & MUSB2_MASK_IVBUSERR) {
2337 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
2338 temp |= MUSB2_MASK_SESS;
2339 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
2341 if (usb_status & MUSB2_MASK_ICONN)
2342 sc->sc_flags.status_bus_reset = 1;
2343 if (usb_status & MUSB2_MASK_IDISC)
2344 sc->sc_flags.status_bus_reset = 0;
2347 /* complete root HUB interrupt endpoint */
2348 musbotg_root_intr(sc);
2350 /* check for any endpoint interrupts */
2352 if (rx_status || tx_status) {
2353 DPRINTFN(4, "real endpoint interrupt "
2354 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
2356 /* poll one time regardless of FIFO status */
2358 musbotg_interrupt_poll(sc);
2363 USB_BUS_UNLOCK(&sc->sc_bus);
2367 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
2369 struct musbotg_td *td;
2371 /* get current Transfer Descriptor */
2375 /* prepare for next TD */
2376 temp->td_next = td->obj_next;
2378 /* fill out the Transfer Descriptor */
2379 td->func = temp->func;
2381 td->offset = temp->offset;
2382 td->remainder = temp->len;
2384 td->transaction_started = 0;
2385 td->did_stall = temp->did_stall;
2386 td->short_pkt = temp->short_pkt;
2387 td->alt_next = temp->setup_alt_next;
2388 td->channel = temp->channel;
2389 td->dev_addr = temp->dev_addr;
2390 td->haddr = temp->haddr;
2391 td->hport = temp->hport;
2392 td->transfer_type = temp->transfer_type;
2396 musbotg_setup_standard_chain(struct usb_xfer *xfer)
2398 struct musbotg_std_temp temp;
2399 struct musbotg_softc *sc;
2400 struct musbotg_td *td;
2404 enum usb_dev_speed speed;
2408 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2409 xfer->address, UE_GET_ADDR(xfer->endpointno),
2410 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2412 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2413 ep_no = (xfer->endpointno & UE_ADDR);
2415 temp.max_frame_size = xfer->max_frame_size;
2417 td = xfer->td_start[0];
2418 xfer->td_transfer_first = td;
2419 xfer->td_transfer_cache = td;
2422 dev_addr = xfer->address;
2424 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE;
2428 temp.td_next = xfer->td_start[0];
2430 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
2431 xfer->flags_int.isochronous_xfr;
2432 temp.did_stall = !xfer->flags_int.control_stall;
2434 temp.dev_addr = dev_addr;
2435 temp.haddr = xfer->xroot->udev->hs_hub_addr;
2436 temp.hport = xfer->xroot->udev->hs_port_no;
2438 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2439 speed = usbd_get_speed(xfer->xroot->udev);
2443 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO;
2445 case USB_SPEED_FULL:
2446 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS;
2448 case USB_SPEED_HIGH:
2449 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS;
2452 temp.transfer_type = 0;
2453 DPRINTFN(-1, "Invalid USB speed: %d\n", speed);
2457 switch (xfer_type) {
2459 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL;
2461 case UE_ISOCHRONOUS:
2462 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC;
2465 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK;
2468 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR;
2471 DPRINTFN(-1, "Invalid USB transfer type: %d\n",
2476 temp.transfer_type |= ep_no;
2477 td->toggle = xfer->endpoint->toggle_next;
2480 /* check if we should prepend a setup message */
2482 if (xfer->flags_int.control_xfr) {
2483 if (xfer->flags_int.control_hdr) {
2485 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE)
2486 temp.func = &musbotg_dev_ctrl_setup_rx;
2488 temp.func = &musbotg_host_ctrl_setup_tx;
2490 temp.len = xfer->frlengths[0];
2491 temp.pc = xfer->frbuffers + 0;
2492 temp.short_pkt = temp.len ? 1 : 0;
2494 musbotg_setup_standard_chain_sub(&temp);
2503 if (x != xfer->nframes) {
2504 if (xfer->endpointno & UE_DIR_IN)
2507 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2511 if (xfer->flags_int.control_xfr)
2512 temp.func = &musbotg_host_ctrl_data_tx;
2514 temp.func = &musbotg_host_data_tx;
2516 if (xfer->flags_int.control_xfr)
2517 temp.func = &musbotg_host_ctrl_data_rx;
2519 temp.func = &musbotg_host_data_rx;
2524 if (xfer->flags_int.control_xfr)
2525 temp.func = &musbotg_dev_ctrl_data_tx;
2527 temp.func = &musbotg_dev_data_tx;
2529 if (xfer->flags_int.control_xfr)
2530 temp.func = &musbotg_dev_ctrl_data_rx;
2532 temp.func = &musbotg_dev_data_rx;
2536 /* setup "pc" pointer */
2537 temp.pc = xfer->frbuffers + x;
2539 while (x != xfer->nframes) {
2541 /* DATA0 / DATA1 message */
2543 temp.len = xfer->frlengths[x];
2547 if (x == xfer->nframes) {
2548 if (xfer->flags_int.control_xfr) {
2549 if (xfer->flags_int.control_act) {
2550 temp.setup_alt_next = 0;
2553 temp.setup_alt_next = 0;
2556 if (temp.len == 0) {
2558 /* make sure that we send an USB packet */
2564 if (xfer->flags_int.isochronous_xfr) {
2565 /* isochronous data transfer */
2566 /* don't force short */
2569 /* regular data transfer */
2570 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
2574 musbotg_setup_standard_chain_sub(&temp);
2576 if (xfer->flags_int.isochronous_xfr) {
2577 temp.offset += temp.len;
2579 /* get next Page Cache pointer */
2580 temp.pc = xfer->frbuffers + x;
2584 /* check for control transfer */
2585 if (xfer->flags_int.control_xfr) {
2587 /* always setup a valid "pc" pointer for status and sync */
2588 temp.pc = xfer->frbuffers + 0;
2591 temp.setup_alt_next = 0;
2593 /* check if we should append a status stage */
2594 if (!xfer->flags_int.control_act) {
2596 * Send a DATA1 message and invert the current
2597 * endpoint direction.
2599 if (sc->sc_mode == MUSB2_DEVICE_MODE)
2600 temp.func = &musbotg_dev_ctrl_status;
2602 if (xfer->endpointno & UE_DIR_IN)
2603 temp.func = musbotg_host_ctrl_status_tx;
2605 temp.func = musbotg_host_ctrl_status_rx;
2607 musbotg_setup_standard_chain_sub(&temp);
2610 /* must have at least one frame! */
2612 xfer->td_transfer_last = td;
2616 musbotg_timeout(void *arg)
2618 struct usb_xfer *xfer = arg;
2620 DPRINTFN(1, "xfer=%p\n", xfer);
2622 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2624 /* transfer is transferred */
2625 musbotg_device_done(xfer, USB_ERR_TIMEOUT);
2629 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
2634 * Only enable the endpoint interrupt when we are
2635 * actually waiting for data, hence we are dealing
2636 * with level triggered interrupts !
2638 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on);
2644 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2646 temp |= MUSB2_MASK_EPINT(0);
2648 temp &= ~MUSB2_MASK_EPINT(0);
2650 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2652 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
2654 temp |= MUSB2_MASK_EPINT(channel);
2656 temp &= ~MUSB2_MASK_EPINT(channel);
2657 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
2659 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2661 temp |= MUSB2_MASK_EPINT(channel);
2663 temp &= ~MUSB2_MASK_EPINT(channel);
2664 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2667 if (sc->sc_ep_int_set)
2668 sc->sc_ep_int_set(sc, channel, on);
2672 musbotg_start_standard_chain(struct usb_xfer *xfer)
2677 if (musbotg_xfer_do_fifo(xfer)) {
2679 DPRINTFN(14, "enabled interrupts on endpoint\n");
2681 /* put transfer on interrupt queue */
2682 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2684 /* start timeout, if any */
2685 if (xfer->timeout != 0) {
2686 usbd_transfer_timeout_ms(xfer,
2687 &musbotg_timeout, xfer->timeout);
2693 musbotg_root_intr(struct musbotg_softc *sc)
2697 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2700 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
2702 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2703 sizeof(sc->sc_hub_idata));
2707 musbotg_standard_done_sub(struct usb_xfer *xfer)
2709 struct musbotg_td *td;
2715 td = xfer->td_transfer_cache;
2718 len = td->remainder;
2720 xfer->endpoint->toggle_next = td->toggle;
2722 if (xfer->aframes != xfer->nframes) {
2724 * Verify the length and subtract
2725 * the remainder from "frlengths[]":
2727 if (len > xfer->frlengths[xfer->aframes]) {
2730 xfer->frlengths[xfer->aframes] -= len;
2733 /* Check for transfer error */
2735 /* the transfer is finished */
2740 /* Check for short transfer */
2742 if (xfer->flags_int.short_frames_ok ||
2743 xfer->flags_int.isochronous_xfr) {
2744 /* follow alt next */
2751 /* the transfer is finished */
2759 /* this USB frame is complete */
2765 /* update transfer cache */
2767 xfer->td_transfer_cache = td;
2770 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
2774 musbotg_standard_done(struct usb_xfer *xfer)
2776 usb_error_t err = 0;
2778 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
2779 xfer, xfer->endpoint);
2783 xfer->td_transfer_cache = xfer->td_transfer_first;
2785 if (xfer->flags_int.control_xfr) {
2787 if (xfer->flags_int.control_hdr) {
2789 err = musbotg_standard_done_sub(xfer);
2793 if (xfer->td_transfer_cache == NULL) {
2797 while (xfer->aframes != xfer->nframes) {
2799 err = musbotg_standard_done_sub(xfer);
2802 if (xfer->td_transfer_cache == NULL) {
2807 if (xfer->flags_int.control_xfr &&
2808 !xfer->flags_int.control_act) {
2810 err = musbotg_standard_done_sub(xfer);
2813 musbotg_device_done(xfer, err);
2816 /*------------------------------------------------------------------------*
2817 * musbotg_device_done
2819 * NOTE: this function can be called more than one time on the
2820 * same USB transfer!
2821 *------------------------------------------------------------------------*/
2823 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
2825 struct musbotg_td *td;
2826 struct musbotg_softc *sc;
2828 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2830 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n",
2831 xfer, xfer->endpoint, error);
2833 DPRINTFN(14, "disabled interrupts on endpoint\n");
2835 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2836 td = xfer->td_transfer_cache;
2838 if (td && (td->channel != -1))
2839 musbotg_channel_free(sc, td);
2841 /* dequeue transfer and start next transfer */
2842 usbd_transfer_done(xfer, error);
2846 musbotg_xfer_stall(struct usb_xfer *xfer)
2848 musbotg_device_done(xfer, USB_ERR_STALLED);
2852 musbotg_set_stall(struct usb_device *udev,
2853 struct usb_endpoint *ep, uint8_t *did_stall)
2855 struct musbotg_softc *sc;
2858 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2860 DPRINTFN(4, "endpoint=%p\n", ep);
2862 /* set FORCESTALL */
2863 sc = MUSBOTG_BUS2SC(udev->bus);
2865 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2867 /* select endpoint */
2868 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2870 if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
2871 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2872 MUSB2_MASK_CSRL_TXSENDSTALL);
2874 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2875 MUSB2_MASK_CSRL_RXSENDSTALL);
2880 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
2881 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2887 if (ep_type == UE_CONTROL) {
2888 /* clearing stall is not needed */
2891 /* select endpoint */
2892 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2894 /* compute max frame size */
2895 mps = wMaxPacket & 0x7FF;
2896 switch ((wMaxPacket >> 11) & 3) {
2907 if (ep_dir == UE_DIR_IN) {
2911 /* Configure endpoint */
2914 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2915 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2916 MUSB2_MASK_CSRH_TXMODE | temp);
2918 case UE_ISOCHRONOUS:
2919 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2920 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2921 MUSB2_MASK_CSRH_TXMODE |
2922 MUSB2_MASK_CSRH_TXISO | temp);
2925 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2926 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2927 MUSB2_MASK_CSRH_TXMODE | temp);
2933 /* Need to flush twice in case of double bufring */
2934 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2935 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2936 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2937 MUSB2_MASK_CSRL_TXFFLUSH);
2938 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2939 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2940 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2941 MUSB2_MASK_CSRL_TXFFLUSH);
2942 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2945 /* reset data toggle */
2946 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2947 MUSB2_MASK_CSRL_TXDT_CLR);
2948 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2949 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2951 /* set double/single buffering */
2952 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
2953 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2954 max_in_frame_size / 2)) {
2956 temp &= ~(1 << ep_no);
2959 temp |= (1 << ep_no);
2961 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
2963 /* clear sent stall */
2964 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
2965 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2966 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2972 /* Configure endpoint */
2975 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2976 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2977 MUSB2_MASK_CSRH_RXNYET | temp);
2979 case UE_ISOCHRONOUS:
2980 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2981 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2982 MUSB2_MASK_CSRH_RXNYET |
2983 MUSB2_MASK_CSRH_RXISO | temp);
2986 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2987 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
2993 /* Need to flush twice in case of double bufring */
2994 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2995 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2996 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2997 MUSB2_MASK_CSRL_RXFFLUSH);
2998 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2999 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
3000 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
3001 MUSB2_MASK_CSRL_RXFFLUSH);
3002 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3005 /* reset data toggle */
3006 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
3007 MUSB2_MASK_CSRL_RXDT_CLR);
3008 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3009 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3011 /* set double/single buffering */
3012 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
3013 if (mps <= (sc->sc_hw_ep_profile[ep_no].
3014 max_out_frame_size / 2)) {
3016 temp &= ~(1 << ep_no);
3019 temp |= (1 << ep_no);
3021 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
3023 /* clear sent stall */
3024 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
3025 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3031 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3033 struct musbotg_softc *sc;
3034 struct usb_endpoint_descriptor *ed;
3036 DPRINTFN(4, "endpoint=%p\n", ep);
3038 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3041 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3046 sc = MUSBOTG_BUS2SC(udev->bus);
3048 /* get endpoint descriptor */
3051 /* reset endpoint */
3052 musbotg_clear_stall_sub(sc,
3053 UGETW(ed->wMaxPacketSize),
3054 (ed->bEndpointAddress & UE_ADDR),
3055 (ed->bmAttributes & UE_XFERTYPE),
3056 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3060 musbotg_init(struct musbotg_softc *sc)
3062 struct usb_hw_ep_profile *pf;
3072 DPRINTFN(1, "start\n");
3074 /* set up the bus structure */
3075 sc->sc_bus.usbrev = USB_REV_2_0;
3076 sc->sc_bus.methods = &musbotg_bus_methods;
3078 USB_BUS_LOCK(&sc->sc_bus);
3080 /* turn on clocks */
3082 if (sc->sc_clocks_on) {
3083 (sc->sc_clocks_on) (sc->sc_clocks_arg);
3086 /* wait a little for things to stabilise */
3087 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
3089 /* disable all interrupts */
3091 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3092 DPRINTF("pre-DEVCTL=0x%02x\n", temp);
3094 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3095 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3096 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3098 /* disable pullup */
3100 musbotg_pull_common(sc, 0);
3102 /* wait a little bit (10ms) */
3103 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3106 /* disable double packet buffering */
3107 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
3108 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
3110 /* enable HighSpeed and ISO Update flags */
3112 MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
3113 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
3115 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3116 /* clear Session bit, if set */
3117 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3118 temp &= ~MUSB2_MASK_SESS;
3119 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3121 /* Enter session for Host mode */
3122 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3123 temp |= MUSB2_MASK_SESS;
3124 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3127 /* wait a little for things to stabilise */
3128 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
3130 DPRINTF("DEVCTL=0x%02x\n", temp);
3132 /* disable testmode */
3134 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
3136 /* set default value */
3138 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
3140 /* select endpoint index 0 */
3142 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
3144 /* read out number of endpoints */
3147 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
3150 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
3152 /* these numbers exclude the control endpoint */
3154 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
3156 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
3157 if (sc->sc_ep_max == 0) {
3158 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
3160 /* read out configuration data */
3162 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
3164 DPRINTFN(2, "Config Data: 0x%02x\n",
3167 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
3170 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
3171 "assuming 16Kbytes of FIFO RAM\n");
3174 DPRINTFN(2, "HW version: 0x%04x\n",
3175 MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
3177 /* initialise endpoint profiles */
3181 for (temp = 1; temp <= sc->sc_ep_max; temp++) {
3182 pf = sc->sc_hw_ep_profile + temp;
3184 /* select endpoint */
3185 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
3187 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
3188 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
3189 ftx = (fsize & MUSB2_MASK_TX_FSIZE);
3191 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
3192 temp, ftx, frx, dynfifo);
3195 if (frx && (temp <= nrx)) {
3198 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3199 MUSB2_VAL_FIFOSZ_4096 |
3201 } else if (temp < 8) {
3203 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3204 MUSB2_VAL_FIFOSZ_512 |
3207 frx = 7; /* 128 bytes */
3208 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3209 MUSB2_VAL_FIFOSZ_128);
3212 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
3215 offset += (1 << frx);
3217 if (ftx && (temp <= ntx)) {
3220 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3221 MUSB2_VAL_FIFOSZ_4096 |
3223 } else if (temp < 8) {
3225 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3226 MUSB2_VAL_FIFOSZ_512 |
3229 ftx = 7; /* 128 bytes */
3230 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3231 MUSB2_VAL_FIFOSZ_128);
3234 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
3237 offset += (1 << ftx);
3241 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
3242 pf->max_in_frame_size = 1 << ftx;
3243 pf->max_out_frame_size = 1 << frx;
3244 pf->is_simplex = 0; /* duplex */
3245 pf->support_multi_buffer = 1;
3246 pf->support_bulk = 1;
3247 pf->support_interrupt = 1;
3248 pf->support_isochronous = 1;
3250 pf->support_out = 1;
3251 } else if (frx && (temp <= nrx)) {
3252 pf->max_out_frame_size = 1 << frx;
3253 pf->max_in_frame_size = 0;
3254 pf->is_simplex = 1; /* simplex */
3255 pf->support_multi_buffer = 1;
3256 pf->support_bulk = 1;
3257 pf->support_interrupt = 1;
3258 pf->support_isochronous = 1;
3259 pf->support_out = 1;
3260 } else if (ftx && (temp <= ntx)) {
3261 pf->max_in_frame_size = 1 << ftx;
3262 pf->max_out_frame_size = 0;
3263 pf->is_simplex = 1; /* simplex */
3264 pf->support_multi_buffer = 1;
3265 pf->support_bulk = 1;
3266 pf->support_interrupt = 1;
3267 pf->support_isochronous = 1;
3272 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
3274 /* turn on default interrupts */
3276 if (sc->sc_mode == MUSB2_HOST_MODE)
3277 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff);
3279 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
3282 musbotg_clocks_off(sc);
3284 USB_BUS_UNLOCK(&sc->sc_bus);
3286 /* catch any lost interrupts */
3288 musbotg_do_poll(&sc->sc_bus);
3290 return (0); /* success */
3294 musbotg_uninit(struct musbotg_softc *sc)
3296 USB_BUS_LOCK(&sc->sc_bus);
3298 /* disable all interrupts */
3299 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3300 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3301 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3303 sc->sc_flags.port_powered = 0;
3304 sc->sc_flags.status_vbus = 0;
3305 sc->sc_flags.status_bus_reset = 0;
3306 sc->sc_flags.status_suspend = 0;
3307 sc->sc_flags.change_suspend = 0;
3308 sc->sc_flags.change_connect = 1;
3310 musbotg_pull_down(sc);
3311 musbotg_clocks_off(sc);
3312 USB_BUS_UNLOCK(&sc->sc_bus);
3316 musbotg_do_poll(struct usb_bus *bus)
3318 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
3320 USB_BUS_LOCK(&sc->sc_bus);
3321 musbotg_interrupt_poll(sc);
3322 USB_BUS_UNLOCK(&sc->sc_bus);
3325 /*------------------------------------------------------------------------*
3326 * musbotg bulk support
3327 *------------------------------------------------------------------------*/
3329 musbotg_device_bulk_open(struct usb_xfer *xfer)
3335 musbotg_device_bulk_close(struct usb_xfer *xfer)
3337 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3341 musbotg_device_bulk_enter(struct usb_xfer *xfer)
3347 musbotg_device_bulk_start(struct usb_xfer *xfer)
3350 musbotg_setup_standard_chain(xfer);
3351 musbotg_start_standard_chain(xfer);
3354 static const struct usb_pipe_methods musbotg_device_bulk_methods =
3356 .open = musbotg_device_bulk_open,
3357 .close = musbotg_device_bulk_close,
3358 .enter = musbotg_device_bulk_enter,
3359 .start = musbotg_device_bulk_start,
3362 /*------------------------------------------------------------------------*
3363 * musbotg control support
3364 *------------------------------------------------------------------------*/
3366 musbotg_device_ctrl_open(struct usb_xfer *xfer)
3372 musbotg_device_ctrl_close(struct usb_xfer *xfer)
3374 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3378 musbotg_device_ctrl_enter(struct usb_xfer *xfer)
3384 musbotg_device_ctrl_start(struct usb_xfer *xfer)
3387 musbotg_setup_standard_chain(xfer);
3388 musbotg_start_standard_chain(xfer);
3391 static const struct usb_pipe_methods musbotg_device_ctrl_methods =
3393 .open = musbotg_device_ctrl_open,
3394 .close = musbotg_device_ctrl_close,
3395 .enter = musbotg_device_ctrl_enter,
3396 .start = musbotg_device_ctrl_start,
3399 /*------------------------------------------------------------------------*
3400 * musbotg interrupt support
3401 *------------------------------------------------------------------------*/
3403 musbotg_device_intr_open(struct usb_xfer *xfer)
3409 musbotg_device_intr_close(struct usb_xfer *xfer)
3411 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3415 musbotg_device_intr_enter(struct usb_xfer *xfer)
3421 musbotg_device_intr_start(struct usb_xfer *xfer)
3424 musbotg_setup_standard_chain(xfer);
3425 musbotg_start_standard_chain(xfer);
3428 static const struct usb_pipe_methods musbotg_device_intr_methods =
3430 .open = musbotg_device_intr_open,
3431 .close = musbotg_device_intr_close,
3432 .enter = musbotg_device_intr_enter,
3433 .start = musbotg_device_intr_start,
3436 /*------------------------------------------------------------------------*
3437 * musbotg full speed isochronous support
3438 *------------------------------------------------------------------------*/
3440 musbotg_device_isoc_open(struct usb_xfer *xfer)
3446 musbotg_device_isoc_close(struct usb_xfer *xfer)
3448 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3452 musbotg_device_isoc_enter(struct usb_xfer *xfer)
3454 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
3459 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
3460 xfer, xfer->endpoint->isoc_next, xfer->nframes);
3462 /* get the current frame index */
3464 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
3467 * check if the frame index is within the window where the frames
3470 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME;
3472 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
3473 fs_frames = (xfer->nframes + 7) / 8;
3475 fs_frames = xfer->nframes;
3478 if ((xfer->endpoint->is_synced == 0) ||
3479 (temp < fs_frames)) {
3481 * If there is data underflow or the pipe queue is
3482 * empty we schedule the transfer a few frames ahead
3483 * of the current frame position. Else two isochronous
3484 * transfers might overlap.
3486 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
3487 xfer->endpoint->is_synced = 1;
3488 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
3491 * compute how many milliseconds the insertion is ahead of the
3492 * current frame position:
3494 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME;
3497 * pre-compute when the isochronous transfer will be finished:
3499 xfer->isoc_time_complete =
3500 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
3503 /* compute frame number for next insertion */
3504 xfer->endpoint->isoc_next += fs_frames;
3507 musbotg_setup_standard_chain(xfer);
3511 musbotg_device_isoc_start(struct usb_xfer *xfer)
3513 /* start TD chain */
3514 musbotg_start_standard_chain(xfer);
3517 static const struct usb_pipe_methods musbotg_device_isoc_methods =
3519 .open = musbotg_device_isoc_open,
3520 .close = musbotg_device_isoc_close,
3521 .enter = musbotg_device_isoc_enter,
3522 .start = musbotg_device_isoc_start,
3525 /*------------------------------------------------------------------------*
3526 * musbotg root control support
3527 *------------------------------------------------------------------------*
3528 * Simulate a hardware HUB by handling all the necessary requests.
3529 *------------------------------------------------------------------------*/
3531 static const struct usb_device_descriptor musbotg_devd = {
3532 .bLength = sizeof(struct usb_device_descriptor),
3533 .bDescriptorType = UDESC_DEVICE,
3534 .bcdUSB = {0x00, 0x02},
3535 .bDeviceClass = UDCLASS_HUB,
3536 .bDeviceSubClass = UDSUBCLASS_HUB,
3537 .bDeviceProtocol = UDPROTO_HSHUBSTT,
3538 .bMaxPacketSize = 64,
3539 .bcdDevice = {0x00, 0x01},
3542 .bNumConfigurations = 1,
3545 static const struct usb_device_qualifier musbotg_odevd = {
3546 .bLength = sizeof(struct usb_device_qualifier),
3547 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
3548 .bcdUSB = {0x00, 0x02},
3549 .bDeviceClass = UDCLASS_HUB,
3550 .bDeviceSubClass = UDSUBCLASS_HUB,
3551 .bDeviceProtocol = UDPROTO_FSHUB,
3552 .bMaxPacketSize0 = 0,
3553 .bNumConfigurations = 0,
3556 static const struct musbotg_config_desc musbotg_confd = {
3558 .bLength = sizeof(struct usb_config_descriptor),
3559 .bDescriptorType = UDESC_CONFIG,
3560 .wTotalLength[0] = sizeof(musbotg_confd),
3562 .bConfigurationValue = 1,
3563 .iConfiguration = 0,
3564 .bmAttributes = UC_SELF_POWERED,
3568 .bLength = sizeof(struct usb_interface_descriptor),
3569 .bDescriptorType = UDESC_INTERFACE,
3571 .bInterfaceClass = UICLASS_HUB,
3572 .bInterfaceSubClass = UISUBCLASS_HUB,
3573 .bInterfaceProtocol = 0,
3576 .bLength = sizeof(struct usb_endpoint_descriptor),
3577 .bDescriptorType = UDESC_ENDPOINT,
3578 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
3579 .bmAttributes = UE_INTERRUPT,
3580 .wMaxPacketSize[0] = 8,
3585 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3587 static const struct usb_hub_descriptor_min musbotg_hubd = {
3588 .bDescLength = sizeof(musbotg_hubd),
3589 .bDescriptorType = UDESC_HUB,
3591 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
3592 .bPwrOn2PwrGood = 50,
3593 .bHubContrCurrent = 0,
3594 .DeviceRemovable = {0}, /* port is removable */
3597 #define STRING_VENDOR \
3598 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s"
3600 #define STRING_PRODUCT \
3601 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
3603 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
3604 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
3607 musbotg_roothub_exec(struct usb_device *udev,
3608 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3610 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
3618 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3621 ptr = (const void *)&sc->sc_hub_temp;
3625 value = UGETW(req->wValue);
3626 index = UGETW(req->wIndex);
3628 /* demultiplex the control request */
3630 switch (req->bmRequestType) {
3631 case UT_READ_DEVICE:
3632 switch (req->bRequest) {
3633 case UR_GET_DESCRIPTOR:
3634 goto tr_handle_get_descriptor;
3636 goto tr_handle_get_config;
3638 goto tr_handle_get_status;
3644 case UT_WRITE_DEVICE:
3645 switch (req->bRequest) {
3646 case UR_SET_ADDRESS:
3647 goto tr_handle_set_address;
3649 goto tr_handle_set_config;
3650 case UR_CLEAR_FEATURE:
3651 goto tr_valid; /* nop */
3652 case UR_SET_DESCRIPTOR:
3653 goto tr_valid; /* nop */
3654 case UR_SET_FEATURE:
3660 case UT_WRITE_ENDPOINT:
3661 switch (req->bRequest) {
3662 case UR_CLEAR_FEATURE:
3663 switch (UGETW(req->wValue)) {
3664 case UF_ENDPOINT_HALT:
3665 goto tr_handle_clear_halt;
3666 case UF_DEVICE_REMOTE_WAKEUP:
3667 goto tr_handle_clear_wakeup;
3672 case UR_SET_FEATURE:
3673 switch (UGETW(req->wValue)) {
3674 case UF_ENDPOINT_HALT:
3675 goto tr_handle_set_halt;
3676 case UF_DEVICE_REMOTE_WAKEUP:
3677 goto tr_handle_set_wakeup;
3682 case UR_SYNCH_FRAME:
3683 goto tr_valid; /* nop */
3689 case UT_READ_ENDPOINT:
3690 switch (req->bRequest) {
3692 goto tr_handle_get_ep_status;
3698 case UT_WRITE_INTERFACE:
3699 switch (req->bRequest) {
3700 case UR_SET_INTERFACE:
3701 goto tr_handle_set_interface;
3702 case UR_CLEAR_FEATURE:
3703 goto tr_valid; /* nop */
3704 case UR_SET_FEATURE:
3710 case UT_READ_INTERFACE:
3711 switch (req->bRequest) {
3712 case UR_GET_INTERFACE:
3713 goto tr_handle_get_interface;
3715 goto tr_handle_get_iface_status;
3721 case UT_WRITE_CLASS_INTERFACE:
3722 case UT_WRITE_VENDOR_INTERFACE:
3726 case UT_READ_CLASS_INTERFACE:
3727 case UT_READ_VENDOR_INTERFACE:
3731 case UT_WRITE_CLASS_DEVICE:
3732 switch (req->bRequest) {
3733 case UR_CLEAR_FEATURE:
3735 case UR_SET_DESCRIPTOR:
3736 case UR_SET_FEATURE:
3743 case UT_WRITE_CLASS_OTHER:
3744 switch (req->bRequest) {
3745 case UR_CLEAR_FEATURE:
3746 goto tr_handle_clear_port_feature;
3747 case UR_SET_FEATURE:
3748 goto tr_handle_set_port_feature;
3749 case UR_CLEAR_TT_BUFFER:
3759 case UT_READ_CLASS_OTHER:
3760 switch (req->bRequest) {
3761 case UR_GET_TT_STATE:
3762 goto tr_handle_get_tt_state;
3764 goto tr_handle_get_port_status;
3770 case UT_READ_CLASS_DEVICE:
3771 switch (req->bRequest) {
3772 case UR_GET_DESCRIPTOR:
3773 goto tr_handle_get_class_descriptor;
3775 goto tr_handle_get_class_status;
3786 tr_handle_get_descriptor:
3787 switch (value >> 8) {
3792 len = sizeof(musbotg_devd);
3793 ptr = (const void *)&musbotg_devd;
3795 case UDESC_DEVICE_QUALIFIER:
3799 len = sizeof(musbotg_odevd);
3800 ptr = (const void *)&musbotg_odevd;
3806 len = sizeof(musbotg_confd);
3807 ptr = (const void *)&musbotg_confd;
3810 switch (value & 0xff) {
3811 case 0: /* Language table */
3812 len = sizeof(usb_string_lang_en);
3813 ptr = (const void *)&usb_string_lang_en;
3816 case 1: /* Vendor */
3817 len = sizeof(musbotg_vendor);
3818 ptr = (const void *)&musbotg_vendor;
3821 case 2: /* Product */
3822 len = sizeof(musbotg_product);
3823 ptr = (const void *)&musbotg_product;
3834 tr_handle_get_config:
3836 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3839 tr_handle_get_status:
3841 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3844 tr_handle_set_address:
3845 if (value & 0xFF00) {
3848 sc->sc_rt_addr = value;
3851 tr_handle_set_config:
3855 sc->sc_conf = value;
3858 tr_handle_get_interface:
3860 sc->sc_hub_temp.wValue[0] = 0;
3863 tr_handle_get_tt_state:
3864 tr_handle_get_class_status:
3865 tr_handle_get_iface_status:
3866 tr_handle_get_ep_status:
3868 USETW(sc->sc_hub_temp.wValue, 0);
3872 tr_handle_set_interface:
3873 tr_handle_set_wakeup:
3874 tr_handle_clear_wakeup:
3875 tr_handle_clear_halt:
3878 tr_handle_clear_port_feature:
3882 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
3885 case UHF_PORT_SUSPEND:
3886 if (sc->sc_mode == MUSB2_HOST_MODE)
3887 musbotg_wakeup_host(sc);
3889 musbotg_wakeup_peer(sc);
3892 case UHF_PORT_ENABLE:
3893 sc->sc_flags.port_enabled = 0;
3896 case UHF_C_PORT_ENABLE:
3897 sc->sc_flags.change_enabled = 0;
3900 case UHF_C_PORT_OVER_CURRENT:
3901 sc->sc_flags.change_over_current = 0;
3904 case UHF_C_PORT_RESET:
3905 sc->sc_flags.change_reset = 0;
3909 case UHF_PORT_INDICATOR:
3913 case UHF_PORT_POWER:
3914 sc->sc_flags.port_powered = 0;
3915 musbotg_pull_down(sc);
3916 musbotg_clocks_off(sc);
3918 case UHF_C_PORT_CONNECTION:
3919 sc->sc_flags.change_connect = 0;
3921 case UHF_C_PORT_SUSPEND:
3922 sc->sc_flags.change_suspend = 0;
3925 err = USB_ERR_IOERROR;
3930 tr_handle_set_port_feature:
3934 DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
3937 case UHF_PORT_ENABLE:
3938 sc->sc_flags.port_enabled = 1;
3940 case UHF_PORT_SUSPEND:
3941 if (sc->sc_mode == MUSB2_HOST_MODE)
3942 musbotg_suspend_host(sc);
3945 case UHF_PORT_RESET:
3946 if (sc->sc_mode == MUSB2_HOST_MODE) {
3947 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3948 reg |= MUSB2_MASK_RESET;
3949 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3951 /* Wait for 20 msec */
3952 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5);
3954 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3955 reg &= ~MUSB2_MASK_RESET;
3956 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3958 /* determine line speed */
3959 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3960 if (reg & MUSB2_MASK_HSMODE)
3961 sc->sc_flags.status_high_speed = 1;
3963 sc->sc_flags.status_high_speed = 0;
3965 sc->sc_flags.change_reset = 1;
3967 err = USB_ERR_IOERROR;
3971 case UHF_PORT_INDICATOR:
3974 case UHF_PORT_POWER:
3975 sc->sc_flags.port_powered = 1;
3978 err = USB_ERR_IOERROR;
3983 tr_handle_get_port_status:
3985 DPRINTFN(8, "UR_GET_PORT_STATUS\n");
3990 if (sc->sc_flags.status_vbus) {
3991 musbotg_clocks_on(sc);
3992 musbotg_pull_up(sc);
3994 musbotg_pull_down(sc);
3995 musbotg_clocks_off(sc);
3998 /* Select Device Side Mode */
3999 if (sc->sc_mode == MUSB2_DEVICE_MODE)
4000 value = UPS_PORT_MODE_DEVICE;
4004 if (sc->sc_flags.status_high_speed) {
4005 value |= UPS_HIGH_SPEED;
4007 if (sc->sc_flags.port_powered) {
4008 value |= UPS_PORT_POWER;
4010 if (sc->sc_flags.port_enabled) {
4011 value |= UPS_PORT_ENABLED;
4014 if (sc->sc_flags.port_over_current)
4015 value |= UPS_OVERCURRENT_INDICATOR;
4017 if (sc->sc_flags.status_vbus &&
4018 sc->sc_flags.status_bus_reset) {
4019 value |= UPS_CURRENT_CONNECT_STATUS;
4021 if (sc->sc_flags.status_suspend) {
4022 value |= UPS_SUSPEND;
4024 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4028 if (sc->sc_flags.change_connect) {
4029 value |= UPS_C_CONNECT_STATUS;
4031 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
4032 if (sc->sc_flags.status_vbus &&
4033 sc->sc_flags.status_bus_reset) {
4034 /* reset EP0 state */
4035 sc->sc_ep0_busy = 0;
4040 if (sc->sc_flags.change_suspend)
4041 value |= UPS_C_SUSPEND;
4042 if (sc->sc_flags.change_reset)
4043 value |= UPS_C_PORT_RESET;
4044 if (sc->sc_flags.change_over_current)
4045 value |= UPS_C_OVERCURRENT_INDICATOR;
4047 USETW(sc->sc_hub_temp.ps.wPortChange, value);
4048 len = sizeof(sc->sc_hub_temp.ps);
4051 tr_handle_get_class_descriptor:
4055 ptr = (const void *)&musbotg_hubd;
4056 len = sizeof(musbotg_hubd);
4060 err = USB_ERR_STALLED;
4069 musbotg_xfer_setup(struct usb_setup_params *parm)
4071 struct musbotg_softc *sc;
4072 struct usb_xfer *xfer;
4078 sc = MUSBOTG_BUS2SC(parm->udev->bus);
4079 xfer = parm->curr_xfer;
4082 * NOTE: This driver does not use any of the parameters that
4083 * are computed from the following values. Just set some
4084 * reasonable dummies:
4086 parm->hc_max_packet_size = 0x400;
4087 parm->hc_max_frame_size = 0xc00;
4089 if ((parm->methods == &musbotg_device_isoc_methods) ||
4090 (parm->methods == &musbotg_device_intr_methods))
4091 parm->hc_max_packet_count = 3;
4093 parm->hc_max_packet_count = 1;
4095 usbd_transfer_setup_sub(parm);
4098 * compute maximum number of TDs
4100 if (parm->methods == &musbotg_device_ctrl_methods) {
4102 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
4104 } else if (parm->methods == &musbotg_device_bulk_methods) {
4106 ntd = xfer->nframes + 1 /* SYNC */ ;
4108 } else if (parm->methods == &musbotg_device_intr_methods) {
4110 ntd = xfer->nframes + 1 /* SYNC */ ;
4112 } else if (parm->methods == &musbotg_device_isoc_methods) {
4114 ntd = xfer->nframes + 1 /* SYNC */ ;
4122 * check if "usbd_transfer_setup_sub" set an error
4128 * allocate transfer descriptors
4132 ep_no = xfer->endpointno & UE_ADDR;
4135 * Check for a valid endpoint profile in USB device mode:
4137 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4138 const struct usb_hw_ep_profile *pf;
4140 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4143 /* should not happen */
4144 parm->err = USB_ERR_INVAL;
4150 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4152 for (n = 0; n != ntd; n++) {
4154 struct musbotg_td *td;
4158 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4161 td->max_frame_size = xfer->max_frame_size;
4162 td->reg_max_packet = xfer->max_packet_size |
4163 ((xfer->max_packet_count - 1) << 11);
4165 td->obj_next = last_obj;
4169 parm->size[0] += sizeof(*td);
4172 xfer->td_start[0] = last_obj;
4176 musbotg_xfer_unsetup(struct usb_xfer *xfer)
4182 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4184 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4186 if (sc->sc_mode == MUSB2_HOST_MODE)
4187 *pus = 2000; /* microseconds */
4193 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4194 struct usb_endpoint *ep)
4196 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4198 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
4200 edesc->bEndpointAddress, udev->flags.usb_mode,
4203 if (udev->device_index != sc->sc_rt_addr) {
4204 switch (edesc->bmAttributes & UE_XFERTYPE) {
4206 ep->methods = &musbotg_device_ctrl_methods;
4209 ep->methods = &musbotg_device_intr_methods;
4211 case UE_ISOCHRONOUS:
4212 ep->methods = &musbotg_device_isoc_methods;
4215 ep->methods = &musbotg_device_bulk_methods;
4225 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4227 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
4230 case USB_HW_POWER_SUSPEND:
4233 case USB_HW_POWER_SHUTDOWN:
4236 case USB_HW_POWER_RESUME:
4244 static const struct usb_bus_methods musbotg_bus_methods =
4246 .endpoint_init = &musbotg_ep_init,
4247 .get_dma_delay = &musbotg_get_dma_delay,
4248 .xfer_setup = &musbotg_xfer_setup,
4249 .xfer_unsetup = &musbotg_xfer_unsetup,
4250 .get_hw_ep_profile = &musbotg_get_hw_ep_profile,
4251 .xfer_stall = &musbotg_xfer_stall,
4252 .set_stall = &musbotg_set_stall,
4253 .clear_stall = &musbotg_clear_stall,
4254 .roothub_exec = &musbotg_roothub_exec,
4255 .xfer_poll = &musbotg_do_poll,
4256 .set_hw_power_sleep = &musbotg_set_hw_power_sleep,