3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip
33 * This file contains the driver for the Mentor Graphics Inventra USB
34 * 2.0 High Speed Dual-Role controller.
36 * NOTE: The current implementation only supports Device Side Mode!
39 #include <dev/usb/usb.h>
40 #include <dev/usb/usb_mfunc.h>
41 #include <dev/usb/usb_error.h>
43 #define USB_DEBUG_VAR musbotgdebug
45 #include <dev/usb/usb_core.h>
46 #include <dev/usb/usb_debug.h>
47 #include <dev/usb/usb_busdma.h>
48 #include <dev/usb/usb_process.h>
49 #include <dev/usb/usb_transfer.h>
50 #include <dev/usb/usb_device.h>
51 #include <dev/usb/usb_hub.h>
52 #include <dev/usb/usb_util.h>
54 #include <dev/usb/usb_controller.h>
55 #include <dev/usb/usb_bus.h>
56 #include <dev/usb/controller/musb_otg.h>
58 #define MUSBOTG_INTR_ENDPT 1
60 #define MUSBOTG_BUS2SC(bus) \
61 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \
62 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
64 #define MUSBOTG_PC2SC(pc) \
65 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
68 static int musbotgdebug = 0;
70 SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg");
71 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RW,
72 &musbotgdebug, 0, "Debug level");
77 struct usb_bus_methods musbotg_bus_methods;
78 struct usb_pipe_methods musbotg_device_bulk_methods;
79 struct usb_pipe_methods musbotg_device_ctrl_methods;
80 struct usb_pipe_methods musbotg_device_intr_methods;
81 struct usb_pipe_methods musbotg_device_isoc_methods;
83 static musbotg_cmd_t musbotg_setup_rx;
84 static musbotg_cmd_t musbotg_setup_data_rx;
85 static musbotg_cmd_t musbotg_setup_data_tx;
86 static musbotg_cmd_t musbotg_setup_status;
87 static musbotg_cmd_t musbotg_data_rx;
88 static musbotg_cmd_t musbotg_data_tx;
89 static void musbotg_device_done(struct usb_xfer *, usb_error_t);
90 static void musbotg_do_poll(struct usb_bus *);
91 static void musbotg_standard_done(struct usb_xfer *);
92 static void musbotg_interrupt_poll(struct musbotg_softc *);
93 static void musbotg_root_intr(struct musbotg_softc *);
96 * Here is a configuration that the chip supports.
98 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
101 .max_in_frame_size = 64,/* fixed */
102 .max_out_frame_size = 64, /* fixed */
104 .support_control = 1,
109 musbotg_get_hw_ep_profile(struct usb_device *udev,
110 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
112 struct musbotg_softc *sc;
114 sc = MUSBOTG_BUS2SC(udev->bus);
117 /* control endpoint */
118 *ppf = musbotg_ep_profile;
119 } else if (ep_addr <= sc->sc_ep_max) {
120 /* other endpoints */
121 *ppf = sc->sc_hw_ep_profile + ep_addr;
128 musbotg_clocks_on(struct musbotg_softc *sc)
130 if (sc->sc_flags.clocks_off &&
131 sc->sc_flags.port_powered) {
135 if (sc->sc_clocks_on) {
136 (sc->sc_clocks_on) (sc->sc_clocks_arg);
138 sc->sc_flags.clocks_off = 0;
140 /* XXX enable Transceiver */
145 musbotg_clocks_off(struct musbotg_softc *sc)
147 if (!sc->sc_flags.clocks_off) {
151 /* XXX disable Transceiver */
153 if (sc->sc_clocks_off) {
154 (sc->sc_clocks_off) (sc->sc_clocks_arg);
156 sc->sc_flags.clocks_off = 1;
161 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
165 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
167 temp |= MUSB2_MASK_SOFTC;
169 temp &= ~MUSB2_MASK_SOFTC;
171 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
175 musbotg_pull_up(struct musbotg_softc *sc)
177 /* pullup D+, if possible */
179 if (!sc->sc_flags.d_pulled_up &&
180 sc->sc_flags.port_powered) {
181 sc->sc_flags.d_pulled_up = 1;
182 musbotg_pull_common(sc, 1);
187 musbotg_pull_down(struct musbotg_softc *sc)
189 /* pulldown D+, if possible */
191 if (sc->sc_flags.d_pulled_up) {
192 sc->sc_flags.d_pulled_up = 0;
193 musbotg_pull_common(sc, 0);
198 musbotg_wakeup_peer(struct musbotg_softc *sc)
202 if (!(sc->sc_flags.status_suspend)) {
206 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
207 temp |= MUSB2_MASK_RESUME;
208 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
210 /* wait 8 milliseconds */
211 /* Wait for reset to complete. */
212 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
214 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
215 temp &= ~MUSB2_MASK_RESUME;
216 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
220 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
222 DPRINTFN(4, "addr=%d\n", addr);
224 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
228 musbotg_setup_rx(struct musbotg_td *td)
230 struct musbotg_softc *sc;
231 struct usb_device_request req;
235 /* get pointer to softc */
236 sc = MUSBOTG_PC2SC(td->pc);
238 /* select endpoint 0 */
239 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
241 /* read out FIFO status */
242 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
244 DPRINTFN(4, "csr=0x%02x\n", csr);
247 * NOTE: If DATAEND is set we should not call the
248 * callback, hence the status stage is not complete.
250 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
251 /* do not stall at this point */
253 /* wait for interrupt */
256 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
257 /* clear SENTSTALL */
258 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
259 /* get latest status */
260 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
261 /* update EP0 state */
264 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
266 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
267 MUSB2_MASK_CSR0L_SETUPEND_CLR);
268 /* get latest status */
269 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
270 /* update EP0 state */
273 if (sc->sc_ep0_busy) {
276 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
279 /* clear did stall flag */
281 /* get the packet byte count */
282 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
284 /* verify data length */
285 if (count != td->remainder) {
286 DPRINTFN(0, "Invalid SETUP packet "
287 "length, %d bytes\n", count);
288 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
289 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
292 if (count != sizeof(req)) {
293 DPRINTFN(0, "Unsupported SETUP packet "
294 "length, %d bytes\n", count);
295 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
296 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
300 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
301 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
303 /* copy data into real buffer */
304 usb2_copy_in(td->pc, 0, &req, sizeof(req));
306 td->offset = sizeof(req);
309 /* set pending command */
310 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
312 /* we need set stall or dataend after this */
315 /* sneak peek the set address */
316 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
317 (req.bRequest == UR_SET_ADDRESS)) {
318 sc->sc_dv_addr = req.wValue[0] & 0x7F;
320 sc->sc_dv_addr = 0xFF;
322 return (0); /* complete */
325 /* abort any ongoing transfer */
326 if (!td->did_stall) {
327 DPRINTFN(4, "stalling\n");
328 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
329 MUSB2_MASK_CSR0L_SENDSTALL);
332 return (1); /* not complete */
335 /* Control endpoint only data handling functions (RX/TX/SYNC) */
338 musbotg_setup_data_rx(struct musbotg_td *td)
340 struct usb_page_search buf_res;
341 struct musbotg_softc *sc;
346 /* get pointer to softc */
347 sc = MUSBOTG_PC2SC(td->pc);
349 /* select endpoint 0 */
350 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
352 /* check if a command is pending */
353 if (sc->sc_ep0_cmd) {
354 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
357 /* read out FIFO status */
358 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
360 DPRINTFN(4, "csr=0x%02x\n", csr);
364 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
365 MUSB2_MASK_CSR0L_SENTSTALL)) {
366 if (td->remainder == 0) {
368 * We are actually complete and have
369 * received the next SETUP
371 DPRINTFN(4, "faking complete\n");
372 return (0); /* complete */
375 * USB Host Aborted the transfer.
378 return (0); /* complete */
380 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
381 return (1); /* not complete */
383 /* get the packet byte count */
384 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
386 /* verify the packet byte count */
387 if (count != td->max_frame_size) {
388 if (count < td->max_frame_size) {
389 /* we have a short packet */
393 /* invalid USB packet */
395 return (0); /* we are complete */
398 /* verify the packet byte count */
399 if (count > td->remainder) {
400 /* invalid USB packet */
402 return (0); /* we are complete */
407 usb2_get_page(td->pc, td->offset, &buf_res);
409 /* get correct length */
410 if (buf_res.length > count) {
411 buf_res.length = count;
413 /* check for unaligned memory address */
414 if (USB_P2U(buf_res.buffer) & 3) {
419 /* receive data 4 bytes at a time */
420 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
421 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
426 /* receive data 1 byte at a time */
427 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
429 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
431 usb2_copy_in(td->pc, td->offset,
432 sc->sc_bounce_buf, count);
434 /* update offset and remainder */
436 td->remainder -= count;
439 /* check if we can optimise */
440 if (buf_res.length >= 4) {
442 /* receive data 4 bytes at a time */
443 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
444 MUSB2_REG_EPFIFO(0), buf_res.buffer,
447 temp = buf_res.length & ~3;
449 /* update counters */
452 td->remainder -= temp;
456 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
457 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
459 /* update counters */
460 count -= buf_res.length;
461 td->offset += buf_res.length;
462 td->remainder -= buf_res.length;
465 /* check if we are complete */
466 if ((td->remainder == 0) || got_short) {
468 /* we are complete */
469 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
472 /* else need to receive a zero length packet */
474 /* write command - need more data */
475 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
476 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
477 return (1); /* not complete */
481 musbotg_setup_data_tx(struct musbotg_td *td)
483 struct usb_page_search buf_res;
484 struct musbotg_softc *sc;
488 /* get pointer to softc */
489 sc = MUSBOTG_PC2SC(td->pc);
491 /* select endpoint 0 */
492 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
494 /* check if a command is pending */
495 if (sc->sc_ep0_cmd) {
496 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
499 /* read out FIFO status */
500 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
502 DPRINTFN(4, "csr=0x%02x\n", csr);
504 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
505 MUSB2_MASK_CSR0L_SENTSTALL)) {
507 * The current transfer was aborted
511 return (0); /* complete */
513 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
514 return (1); /* not complete */
516 count = td->max_frame_size;
517 if (td->remainder < count) {
518 /* we have a short packet */
520 count = td->remainder;
525 usb2_get_page(td->pc, td->offset, &buf_res);
527 /* get correct length */
528 if (buf_res.length > count) {
529 buf_res.length = count;
531 /* check for unaligned memory address */
532 if (USB_P2U(buf_res.buffer) & 3) {
534 usb2_copy_out(td->pc, td->offset,
535 sc->sc_bounce_buf, count);
540 /* transmit data 4 bytes at a time */
541 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
542 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
547 /* receive data 1 byte at a time */
548 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
550 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
552 /* update offset and remainder */
554 td->remainder -= count;
557 /* check if we can optimise */
558 if (buf_res.length >= 4) {
560 /* transmit data 4 bytes at a time */
561 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
562 MUSB2_REG_EPFIFO(0), buf_res.buffer,
565 temp = buf_res.length & ~3;
567 /* update counters */
570 td->remainder -= temp;
574 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
575 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
577 /* update counters */
578 count -= buf_res.length;
579 td->offset += buf_res.length;
580 td->remainder -= buf_res.length;
583 /* check remainder */
584 if (td->remainder == 0) {
586 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
587 return (0); /* complete */
589 /* else we need to transmit a short packet */
592 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
593 MUSB2_MASK_CSR0L_TXPKTRDY);
595 return (1); /* not complete */
599 musbotg_setup_status(struct musbotg_td *td)
601 struct musbotg_softc *sc;
604 /* get pointer to softc */
605 sc = MUSBOTG_PC2SC(td->pc);
607 /* select endpoint 0 */
608 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
610 if (sc->sc_ep0_busy) {
612 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
613 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
616 /* read out FIFO status */
617 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
619 DPRINTFN(4, "csr=0x%02x\n", csr);
621 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
622 /* wait for interrupt */
623 return (1); /* not complete */
625 if (sc->sc_dv_addr != 0xFF) {
626 /* write function address */
627 musbotg_set_address(sc, sc->sc_dv_addr);
629 return (0); /* complete */
633 musbotg_data_rx(struct musbotg_td *td)
635 struct usb_page_search buf_res;
636 struct musbotg_softc *sc;
642 to = 8; /* don't loop forever! */
645 /* get pointer to softc */
646 sc = MUSBOTG_PC2SC(td->pc);
648 /* select endpoint */
649 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no);
652 /* read out FIFO status */
653 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
655 DPRINTFN(4, "csr=0x%02x\n", csr);
658 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
659 /* make sure we don't clear "RXPKTRDY" */
660 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
661 MUSB2_MASK_CSRL_RXPKTRDY);
664 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
665 return (1); /* not complete */
667 /* get the packet byte count */
668 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
670 DPRINTFN(4, "count=0x%04x\n", count);
673 * Check for short or invalid packet:
675 if (count != td->max_frame_size) {
676 if (count < td->max_frame_size) {
677 /* we have a short packet */
681 /* invalid USB packet */
683 return (0); /* we are complete */
686 /* verify the packet byte count */
687 if (count > td->remainder) {
688 /* invalid USB packet */
690 return (0); /* we are complete */
695 usb2_get_page(td->pc, td->offset, &buf_res);
697 /* get correct length */
698 if (buf_res.length > count) {
699 buf_res.length = count;
701 /* check for unaligned memory address */
702 if (USB_P2U(buf_res.buffer) & 3) {
707 /* receive data 4 bytes at a time */
708 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
709 MUSB2_REG_EPFIFO(td->ep_no), sc->sc_bounce_buf,
714 /* receive data 1 byte at a time */
715 bus_space_read_multi_1(sc->sc_io_tag,
716 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no),
717 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
719 usb2_copy_in(td->pc, td->offset,
720 sc->sc_bounce_buf, count);
722 /* update offset and remainder */
724 td->remainder -= count;
727 /* check if we can optimise */
728 if (buf_res.length >= 4) {
730 /* receive data 4 bytes at a time */
731 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
732 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer,
735 temp = buf_res.length & ~3;
737 /* update counters */
740 td->remainder -= temp;
744 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
745 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer,
748 /* update counters */
749 count -= buf_res.length;
750 td->offset += buf_res.length;
751 td->remainder -= buf_res.length;
754 /* clear status bits */
755 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
757 /* check if we are complete */
758 if ((td->remainder == 0) || got_short) {
760 /* we are complete */
763 /* else need to receive a zero length packet */
768 return (1); /* not complete */
772 musbotg_data_tx(struct musbotg_td *td)
774 struct usb_page_search buf_res;
775 struct musbotg_softc *sc;
780 to = 8; /* don't loop forever! */
782 /* get pointer to softc */
783 sc = MUSBOTG_PC2SC(td->pc);
785 /* select endpoint */
786 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->ep_no);
790 /* read out FIFO status */
791 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
793 DPRINTFN(4, "csr=0x%02x\n", csr);
795 if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
796 MUSB2_MASK_CSRL_TXUNDERRUN)) {
797 /* clear status bits */
798 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
800 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
801 return (1); /* not complete */
803 /* check for short packet */
804 count = td->max_frame_size;
805 if (td->remainder < count) {
806 /* we have a short packet */
808 count = td->remainder;
813 usb2_get_page(td->pc, td->offset, &buf_res);
815 /* get correct length */
816 if (buf_res.length > count) {
817 buf_res.length = count;
819 /* check for unaligned memory address */
820 if (USB_P2U(buf_res.buffer) & 3) {
822 usb2_copy_out(td->pc, td->offset,
823 sc->sc_bounce_buf, count);
828 /* transmit data 4 bytes at a time */
829 bus_space_write_multi_4(sc->sc_io_tag,
830 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->ep_no),
831 sc->sc_bounce_buf, temp / 4);
835 /* receive data 1 byte at a time */
836 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
837 MUSB2_REG_EPFIFO(td->ep_no),
838 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
840 /* update offset and remainder */
842 td->remainder -= count;
845 /* check if we can optimise */
846 if (buf_res.length >= 4) {
848 /* transmit data 4 bytes at a time */
849 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
850 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer,
853 temp = buf_res.length & ~3;
855 /* update counters */
858 td->remainder -= temp;
862 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
863 MUSB2_REG_EPFIFO(td->ep_no), buf_res.buffer,
866 /* update counters */
867 count -= buf_res.length;
868 td->offset += buf_res.length;
869 td->remainder -= buf_res.length;
873 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
874 MUSB2_MASK_CSRL_TXPKTRDY);
876 /* check remainder */
877 if (td->remainder == 0) {
879 return (0); /* complete */
881 /* else we need to transmit a short packet */
886 return (1); /* not complete */
890 musbotg_xfer_do_fifo(struct usb_xfer *xfer)
892 struct musbotg_softc *sc;
893 struct musbotg_td *td;
897 td = xfer->td_transfer_cache;
899 if ((td->func) (td)) {
900 /* operation in progress */
903 if (((void *)td) == xfer->td_transfer_last) {
908 } else if (td->remainder > 0) {
910 * We had a short transfer. If there is no alternate
911 * next, stop processing !
918 * Fetch the next transfer descriptor and transfer
919 * some flags to the next transfer descriptor
922 xfer->td_transfer_cache = td;
924 return (1); /* not complete */
927 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
929 /* compute all actual lengths */
931 musbotg_standard_done(xfer);
933 return (0); /* complete */
937 musbotg_interrupt_poll(struct musbotg_softc *sc)
939 struct usb_xfer *xfer;
942 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
943 if (!musbotg_xfer_do_fifo(xfer)) {
944 /* queue has been modified */
951 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
953 DPRINTFN(4, "vbus = %u\n", is_on);
955 USB_BUS_LOCK(&sc->sc_bus);
957 if (!sc->sc_flags.status_vbus) {
958 sc->sc_flags.status_vbus = 1;
960 /* complete root HUB interrupt endpoint */
961 musbotg_root_intr(sc);
964 if (sc->sc_flags.status_vbus) {
965 sc->sc_flags.status_vbus = 0;
966 sc->sc_flags.status_bus_reset = 0;
967 sc->sc_flags.status_suspend = 0;
968 sc->sc_flags.change_suspend = 0;
969 sc->sc_flags.change_connect = 1;
971 /* complete root HUB interrupt endpoint */
972 musbotg_root_intr(sc);
976 USB_BUS_UNLOCK(&sc->sc_bus);
980 musbotg_interrupt(struct musbotg_softc *sc)
988 USB_BUS_LOCK(&sc->sc_bus);
992 /* read all interrupt registers */
993 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
995 /* read all FIFO interrupts */
996 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
997 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
999 /* check for any bus state change interrupts */
1001 if (usb_status & (MUSB2_MASK_IRESET |
1002 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP)) {
1004 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
1006 if (usb_status & MUSB2_MASK_IRESET) {
1008 /* set correct state */
1009 sc->sc_flags.status_bus_reset = 1;
1010 sc->sc_flags.status_suspend = 0;
1011 sc->sc_flags.change_suspend = 0;
1012 sc->sc_flags.change_connect = 1;
1014 /* determine line speed */
1015 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
1016 if (temp & MUSB2_MASK_HSMODE)
1017 sc->sc_flags.status_high_speed = 1;
1019 sc->sc_flags.status_high_speed = 0;
1022 * After reset all interrupts are on and we need to
1025 temp = MUSB2_MASK_IRESET;
1026 /* disable resume interrupt */
1027 temp &= ~MUSB2_MASK_IRESUME;
1028 /* enable suspend interrupt */
1029 temp |= MUSB2_MASK_ISUSP;
1030 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
1031 /* disable TX and RX interrupts */
1032 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
1033 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
1036 * If RXRSM and RXSUSP is set at the same time we interpret
1037 * that like RESUME. Resume is set when there is at least 3
1038 * milliseconds of inactivity on the USB BUS.
1040 if (usb_status & MUSB2_MASK_IRESUME) {
1041 if (sc->sc_flags.status_suspend) {
1042 sc->sc_flags.status_suspend = 0;
1043 sc->sc_flags.change_suspend = 1;
1045 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
1046 /* disable resume interrupt */
1047 temp &= ~MUSB2_MASK_IRESUME;
1048 /* enable suspend interrupt */
1049 temp |= MUSB2_MASK_ISUSP;
1050 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
1052 } else if (usb_status & MUSB2_MASK_ISUSP) {
1053 if (!sc->sc_flags.status_suspend) {
1054 sc->sc_flags.status_suspend = 1;
1055 sc->sc_flags.change_suspend = 1;
1057 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
1058 /* disable suspend interrupt */
1059 temp &= ~MUSB2_MASK_ISUSP;
1060 /* enable resume interrupt */
1061 temp |= MUSB2_MASK_IRESUME;
1062 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
1065 /* complete root HUB interrupt endpoint */
1066 musbotg_root_intr(sc);
1068 /* check for any endpoint interrupts */
1070 if (rx_status || tx_status) {
1071 DPRINTFN(4, "real endpoint interrupt "
1072 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
1074 /* poll one time regardless of FIFO status */
1076 musbotg_interrupt_poll(sc);
1081 USB_BUS_UNLOCK(&sc->sc_bus);
1085 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
1087 struct musbotg_td *td;
1089 /* get current Transfer Descriptor */
1093 /* prepare for next TD */
1094 temp->td_next = td->obj_next;
1096 /* fill out the Transfer Descriptor */
1097 td->func = temp->func;
1099 td->offset = temp->offset;
1100 td->remainder = temp->len;
1102 td->did_stall = temp->did_stall;
1103 td->short_pkt = temp->short_pkt;
1104 td->alt_next = temp->setup_alt_next;
1108 musbotg_setup_standard_chain(struct usb_xfer *xfer)
1110 struct musbotg_std_temp temp;
1111 struct musbotg_softc *sc;
1112 struct musbotg_td *td;
1116 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1117 xfer->address, UE_GET_ADDR(xfer->endpoint),
1118 xfer->sumlen, usb2_get_speed(xfer->xroot->udev));
1120 temp.max_frame_size = xfer->max_frame_size;
1122 td = xfer->td_start[0];
1123 xfer->td_transfer_first = td;
1124 xfer->td_transfer_cache = td;
1129 temp.td_next = xfer->td_start[0];
1131 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1132 temp.did_stall = !xfer->flags_int.control_stall;
1134 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
1135 ep_no = (xfer->endpoint & UE_ADDR);
1137 /* check if we should prepend a setup message */
1139 if (xfer->flags_int.control_xfr) {
1140 if (xfer->flags_int.control_hdr) {
1142 temp.func = &musbotg_setup_rx;
1143 temp.len = xfer->frlengths[0];
1144 temp.pc = xfer->frbuffers + 0;
1145 temp.short_pkt = temp.len ? 1 : 0;
1147 musbotg_setup_standard_chain_sub(&temp);
1154 if (x != xfer->nframes) {
1155 if (xfer->endpoint & UE_DIR_IN) {
1156 if (xfer->flags_int.control_xfr)
1157 temp.func = &musbotg_setup_data_tx;
1159 temp.func = &musbotg_data_tx;
1161 if (xfer->flags_int.control_xfr)
1162 temp.func = &musbotg_setup_data_rx;
1164 temp.func = &musbotg_data_rx;
1167 /* setup "pc" pointer */
1168 temp.pc = xfer->frbuffers + x;
1170 while (x != xfer->nframes) {
1172 /* DATA0 / DATA1 message */
1174 temp.len = xfer->frlengths[x];
1178 if (x == xfer->nframes) {
1179 if (xfer->flags_int.control_xfr) {
1180 if (xfer->flags_int.control_act) {
1181 temp.setup_alt_next = 0;
1184 temp.setup_alt_next = 0;
1187 if (temp.len == 0) {
1189 /* make sure that we send an USB packet */
1195 /* regular data transfer */
1197 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1200 musbotg_setup_standard_chain_sub(&temp);
1202 if (xfer->flags_int.isochronous_xfr) {
1203 temp.offset += temp.len;
1205 /* get next Page Cache pointer */
1206 temp.pc = xfer->frbuffers + x;
1210 /* check for control transfer */
1211 if (xfer->flags_int.control_xfr) {
1213 /* always setup a valid "pc" pointer for status and sync */
1214 temp.pc = xfer->frbuffers + 0;
1217 temp.setup_alt_next = 0;
1219 /* check if we should append a status stage */
1220 if (!xfer->flags_int.control_act) {
1222 * Send a DATA1 message and invert the current
1223 * endpoint direction.
1225 temp.func = &musbotg_setup_status;
1226 musbotg_setup_standard_chain_sub(&temp);
1229 /* must have at least one frame! */
1231 xfer->td_transfer_last = td;
1235 musbotg_timeout(void *arg)
1237 struct usb_xfer *xfer = arg;
1239 DPRINTFN(1, "xfer=%p\n", xfer);
1241 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1243 /* transfer is transferred */
1244 musbotg_device_done(xfer, USB_ERR_TIMEOUT);
1248 musbotg_ep_int_set(struct usb_xfer *xfer, uint8_t on)
1250 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
1252 uint8_t ep_no = xfer->endpoint & UE_ADDR;
1255 * Only enable the endpoint interrupt when we are
1256 * actually waiting for data, hence we are dealing
1257 * with level triggered interrupts !
1260 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
1262 temp |= MUSB2_MASK_EPINT(0);
1264 temp &= ~MUSB2_MASK_EPINT(0);
1266 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
1268 if (USB_GET_DATA_ISREAD(xfer)) {
1269 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
1271 temp |= MUSB2_MASK_EPINT(ep_no);
1273 temp &= ~MUSB2_MASK_EPINT(ep_no);
1274 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
1277 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
1279 temp |= MUSB2_MASK_EPINT(ep_no);
1281 temp &= ~MUSB2_MASK_EPINT(ep_no);
1282 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
1288 musbotg_start_standard_chain(struct usb_xfer *xfer)
1293 if (musbotg_xfer_do_fifo(xfer)) {
1295 musbotg_ep_int_set(xfer, 1);
1297 DPRINTFN(14, "enabled interrupts on endpoint\n");
1299 /* put transfer on interrupt queue */
1300 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1302 /* start timeout, if any */
1303 if (xfer->timeout != 0) {
1304 usb2_transfer_timeout_ms(xfer,
1305 &musbotg_timeout, xfer->timeout);
1311 musbotg_root_intr(struct musbotg_softc *sc)
1315 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1318 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
1320 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1321 sizeof(sc->sc_hub_idata));
1325 musbotg_standard_done_sub(struct usb_xfer *xfer)
1327 struct musbotg_td *td;
1333 td = xfer->td_transfer_cache;
1336 len = td->remainder;
1338 if (xfer->aframes != xfer->nframes) {
1340 * Verify the length and subtract
1341 * the remainder from "frlengths[]":
1343 if (len > xfer->frlengths[xfer->aframes]) {
1346 xfer->frlengths[xfer->aframes] -= len;
1349 /* Check for transfer error */
1351 /* the transfer is finished */
1356 /* Check for short transfer */
1358 if (xfer->flags_int.short_frames_ok) {
1359 /* follow alt next */
1366 /* the transfer is finished */
1374 /* this USB frame is complete */
1380 /* update transfer cache */
1382 xfer->td_transfer_cache = td;
1385 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1389 musbotg_standard_done(struct usb_xfer *xfer)
1391 usb_error_t err = 0;
1393 DPRINTFN(12, "xfer=%p pipe=%p transfer done\n",
1398 xfer->td_transfer_cache = xfer->td_transfer_first;
1400 if (xfer->flags_int.control_xfr) {
1402 if (xfer->flags_int.control_hdr) {
1404 err = musbotg_standard_done_sub(xfer);
1408 if (xfer->td_transfer_cache == NULL) {
1412 while (xfer->aframes != xfer->nframes) {
1414 err = musbotg_standard_done_sub(xfer);
1417 if (xfer->td_transfer_cache == NULL) {
1422 if (xfer->flags_int.control_xfr &&
1423 !xfer->flags_int.control_act) {
1425 err = musbotg_standard_done_sub(xfer);
1428 musbotg_device_done(xfer, err);
1431 /*------------------------------------------------------------------------*
1432 * musbotg_device_done
1434 * NOTE: this function can be called more than one time on the
1435 * same USB transfer!
1436 *------------------------------------------------------------------------*/
1438 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
1440 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1442 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n",
1443 xfer, xfer->pipe, error);
1445 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1447 musbotg_ep_int_set(xfer, 0);
1449 DPRINTFN(14, "disabled interrupts on endpoint\n");
1451 /* dequeue transfer and start next transfer */
1452 usb2_transfer_done(xfer, error);
1456 musbotg_set_stall(struct usb_device *udev, struct usb_xfer *xfer,
1457 struct usb_pipe *pipe)
1459 struct musbotg_softc *sc;
1462 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1464 DPRINTFN(4, "pipe=%p\n", pipe);
1467 /* cancel any ongoing transfers */
1468 musbotg_device_done(xfer, USB_ERR_STALLED);
1470 /* set FORCESTALL */
1471 sc = MUSBOTG_BUS2SC(udev->bus);
1473 ep_no = (pipe->edesc->bEndpointAddress & UE_ADDR);
1475 /* select endpoint */
1476 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
1478 if (pipe->edesc->bEndpointAddress & UE_DIR_IN) {
1479 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1480 MUSB2_MASK_CSRL_TXSENDSTALL);
1482 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1483 MUSB2_MASK_CSRL_RXSENDSTALL);
1488 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
1489 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
1495 if (ep_type == UE_CONTROL) {
1496 /* clearing stall is not needed */
1499 /* select endpoint */
1500 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
1502 /* compute max frame size */
1503 mps = wMaxPacket & 0x7FF;
1504 switch ((wMaxPacket >> 11) & 3) {
1515 if (ep_dir == UE_DIR_IN) {
1519 /* Configure endpoint */
1522 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket);
1523 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
1524 MUSB2_MASK_CSRH_TXMODE | temp);
1526 case UE_ISOCHRONOUS:
1527 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket);
1528 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
1529 MUSB2_MASK_CSRH_TXMODE |
1530 MUSB2_MASK_CSRH_TXISO | temp);
1533 MUSB2_WRITE_1(sc, MUSB2_REG_TXMAXP, wMaxPacket);
1534 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
1535 MUSB2_MASK_CSRH_TXMODE | temp);
1541 /* Need to flush twice in case of double bufring */
1542 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1543 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1544 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1545 MUSB2_MASK_CSRL_TXFFLUSH);
1546 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1547 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1548 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1549 MUSB2_MASK_CSRL_TXFFLUSH);
1550 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1553 /* reset data toggle */
1554 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1555 MUSB2_MASK_CSRL_TXDT_CLR);
1556 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1557 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1559 /* set double/single buffering */
1560 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
1561 if (mps <= (sc->sc_hw_ep_profile[ep_no].
1562 max_in_frame_size / 2)) {
1564 temp &= ~(1 << ep_no);
1567 temp |= (1 << ep_no);
1569 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
1571 /* clear sent stall */
1572 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
1573 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1574 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1580 /* Configure endpoint */
1583 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket);
1584 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
1585 MUSB2_MASK_CSRH_RXNYET | temp);
1587 case UE_ISOCHRONOUS:
1588 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket);
1589 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
1590 MUSB2_MASK_CSRH_RXNYET |
1591 MUSB2_MASK_CSRH_RXISO | temp);
1594 MUSB2_WRITE_1(sc, MUSB2_REG_RXMAXP, wMaxPacket);
1595 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
1601 /* Need to flush twice in case of double bufring */
1602 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1603 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
1604 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1605 MUSB2_MASK_CSRL_RXFFLUSH);
1606 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1607 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
1608 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1609 MUSB2_MASK_CSRL_RXFFLUSH);
1610 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1613 /* reset data toggle */
1614 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1615 MUSB2_MASK_CSRL_RXDT_CLR);
1616 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1617 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1619 /* set double/single buffering */
1620 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
1621 if (mps <= (sc->sc_hw_ep_profile[ep_no].
1622 max_out_frame_size / 2)) {
1624 temp &= ~(1 << ep_no);
1627 temp |= (1 << ep_no);
1629 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
1631 /* clear sent stall */
1632 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
1633 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1639 musbotg_clear_stall(struct usb_device *udev, struct usb_pipe *pipe)
1641 struct musbotg_softc *sc;
1642 struct usb_endpoint_descriptor *ed;
1644 DPRINTFN(4, "pipe=%p\n", pipe);
1646 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1649 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1654 sc = MUSBOTG_BUS2SC(udev->bus);
1656 /* get endpoint descriptor */
1659 /* reset endpoint */
1660 musbotg_clear_stall_sub(sc,
1661 UGETW(ed->wMaxPacketSize),
1662 (ed->bEndpointAddress & UE_ADDR),
1663 (ed->bmAttributes & UE_XFERTYPE),
1664 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1668 musbotg_init(struct musbotg_softc *sc)
1670 struct usb_hw_ep_profile *pf;
1678 DPRINTFN(1, "start\n");
1680 /* set up the bus structure */
1681 sc->sc_bus.usbrev = USB_REV_2_0;
1682 sc->sc_bus.methods = &musbotg_bus_methods;
1684 USB_BUS_LOCK(&sc->sc_bus);
1686 /* turn on clocks */
1688 if (sc->sc_clocks_on) {
1689 (sc->sc_clocks_on) (sc->sc_clocks_arg);
1691 /* wait a little for things to stabilise */
1692 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
1694 /* disable all interrupts */
1696 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
1697 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
1698 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
1700 /* disable pullup */
1702 musbotg_pull_common(sc, 0);
1704 /* wait a little bit (10ms) */
1705 usb2_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
1707 /* disable double packet buffering */
1708 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
1709 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
1711 /* enable HighSpeed and ISO Update flags */
1713 MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
1714 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
1716 /* clear Session bit, if set */
1718 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
1719 temp &= ~MUSB2_MASK_SESS;
1720 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
1722 DPRINTF("DEVCTL=0x%02x\n", temp);
1724 /* disable testmode */
1726 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
1728 /* set default value */
1730 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
1732 /* select endpoint index 0 */
1734 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1736 /* read out number of endpoints */
1739 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
1742 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
1744 /* these numbers exclude the control endpoint */
1746 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
1748 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
1749 if (sc->sc_ep_max == 0) {
1750 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
1752 /* read out configuration data */
1754 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
1756 DPRINTFN(2, "Config Data: 0x%02x\n",
1759 DPRINTFN(2, "HW version: 0x%04x\n",
1760 MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
1762 /* initialise endpoint profiles */
1764 for (temp = 1; temp <= sc->sc_ep_max; temp++) {
1765 pf = sc->sc_hw_ep_profile + temp;
1767 /* select endpoint */
1768 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
1770 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
1771 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;;
1772 ftx = (fsize & MUSB2_MASK_TX_FSIZE);
1774 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u\n",
1775 temp, pf->max_in_frame_size,
1776 pf->max_out_frame_size);
1778 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
1779 pf->max_in_frame_size = 1 << ftx;
1780 pf->max_out_frame_size = 1 << frx;
1781 pf->is_simplex = 0; /* duplex */
1782 pf->support_multi_buffer = 1;
1783 pf->support_bulk = 1;
1784 pf->support_interrupt = 1;
1785 pf->support_isochronous = 1;
1787 pf->support_out = 1;
1788 } else if (frx && (temp <= nrx)) {
1789 pf->max_out_frame_size = 1 << frx;
1790 pf->is_simplex = 1; /* simplex */
1791 pf->support_multi_buffer = 1;
1792 pf->support_bulk = 1;
1793 pf->support_interrupt = 1;
1794 pf->support_isochronous = 1;
1795 pf->support_out = 1;
1796 } else if (ftx && (temp <= ntx)) {
1797 pf->max_in_frame_size = 1 << ftx;
1798 pf->is_simplex = 1; /* simplex */
1799 pf->support_multi_buffer = 1;
1800 pf->support_bulk = 1;
1801 pf->support_interrupt = 1;
1802 pf->support_isochronous = 1;
1807 /* turn on default interrupts */
1809 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
1812 musbotg_clocks_off(sc);
1814 USB_BUS_UNLOCK(&sc->sc_bus);
1816 /* catch any lost interrupts */
1818 musbotg_do_poll(&sc->sc_bus);
1820 return (0); /* success */
1824 musbotg_uninit(struct musbotg_softc *sc)
1826 USB_BUS_LOCK(&sc->sc_bus);
1828 /* disable all interrupts */
1829 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
1830 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
1831 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
1833 sc->sc_flags.port_powered = 0;
1834 sc->sc_flags.status_vbus = 0;
1835 sc->sc_flags.status_bus_reset = 0;
1836 sc->sc_flags.status_suspend = 0;
1837 sc->sc_flags.change_suspend = 0;
1838 sc->sc_flags.change_connect = 1;
1840 musbotg_pull_down(sc);
1841 musbotg_clocks_off(sc);
1842 USB_BUS_UNLOCK(&sc->sc_bus);
1846 musbotg_suspend(struct musbotg_softc *sc)
1852 musbotg_resume(struct musbotg_softc *sc)
1858 musbotg_do_poll(struct usb_bus *bus)
1860 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
1862 USB_BUS_LOCK(&sc->sc_bus);
1863 musbotg_interrupt_poll(sc);
1864 USB_BUS_UNLOCK(&sc->sc_bus);
1867 /*------------------------------------------------------------------------*
1868 * musbotg bulk support
1869 *------------------------------------------------------------------------*/
1871 musbotg_device_bulk_open(struct usb_xfer *xfer)
1877 musbotg_device_bulk_close(struct usb_xfer *xfer)
1879 musbotg_device_done(xfer, USB_ERR_CANCELLED);
1883 musbotg_device_bulk_enter(struct usb_xfer *xfer)
1889 musbotg_device_bulk_start(struct usb_xfer *xfer)
1892 musbotg_setup_standard_chain(xfer);
1893 musbotg_start_standard_chain(xfer);
1896 struct usb_pipe_methods musbotg_device_bulk_methods =
1898 .open = musbotg_device_bulk_open,
1899 .close = musbotg_device_bulk_close,
1900 .enter = musbotg_device_bulk_enter,
1901 .start = musbotg_device_bulk_start,
1904 /*------------------------------------------------------------------------*
1905 * musbotg control support
1906 *------------------------------------------------------------------------*/
1908 musbotg_device_ctrl_open(struct usb_xfer *xfer)
1914 musbotg_device_ctrl_close(struct usb_xfer *xfer)
1916 musbotg_device_done(xfer, USB_ERR_CANCELLED);
1920 musbotg_device_ctrl_enter(struct usb_xfer *xfer)
1926 musbotg_device_ctrl_start(struct usb_xfer *xfer)
1929 musbotg_setup_standard_chain(xfer);
1930 musbotg_start_standard_chain(xfer);
1933 struct usb_pipe_methods musbotg_device_ctrl_methods =
1935 .open = musbotg_device_ctrl_open,
1936 .close = musbotg_device_ctrl_close,
1937 .enter = musbotg_device_ctrl_enter,
1938 .start = musbotg_device_ctrl_start,
1941 /*------------------------------------------------------------------------*
1942 * musbotg interrupt support
1943 *------------------------------------------------------------------------*/
1945 musbotg_device_intr_open(struct usb_xfer *xfer)
1951 musbotg_device_intr_close(struct usb_xfer *xfer)
1953 musbotg_device_done(xfer, USB_ERR_CANCELLED);
1957 musbotg_device_intr_enter(struct usb_xfer *xfer)
1963 musbotg_device_intr_start(struct usb_xfer *xfer)
1966 musbotg_setup_standard_chain(xfer);
1967 musbotg_start_standard_chain(xfer);
1970 struct usb_pipe_methods musbotg_device_intr_methods =
1972 .open = musbotg_device_intr_open,
1973 .close = musbotg_device_intr_close,
1974 .enter = musbotg_device_intr_enter,
1975 .start = musbotg_device_intr_start,
1978 /*------------------------------------------------------------------------*
1979 * musbotg full speed isochronous support
1980 *------------------------------------------------------------------------*/
1982 musbotg_device_isoc_open(struct usb_xfer *xfer)
1988 musbotg_device_isoc_close(struct usb_xfer *xfer)
1990 musbotg_device_done(xfer, USB_ERR_CANCELLED);
1994 musbotg_device_isoc_enter(struct usb_xfer *xfer)
1996 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2001 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
2002 xfer, xfer->pipe->isoc_next, xfer->nframes);
2004 /* get the current frame index */
2006 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
2009 * check if the frame index is within the window where the frames
2012 temp = (nframes - xfer->pipe->isoc_next) & MUSB2_MASK_FRAME;
2014 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
2015 fs_frames = (xfer->nframes + 7) / 8;
2017 fs_frames = xfer->nframes;
2020 if ((xfer->pipe->is_synced == 0) ||
2021 (temp < fs_frames)) {
2023 * If there is data underflow or the pipe queue is
2024 * empty we schedule the transfer a few frames ahead
2025 * of the current frame position. Else two isochronous
2026 * transfers might overlap.
2028 xfer->pipe->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
2029 xfer->pipe->is_synced = 1;
2030 DPRINTFN(2, "start next=%d\n", xfer->pipe->isoc_next);
2033 * compute how many milliseconds the insertion is ahead of the
2034 * current frame position:
2036 temp = (xfer->pipe->isoc_next - nframes) & MUSB2_MASK_FRAME;
2039 * pre-compute when the isochronous transfer will be finished:
2041 xfer->isoc_time_complete =
2042 usb2_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2045 /* compute frame number for next insertion */
2046 xfer->pipe->isoc_next += fs_frames;
2049 musbotg_setup_standard_chain(xfer);
2053 musbotg_device_isoc_start(struct usb_xfer *xfer)
2055 /* start TD chain */
2056 musbotg_start_standard_chain(xfer);
2059 struct usb_pipe_methods musbotg_device_isoc_methods =
2061 .open = musbotg_device_isoc_open,
2062 .close = musbotg_device_isoc_close,
2063 .enter = musbotg_device_isoc_enter,
2064 .start = musbotg_device_isoc_start,
2067 /*------------------------------------------------------------------------*
2068 * musbotg root control support
2069 *------------------------------------------------------------------------*
2070 * Simulate a hardware HUB by handling all the necessary requests.
2071 *------------------------------------------------------------------------*/
2073 static const struct usb_device_descriptor musbotg_devd = {
2074 .bLength = sizeof(struct usb_device_descriptor),
2075 .bDescriptorType = UDESC_DEVICE,
2076 .bcdUSB = {0x00, 0x02},
2077 .bDeviceClass = UDCLASS_HUB,
2078 .bDeviceSubClass = UDSUBCLASS_HUB,
2079 .bDeviceProtocol = UDPROTO_HSHUBSTT,
2080 .bMaxPacketSize = 64,
2081 .bcdDevice = {0x00, 0x01},
2084 .bNumConfigurations = 1,
2087 static const struct usb_device_qualifier musbotg_odevd = {
2088 .bLength = sizeof(struct usb_device_qualifier),
2089 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
2090 .bcdUSB = {0x00, 0x02},
2091 .bDeviceClass = UDCLASS_HUB,
2092 .bDeviceSubClass = UDSUBCLASS_HUB,
2093 .bDeviceProtocol = UDPROTO_FSHUB,
2094 .bMaxPacketSize0 = 0,
2095 .bNumConfigurations = 0,
2098 static const struct musbotg_config_desc musbotg_confd = {
2100 .bLength = sizeof(struct usb_config_descriptor),
2101 .bDescriptorType = UDESC_CONFIG,
2102 .wTotalLength[0] = sizeof(musbotg_confd),
2104 .bConfigurationValue = 1,
2105 .iConfiguration = 0,
2106 .bmAttributes = UC_SELF_POWERED,
2110 .bLength = sizeof(struct usb_interface_descriptor),
2111 .bDescriptorType = UDESC_INTERFACE,
2113 .bInterfaceClass = UICLASS_HUB,
2114 .bInterfaceSubClass = UISUBCLASS_HUB,
2115 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
2118 .bLength = sizeof(struct usb_endpoint_descriptor),
2119 .bDescriptorType = UDESC_ENDPOINT,
2120 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
2121 .bmAttributes = UE_INTERRUPT,
2122 .wMaxPacketSize[0] = 8,
2127 static const struct usb_hub_descriptor_min musbotg_hubd = {
2128 .bDescLength = sizeof(musbotg_hubd),
2129 .bDescriptorType = UDESC_HUB,
2131 .wHubCharacteristics[0] =
2132 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) & 0xFF,
2133 .wHubCharacteristics[1] =
2134 (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL) >> 16,
2135 .bPwrOn2PwrGood = 50,
2136 .bHubContrCurrent = 0,
2137 .DeviceRemovable = {0}, /* port is removable */
2140 #define STRING_LANG \
2141 0x09, 0x04, /* American English */
2143 #define STRING_VENDOR \
2144 'M', 0, 'e', 0, 'n', 0, 't', 0, 'o', 0, 'r', 0, ' ', 0, \
2145 'G', 0, 'r', 0, 'a', 0, 'p', 0, 'h', 0, 'i', 0, 'c', 0, 's', 0
2147 #define STRING_PRODUCT \
2148 'O', 0, 'T', 0, 'G', 0, ' ', 0, 'R', 0, \
2149 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \
2152 USB_MAKE_STRING_DESC(STRING_LANG, musbotg_langtab);
2153 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
2154 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
2157 musbotg_roothub_exec(struct usb_device *udev,
2158 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2160 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
2167 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2170 ptr = (const void *)&sc->sc_hub_temp;
2174 value = UGETW(req->wValue);
2175 index = UGETW(req->wIndex);
2177 /* demultiplex the control request */
2179 switch (req->bmRequestType) {
2180 case UT_READ_DEVICE:
2181 switch (req->bRequest) {
2182 case UR_GET_DESCRIPTOR:
2183 goto tr_handle_get_descriptor;
2185 goto tr_handle_get_config;
2187 goto tr_handle_get_status;
2193 case UT_WRITE_DEVICE:
2194 switch (req->bRequest) {
2195 case UR_SET_ADDRESS:
2196 goto tr_handle_set_address;
2198 goto tr_handle_set_config;
2199 case UR_CLEAR_FEATURE:
2200 goto tr_valid; /* nop */
2201 case UR_SET_DESCRIPTOR:
2202 goto tr_valid; /* nop */
2203 case UR_SET_FEATURE:
2209 case UT_WRITE_ENDPOINT:
2210 switch (req->bRequest) {
2211 case UR_CLEAR_FEATURE:
2212 switch (UGETW(req->wValue)) {
2213 case UF_ENDPOINT_HALT:
2214 goto tr_handle_clear_halt;
2215 case UF_DEVICE_REMOTE_WAKEUP:
2216 goto tr_handle_clear_wakeup;
2221 case UR_SET_FEATURE:
2222 switch (UGETW(req->wValue)) {
2223 case UF_ENDPOINT_HALT:
2224 goto tr_handle_set_halt;
2225 case UF_DEVICE_REMOTE_WAKEUP:
2226 goto tr_handle_set_wakeup;
2231 case UR_SYNCH_FRAME:
2232 goto tr_valid; /* nop */
2238 case UT_READ_ENDPOINT:
2239 switch (req->bRequest) {
2241 goto tr_handle_get_ep_status;
2247 case UT_WRITE_INTERFACE:
2248 switch (req->bRequest) {
2249 case UR_SET_INTERFACE:
2250 goto tr_handle_set_interface;
2251 case UR_CLEAR_FEATURE:
2252 goto tr_valid; /* nop */
2253 case UR_SET_FEATURE:
2259 case UT_READ_INTERFACE:
2260 switch (req->bRequest) {
2261 case UR_GET_INTERFACE:
2262 goto tr_handle_get_interface;
2264 goto tr_handle_get_iface_status;
2270 case UT_WRITE_CLASS_INTERFACE:
2271 case UT_WRITE_VENDOR_INTERFACE:
2275 case UT_READ_CLASS_INTERFACE:
2276 case UT_READ_VENDOR_INTERFACE:
2280 case UT_WRITE_CLASS_DEVICE:
2281 switch (req->bRequest) {
2282 case UR_CLEAR_FEATURE:
2284 case UR_SET_DESCRIPTOR:
2285 case UR_SET_FEATURE:
2292 case UT_WRITE_CLASS_OTHER:
2293 switch (req->bRequest) {
2294 case UR_CLEAR_FEATURE:
2295 goto tr_handle_clear_port_feature;
2296 case UR_SET_FEATURE:
2297 goto tr_handle_set_port_feature;
2298 case UR_CLEAR_TT_BUFFER:
2308 case UT_READ_CLASS_OTHER:
2309 switch (req->bRequest) {
2310 case UR_GET_TT_STATE:
2311 goto tr_handle_get_tt_state;
2313 goto tr_handle_get_port_status;
2319 case UT_READ_CLASS_DEVICE:
2320 switch (req->bRequest) {
2321 case UR_GET_DESCRIPTOR:
2322 goto tr_handle_get_class_descriptor;
2324 goto tr_handle_get_class_status;
2335 tr_handle_get_descriptor:
2336 switch (value >> 8) {
2341 len = sizeof(musbotg_devd);
2342 ptr = (const void *)&musbotg_devd;
2348 len = sizeof(musbotg_confd);
2349 ptr = (const void *)&musbotg_confd;
2352 switch (value & 0xff) {
2353 case 0: /* Language table */
2354 len = sizeof(musbotg_langtab);
2355 ptr = (const void *)&musbotg_langtab;
2358 case 1: /* Vendor */
2359 len = sizeof(musbotg_vendor);
2360 ptr = (const void *)&musbotg_vendor;
2363 case 2: /* Product */
2364 len = sizeof(musbotg_product);
2365 ptr = (const void *)&musbotg_product;
2376 tr_handle_get_config:
2378 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
2381 tr_handle_get_status:
2383 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
2386 tr_handle_set_address:
2387 if (value & 0xFF00) {
2390 sc->sc_rt_addr = value;
2393 tr_handle_set_config:
2397 sc->sc_conf = value;
2400 tr_handle_get_interface:
2402 sc->sc_hub_temp.wValue[0] = 0;
2405 tr_handle_get_tt_state:
2406 tr_handle_get_class_status:
2407 tr_handle_get_iface_status:
2408 tr_handle_get_ep_status:
2410 USETW(sc->sc_hub_temp.wValue, 0);
2414 tr_handle_set_interface:
2415 tr_handle_set_wakeup:
2416 tr_handle_clear_wakeup:
2417 tr_handle_clear_halt:
2420 tr_handle_clear_port_feature:
2424 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
2427 case UHF_PORT_SUSPEND:
2428 musbotg_wakeup_peer(sc);
2431 case UHF_PORT_ENABLE:
2432 sc->sc_flags.port_enabled = 0;
2436 case UHF_PORT_INDICATOR:
2437 case UHF_C_PORT_ENABLE:
2438 case UHF_C_PORT_OVER_CURRENT:
2439 case UHF_C_PORT_RESET:
2442 case UHF_PORT_POWER:
2443 sc->sc_flags.port_powered = 0;
2444 musbotg_pull_down(sc);
2445 musbotg_clocks_off(sc);
2447 case UHF_C_PORT_CONNECTION:
2448 sc->sc_flags.change_connect = 0;
2450 case UHF_C_PORT_SUSPEND:
2451 sc->sc_flags.change_suspend = 0;
2454 err = USB_ERR_IOERROR;
2459 tr_handle_set_port_feature:
2463 DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
2466 case UHF_PORT_ENABLE:
2467 sc->sc_flags.port_enabled = 1;
2469 case UHF_PORT_SUSPEND:
2470 case UHF_PORT_RESET:
2472 case UHF_PORT_INDICATOR:
2475 case UHF_PORT_POWER:
2476 sc->sc_flags.port_powered = 1;
2479 err = USB_ERR_IOERROR;
2484 tr_handle_get_port_status:
2486 DPRINTFN(8, "UR_GET_PORT_STATUS\n");
2491 if (sc->sc_flags.status_vbus) {
2492 musbotg_clocks_on(sc);
2493 musbotg_pull_up(sc);
2495 musbotg_pull_down(sc);
2496 musbotg_clocks_off(sc);
2499 /* Select Device Side Mode */
2500 value = UPS_PORT_MODE_DEVICE;
2502 if (sc->sc_flags.status_high_speed) {
2503 value |= UPS_HIGH_SPEED;
2505 if (sc->sc_flags.port_powered) {
2506 value |= UPS_PORT_POWER;
2508 if (sc->sc_flags.port_enabled) {
2509 value |= UPS_PORT_ENABLED;
2511 if (sc->sc_flags.status_vbus &&
2512 sc->sc_flags.status_bus_reset) {
2513 value |= UPS_CURRENT_CONNECT_STATUS;
2515 if (sc->sc_flags.status_suspend) {
2516 value |= UPS_SUSPEND;
2518 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
2522 if (sc->sc_flags.change_connect) {
2523 value |= UPS_C_CONNECT_STATUS;
2525 if (sc->sc_flags.status_vbus &&
2526 sc->sc_flags.status_bus_reset) {
2527 /* reset EP0 state */
2528 sc->sc_ep0_busy = 0;
2532 if (sc->sc_flags.change_suspend) {
2533 value |= UPS_C_SUSPEND;
2535 USETW(sc->sc_hub_temp.ps.wPortChange, value);
2536 len = sizeof(sc->sc_hub_temp.ps);
2539 tr_handle_get_class_descriptor:
2543 ptr = (const void *)&musbotg_hubd;
2544 len = sizeof(musbotg_hubd);
2548 err = USB_ERR_STALLED;
2557 musbotg_xfer_setup(struct usb_setup_params *parm)
2559 const struct usb_hw_ep_profile *pf;
2560 struct musbotg_softc *sc;
2561 struct usb_xfer *xfer;
2567 sc = MUSBOTG_BUS2SC(parm->udev->bus);
2568 xfer = parm->curr_xfer;
2571 * NOTE: This driver does not use any of the parameters that
2572 * are computed from the following values. Just set some
2573 * reasonable dummies:
2575 parm->hc_max_packet_size = 0x400;
2576 parm->hc_max_frame_size = 0x400;
2578 if ((parm->methods == &musbotg_device_isoc_methods) ||
2579 (parm->methods == &musbotg_device_intr_methods))
2580 parm->hc_max_packet_count = 3;
2582 parm->hc_max_packet_count = 1;
2584 usb2_transfer_setup_sub(parm);
2587 * compute maximum number of TDs
2589 if (parm->methods == &musbotg_device_ctrl_methods) {
2591 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
2593 } else if (parm->methods == &musbotg_device_bulk_methods) {
2595 ntd = xfer->nframes + 1 /* SYNC */ ;
2597 } else if (parm->methods == &musbotg_device_intr_methods) {
2599 ntd = xfer->nframes + 1 /* SYNC */ ;
2601 } else if (parm->methods == &musbotg_device_isoc_methods) {
2603 ntd = xfer->nframes + 1 /* SYNC */ ;
2611 * check if "usb2_transfer_setup_sub" set an error
2617 * allocate transfer descriptors
2626 ep_no = xfer->endpoint & UE_ADDR;
2627 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
2630 /* should not happen */
2631 parm->err = USB_ERR_INVAL;
2640 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2642 for (n = 0; n != ntd; n++) {
2644 struct musbotg_td *td;
2648 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2651 td->max_frame_size = xfer->max_frame_size;
2653 td->obj_next = last_obj;
2657 parm->size[0] += sizeof(*td);
2660 xfer->td_start[0] = last_obj;
2664 musbotg_xfer_unsetup(struct usb_xfer *xfer)
2670 musbotg_pipe_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2671 struct usb_pipe *pipe)
2673 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
2675 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2676 pipe, udev->address,
2677 edesc->bEndpointAddress, udev->flags.usb_mode,
2680 if (udev->device_index != sc->sc_rt_addr) {
2682 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2686 if ((udev->speed != USB_SPEED_FULL) &&
2687 (udev->speed != USB_SPEED_HIGH)) {
2691 switch (edesc->bmAttributes & UE_XFERTYPE) {
2693 pipe->methods = &musbotg_device_ctrl_methods;
2696 pipe->methods = &musbotg_device_intr_methods;
2698 case UE_ISOCHRONOUS:
2699 pipe->methods = &musbotg_device_isoc_methods;
2702 pipe->methods = &musbotg_device_bulk_methods;
2711 struct usb_bus_methods musbotg_bus_methods =
2713 .pipe_init = &musbotg_pipe_init,
2714 .xfer_setup = &musbotg_xfer_setup,
2715 .xfer_unsetup = &musbotg_xfer_unsetup,
2716 .get_hw_ep_profile = &musbotg_get_hw_ep_profile,
2717 .set_stall = &musbotg_set_stall,
2718 .clear_stall = &musbotg_clear_stall,
2719 .roothub_exec = &musbotg_roothub_exec,