3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Thanks to Mentor Graphics for providing a reference driver for this USB chip
33 * This file contains the driver for the Mentor Graphics Inventra USB
34 * 2.0 High Speed Dual-Role controller.
38 #ifdef USB_GLOBAL_INCLUDE_FILE
39 #include USB_GLOBAL_INCLUDE_FILE
41 #include <sys/stdint.h>
42 #include <sys/stddef.h>
43 #include <sys/param.h>
44 #include <sys/queue.h>
45 #include <sys/types.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
49 #include <sys/module.h>
51 #include <sys/mutex.h>
52 #include <sys/condvar.h>
53 #include <sys/sysctl.h>
55 #include <sys/unistd.h>
56 #include <sys/callout.h>
57 #include <sys/malloc.h>
60 #include <dev/usb/usb.h>
61 #include <dev/usb/usbdi.h>
63 #define USB_DEBUG_VAR musbotgdebug
65 #include <dev/usb/usb_core.h>
66 #include <dev/usb/usb_debug.h>
67 #include <dev/usb/usb_busdma.h>
68 #include <dev/usb/usb_process.h>
69 #include <dev/usb/usb_transfer.h>
70 #include <dev/usb/usb_device.h>
71 #include <dev/usb/usb_hub.h>
72 #include <dev/usb/usb_util.h>
74 #include <dev/usb/usb_controller.h>
75 #include <dev/usb/usb_bus.h>
76 #endif /* USB_GLOBAL_INCLUDE_FILE */
78 #include <dev/usb/controller/musb_otg.h>
80 #define MUSBOTG_INTR_ENDPT 1
82 #define MUSBOTG_BUS2SC(bus) \
83 ((struct musbotg_softc *)(((uint8_t *)(bus)) - \
84 USB_P2U(&(((struct musbotg_softc *)0)->sc_bus))))
86 #define MUSBOTG_PC2SC(pc) \
87 MUSBOTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
90 static int musbotgdebug = 0;
92 static SYSCTL_NODE(_hw_usb, OID_AUTO, musbotg, CTLFLAG_RW, 0, "USB musbotg");
93 SYSCTL_INT(_hw_usb_musbotg, OID_AUTO, debug, CTLFLAG_RWTUN,
94 &musbotgdebug, 0, "Debug level");
101 static const struct usb_bus_methods musbotg_bus_methods;
102 static const struct usb_pipe_methods musbotg_device_bulk_methods;
103 static const struct usb_pipe_methods musbotg_device_ctrl_methods;
104 static const struct usb_pipe_methods musbotg_device_intr_methods;
105 static const struct usb_pipe_methods musbotg_device_isoc_methods;
107 /* Control transfers: Device mode */
108 static musbotg_cmd_t musbotg_dev_ctrl_setup_rx;
109 static musbotg_cmd_t musbotg_dev_ctrl_data_rx;
110 static musbotg_cmd_t musbotg_dev_ctrl_data_tx;
111 static musbotg_cmd_t musbotg_dev_ctrl_status;
113 /* Control transfers: Host mode */
114 static musbotg_cmd_t musbotg_host_ctrl_setup_tx;
115 static musbotg_cmd_t musbotg_host_ctrl_data_rx;
116 static musbotg_cmd_t musbotg_host_ctrl_data_tx;
117 static musbotg_cmd_t musbotg_host_ctrl_status_rx;
118 static musbotg_cmd_t musbotg_host_ctrl_status_tx;
120 /* Bulk, Interrupt, Isochronous: Device mode */
121 static musbotg_cmd_t musbotg_dev_data_rx;
122 static musbotg_cmd_t musbotg_dev_data_tx;
124 /* Bulk, Interrupt, Isochronous: Host mode */
125 static musbotg_cmd_t musbotg_host_data_rx;
126 static musbotg_cmd_t musbotg_host_data_tx;
128 static void musbotg_device_done(struct usb_xfer *, usb_error_t);
129 static void musbotg_do_poll(struct usb_bus *);
130 static void musbotg_standard_done(struct usb_xfer *);
131 static void musbotg_interrupt_poll(struct musbotg_softc *);
132 static void musbotg_root_intr(struct musbotg_softc *);
133 static int musbotg_channel_alloc(struct musbotg_softc *, struct musbotg_td *td, uint8_t);
134 static void musbotg_channel_free(struct musbotg_softc *, struct musbotg_td *td);
135 static void musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on);
138 * Here is a configuration that the chip supports.
140 static const struct usb_hw_ep_profile musbotg_ep_profile[1] = {
143 .max_in_frame_size = 64,/* fixed */
144 .max_out_frame_size = 64, /* fixed */
146 .support_control = 1,
151 musbotg_channel_alloc(struct musbotg_softc *sc, struct musbotg_td *td, uint8_t is_tx)
158 /* In device mode each EP got its own channel */
159 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
160 musbotg_ep_int_set(sc, ep, 1);
165 * All control transactions go through EP0
168 if (sc->sc_channel_mask & (1 << 0))
170 sc->sc_channel_mask |= (1 << 0);
171 musbotg_ep_int_set(sc, ep, 1);
175 for (ch = sc->sc_ep_max; ch != 0; ch--) {
176 if (sc->sc_channel_mask & (1 << ch))
179 /* check FIFO size requirement */
181 if (td->max_frame_size >
182 sc->sc_hw_ep_profile[ch].max_in_frame_size)
185 if (td->max_frame_size >
186 sc->sc_hw_ep_profile[ch].max_out_frame_size)
189 sc->sc_channel_mask |= (1 << ch);
190 musbotg_ep_int_set(sc, ch, 1);
194 DPRINTFN(-1, "No available channels. Mask: %04x\n", sc->sc_channel_mask);
200 musbotg_channel_free(struct musbotg_softc *sc, struct musbotg_td *td)
203 DPRINTFN(1, "ep_no=%d\n", td->channel);
205 if (sc->sc_mode == MUSB2_DEVICE_MODE)
210 if (td->channel == -1)
213 musbotg_ep_int_set(sc, td->channel, 0);
214 sc->sc_channel_mask &= ~(1 << td->channel);
220 musbotg_get_hw_ep_profile(struct usb_device *udev,
221 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
223 struct musbotg_softc *sc;
225 sc = MUSBOTG_BUS2SC(udev->bus);
228 /* control endpoint */
229 *ppf = musbotg_ep_profile;
230 } else if (ep_addr <= sc->sc_ep_max) {
231 /* other endpoints */
232 *ppf = sc->sc_hw_ep_profile + ep_addr;
239 musbotg_clocks_on(struct musbotg_softc *sc)
241 if (sc->sc_flags.clocks_off &&
242 sc->sc_flags.port_powered) {
246 if (sc->sc_clocks_on) {
247 (sc->sc_clocks_on) (sc->sc_clocks_arg);
249 sc->sc_flags.clocks_off = 0;
251 /* XXX enable Transceiver */
256 musbotg_clocks_off(struct musbotg_softc *sc)
258 if (!sc->sc_flags.clocks_off) {
262 /* XXX disable Transceiver */
264 if (sc->sc_clocks_off) {
265 (sc->sc_clocks_off) (sc->sc_clocks_arg);
267 sc->sc_flags.clocks_off = 1;
272 musbotg_pull_common(struct musbotg_softc *sc, uint8_t on)
276 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
278 temp |= MUSB2_MASK_SOFTC;
280 temp &= ~MUSB2_MASK_SOFTC;
282 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
286 musbotg_pull_up(struct musbotg_softc *sc)
288 /* pullup D+, if possible */
290 if (!sc->sc_flags.d_pulled_up &&
291 sc->sc_flags.port_powered) {
292 sc->sc_flags.d_pulled_up = 1;
293 musbotg_pull_common(sc, 1);
298 musbotg_pull_down(struct musbotg_softc *sc)
300 /* pulldown D+, if possible */
302 if (sc->sc_flags.d_pulled_up) {
303 sc->sc_flags.d_pulled_up = 0;
304 musbotg_pull_common(sc, 0);
309 musbotg_suspend_host(struct musbotg_softc *sc)
313 if (sc->sc_flags.status_suspend) {
317 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
318 temp |= MUSB2_MASK_SUSPMODE;
319 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
320 sc->sc_flags.status_suspend = 1;
324 musbotg_wakeup_host(struct musbotg_softc *sc)
328 if (!(sc->sc_flags.status_suspend)) {
332 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
333 temp &= ~MUSB2_MASK_SUSPMODE;
334 temp |= MUSB2_MASK_RESUME;
335 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
337 /* wait 20 milliseconds */
338 /* Wait for reset to complete. */
339 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
341 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
342 temp &= ~MUSB2_MASK_RESUME;
343 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
345 sc->sc_flags.status_suspend = 0;
349 musbotg_wakeup_peer(struct musbotg_softc *sc)
353 if (!(sc->sc_flags.status_suspend)) {
357 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
358 temp |= MUSB2_MASK_RESUME;
359 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
361 /* wait 8 milliseconds */
362 /* Wait for reset to complete. */
363 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
365 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
366 temp &= ~MUSB2_MASK_RESUME;
367 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, temp);
371 musbotg_set_address(struct musbotg_softc *sc, uint8_t addr)
373 DPRINTFN(4, "addr=%d\n", addr);
375 MUSB2_WRITE_1(sc, MUSB2_REG_FADDR, addr);
379 musbotg_dev_ctrl_setup_rx(struct musbotg_td *td)
381 struct musbotg_softc *sc;
382 struct usb_device_request req;
386 /* get pointer to softc */
387 sc = MUSBOTG_PC2SC(td->pc);
389 if (td->channel == -1)
390 td->channel = musbotg_channel_alloc(sc, td, 0);
392 /* EP0 is busy, wait */
393 if (td->channel == -1)
396 DPRINTFN(1, "ep_no=%d\n", td->channel);
398 /* select endpoint 0 */
399 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
401 /* read out FIFO status */
402 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
404 DPRINTFN(4, "csr=0x%02x\n", csr);
407 * NOTE: If DATAEND is set we should not call the
408 * callback, hence the status stage is not complete.
410 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
411 /* do not stall at this point */
413 /* wait for interrupt */
414 DPRINTFN(1, "CSR0 DATAEND\n");
418 if (csr & MUSB2_MASK_CSR0L_SENTSTALL) {
419 /* clear SENTSTALL */
420 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
421 /* get latest status */
422 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
423 /* update EP0 state */
426 if (csr & MUSB2_MASK_CSR0L_SETUPEND) {
428 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
429 MUSB2_MASK_CSR0L_SETUPEND_CLR);
430 /* get latest status */
431 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
432 /* update EP0 state */
435 if (sc->sc_ep0_busy) {
436 DPRINTFN(1, "EP0 BUSY\n");
439 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
442 /* get the packet byte count */
443 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
445 /* verify data length */
446 if (count != td->remainder) {
447 DPRINTFN(1, "Invalid SETUP packet "
448 "length, %d bytes\n", count);
449 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
450 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
451 /* don't clear stall */
455 if (count != sizeof(req)) {
456 DPRINTFN(1, "Unsupported SETUP packet "
457 "length, %d bytes\n", count);
458 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
459 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
460 /* don't clear stall */
464 /* clear did stall flag */
468 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
469 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
471 /* copy data into real buffer */
472 usbd_copy_in(td->pc, 0, &req, sizeof(req));
474 td->offset = sizeof(req);
477 /* set pending command */
478 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
480 /* we need set stall or dataend after this */
483 /* sneak peek the set address */
484 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
485 (req.bRequest == UR_SET_ADDRESS)) {
486 sc->sc_dv_addr = req.wValue[0] & 0x7F;
488 sc->sc_dv_addr = 0xFF;
491 musbotg_channel_free(sc, td);
492 return (0); /* complete */
495 /* abort any ongoing transfer */
496 if (!td->did_stall) {
497 DPRINTFN(4, "stalling\n");
498 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
499 MUSB2_MASK_CSR0L_SENDSTALL);
502 return (1); /* not complete */
506 musbotg_host_ctrl_setup_tx(struct musbotg_td *td)
508 struct musbotg_softc *sc;
509 struct usb_device_request req;
512 /* get pointer to softc */
513 sc = MUSBOTG_PC2SC(td->pc);
515 if (td->channel == -1)
516 td->channel = musbotg_channel_alloc(sc, td, 1);
518 /* EP0 is busy, wait */
519 if (td->channel == -1)
522 DPRINTFN(1, "ep_no=%d\n", td->channel);
524 /* select endpoint 0 */
525 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
527 /* read out FIFO status */
528 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
529 DPRINTFN(4, "csr=0x%02x\n", csr);
531 /* Not ready yet yet */
532 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
536 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
537 MUSB2_MASK_CSR0L_ERROR))
539 /* Clear status bit */
540 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
541 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
545 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
546 DPRINTFN(1, "NAK timeout\n");
548 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
549 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
550 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
551 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
552 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
553 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
554 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
555 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
556 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
557 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
561 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
562 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
568 musbotg_channel_free(sc, td);
572 /* Fifo is not empty and there is no NAK timeout */
573 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
576 /* check if we are complete */
577 if (td->remainder == 0) {
578 /* we are complete */
579 musbotg_channel_free(sc, td);
583 /* copy data into real buffer */
584 usbd_copy_out(td->pc, 0, &req, sizeof(req));
587 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
588 MUSB2_REG_EPFIFO(0), (void *)&req, sizeof(req));
590 /* update offset and remainder */
591 td->offset += sizeof(req);
592 td->remainder -= sizeof(req);
595 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
596 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
597 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
598 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
599 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
602 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
603 MUSB2_MASK_CSR0L_TXPKTRDY |
604 MUSB2_MASK_CSR0L_SETUPPKT);
606 /* Just to be consistent, not used above */
607 td->transaction_started = 1;
609 return (1); /* in progress */
612 /* Control endpoint only data handling functions (RX/TX/SYNC) */
615 musbotg_dev_ctrl_data_rx(struct musbotg_td *td)
617 struct usb_page_search buf_res;
618 struct musbotg_softc *sc;
623 /* get pointer to softc */
624 sc = MUSBOTG_PC2SC(td->pc);
626 /* select endpoint 0 */
627 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
629 /* check if a command is pending */
630 if (sc->sc_ep0_cmd) {
631 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
634 /* read out FIFO status */
635 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
637 DPRINTFN(4, "csr=0x%02x\n", csr);
641 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
642 MUSB2_MASK_CSR0L_SENTSTALL)) {
643 if (td->remainder == 0) {
645 * We are actually complete and have
646 * received the next SETUP
648 DPRINTFN(4, "faking complete\n");
649 return (0); /* complete */
652 * USB Host Aborted the transfer.
655 return (0); /* complete */
657 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY)) {
658 return (1); /* not complete */
660 /* get the packet byte count */
661 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
663 /* verify the packet byte count */
664 if (count != td->max_frame_size) {
665 if (count < td->max_frame_size) {
666 /* we have a short packet */
670 /* invalid USB packet */
672 return (0); /* we are complete */
675 /* verify the packet byte count */
676 if (count > td->remainder) {
677 /* invalid USB packet */
679 return (0); /* we are complete */
684 usbd_get_page(td->pc, td->offset, &buf_res);
686 /* get correct length */
687 if (buf_res.length > count) {
688 buf_res.length = count;
690 /* check for unaligned memory address */
691 if (USB_P2U(buf_res.buffer) & 3) {
696 /* receive data 4 bytes at a time */
697 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
698 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
703 /* receive data 1 byte at a time */
704 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
706 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
708 usbd_copy_in(td->pc, td->offset,
709 sc->sc_bounce_buf, count);
711 /* update offset and remainder */
713 td->remainder -= count;
716 /* check if we can optimise */
717 if (buf_res.length >= 4) {
719 /* receive data 4 bytes at a time */
720 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
721 MUSB2_REG_EPFIFO(0), buf_res.buffer,
724 temp = buf_res.length & ~3;
726 /* update counters */
729 td->remainder -= temp;
733 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
734 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
736 /* update counters */
737 count -= buf_res.length;
738 td->offset += buf_res.length;
739 td->remainder -= buf_res.length;
742 /* check if we are complete */
743 if ((td->remainder == 0) || got_short) {
745 /* we are complete */
746 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_RXPKTRDY_CLR;
749 /* else need to receive a zero length packet */
751 /* write command - need more data */
752 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
753 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
754 return (1); /* not complete */
758 musbotg_dev_ctrl_data_tx(struct musbotg_td *td)
760 struct usb_page_search buf_res;
761 struct musbotg_softc *sc;
765 /* get pointer to softc */
766 sc = MUSBOTG_PC2SC(td->pc);
768 /* select endpoint 0 */
769 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
771 /* check if a command is pending */
772 if (sc->sc_ep0_cmd) {
773 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
776 /* read out FIFO status */
777 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
779 DPRINTFN(4, "csr=0x%02x\n", csr);
781 if (csr & (MUSB2_MASK_CSR0L_SETUPEND |
782 MUSB2_MASK_CSR0L_SENTSTALL)) {
784 * The current transfer was aborted
788 return (0); /* complete */
790 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY) {
791 return (1); /* not complete */
793 count = td->max_frame_size;
794 if (td->remainder < count) {
795 /* we have a short packet */
797 count = td->remainder;
802 usbd_get_page(td->pc, td->offset, &buf_res);
804 /* get correct length */
805 if (buf_res.length > count) {
806 buf_res.length = count;
808 /* check for unaligned memory address */
809 if (USB_P2U(buf_res.buffer) & 3) {
811 usbd_copy_out(td->pc, td->offset,
812 sc->sc_bounce_buf, count);
817 /* transmit data 4 bytes at a time */
818 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
819 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
824 /* receive data 1 byte at a time */
825 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
827 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
829 /* update offset and remainder */
831 td->remainder -= count;
834 /* check if we can optimise */
835 if (buf_res.length >= 4) {
837 /* transmit data 4 bytes at a time */
838 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
839 MUSB2_REG_EPFIFO(0), buf_res.buffer,
842 temp = buf_res.length & ~3;
844 /* update counters */
847 td->remainder -= temp;
851 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
852 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
854 /* update counters */
855 count -= buf_res.length;
856 td->offset += buf_res.length;
857 td->remainder -= buf_res.length;
860 /* check remainder */
861 if (td->remainder == 0) {
863 sc->sc_ep0_cmd = MUSB2_MASK_CSR0L_TXPKTRDY;
864 return (0); /* complete */
866 /* else we need to transmit a short packet */
869 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
870 MUSB2_MASK_CSR0L_TXPKTRDY);
872 return (1); /* not complete */
876 musbotg_host_ctrl_data_rx(struct musbotg_td *td)
878 struct usb_page_search buf_res;
879 struct musbotg_softc *sc;
884 /* get pointer to softc */
885 sc = MUSBOTG_PC2SC(td->pc);
887 if (td->channel == -1)
888 td->channel = musbotg_channel_alloc(sc, td, 0);
890 /* EP0 is busy, wait */
891 if (td->channel == -1)
894 DPRINTFN(1, "ep_no=%d\n", td->channel);
896 /* select endpoint 0 */
897 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
899 /* read out FIFO status */
900 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
902 DPRINTFN(4, "csr=0x%02x\n", csr);
905 if (!td->transaction_started) {
906 td->transaction_started = 1;
908 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
910 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
912 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
913 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
914 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
916 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
917 MUSB2_MASK_CSR0L_REQPKT);
922 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
923 csr &= ~MUSB2_MASK_CSR0L_REQPKT;
924 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
926 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
927 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
933 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
934 MUSB2_MASK_CSR0L_ERROR))
936 /* Clear status bit */
937 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
938 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
943 musbotg_channel_free(sc, td);
944 return (0); /* we are complete */
947 if (!(csr & MUSB2_MASK_CSR0L_RXPKTRDY))
948 return (1); /* not yet */
950 /* get the packet byte count */
951 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
953 /* verify the packet byte count */
954 if (count != td->max_frame_size) {
955 if (count < td->max_frame_size) {
956 /* we have a short packet */
960 /* invalid USB packet */
962 musbotg_channel_free(sc, td);
963 return (0); /* we are complete */
966 /* verify the packet byte count */
967 if (count > td->remainder) {
968 /* invalid USB packet */
970 musbotg_channel_free(sc, td);
971 return (0); /* we are complete */
976 usbd_get_page(td->pc, td->offset, &buf_res);
978 /* get correct length */
979 if (buf_res.length > count) {
980 buf_res.length = count;
982 /* check for unaligned memory address */
983 if (USB_P2U(buf_res.buffer) & 3) {
988 /* receive data 4 bytes at a time */
989 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
990 MUSB2_REG_EPFIFO(0), sc->sc_bounce_buf,
995 /* receive data 1 byte at a time */
996 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
998 (void *)(&sc->sc_bounce_buf[count / 4]), temp);
1000 usbd_copy_in(td->pc, td->offset,
1001 sc->sc_bounce_buf, count);
1003 /* update offset and remainder */
1004 td->offset += count;
1005 td->remainder -= count;
1008 /* check if we can optimise */
1009 if (buf_res.length >= 4) {
1011 /* receive data 4 bytes at a time */
1012 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1013 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1014 buf_res.length / 4);
1016 temp = buf_res.length & ~3;
1018 /* update counters */
1021 td->remainder -= temp;
1025 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1026 MUSB2_REG_EPFIFO(0), buf_res.buffer, buf_res.length);
1028 /* update counters */
1029 count -= buf_res.length;
1030 td->offset += buf_res.length;
1031 td->remainder -= buf_res.length;
1034 csr &= ~MUSB2_MASK_CSR0L_RXPKTRDY;
1035 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1037 /* check if we are complete */
1038 if ((td->remainder == 0) || got_short) {
1039 if (td->short_pkt) {
1040 /* we are complete */
1042 musbotg_channel_free(sc, td);
1045 /* else need to receive a zero length packet */
1048 td->transaction_started = 1;
1049 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1050 MUSB2_MASK_CSR0L_REQPKT);
1052 return (1); /* not complete */
1056 musbotg_host_ctrl_data_tx(struct musbotg_td *td)
1058 struct usb_page_search buf_res;
1059 struct musbotg_softc *sc;
1063 /* get pointer to softc */
1064 sc = MUSBOTG_PC2SC(td->pc);
1066 if (td->channel == -1)
1067 td->channel = musbotg_channel_alloc(sc, td, 1);
1070 if (td->channel == -1)
1073 DPRINTFN(1, "ep_no=%d\n", td->channel);
1075 /* select endpoint */
1076 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1078 /* read out FIFO status */
1079 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1080 DPRINTFN(4, "csr=0x%02x\n", csr);
1082 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1083 MUSB2_MASK_CSR0L_ERROR)) {
1084 /* clear status bits */
1085 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1089 if (csr & MUSB2_MASK_CSR0L_NAKTIMO ) {
1091 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1092 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1093 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1094 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1095 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1096 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) {
1097 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
1098 csrh |= MUSB2_MASK_CSR0H_FFLUSH;
1099 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
1100 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1104 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1105 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1112 musbotg_channel_free(sc, td);
1113 return (0); /* complete */
1117 * Wait while FIFO is empty.
1118 * Do not flush it because it will cause transactions
1119 * with size more then packet size. It might upset
1122 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY)
1125 /* Packet still being processed */
1126 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1129 if (td->transaction_started) {
1130 /* check remainder */
1131 if (td->remainder == 0) {
1132 if (td->short_pkt) {
1133 musbotg_channel_free(sc, td);
1134 return (0); /* complete */
1136 /* else we need to transmit a short packet */
1139 /* We're not complete - more transactions required */
1140 td->transaction_started = 0;
1143 /* check for short packet */
1144 count = td->max_frame_size;
1145 if (td->remainder < count) {
1146 /* we have a short packet */
1148 count = td->remainder;
1154 usbd_get_page(td->pc, td->offset, &buf_res);
1156 /* get correct length */
1157 if (buf_res.length > count) {
1158 buf_res.length = count;
1160 /* check for unaligned memory address */
1161 if (USB_P2U(buf_res.buffer) & 3) {
1163 usbd_copy_out(td->pc, td->offset,
1164 sc->sc_bounce_buf, count);
1169 /* transmit data 4 bytes at a time */
1170 bus_space_write_multi_4(sc->sc_io_tag,
1171 sc->sc_io_hdl, MUSB2_REG_EPFIFO(0),
1172 sc->sc_bounce_buf, temp / 4);
1176 /* receive data 1 byte at a time */
1177 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1178 MUSB2_REG_EPFIFO(0),
1179 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1181 /* update offset and remainder */
1182 td->offset += count;
1183 td->remainder -= count;
1186 /* check if we can optimise */
1187 if (buf_res.length >= 4) {
1189 /* transmit data 4 bytes at a time */
1190 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1191 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1192 buf_res.length / 4);
1194 temp = buf_res.length & ~3;
1196 /* update counters */
1199 td->remainder -= temp;
1203 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1204 MUSB2_REG_EPFIFO(0), buf_res.buffer,
1207 /* update counters */
1208 count -= buf_res.length;
1209 td->offset += buf_res.length;
1210 td->remainder -= buf_res.length;
1213 /* Function address */
1214 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1215 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1216 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1217 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1219 /* TX NAK timeout */
1220 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1223 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1224 MUSB2_MASK_CSR0L_TXPKTRDY);
1226 td->transaction_started = 1;
1228 return (1); /* not complete */
1232 musbotg_dev_ctrl_status(struct musbotg_td *td)
1234 struct musbotg_softc *sc;
1237 /* get pointer to softc */
1238 sc = MUSBOTG_PC2SC(td->pc);
1240 /* select endpoint 0 */
1241 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1243 if (sc->sc_ep0_busy) {
1244 sc->sc_ep0_busy = 0;
1245 sc->sc_ep0_cmd |= MUSB2_MASK_CSR0L_DATAEND;
1246 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, sc->sc_ep0_cmd);
1249 /* read out FIFO status */
1250 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1252 DPRINTFN(4, "csr=0x%02x\n", csr);
1254 if (csr & MUSB2_MASK_CSR0L_DATAEND) {
1255 /* wait for interrupt */
1256 return (1); /* not complete */
1258 if (sc->sc_dv_addr != 0xFF) {
1259 /* write function address */
1260 musbotg_set_address(sc, sc->sc_dv_addr);
1263 musbotg_channel_free(sc, td);
1264 return (0); /* complete */
1268 musbotg_host_ctrl_status_rx(struct musbotg_td *td)
1270 struct musbotg_softc *sc;
1273 /* get pointer to softc */
1274 sc = MUSBOTG_PC2SC(td->pc);
1276 if (td->channel == -1)
1277 td->channel = musbotg_channel_alloc(sc, td, 0);
1279 /* EP0 is busy, wait */
1280 if (td->channel == -1)
1283 DPRINTFN(1, "ep_no=%d\n", td->channel);
1285 /* select endpoint 0 */
1286 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1288 if (!td->transaction_started) {
1289 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(0),
1292 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(0), td->haddr);
1293 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(0), td->hport);
1294 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1296 /* RX NAK timeout */
1297 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1299 td->transaction_started = 1;
1302 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1303 csrh |= MUSB2_MASK_CSR0H_PING_DIS;
1304 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1307 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1308 MUSB2_MASK_CSR0L_STATUSPKT |
1309 MUSB2_MASK_CSR0L_REQPKT);
1311 return (1); /* Just started */
1315 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1317 DPRINTFN(4, "IN STATUS csr=0x%02x\n", csr);
1319 if (csr & MUSB2_MASK_CSR0L_RXPKTRDY) {
1320 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1321 MUSB2_MASK_CSR0L_RXPKTRDY_CLR);
1322 musbotg_channel_free(sc, td);
1323 return (0); /* complete */
1326 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) {
1327 csr &= ~ (MUSB2_MASK_CSR0L_STATUSPKT |
1328 MUSB2_MASK_CSR0L_REQPKT);
1329 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1331 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO;
1332 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1337 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1338 MUSB2_MASK_CSR0L_ERROR))
1340 /* Clear status bit */
1341 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1342 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1347 musbotg_channel_free(sc, td);
1351 return (1); /* Not ready yet */
1355 musbotg_host_ctrl_status_tx(struct musbotg_td *td)
1357 struct musbotg_softc *sc;
1360 /* get pointer to softc */
1361 sc = MUSBOTG_PC2SC(td->pc);
1363 if (td->channel == -1)
1364 td->channel = musbotg_channel_alloc(sc, td, 1);
1366 /* EP0 is busy, wait */
1367 if (td->channel == -1)
1370 DPRINTFN(1, "ep_no=%d/%d [%d@%d.%d/%02x]\n", td->channel, td->transaction_started,
1371 td->dev_addr,td->haddr,td->hport, td->transfer_type);
1373 /* select endpoint 0 */
1374 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
1376 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1377 DPRINTFN(4, "csr=0x%02x\n", csr);
1380 if (csr & MUSB2_MASK_CSR0L_TXPKTRDY)
1384 if (csr & (MUSB2_MASK_CSR0L_RXSTALL |
1385 MUSB2_MASK_CSR0L_ERROR))
1387 /* Clear status bit */
1388 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1389 DPRINTFN(1, "error bit set, csr=0x%02x\n", csr);
1391 musbotg_channel_free(sc, td);
1392 return (0); /* complete */
1395 if (td->transaction_started) {
1396 musbotg_channel_free(sc, td);
1397 return (0); /* complete */
1400 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, MUSB2_MASK_CSR0H_PING_DIS);
1402 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(0), td->dev_addr);
1403 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(0), td->haddr);
1404 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(0), td->hport);
1405 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
1407 /* TX NAK timeout */
1408 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
1410 td->transaction_started = 1;
1413 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1414 MUSB2_MASK_CSR0L_STATUSPKT |
1415 MUSB2_MASK_CSR0L_TXPKTRDY);
1417 return (1); /* wait for interrupt */
1421 musbotg_dev_data_rx(struct musbotg_td *td)
1423 struct usb_page_search buf_res;
1424 struct musbotg_softc *sc;
1430 to = 8; /* don't loop forever! */
1433 /* get pointer to softc */
1434 sc = MUSBOTG_PC2SC(td->pc);
1436 if (td->channel == -1)
1437 td->channel = musbotg_channel_alloc(sc, td, 0);
1439 /* EP0 is busy, wait */
1440 if (td->channel == -1)
1443 /* select endpoint */
1444 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1447 /* read out FIFO status */
1448 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1450 DPRINTFN(4, "csr=0x%02x\n", csr);
1453 if (csr & MUSB2_MASK_CSRL_RXOVERRUN) {
1454 /* make sure we don't clear "RXPKTRDY" */
1455 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1456 MUSB2_MASK_CSRL_RXPKTRDY);
1460 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY))
1461 return (1); /* not complete */
1463 /* get the packet byte count */
1464 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1466 DPRINTFN(4, "count=0x%04x\n", count);
1469 * Check for short or invalid packet:
1471 if (count != td->max_frame_size) {
1472 if (count < td->max_frame_size) {
1473 /* we have a short packet */
1477 /* invalid USB packet */
1479 musbotg_channel_free(sc, td);
1480 return (0); /* we are complete */
1483 /* verify the packet byte count */
1484 if (count > td->remainder) {
1485 /* invalid USB packet */
1487 musbotg_channel_free(sc, td);
1488 return (0); /* we are complete */
1493 usbd_get_page(td->pc, td->offset, &buf_res);
1495 /* get correct length */
1496 if (buf_res.length > count) {
1497 buf_res.length = count;
1499 /* check for unaligned memory address */
1500 if (USB_P2U(buf_res.buffer) & 3) {
1505 /* receive data 4 bytes at a time */
1506 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1507 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1512 /* receive data 1 byte at a time */
1513 bus_space_read_multi_1(sc->sc_io_tag,
1514 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1515 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1517 usbd_copy_in(td->pc, td->offset,
1518 sc->sc_bounce_buf, count);
1520 /* update offset and remainder */
1521 td->offset += count;
1522 td->remainder -= count;
1525 /* check if we can optimise */
1526 if (buf_res.length >= 4) {
1528 /* receive data 4 bytes at a time */
1529 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1530 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1531 buf_res.length / 4);
1533 temp = buf_res.length & ~3;
1535 /* update counters */
1538 td->remainder -= temp;
1542 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1543 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1546 /* update counters */
1547 count -= buf_res.length;
1548 td->offset += buf_res.length;
1549 td->remainder -= buf_res.length;
1552 /* clear status bits */
1553 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1555 /* check if we are complete */
1556 if ((td->remainder == 0) || got_short) {
1557 if (td->short_pkt) {
1558 /* we are complete */
1559 musbotg_channel_free(sc, td);
1562 /* else need to receive a zero length packet */
1567 return (1); /* not complete */
1571 musbotg_dev_data_tx(struct musbotg_td *td)
1573 struct usb_page_search buf_res;
1574 struct musbotg_softc *sc;
1579 to = 8; /* don't loop forever! */
1581 /* get pointer to softc */
1582 sc = MUSBOTG_PC2SC(td->pc);
1584 if (td->channel == -1)
1585 td->channel = musbotg_channel_alloc(sc, td, 1);
1587 /* EP0 is busy, wait */
1588 if (td->channel == -1)
1591 /* select endpoint */
1592 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1596 /* read out FIFO status */
1597 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1599 DPRINTFN(4, "csr=0x%02x\n", csr);
1601 if (csr & (MUSB2_MASK_CSRL_TXINCOMP |
1602 MUSB2_MASK_CSRL_TXUNDERRUN)) {
1603 /* clear status bits */
1604 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1606 if (csr & MUSB2_MASK_CSRL_TXPKTRDY) {
1607 return (1); /* not complete */
1609 /* check for short packet */
1610 count = td->max_frame_size;
1611 if (td->remainder < count) {
1612 /* we have a short packet */
1614 count = td->remainder;
1619 usbd_get_page(td->pc, td->offset, &buf_res);
1621 /* get correct length */
1622 if (buf_res.length > count) {
1623 buf_res.length = count;
1625 /* check for unaligned memory address */
1626 if (USB_P2U(buf_res.buffer) & 3) {
1628 usbd_copy_out(td->pc, td->offset,
1629 sc->sc_bounce_buf, count);
1634 /* transmit data 4 bytes at a time */
1635 bus_space_write_multi_4(sc->sc_io_tag,
1636 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1637 sc->sc_bounce_buf, temp / 4);
1641 /* receive data 1 byte at a time */
1642 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1643 MUSB2_REG_EPFIFO(td->channel),
1644 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1646 /* update offset and remainder */
1647 td->offset += count;
1648 td->remainder -= count;
1651 /* check if we can optimise */
1652 if (buf_res.length >= 4) {
1654 /* transmit data 4 bytes at a time */
1655 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1656 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1657 buf_res.length / 4);
1659 temp = buf_res.length & ~3;
1661 /* update counters */
1664 td->remainder -= temp;
1668 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1669 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1672 /* update counters */
1673 count -= buf_res.length;
1674 td->offset += buf_res.length;
1675 td->remainder -= buf_res.length;
1678 /* Max packet size */
1679 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
1682 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
1683 MUSB2_MASK_CSRL_TXPKTRDY);
1685 /* check remainder */
1686 if (td->remainder == 0) {
1687 if (td->short_pkt) {
1688 musbotg_channel_free(sc, td);
1689 return (0); /* complete */
1691 /* else we need to transmit a short packet */
1696 return (1); /* not complete */
1700 musbotg_host_data_rx(struct musbotg_td *td)
1702 struct usb_page_search buf_res;
1703 struct musbotg_softc *sc;
1709 /* get pointer to softc */
1710 sc = MUSBOTG_PC2SC(td->pc);
1712 if (td->channel == -1)
1713 td->channel = musbotg_channel_alloc(sc, td, 0);
1716 if (td->channel == -1)
1719 DPRINTFN(1, "ep_no=%d\n", td->channel);
1721 to = 8; /* don't loop forever! */
1724 /* select endpoint */
1725 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1728 /* read out FIFO status */
1729 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
1730 DPRINTFN(4, "csr=0x%02x\n", csr);
1732 if (!td->transaction_started) {
1733 /* Function address */
1734 MUSB2_WRITE_1(sc, MUSB2_REG_RXFADDR(td->channel),
1737 /* SPLIT transaction */
1738 MUSB2_WRITE_1(sc, MUSB2_REG_RXHADDR(td->channel),
1740 MUSB2_WRITE_1(sc, MUSB2_REG_RXHUBPORT(td->channel),
1743 /* RX NAK timeout */
1744 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
1745 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, 0);
1747 MUSB2_WRITE_1(sc, MUSB2_REG_RXNAKLIMIT, MAX_NAK_TO);
1749 /* Protocol, speed, device endpoint */
1750 MUSB2_WRITE_1(sc, MUSB2_REG_RXTI, td->transfer_type);
1752 /* Max packet size */
1753 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, td->reg_max_packet);
1756 csrh = MUSB2_READ_1(sc, MUSB2_REG_RXCSRH);
1757 DPRINTFN(4, "csrh=0x%02x\n", csrh);
1759 csrh |= MUSB2_MASK_CSRH_RXDT_WREN;
1761 csrh |= MUSB2_MASK_CSRH_RXDT_VAL;
1763 csrh &= ~MUSB2_MASK_CSRH_RXDT_VAL;
1765 /* Set data toggle */
1766 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, csrh);
1769 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
1770 MUSB2_MASK_CSRL_RXREQPKT);
1772 td->transaction_started = 1;
1776 /* clear NAK timeout */
1777 if (csr & MUSB2_MASK_CSRL_RXNAKTO) {
1778 DPRINTFN(4, "NAK Timeout\n");
1779 if (csr & MUSB2_MASK_CSRL_RXREQPKT) {
1780 csr &= ~MUSB2_MASK_CSRL_RXREQPKT;
1781 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1783 csr &= ~MUSB2_MASK_CSRL_RXNAKTO;
1784 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, csr);
1790 if (csr & MUSB2_MASK_CSRL_RXERROR) {
1791 DPRINTFN(4, "RXERROR\n");
1795 if (csr & MUSB2_MASK_CSRL_RXSTALL) {
1796 DPRINTFN(4, "RXSTALL\n");
1801 musbotg_channel_free(sc, td);
1802 return (0); /* we are complete */
1805 if (!(csr & MUSB2_MASK_CSRL_RXPKTRDY)) {
1806 /* No data available yet */
1811 /* get the packet byte count */
1812 count = MUSB2_READ_2(sc, MUSB2_REG_RXCOUNT);
1813 DPRINTFN(4, "count=0x%04x\n", count);
1816 * Check for short or invalid packet:
1818 if (count != td->max_frame_size) {
1819 if (count < td->max_frame_size) {
1820 /* we have a short packet */
1824 /* invalid USB packet */
1826 musbotg_channel_free(sc, td);
1827 return (0); /* we are complete */
1831 /* verify the packet byte count */
1832 if (count > td->remainder) {
1833 /* invalid USB packet */
1835 musbotg_channel_free(sc, td);
1836 return (0); /* we are complete */
1842 usbd_get_page(td->pc, td->offset, &buf_res);
1844 /* get correct length */
1845 if (buf_res.length > count) {
1846 buf_res.length = count;
1848 /* check for unaligned memory address */
1849 if (USB_P2U(buf_res.buffer) & 3) {
1854 /* receive data 4 bytes at a time */
1855 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1856 MUSB2_REG_EPFIFO(td->channel), sc->sc_bounce_buf,
1861 /* receive data 1 byte at a time */
1862 bus_space_read_multi_1(sc->sc_io_tag,
1863 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
1864 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
1866 usbd_copy_in(td->pc, td->offset,
1867 sc->sc_bounce_buf, count);
1869 /* update offset and remainder */
1870 td->offset += count;
1871 td->remainder -= count;
1874 /* check if we can optimise */
1875 if (buf_res.length >= 4) {
1877 /* receive data 4 bytes at a time */
1878 bus_space_read_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
1879 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1880 buf_res.length / 4);
1882 temp = buf_res.length & ~3;
1884 /* update counters */
1887 td->remainder -= temp;
1891 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
1892 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
1895 /* update counters */
1896 count -= buf_res.length;
1897 td->offset += buf_res.length;
1898 td->remainder -= buf_res.length;
1901 /* clear status bits */
1902 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
1904 /* check if we are complete */
1905 if ((td->remainder == 0) || got_short) {
1906 if (td->short_pkt) {
1907 /* we are complete */
1908 musbotg_channel_free(sc, td);
1911 /* else need to receive a zero length packet */
1914 /* Reset transaction state and restart */
1915 td->transaction_started = 0;
1920 return (1); /* not complete */
1924 musbotg_host_data_tx(struct musbotg_td *td)
1926 struct usb_page_search buf_res;
1927 struct musbotg_softc *sc;
1931 /* get pointer to softc */
1932 sc = MUSBOTG_PC2SC(td->pc);
1934 if (td->channel == -1)
1935 td->channel = musbotg_channel_alloc(sc, td, 1);
1938 if (td->channel == -1)
1941 DPRINTFN(1, "ep_no=%d\n", td->channel);
1943 /* select endpoint */
1944 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, td->channel);
1946 /* read out FIFO status */
1947 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1948 DPRINTFN(4, "csr=0x%02x\n", csr);
1950 if (csr & (MUSB2_MASK_CSRL_TXSTALLED |
1951 MUSB2_MASK_CSRL_TXERROR)) {
1952 /* clear status bits */
1953 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
1955 musbotg_channel_free(sc, td);
1956 return (0); /* complete */
1959 if (csr & MUSB2_MASK_CSRL_TXNAKTO) {
1961 * Flush TX FIFO before clearing NAK TO
1963 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1964 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1965 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1966 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1967 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
1968 csr |= MUSB2_MASK_CSRL_TXFFLUSH;
1969 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1970 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
1974 csr &= ~MUSB2_MASK_CSRL_TXNAKTO;
1975 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, csr);
1978 musbotg_channel_free(sc, td);
1979 return (0); /* complete */
1983 * Wait while FIFO is empty.
1984 * Do not flush it because it will cause transactions
1985 * with size more then packet size. It might upset
1988 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY)
1991 /* Packet still being processed */
1992 if (csr & MUSB2_MASK_CSRL_TXPKTRDY)
1995 if (td->transaction_started) {
1996 /* check remainder */
1997 if (td->remainder == 0) {
1998 if (td->short_pkt) {
1999 musbotg_channel_free(sc, td);
2000 return (0); /* complete */
2002 /* else we need to transmit a short packet */
2005 /* We're not complete - more transactions required */
2006 td->transaction_started = 0;
2009 /* check for short packet */
2010 count = td->max_frame_size;
2011 if (td->remainder < count) {
2012 /* we have a short packet */
2014 count = td->remainder;
2020 usbd_get_page(td->pc, td->offset, &buf_res);
2022 /* get correct length */
2023 if (buf_res.length > count) {
2024 buf_res.length = count;
2026 /* check for unaligned memory address */
2027 if (USB_P2U(buf_res.buffer) & 3) {
2029 usbd_copy_out(td->pc, td->offset,
2030 sc->sc_bounce_buf, count);
2035 /* transmit data 4 bytes at a time */
2036 bus_space_write_multi_4(sc->sc_io_tag,
2037 sc->sc_io_hdl, MUSB2_REG_EPFIFO(td->channel),
2038 sc->sc_bounce_buf, temp / 4);
2042 /* receive data 1 byte at a time */
2043 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2044 MUSB2_REG_EPFIFO(td->channel),
2045 ((void *)&sc->sc_bounce_buf[count / 4]), temp);
2047 /* update offset and remainder */
2048 td->offset += count;
2049 td->remainder -= count;
2052 /* check if we can optimise */
2053 if (buf_res.length >= 4) {
2055 /* transmit data 4 bytes at a time */
2056 bus_space_write_multi_4(sc->sc_io_tag, sc->sc_io_hdl,
2057 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2058 buf_res.length / 4);
2060 temp = buf_res.length & ~3;
2062 /* update counters */
2065 td->remainder -= temp;
2069 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
2070 MUSB2_REG_EPFIFO(td->channel), buf_res.buffer,
2073 /* update counters */
2074 count -= buf_res.length;
2075 td->offset += buf_res.length;
2076 td->remainder -= buf_res.length;
2079 /* Function address */
2080 MUSB2_WRITE_1(sc, MUSB2_REG_TXFADDR(td->channel),
2083 /* SPLIT transaction */
2084 MUSB2_WRITE_1(sc, MUSB2_REG_TXHADDR(td->channel),
2086 MUSB2_WRITE_1(sc, MUSB2_REG_TXHUBPORT(td->channel),
2089 /* TX NAK timeout */
2090 if (td->transfer_type & MUSB2_MASK_TI_PROTO_ISOC)
2091 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, 0);
2093 MUSB2_WRITE_1(sc, MUSB2_REG_TXNAKLIMIT, MAX_NAK_TO);
2095 /* Protocol, speed, device endpoint */
2096 MUSB2_WRITE_1(sc, MUSB2_REG_TXTI, td->transfer_type);
2098 /* Max packet size */
2099 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, td->reg_max_packet);
2101 if (!td->transaction_started) {
2102 csrh = MUSB2_READ_1(sc, MUSB2_REG_TXCSRH);
2103 DPRINTFN(4, "csrh=0x%02x\n", csrh);
2105 csrh |= MUSB2_MASK_CSRH_TXDT_WREN;
2107 csrh |= MUSB2_MASK_CSRH_TXDT_VAL;
2109 csrh &= ~MUSB2_MASK_CSRH_TXDT_VAL;
2111 /* Set data toggle */
2112 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH, csrh);
2116 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2117 MUSB2_MASK_CSRL_TXPKTRDY);
2119 /* Update Data Toggle */
2121 td->transaction_started = 1;
2123 return (1); /* not complete */
2127 musbotg_xfer_do_fifo(struct usb_xfer *xfer)
2129 struct musbotg_softc *sc;
2130 struct musbotg_td *td;
2133 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2135 td = xfer->td_transfer_cache;
2138 if ((td->func) (td)) {
2139 /* operation in progress */
2143 if (((void *)td) == xfer->td_transfer_last) {
2148 } else if (td->remainder > 0) {
2150 * We had a short transfer. If there is no alternate
2151 * next, stop processing !
2153 if (!td->alt_next) {
2158 * Fetch the next transfer descriptor and transfer
2159 * some flags to the next transfer descriptor
2162 xfer->td_transfer_cache = td;
2165 return (1); /* not complete */
2167 /* compute all actual lengths */
2168 musbotg_standard_done(xfer);
2170 return (0); /* complete */
2174 musbotg_interrupt_poll(struct musbotg_softc *sc)
2176 struct usb_xfer *xfer;
2179 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
2180 if (!musbotg_xfer_do_fifo(xfer)) {
2181 /* queue has been modified */
2188 musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on)
2190 DPRINTFN(4, "vbus = %u\n", is_on);
2192 USB_BUS_LOCK(&sc->sc_bus);
2194 if (!sc->sc_flags.status_vbus) {
2195 sc->sc_flags.status_vbus = 1;
2197 /* complete root HUB interrupt endpoint */
2198 musbotg_root_intr(sc);
2201 if (sc->sc_flags.status_vbus) {
2202 sc->sc_flags.status_vbus = 0;
2203 sc->sc_flags.status_bus_reset = 0;
2204 sc->sc_flags.status_suspend = 0;
2205 sc->sc_flags.change_suspend = 0;
2206 sc->sc_flags.change_connect = 1;
2208 /* complete root HUB interrupt endpoint */
2209 musbotg_root_intr(sc);
2213 USB_BUS_UNLOCK(&sc->sc_bus);
2217 musbotg_connect_interrupt(struct musbotg_softc *sc)
2219 USB_BUS_LOCK(&sc->sc_bus);
2220 sc->sc_flags.change_connect = 1;
2222 /* complete root HUB interrupt endpoint */
2223 musbotg_root_intr(sc);
2224 USB_BUS_UNLOCK(&sc->sc_bus);
2228 musbotg_interrupt(struct musbotg_softc *sc,
2229 uint16_t rxstat, uint16_t txstat, uint8_t stat)
2237 USB_BUS_LOCK(&sc->sc_bus);
2241 /* read all interrupt registers */
2242 usb_status = MUSB2_READ_1(sc, MUSB2_REG_INTUSB);
2244 /* read all FIFO interrupts */
2245 rx_status = MUSB2_READ_2(sc, MUSB2_REG_INTRX);
2246 tx_status = MUSB2_READ_2(sc, MUSB2_REG_INTTX);
2247 rx_status |= rxstat;
2248 tx_status |= txstat;
2251 /* Clear platform flags after first time */
2256 /* check for any bus state change interrupts */
2258 if (usb_status & (MUSB2_MASK_IRESET |
2259 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP |
2260 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC |
2261 MUSB2_MASK_IVBUSERR)) {
2263 DPRINTFN(4, "real bus interrupt 0x%08x\n", usb_status);
2265 if (usb_status & MUSB2_MASK_IRESET) {
2267 /* set correct state */
2268 sc->sc_flags.status_bus_reset = 1;
2269 sc->sc_flags.status_suspend = 0;
2270 sc->sc_flags.change_suspend = 0;
2271 sc->sc_flags.change_connect = 1;
2273 /* determine line speed */
2274 temp = MUSB2_READ_1(sc, MUSB2_REG_POWER);
2275 if (temp & MUSB2_MASK_HSMODE)
2276 sc->sc_flags.status_high_speed = 1;
2278 sc->sc_flags.status_high_speed = 0;
2281 * After reset all interrupts are on and we need to
2284 temp = MUSB2_MASK_IRESET;
2285 /* disable resume interrupt */
2286 temp &= ~MUSB2_MASK_IRESUME;
2287 /* enable suspend interrupt */
2288 temp |= MUSB2_MASK_ISUSP;
2289 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2290 /* disable TX and RX interrupts */
2291 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
2292 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
2295 * If RXRSM and RXSUSP is set at the same time we interpret
2296 * that like RESUME. Resume is set when there is at least 3
2297 * milliseconds of inactivity on the USB BUS.
2299 if (usb_status & MUSB2_MASK_IRESUME) {
2300 if (sc->sc_flags.status_suspend) {
2301 sc->sc_flags.status_suspend = 0;
2302 sc->sc_flags.change_suspend = 1;
2304 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2305 /* disable resume interrupt */
2306 temp &= ~MUSB2_MASK_IRESUME;
2307 /* enable suspend interrupt */
2308 temp |= MUSB2_MASK_ISUSP;
2309 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2311 } else if (usb_status & MUSB2_MASK_ISUSP) {
2312 if (!sc->sc_flags.status_suspend) {
2313 sc->sc_flags.status_suspend = 1;
2314 sc->sc_flags.change_suspend = 1;
2316 temp = MUSB2_READ_1(sc, MUSB2_REG_INTUSBE);
2317 /* disable suspend interrupt */
2318 temp &= ~MUSB2_MASK_ISUSP;
2319 /* enable resume interrupt */
2320 temp |= MUSB2_MASK_IRESUME;
2321 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, temp);
2325 (MUSB2_MASK_ICONN | MUSB2_MASK_IDISC))
2326 sc->sc_flags.change_connect = 1;
2329 * Host Mode: There is no IRESET so assume bus is
2330 * always in reset state once device is connected.
2332 if (sc->sc_mode == MUSB2_HOST_MODE) {
2333 /* check for VBUS error in USB host mode */
2334 if (usb_status & MUSB2_MASK_IVBUSERR) {
2335 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
2336 temp |= MUSB2_MASK_SESS;
2337 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
2339 if (usb_status & MUSB2_MASK_ICONN)
2340 sc->sc_flags.status_bus_reset = 1;
2341 if (usb_status & MUSB2_MASK_IDISC)
2342 sc->sc_flags.status_bus_reset = 0;
2345 /* complete root HUB interrupt endpoint */
2346 musbotg_root_intr(sc);
2348 /* check for any endpoint interrupts */
2350 if (rx_status || tx_status) {
2351 DPRINTFN(4, "real endpoint interrupt "
2352 "rx=0x%04x, tx=0x%04x\n", rx_status, tx_status);
2354 /* poll one time regardless of FIFO status */
2356 musbotg_interrupt_poll(sc);
2361 USB_BUS_UNLOCK(&sc->sc_bus);
2365 musbotg_setup_standard_chain_sub(struct musbotg_std_temp *temp)
2367 struct musbotg_td *td;
2369 /* get current Transfer Descriptor */
2373 /* prepare for next TD */
2374 temp->td_next = td->obj_next;
2376 /* fill out the Transfer Descriptor */
2377 td->func = temp->func;
2379 td->offset = temp->offset;
2380 td->remainder = temp->len;
2382 td->transaction_started = 0;
2383 td->did_stall = temp->did_stall;
2384 td->short_pkt = temp->short_pkt;
2385 td->alt_next = temp->setup_alt_next;
2386 td->channel = temp->channel;
2387 td->dev_addr = temp->dev_addr;
2388 td->haddr = temp->haddr;
2389 td->hport = temp->hport;
2390 td->transfer_type = temp->transfer_type;
2394 musbotg_setup_standard_chain(struct usb_xfer *xfer)
2396 struct musbotg_std_temp temp;
2397 struct musbotg_softc *sc;
2398 struct musbotg_td *td;
2402 enum usb_dev_speed speed;
2406 DPRINTFN(8, "addr=%d endpt=%d sumlen=%d speed=%d\n",
2407 xfer->address, UE_GET_ADDR(xfer->endpointno),
2408 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
2410 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2411 ep_no = (xfer->endpointno & UE_ADDR);
2413 temp.max_frame_size = xfer->max_frame_size;
2415 td = xfer->td_start[0];
2416 xfer->td_transfer_first = td;
2417 xfer->td_transfer_cache = td;
2420 dev_addr = xfer->address;
2422 xfer_type = xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE;
2426 temp.td_next = xfer->td_start[0];
2428 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
2429 xfer->flags_int.isochronous_xfr;
2430 temp.did_stall = !xfer->flags_int.control_stall;
2432 temp.dev_addr = dev_addr;
2433 temp.haddr = xfer->xroot->udev->hs_hub_addr;
2434 temp.hport = xfer->xroot->udev->hs_port_no;
2436 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2437 speed = usbd_get_speed(xfer->xroot->udev);
2441 temp.transfer_type = MUSB2_MASK_TI_SPEED_LO;
2443 case USB_SPEED_FULL:
2444 temp.transfer_type = MUSB2_MASK_TI_SPEED_FS;
2446 case USB_SPEED_HIGH:
2447 temp.transfer_type = MUSB2_MASK_TI_SPEED_HS;
2450 temp.transfer_type = 0;
2451 DPRINTFN(-1, "Invalid USB speed: %d\n", speed);
2455 switch (xfer_type) {
2457 temp.transfer_type |= MUSB2_MASK_TI_PROTO_CTRL;
2459 case UE_ISOCHRONOUS:
2460 temp.transfer_type |= MUSB2_MASK_TI_PROTO_ISOC;
2463 temp.transfer_type |= MUSB2_MASK_TI_PROTO_BULK;
2466 temp.transfer_type |= MUSB2_MASK_TI_PROTO_INTR;
2469 DPRINTFN(-1, "Invalid USB transfer type: %d\n",
2474 temp.transfer_type |= ep_no;
2475 td->toggle = xfer->endpoint->toggle_next;
2478 /* check if we should prepend a setup message */
2480 if (xfer->flags_int.control_xfr) {
2481 if (xfer->flags_int.control_hdr) {
2483 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE)
2484 temp.func = &musbotg_dev_ctrl_setup_rx;
2486 temp.func = &musbotg_host_ctrl_setup_tx;
2488 temp.len = xfer->frlengths[0];
2489 temp.pc = xfer->frbuffers + 0;
2490 temp.short_pkt = temp.len ? 1 : 0;
2492 musbotg_setup_standard_chain_sub(&temp);
2501 if (x != xfer->nframes) {
2502 if (xfer->endpointno & UE_DIR_IN)
2505 if (xfer->flags_int.usb_mode == USB_MODE_HOST) {
2509 if (xfer->flags_int.control_xfr)
2510 temp.func = &musbotg_host_ctrl_data_tx;
2512 temp.func = &musbotg_host_data_tx;
2514 if (xfer->flags_int.control_xfr)
2515 temp.func = &musbotg_host_ctrl_data_rx;
2517 temp.func = &musbotg_host_data_rx;
2522 if (xfer->flags_int.control_xfr)
2523 temp.func = &musbotg_dev_ctrl_data_tx;
2525 temp.func = &musbotg_dev_data_tx;
2527 if (xfer->flags_int.control_xfr)
2528 temp.func = &musbotg_dev_ctrl_data_rx;
2530 temp.func = &musbotg_dev_data_rx;
2534 /* setup "pc" pointer */
2535 temp.pc = xfer->frbuffers + x;
2537 while (x != xfer->nframes) {
2539 /* DATA0 / DATA1 message */
2541 temp.len = xfer->frlengths[x];
2545 if (x == xfer->nframes) {
2546 if (xfer->flags_int.control_xfr) {
2547 if (xfer->flags_int.control_act) {
2548 temp.setup_alt_next = 0;
2551 temp.setup_alt_next = 0;
2554 if (temp.len == 0) {
2556 /* make sure that we send an USB packet */
2562 if (xfer->flags_int.isochronous_xfr) {
2563 /* isochronous data transfer */
2564 /* don't force short */
2567 /* regular data transfer */
2568 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1);
2572 musbotg_setup_standard_chain_sub(&temp);
2574 if (xfer->flags_int.isochronous_xfr) {
2575 temp.offset += temp.len;
2577 /* get next Page Cache pointer */
2578 temp.pc = xfer->frbuffers + x;
2582 /* check for control transfer */
2583 if (xfer->flags_int.control_xfr) {
2585 /* always setup a valid "pc" pointer for status and sync */
2586 temp.pc = xfer->frbuffers + 0;
2589 temp.setup_alt_next = 0;
2591 /* check if we should append a status stage */
2592 if (!xfer->flags_int.control_act) {
2594 * Send a DATA1 message and invert the current
2595 * endpoint direction.
2597 if (sc->sc_mode == MUSB2_DEVICE_MODE)
2598 temp.func = &musbotg_dev_ctrl_status;
2600 if (xfer->endpointno & UE_DIR_IN)
2601 temp.func = musbotg_host_ctrl_status_tx;
2603 temp.func = musbotg_host_ctrl_status_rx;
2605 musbotg_setup_standard_chain_sub(&temp);
2608 /* must have at least one frame! */
2610 xfer->td_transfer_last = td;
2614 musbotg_timeout(void *arg)
2616 struct usb_xfer *xfer = arg;
2618 DPRINTFN(1, "xfer=%p\n", xfer);
2620 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2622 /* transfer is transferred */
2623 musbotg_device_done(xfer, USB_ERR_TIMEOUT);
2627 musbotg_ep_int_set(struct musbotg_softc *sc, int channel, int on)
2632 * Only enable the endpoint interrupt when we are
2633 * actually waiting for data, hence we are dealing
2634 * with level triggered interrupts !
2636 DPRINTFN(1, "ep_no=%d, on=%d\n", channel, on);
2642 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2644 temp |= MUSB2_MASK_EPINT(0);
2646 temp &= ~MUSB2_MASK_EPINT(0);
2648 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2650 temp = MUSB2_READ_2(sc, MUSB2_REG_INTRXE);
2652 temp |= MUSB2_MASK_EPINT(channel);
2654 temp &= ~MUSB2_MASK_EPINT(channel);
2655 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, temp);
2657 temp = MUSB2_READ_2(sc, MUSB2_REG_INTTXE);
2659 temp |= MUSB2_MASK_EPINT(channel);
2661 temp &= ~MUSB2_MASK_EPINT(channel);
2662 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, temp);
2665 if (sc->sc_ep_int_set)
2666 sc->sc_ep_int_set(sc, channel, on);
2670 musbotg_start_standard_chain(struct usb_xfer *xfer)
2675 if (musbotg_xfer_do_fifo(xfer)) {
2677 DPRINTFN(14, "enabled interrupts on endpoint\n");
2679 /* put transfer on interrupt queue */
2680 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2682 /* start timeout, if any */
2683 if (xfer->timeout != 0) {
2684 usbd_transfer_timeout_ms(xfer,
2685 &musbotg_timeout, xfer->timeout);
2691 musbotg_root_intr(struct musbotg_softc *sc)
2695 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2698 sc->sc_hub_idata[0] = 0x02; /* we only have one port */
2700 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2701 sizeof(sc->sc_hub_idata));
2705 musbotg_standard_done_sub(struct usb_xfer *xfer)
2707 struct musbotg_td *td;
2713 td = xfer->td_transfer_cache;
2716 len = td->remainder;
2718 xfer->endpoint->toggle_next = td->toggle;
2720 if (xfer->aframes != xfer->nframes) {
2722 * Verify the length and subtract
2723 * the remainder from "frlengths[]":
2725 if (len > xfer->frlengths[xfer->aframes]) {
2728 xfer->frlengths[xfer->aframes] -= len;
2731 /* Check for transfer error */
2733 /* the transfer is finished */
2738 /* Check for short transfer */
2740 if (xfer->flags_int.short_frames_ok ||
2741 xfer->flags_int.isochronous_xfr) {
2742 /* follow alt next */
2749 /* the transfer is finished */
2757 /* this USB frame is complete */
2763 /* update transfer cache */
2765 xfer->td_transfer_cache = td;
2768 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
2772 musbotg_standard_done(struct usb_xfer *xfer)
2774 usb_error_t err = 0;
2776 DPRINTFN(12, "xfer=%p endpoint=%p transfer done\n",
2777 xfer, xfer->endpoint);
2781 xfer->td_transfer_cache = xfer->td_transfer_first;
2783 if (xfer->flags_int.control_xfr) {
2785 if (xfer->flags_int.control_hdr) {
2787 err = musbotg_standard_done_sub(xfer);
2791 if (xfer->td_transfer_cache == NULL) {
2795 while (xfer->aframes != xfer->nframes) {
2797 err = musbotg_standard_done_sub(xfer);
2800 if (xfer->td_transfer_cache == NULL) {
2805 if (xfer->flags_int.control_xfr &&
2806 !xfer->flags_int.control_act) {
2808 err = musbotg_standard_done_sub(xfer);
2811 musbotg_device_done(xfer, err);
2814 /*------------------------------------------------------------------------*
2815 * musbotg_device_done
2817 * NOTE: this function can be called more than one time on the
2818 * same USB transfer!
2819 *------------------------------------------------------------------------*/
2821 musbotg_device_done(struct usb_xfer *xfer, usb_error_t error)
2823 struct musbotg_td *td;
2824 struct musbotg_softc *sc;
2826 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2828 DPRINTFN(1, "xfer=%p, endpoint=%p, error=%d\n",
2829 xfer, xfer->endpoint, error);
2831 DPRINTFN(14, "disabled interrupts on endpoint\n");
2833 sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
2834 td = xfer->td_transfer_cache;
2836 if (td && (td->channel != -1))
2837 musbotg_channel_free(sc, td);
2839 /* dequeue transfer and start next transfer */
2840 usbd_transfer_done(xfer, error);
2844 musbotg_xfer_stall(struct usb_xfer *xfer)
2846 musbotg_device_done(xfer, USB_ERR_STALLED);
2850 musbotg_set_stall(struct usb_device *udev,
2851 struct usb_endpoint *ep, uint8_t *did_stall)
2853 struct musbotg_softc *sc;
2856 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2858 DPRINTFN(4, "endpoint=%p\n", ep);
2860 /* set FORCESTALL */
2861 sc = MUSBOTG_BUS2SC(udev->bus);
2863 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2865 /* select endpoint */
2866 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2868 if (ep->edesc->bEndpointAddress & UE_DIR_IN) {
2869 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2870 MUSB2_MASK_CSRL_TXSENDSTALL);
2872 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2873 MUSB2_MASK_CSRL_RXSENDSTALL);
2878 musbotg_clear_stall_sub(struct musbotg_softc *sc, uint16_t wMaxPacket,
2879 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2885 if (ep_type == UE_CONTROL) {
2886 /* clearing stall is not needed */
2889 /* select endpoint */
2890 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, ep_no);
2892 /* compute max frame size */
2893 mps = wMaxPacket & 0x7FF;
2894 switch ((wMaxPacket >> 11) & 3) {
2905 if (ep_dir == UE_DIR_IN) {
2909 /* Configure endpoint */
2912 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2913 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2914 MUSB2_MASK_CSRH_TXMODE | temp);
2916 case UE_ISOCHRONOUS:
2917 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2918 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2919 MUSB2_MASK_CSRH_TXMODE |
2920 MUSB2_MASK_CSRH_TXISO | temp);
2923 MUSB2_WRITE_2(sc, MUSB2_REG_TXMAXP, wMaxPacket);
2924 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRH,
2925 MUSB2_MASK_CSRH_TXMODE | temp);
2931 /* Need to flush twice in case of double bufring */
2932 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2933 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2934 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2935 MUSB2_MASK_CSRL_TXFFLUSH);
2936 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2937 if (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) {
2938 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2939 MUSB2_MASK_CSRL_TXFFLUSH);
2940 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2943 /* reset data toggle */
2944 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL,
2945 MUSB2_MASK_CSRL_TXDT_CLR);
2946 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2947 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2949 /* set double/single buffering */
2950 temp = MUSB2_READ_2(sc, MUSB2_REG_TXDBDIS);
2951 if (mps <= (sc->sc_hw_ep_profile[ep_no].
2952 max_in_frame_size / 2)) {
2954 temp &= ~(1 << ep_no);
2957 temp |= (1 << ep_no);
2959 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, temp);
2961 /* clear sent stall */
2962 if (csr & MUSB2_MASK_CSRL_TXSENTSTALL) {
2963 MUSB2_WRITE_1(sc, MUSB2_REG_TXCSRL, 0);
2964 csr = MUSB2_READ_1(sc, MUSB2_REG_TXCSRL);
2970 /* Configure endpoint */
2973 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2974 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2975 MUSB2_MASK_CSRH_RXNYET | temp);
2977 case UE_ISOCHRONOUS:
2978 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2979 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH,
2980 MUSB2_MASK_CSRH_RXNYET |
2981 MUSB2_MASK_CSRH_RXISO | temp);
2984 MUSB2_WRITE_2(sc, MUSB2_REG_RXMAXP, wMaxPacket);
2985 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRH, temp);
2991 /* Need to flush twice in case of double bufring */
2992 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2993 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2994 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2995 MUSB2_MASK_CSRL_RXFFLUSH);
2996 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
2997 if (csr & MUSB2_MASK_CSRL_RXPKTRDY) {
2998 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
2999 MUSB2_MASK_CSRL_RXFFLUSH);
3000 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3003 /* reset data toggle */
3004 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL,
3005 MUSB2_MASK_CSRL_RXDT_CLR);
3006 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3007 csr = MUSB2_READ_1(sc, MUSB2_REG_RXCSRL);
3009 /* set double/single buffering */
3010 temp = MUSB2_READ_2(sc, MUSB2_REG_RXDBDIS);
3011 if (mps <= (sc->sc_hw_ep_profile[ep_no].
3012 max_out_frame_size / 2)) {
3014 temp &= ~(1 << ep_no);
3017 temp |= (1 << ep_no);
3019 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, temp);
3021 /* clear sent stall */
3022 if (csr & MUSB2_MASK_CSRL_RXSENTSTALL) {
3023 MUSB2_WRITE_1(sc, MUSB2_REG_RXCSRL, 0);
3029 musbotg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3031 struct musbotg_softc *sc;
3032 struct usb_endpoint_descriptor *ed;
3034 DPRINTFN(4, "endpoint=%p\n", ep);
3036 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
3039 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
3044 sc = MUSBOTG_BUS2SC(udev->bus);
3046 /* get endpoint descriptor */
3049 /* reset endpoint */
3050 musbotg_clear_stall_sub(sc,
3051 UGETW(ed->wMaxPacketSize),
3052 (ed->bEndpointAddress & UE_ADDR),
3053 (ed->bmAttributes & UE_XFERTYPE),
3054 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
3058 musbotg_init(struct musbotg_softc *sc)
3060 struct usb_hw_ep_profile *pf;
3070 DPRINTFN(1, "start\n");
3072 /* set up the bus structure */
3073 sc->sc_bus.usbrev = USB_REV_2_0;
3074 sc->sc_bus.methods = &musbotg_bus_methods;
3076 USB_BUS_LOCK(&sc->sc_bus);
3078 /* turn on clocks */
3080 if (sc->sc_clocks_on) {
3081 (sc->sc_clocks_on) (sc->sc_clocks_arg);
3084 /* wait a little for things to stabilise */
3085 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
3087 /* disable all interrupts */
3089 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3090 DPRINTF("pre-DEVCTL=0x%02x\n", temp);
3092 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3093 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3094 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3096 /* disable pullup */
3098 musbotg_pull_common(sc, 0);
3100 /* wait a little bit (10ms) */
3101 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
3104 /* disable double packet buffering */
3105 MUSB2_WRITE_2(sc, MUSB2_REG_RXDBDIS, 0xFFFF);
3106 MUSB2_WRITE_2(sc, MUSB2_REG_TXDBDIS, 0xFFFF);
3108 /* enable HighSpeed and ISO Update flags */
3110 MUSB2_WRITE_1(sc, MUSB2_REG_POWER,
3111 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD);
3113 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
3114 /* clear Session bit, if set */
3115 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3116 temp &= ~MUSB2_MASK_SESS;
3117 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3119 /* Enter session for Host mode */
3120 temp = MUSB2_READ_1(sc, MUSB2_REG_DEVCTL);
3121 temp |= MUSB2_MASK_SESS;
3122 MUSB2_WRITE_1(sc, MUSB2_REG_DEVCTL, temp);
3125 /* wait a little for things to stabilise */
3126 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
3128 DPRINTF("DEVCTL=0x%02x\n", temp);
3130 /* disable testmode */
3132 MUSB2_WRITE_1(sc, MUSB2_REG_TESTMODE, 0);
3134 /* set default value */
3136 MUSB2_WRITE_1(sc, MUSB2_REG_MISC, 0);
3138 /* select endpoint index 0 */
3140 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, 0);
3142 /* read out number of endpoints */
3145 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) / 16);
3148 (MUSB2_READ_1(sc, MUSB2_REG_EPINFO) % 16);
3150 /* these numbers exclude the control endpoint */
3152 DPRINTFN(2, "RX/TX endpoints: %u/%u\n", nrx, ntx);
3154 sc->sc_ep_max = (nrx > ntx) ? nrx : ntx;
3155 if (sc->sc_ep_max == 0) {
3156 DPRINTFN(2, "ERROR: Looks like the clocks are off!\n");
3158 /* read out configuration data */
3160 sc->sc_conf_data = MUSB2_READ_1(sc, MUSB2_REG_CONFDATA);
3162 DPRINTFN(2, "Config Data: 0x%02x\n",
3165 dynfifo = (sc->sc_conf_data & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0;
3168 device_printf(sc->sc_bus.bdev, "Dynamic FIFO sizing detected, "
3169 "assuming 16Kbytes of FIFO RAM\n");
3172 DPRINTFN(2, "HW version: 0x%04x\n",
3173 MUSB2_READ_1(sc, MUSB2_REG_HWVERS));
3175 /* initialise endpoint profiles */
3179 for (temp = 1; temp <= sc->sc_ep_max; temp++) {
3180 pf = sc->sc_hw_ep_profile + temp;
3182 /* select endpoint */
3183 MUSB2_WRITE_1(sc, MUSB2_REG_EPINDEX, temp);
3185 fsize = MUSB2_READ_1(sc, MUSB2_REG_FSIZE);
3186 frx = (fsize & MUSB2_MASK_RX_FSIZE) / 16;
3187 ftx = (fsize & MUSB2_MASK_TX_FSIZE);
3189 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n",
3190 temp, ftx, frx, dynfifo);
3193 if (frx && (temp <= nrx)) {
3196 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3197 MUSB2_VAL_FIFOSZ_4096 |
3199 } else if (temp < 8) {
3201 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3202 MUSB2_VAL_FIFOSZ_512 |
3205 frx = 7; /* 128 bytes */
3206 MUSB2_WRITE_1(sc, MUSB2_REG_RXFIFOSZ,
3207 MUSB2_VAL_FIFOSZ_128);
3210 MUSB2_WRITE_2(sc, MUSB2_REG_RXFIFOADD,
3213 offset += (1 << frx);
3215 if (ftx && (temp <= ntx)) {
3218 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3219 MUSB2_VAL_FIFOSZ_4096 |
3221 } else if (temp < 8) {
3223 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3224 MUSB2_VAL_FIFOSZ_512 |
3227 ftx = 7; /* 128 bytes */
3228 MUSB2_WRITE_1(sc, MUSB2_REG_TXFIFOSZ,
3229 MUSB2_VAL_FIFOSZ_128);
3232 MUSB2_WRITE_2(sc, MUSB2_REG_TXFIFOADD,
3235 offset += (1 << ftx);
3239 if (frx && ftx && (temp <= nrx) && (temp <= ntx)) {
3240 pf->max_in_frame_size = 1 << ftx;
3241 pf->max_out_frame_size = 1 << frx;
3242 pf->is_simplex = 0; /* duplex */
3243 pf->support_multi_buffer = 1;
3244 pf->support_bulk = 1;
3245 pf->support_interrupt = 1;
3246 pf->support_isochronous = 1;
3248 pf->support_out = 1;
3249 } else if (frx && (temp <= nrx)) {
3250 pf->max_out_frame_size = 1 << frx;
3251 pf->max_in_frame_size = 0;
3252 pf->is_simplex = 1; /* simplex */
3253 pf->support_multi_buffer = 1;
3254 pf->support_bulk = 1;
3255 pf->support_interrupt = 1;
3256 pf->support_isochronous = 1;
3257 pf->support_out = 1;
3258 } else if (ftx && (temp <= ntx)) {
3259 pf->max_in_frame_size = 1 << ftx;
3260 pf->max_out_frame_size = 0;
3261 pf->is_simplex = 1; /* simplex */
3262 pf->support_multi_buffer = 1;
3263 pf->support_bulk = 1;
3264 pf->support_interrupt = 1;
3265 pf->support_isochronous = 1;
3270 DPRINTFN(2, "Dynamic FIFO size = %d bytes\n", offset);
3272 /* turn on default interrupts */
3274 if (sc->sc_mode == MUSB2_HOST_MODE)
3275 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0xff);
3277 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE,
3280 musbotg_clocks_off(sc);
3282 USB_BUS_UNLOCK(&sc->sc_bus);
3284 /* catch any lost interrupts */
3286 musbotg_do_poll(&sc->sc_bus);
3288 return (0); /* success */
3292 musbotg_uninit(struct musbotg_softc *sc)
3294 USB_BUS_LOCK(&sc->sc_bus);
3296 /* disable all interrupts */
3297 MUSB2_WRITE_1(sc, MUSB2_REG_INTUSBE, 0);
3298 MUSB2_WRITE_2(sc, MUSB2_REG_INTTXE, 0);
3299 MUSB2_WRITE_2(sc, MUSB2_REG_INTRXE, 0);
3301 sc->sc_flags.port_powered = 0;
3302 sc->sc_flags.status_vbus = 0;
3303 sc->sc_flags.status_bus_reset = 0;
3304 sc->sc_flags.status_suspend = 0;
3305 sc->sc_flags.change_suspend = 0;
3306 sc->sc_flags.change_connect = 1;
3308 musbotg_pull_down(sc);
3309 musbotg_clocks_off(sc);
3310 USB_BUS_UNLOCK(&sc->sc_bus);
3314 musbotg_do_poll(struct usb_bus *bus)
3316 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
3318 USB_BUS_LOCK(&sc->sc_bus);
3319 musbotg_interrupt_poll(sc);
3320 USB_BUS_UNLOCK(&sc->sc_bus);
3323 /*------------------------------------------------------------------------*
3324 * musbotg bulk support
3325 *------------------------------------------------------------------------*/
3327 musbotg_device_bulk_open(struct usb_xfer *xfer)
3333 musbotg_device_bulk_close(struct usb_xfer *xfer)
3335 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3339 musbotg_device_bulk_enter(struct usb_xfer *xfer)
3345 musbotg_device_bulk_start(struct usb_xfer *xfer)
3348 musbotg_setup_standard_chain(xfer);
3349 musbotg_start_standard_chain(xfer);
3352 static const struct usb_pipe_methods musbotg_device_bulk_methods =
3354 .open = musbotg_device_bulk_open,
3355 .close = musbotg_device_bulk_close,
3356 .enter = musbotg_device_bulk_enter,
3357 .start = musbotg_device_bulk_start,
3360 /*------------------------------------------------------------------------*
3361 * musbotg control support
3362 *------------------------------------------------------------------------*/
3364 musbotg_device_ctrl_open(struct usb_xfer *xfer)
3370 musbotg_device_ctrl_close(struct usb_xfer *xfer)
3372 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3376 musbotg_device_ctrl_enter(struct usb_xfer *xfer)
3382 musbotg_device_ctrl_start(struct usb_xfer *xfer)
3385 musbotg_setup_standard_chain(xfer);
3386 musbotg_start_standard_chain(xfer);
3389 static const struct usb_pipe_methods musbotg_device_ctrl_methods =
3391 .open = musbotg_device_ctrl_open,
3392 .close = musbotg_device_ctrl_close,
3393 .enter = musbotg_device_ctrl_enter,
3394 .start = musbotg_device_ctrl_start,
3397 /*------------------------------------------------------------------------*
3398 * musbotg interrupt support
3399 *------------------------------------------------------------------------*/
3401 musbotg_device_intr_open(struct usb_xfer *xfer)
3407 musbotg_device_intr_close(struct usb_xfer *xfer)
3409 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3413 musbotg_device_intr_enter(struct usb_xfer *xfer)
3419 musbotg_device_intr_start(struct usb_xfer *xfer)
3422 musbotg_setup_standard_chain(xfer);
3423 musbotg_start_standard_chain(xfer);
3426 static const struct usb_pipe_methods musbotg_device_intr_methods =
3428 .open = musbotg_device_intr_open,
3429 .close = musbotg_device_intr_close,
3430 .enter = musbotg_device_intr_enter,
3431 .start = musbotg_device_intr_start,
3434 /*------------------------------------------------------------------------*
3435 * musbotg full speed isochronous support
3436 *------------------------------------------------------------------------*/
3438 musbotg_device_isoc_open(struct usb_xfer *xfer)
3444 musbotg_device_isoc_close(struct usb_xfer *xfer)
3446 musbotg_device_done(xfer, USB_ERR_CANCELLED);
3450 musbotg_device_isoc_enter(struct usb_xfer *xfer)
3452 struct musbotg_softc *sc = MUSBOTG_BUS2SC(xfer->xroot->bus);
3457 DPRINTFN(5, "xfer=%p next=%d nframes=%d\n",
3458 xfer, xfer->endpoint->isoc_next, xfer->nframes);
3460 /* get the current frame index */
3462 nframes = MUSB2_READ_2(sc, MUSB2_REG_FRAME);
3465 * check if the frame index is within the window where the frames
3468 temp = (nframes - xfer->endpoint->isoc_next) & MUSB2_MASK_FRAME;
3470 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
3471 fs_frames = (xfer->nframes + 7) / 8;
3473 fs_frames = xfer->nframes;
3476 if ((xfer->endpoint->is_synced == 0) ||
3477 (temp < fs_frames)) {
3479 * If there is data underflow or the pipe queue is
3480 * empty we schedule the transfer a few frames ahead
3481 * of the current frame position. Else two isochronous
3482 * transfers might overlap.
3484 xfer->endpoint->isoc_next = (nframes + 3) & MUSB2_MASK_FRAME;
3485 xfer->endpoint->is_synced = 1;
3486 DPRINTFN(2, "start next=%d\n", xfer->endpoint->isoc_next);
3489 * compute how many milliseconds the insertion is ahead of the
3490 * current frame position:
3492 temp = (xfer->endpoint->isoc_next - nframes) & MUSB2_MASK_FRAME;
3495 * pre-compute when the isochronous transfer will be finished:
3497 xfer->isoc_time_complete =
3498 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
3501 /* compute frame number for next insertion */
3502 xfer->endpoint->isoc_next += fs_frames;
3505 musbotg_setup_standard_chain(xfer);
3509 musbotg_device_isoc_start(struct usb_xfer *xfer)
3511 /* start TD chain */
3512 musbotg_start_standard_chain(xfer);
3515 static const struct usb_pipe_methods musbotg_device_isoc_methods =
3517 .open = musbotg_device_isoc_open,
3518 .close = musbotg_device_isoc_close,
3519 .enter = musbotg_device_isoc_enter,
3520 .start = musbotg_device_isoc_start,
3523 /*------------------------------------------------------------------------*
3524 * musbotg root control support
3525 *------------------------------------------------------------------------*
3526 * Simulate a hardware HUB by handling all the necessary requests.
3527 *------------------------------------------------------------------------*/
3529 static const struct usb_device_descriptor musbotg_devd = {
3530 .bLength = sizeof(struct usb_device_descriptor),
3531 .bDescriptorType = UDESC_DEVICE,
3532 .bcdUSB = {0x00, 0x02},
3533 .bDeviceClass = UDCLASS_HUB,
3534 .bDeviceSubClass = UDSUBCLASS_HUB,
3535 .bDeviceProtocol = UDPROTO_HSHUBSTT,
3536 .bMaxPacketSize = 64,
3537 .bcdDevice = {0x00, 0x01},
3540 .bNumConfigurations = 1,
3543 static const struct usb_device_qualifier musbotg_odevd = {
3544 .bLength = sizeof(struct usb_device_qualifier),
3545 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
3546 .bcdUSB = {0x00, 0x02},
3547 .bDeviceClass = UDCLASS_HUB,
3548 .bDeviceSubClass = UDSUBCLASS_HUB,
3549 .bDeviceProtocol = UDPROTO_FSHUB,
3550 .bMaxPacketSize0 = 0,
3551 .bNumConfigurations = 0,
3554 static const struct musbotg_config_desc musbotg_confd = {
3556 .bLength = sizeof(struct usb_config_descriptor),
3557 .bDescriptorType = UDESC_CONFIG,
3558 .wTotalLength[0] = sizeof(musbotg_confd),
3560 .bConfigurationValue = 1,
3561 .iConfiguration = 0,
3562 .bmAttributes = UC_SELF_POWERED,
3566 .bLength = sizeof(struct usb_interface_descriptor),
3567 .bDescriptorType = UDESC_INTERFACE,
3569 .bInterfaceClass = UICLASS_HUB,
3570 .bInterfaceSubClass = UISUBCLASS_HUB,
3571 .bInterfaceProtocol = 0,
3574 .bLength = sizeof(struct usb_endpoint_descriptor),
3575 .bDescriptorType = UDESC_ENDPOINT,
3576 .bEndpointAddress = (UE_DIR_IN | MUSBOTG_INTR_ENDPT),
3577 .bmAttributes = UE_INTERRUPT,
3578 .wMaxPacketSize[0] = 8,
3583 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3585 static const struct usb_hub_descriptor_min musbotg_hubd = {
3586 .bDescLength = sizeof(musbotg_hubd),
3587 .bDescriptorType = UDESC_HUB,
3589 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
3590 .bPwrOn2PwrGood = 50,
3591 .bHubContrCurrent = 0,
3592 .DeviceRemovable = {0}, /* port is removable */
3595 #define STRING_VENDOR \
3596 "M\0e\0n\0t\0o\0r\0 \0G\0r\0a\0p\0h\0i\0c\0s"
3598 #define STRING_PRODUCT \
3599 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B"
3601 USB_MAKE_STRING_DESC(STRING_VENDOR, musbotg_vendor);
3602 USB_MAKE_STRING_DESC(STRING_PRODUCT, musbotg_product);
3605 musbotg_roothub_exec(struct usb_device *udev,
3606 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3608 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
3616 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3619 ptr = (const void *)&sc->sc_hub_temp;
3623 value = UGETW(req->wValue);
3624 index = UGETW(req->wIndex);
3626 /* demultiplex the control request */
3628 switch (req->bmRequestType) {
3629 case UT_READ_DEVICE:
3630 switch (req->bRequest) {
3631 case UR_GET_DESCRIPTOR:
3632 goto tr_handle_get_descriptor;
3634 goto tr_handle_get_config;
3636 goto tr_handle_get_status;
3642 case UT_WRITE_DEVICE:
3643 switch (req->bRequest) {
3644 case UR_SET_ADDRESS:
3645 goto tr_handle_set_address;
3647 goto tr_handle_set_config;
3648 case UR_CLEAR_FEATURE:
3649 goto tr_valid; /* nop */
3650 case UR_SET_DESCRIPTOR:
3651 goto tr_valid; /* nop */
3652 case UR_SET_FEATURE:
3658 case UT_WRITE_ENDPOINT:
3659 switch (req->bRequest) {
3660 case UR_CLEAR_FEATURE:
3661 switch (UGETW(req->wValue)) {
3662 case UF_ENDPOINT_HALT:
3663 goto tr_handle_clear_halt;
3664 case UF_DEVICE_REMOTE_WAKEUP:
3665 goto tr_handle_clear_wakeup;
3670 case UR_SET_FEATURE:
3671 switch (UGETW(req->wValue)) {
3672 case UF_ENDPOINT_HALT:
3673 goto tr_handle_set_halt;
3674 case UF_DEVICE_REMOTE_WAKEUP:
3675 goto tr_handle_set_wakeup;
3680 case UR_SYNCH_FRAME:
3681 goto tr_valid; /* nop */
3687 case UT_READ_ENDPOINT:
3688 switch (req->bRequest) {
3690 goto tr_handle_get_ep_status;
3696 case UT_WRITE_INTERFACE:
3697 switch (req->bRequest) {
3698 case UR_SET_INTERFACE:
3699 goto tr_handle_set_interface;
3700 case UR_CLEAR_FEATURE:
3701 goto tr_valid; /* nop */
3702 case UR_SET_FEATURE:
3708 case UT_READ_INTERFACE:
3709 switch (req->bRequest) {
3710 case UR_GET_INTERFACE:
3711 goto tr_handle_get_interface;
3713 goto tr_handle_get_iface_status;
3719 case UT_WRITE_CLASS_INTERFACE:
3720 case UT_WRITE_VENDOR_INTERFACE:
3724 case UT_READ_CLASS_INTERFACE:
3725 case UT_READ_VENDOR_INTERFACE:
3729 case UT_WRITE_CLASS_DEVICE:
3730 switch (req->bRequest) {
3731 case UR_CLEAR_FEATURE:
3733 case UR_SET_DESCRIPTOR:
3734 case UR_SET_FEATURE:
3741 case UT_WRITE_CLASS_OTHER:
3742 switch (req->bRequest) {
3743 case UR_CLEAR_FEATURE:
3744 goto tr_handle_clear_port_feature;
3745 case UR_SET_FEATURE:
3746 goto tr_handle_set_port_feature;
3747 case UR_CLEAR_TT_BUFFER:
3757 case UT_READ_CLASS_OTHER:
3758 switch (req->bRequest) {
3759 case UR_GET_TT_STATE:
3760 goto tr_handle_get_tt_state;
3762 goto tr_handle_get_port_status;
3768 case UT_READ_CLASS_DEVICE:
3769 switch (req->bRequest) {
3770 case UR_GET_DESCRIPTOR:
3771 goto tr_handle_get_class_descriptor;
3773 goto tr_handle_get_class_status;
3784 tr_handle_get_descriptor:
3785 switch (value >> 8) {
3790 len = sizeof(musbotg_devd);
3791 ptr = (const void *)&musbotg_devd;
3793 case UDESC_DEVICE_QUALIFIER:
3797 len = sizeof(musbotg_odevd);
3798 ptr = (const void *)&musbotg_odevd;
3804 len = sizeof(musbotg_confd);
3805 ptr = (const void *)&musbotg_confd;
3808 switch (value & 0xff) {
3809 case 0: /* Language table */
3810 len = sizeof(usb_string_lang_en);
3811 ptr = (const void *)&usb_string_lang_en;
3814 case 1: /* Vendor */
3815 len = sizeof(musbotg_vendor);
3816 ptr = (const void *)&musbotg_vendor;
3819 case 2: /* Product */
3820 len = sizeof(musbotg_product);
3821 ptr = (const void *)&musbotg_product;
3832 tr_handle_get_config:
3834 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3837 tr_handle_get_status:
3839 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3842 tr_handle_set_address:
3843 if (value & 0xFF00) {
3846 sc->sc_rt_addr = value;
3849 tr_handle_set_config:
3853 sc->sc_conf = value;
3856 tr_handle_get_interface:
3858 sc->sc_hub_temp.wValue[0] = 0;
3861 tr_handle_get_tt_state:
3862 tr_handle_get_class_status:
3863 tr_handle_get_iface_status:
3864 tr_handle_get_ep_status:
3866 USETW(sc->sc_hub_temp.wValue, 0);
3870 tr_handle_set_interface:
3871 tr_handle_set_wakeup:
3872 tr_handle_clear_wakeup:
3873 tr_handle_clear_halt:
3876 tr_handle_clear_port_feature:
3880 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
3883 case UHF_PORT_SUSPEND:
3884 if (sc->sc_mode == MUSB2_HOST_MODE)
3885 musbotg_wakeup_host(sc);
3887 musbotg_wakeup_peer(sc);
3890 case UHF_PORT_ENABLE:
3891 sc->sc_flags.port_enabled = 0;
3894 case UHF_C_PORT_ENABLE:
3895 sc->sc_flags.change_enabled = 0;
3898 case UHF_C_PORT_OVER_CURRENT:
3899 sc->sc_flags.change_over_current = 0;
3902 case UHF_C_PORT_RESET:
3903 sc->sc_flags.change_reset = 0;
3907 case UHF_PORT_INDICATOR:
3911 case UHF_PORT_POWER:
3912 sc->sc_flags.port_powered = 0;
3913 musbotg_pull_down(sc);
3914 musbotg_clocks_off(sc);
3916 case UHF_C_PORT_CONNECTION:
3917 sc->sc_flags.change_connect = 0;
3919 case UHF_C_PORT_SUSPEND:
3920 sc->sc_flags.change_suspend = 0;
3923 err = USB_ERR_IOERROR;
3928 tr_handle_set_port_feature:
3932 DPRINTFN(8, "UR_SET_PORT_FEATURE\n");
3935 case UHF_PORT_ENABLE:
3936 sc->sc_flags.port_enabled = 1;
3938 case UHF_PORT_SUSPEND:
3939 if (sc->sc_mode == MUSB2_HOST_MODE)
3940 musbotg_suspend_host(sc);
3943 case UHF_PORT_RESET:
3944 if (sc->sc_mode == MUSB2_HOST_MODE) {
3945 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3946 reg |= MUSB2_MASK_RESET;
3947 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3949 /* Wait for 20 msec */
3950 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 5);
3952 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3953 reg &= ~MUSB2_MASK_RESET;
3954 MUSB2_WRITE_1(sc, MUSB2_REG_POWER, reg);
3956 /* determine line speed */
3957 reg = MUSB2_READ_1(sc, MUSB2_REG_POWER);
3958 if (reg & MUSB2_MASK_HSMODE)
3959 sc->sc_flags.status_high_speed = 1;
3961 sc->sc_flags.status_high_speed = 0;
3963 sc->sc_flags.change_reset = 1;
3965 err = USB_ERR_IOERROR;
3969 case UHF_PORT_INDICATOR:
3972 case UHF_PORT_POWER:
3973 sc->sc_flags.port_powered = 1;
3976 err = USB_ERR_IOERROR;
3981 tr_handle_get_port_status:
3983 DPRINTFN(8, "UR_GET_PORT_STATUS\n");
3988 if (sc->sc_flags.status_vbus) {
3989 musbotg_clocks_on(sc);
3990 musbotg_pull_up(sc);
3992 musbotg_pull_down(sc);
3993 musbotg_clocks_off(sc);
3996 /* Select Device Side Mode */
3997 if (sc->sc_mode == MUSB2_DEVICE_MODE)
3998 value = UPS_PORT_MODE_DEVICE;
4002 if (sc->sc_flags.status_high_speed) {
4003 value |= UPS_HIGH_SPEED;
4005 if (sc->sc_flags.port_powered) {
4006 value |= UPS_PORT_POWER;
4008 if (sc->sc_flags.port_enabled) {
4009 value |= UPS_PORT_ENABLED;
4012 if (sc->sc_flags.port_over_current)
4013 value |= UPS_OVERCURRENT_INDICATOR;
4015 if (sc->sc_flags.status_vbus &&
4016 sc->sc_flags.status_bus_reset) {
4017 value |= UPS_CURRENT_CONNECT_STATUS;
4019 if (sc->sc_flags.status_suspend) {
4020 value |= UPS_SUSPEND;
4022 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
4026 if (sc->sc_flags.change_connect) {
4027 value |= UPS_C_CONNECT_STATUS;
4029 if (sc->sc_mode == MUSB2_DEVICE_MODE) {
4030 if (sc->sc_flags.status_vbus &&
4031 sc->sc_flags.status_bus_reset) {
4032 /* reset EP0 state */
4033 sc->sc_ep0_busy = 0;
4038 if (sc->sc_flags.change_suspend)
4039 value |= UPS_C_SUSPEND;
4040 if (sc->sc_flags.change_reset)
4041 value |= UPS_C_PORT_RESET;
4042 if (sc->sc_flags.change_over_current)
4043 value |= UPS_C_OVERCURRENT_INDICATOR;
4045 USETW(sc->sc_hub_temp.ps.wPortChange, value);
4046 len = sizeof(sc->sc_hub_temp.ps);
4049 tr_handle_get_class_descriptor:
4053 ptr = (const void *)&musbotg_hubd;
4054 len = sizeof(musbotg_hubd);
4058 err = USB_ERR_STALLED;
4067 musbotg_xfer_setup(struct usb_setup_params *parm)
4069 struct musbotg_softc *sc;
4070 struct usb_xfer *xfer;
4076 sc = MUSBOTG_BUS2SC(parm->udev->bus);
4077 xfer = parm->curr_xfer;
4080 * NOTE: This driver does not use any of the parameters that
4081 * are computed from the following values. Just set some
4082 * reasonable dummies:
4084 parm->hc_max_packet_size = 0x400;
4085 parm->hc_max_frame_size = 0xc00;
4087 if ((parm->methods == &musbotg_device_isoc_methods) ||
4088 (parm->methods == &musbotg_device_intr_methods))
4089 parm->hc_max_packet_count = 3;
4091 parm->hc_max_packet_count = 1;
4093 usbd_transfer_setup_sub(parm);
4096 * compute maximum number of TDs
4098 if (parm->methods == &musbotg_device_ctrl_methods) {
4100 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
4102 } else if (parm->methods == &musbotg_device_bulk_methods) {
4104 ntd = xfer->nframes + 1 /* SYNC */ ;
4106 } else if (parm->methods == &musbotg_device_intr_methods) {
4108 ntd = xfer->nframes + 1 /* SYNC */ ;
4110 } else if (parm->methods == &musbotg_device_isoc_methods) {
4112 ntd = xfer->nframes + 1 /* SYNC */ ;
4120 * check if "usbd_transfer_setup_sub" set an error
4126 * allocate transfer descriptors
4130 ep_no = xfer->endpointno & UE_ADDR;
4133 * Check for a valid endpoint profile in USB device mode:
4135 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
4136 const struct usb_hw_ep_profile *pf;
4138 musbotg_get_hw_ep_profile(parm->udev, &pf, ep_no);
4141 /* should not happen */
4142 parm->err = USB_ERR_INVAL;
4148 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
4150 for (n = 0; n != ntd; n++) {
4152 struct musbotg_td *td;
4156 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
4159 td->max_frame_size = xfer->max_frame_size;
4160 td->reg_max_packet = xfer->max_packet_size |
4161 ((xfer->max_packet_count - 1) << 11);
4163 td->obj_next = last_obj;
4167 parm->size[0] += sizeof(*td);
4170 xfer->td_start[0] = last_obj;
4174 musbotg_xfer_unsetup(struct usb_xfer *xfer)
4180 musbotg_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4182 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4184 if (sc->sc_mode == MUSB2_HOST_MODE)
4185 *pus = 2000; /* microseconds */
4191 musbotg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4192 struct usb_endpoint *ep)
4194 struct musbotg_softc *sc = MUSBOTG_BUS2SC(udev->bus);
4196 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
4198 edesc->bEndpointAddress, udev->flags.usb_mode,
4201 if (udev->device_index != sc->sc_rt_addr) {
4202 switch (edesc->bmAttributes & UE_XFERTYPE) {
4204 ep->methods = &musbotg_device_ctrl_methods;
4207 ep->methods = &musbotg_device_intr_methods;
4209 case UE_ISOCHRONOUS:
4210 ep->methods = &musbotg_device_isoc_methods;
4213 ep->methods = &musbotg_device_bulk_methods;
4223 musbotg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
4225 struct musbotg_softc *sc = MUSBOTG_BUS2SC(bus);
4228 case USB_HW_POWER_SUSPEND:
4231 case USB_HW_POWER_SHUTDOWN:
4234 case USB_HW_POWER_RESUME:
4242 static const struct usb_bus_methods musbotg_bus_methods =
4244 .endpoint_init = &musbotg_ep_init,
4245 .get_dma_delay = &musbotg_get_dma_delay,
4246 .xfer_setup = &musbotg_xfer_setup,
4247 .xfer_unsetup = &musbotg_xfer_unsetup,
4248 .get_hw_ep_profile = &musbotg_get_hw_ep_profile,
4249 .xfer_stall = &musbotg_xfer_stall,
4250 .set_stall = &musbotg_set_stall,
4251 .clear_stall = &musbotg_clear_stall,
4252 .roothub_exec = &musbotg_roothub_exec,
4253 .xfer_poll = &musbotg_do_poll,
4254 .set_hw_power_sleep = &musbotg_set_hw_power_sleep,