2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net) at
9 * Carlstedt Research & Technology.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
36 /* PCI config registers */
37 #define PCI_CBMEM 0x10 /* configuration base memory */
38 #define PCI_INTERFACE_OHCI 0x10
41 #define OHCI_REVISION 0x00 /* OHCI revision */
42 #define OHCI_REV_LO(rev) ((rev) & 0xf)
43 #define OHCI_REV_HI(rev) (((rev)>>4) & 0xf)
44 #define OHCI_REV_LEGACY(rev) ((rev) & 0x100)
45 #define OHCI_CONTROL 0x04
46 #define OHCI_CBSR_MASK 0x00000003 /* Control/Bulk Service Ratio */
47 #define OHCI_RATIO_1_1 0x00000000
48 #define OHCI_RATIO_1_2 0x00000001
49 #define OHCI_RATIO_1_3 0x00000002
50 #define OHCI_RATIO_1_4 0x00000003
51 #define OHCI_PLE 0x00000004 /* Periodic List Enable */
52 #define OHCI_IE 0x00000008 /* Isochronous Enable */
53 #define OHCI_CLE 0x00000010 /* Control List Enable */
54 #define OHCI_BLE 0x00000020 /* Bulk List Enable */
55 #define OHCI_HCFS_MASK 0x000000c0 /* HostControllerFunctionalStat
57 #define OHCI_HCFS_RESET 0x00000000
58 #define OHCI_HCFS_RESUME 0x00000040
59 #define OHCI_HCFS_OPERATIONAL 0x00000080
60 #define OHCI_HCFS_SUSPEND 0x000000c0
61 #define OHCI_IR 0x00000100 /* Interrupt Routing */
62 #define OHCI_RWC 0x00000200 /* Remote Wakeup Connected */
63 #define OHCI_RWE 0x00000400 /* Remote Wakeup Enabled */
64 #define OHCI_COMMAND_STATUS 0x08
65 #define OHCI_HCR 0x00000001 /* Host Controller Reset */
66 #define OHCI_CLF 0x00000002 /* Control List Filled */
67 #define OHCI_BLF 0x00000004 /* Bulk List Filled */
68 #define OHCI_OCR 0x00000008 /* Ownership Change Request */
69 #define OHCI_SOC_MASK 0x00030000 /* Scheduling Overrun Count */
70 #define OHCI_INTERRUPT_STATUS 0x0c
71 #define OHCI_SO 0x00000001 /* Scheduling Overrun */
72 #define OHCI_WDH 0x00000002 /* Writeback Done Head */
73 #define OHCI_SF 0x00000004 /* Start of Frame */
74 #define OHCI_RD 0x00000008 /* Resume Detected */
75 #define OHCI_UE 0x00000010 /* Unrecoverable Error */
76 #define OHCI_FNO 0x00000020 /* Frame Number Overflow */
77 #define OHCI_RHSC 0x00000040 /* Root Hub Status Change */
78 #define OHCI_OC 0x40000000 /* Ownership Change */
79 #define OHCI_MIE 0x80000000 /* Master Interrupt Enable */
80 #define OHCI_INTERRUPT_ENABLE 0x10
81 #define OHCI_INTERRUPT_DISABLE 0x14
82 #define OHCI_HCCA 0x18
83 #define OHCI_PERIOD_CURRENT_ED 0x1c
84 #define OHCI_CONTROL_HEAD_ED 0x20
85 #define OHCI_CONTROL_CURRENT_ED 0x24
86 #define OHCI_BULK_HEAD_ED 0x28
87 #define OHCI_BULK_CURRENT_ED 0x2c
88 #define OHCI_DONE_HEAD 0x30
89 #define OHCI_FM_INTERVAL 0x34
90 #define OHCI_GET_IVAL(s) ((s) & 0x3fff)
91 #define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff)
92 #define OHCI_FIT 0x80000000
93 #define OHCI_FM_REMAINING 0x38
94 #define OHCI_FM_NUMBER 0x3c
95 #define OHCI_PERIODIC_START 0x40
96 #define OHCI_LS_THRESHOLD 0x44
97 #define OHCI_RH_DESCRIPTOR_A 0x48
98 #define OHCI_GET_NDP(s) ((s) & 0xff)
99 #define OHCI_PSM 0x0100 /* Power Switching Mode */
100 #define OHCI_NPS 0x0200 /* No Power Switching */
101 #define OHCI_DT 0x0400 /* Device Type */
102 #define OHCI_OCPM 0x0800 /* Overcurrent Protection Mode */
103 #define OHCI_NOCP 0x1000 /* No Overcurrent Protection */
104 #define OHCI_GET_POTPGT(s) ((s) >> 24)
105 #define OHCI_RH_DESCRIPTOR_B 0x4c
106 #define OHCI_RH_STATUS 0x50
107 #define OHCI_LPS 0x00000001 /* Local Power Status */
108 #define OHCI_OCI 0x00000002 /* OverCurrent Indicator */
109 #define OHCI_DRWE 0x00008000 /* Device Remote Wakeup Enable */
110 #define OHCI_LPSC 0x00010000 /* Local Power Status Change */
111 #define OHCI_CCIC 0x00020000 /* OverCurrent Indicator
113 #define OHCI_CRWE 0x80000000 /* Clear Remote Wakeup Enable */
114 #define OHCI_RH_PORT_STATUS(n) (0x50 + ((n)*4)) /* 1 based indexing */
116 #define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE)
117 #define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | \
118 OHCI_RD | OHCI_UE | OHCI_FNO | \
120 #define OHCI_NORMAL_INTRS (OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC)
122 #define OHCI_FSMPS(i) (((i-210)*6/7) << 16)
123 #define OHCI_PERIODIC(i) ((i)*9/10)
125 #endif /* _OHCIREG_H_ */