3 * Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
6 * This software was developed by SRI International and the University of
7 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
8 * ("CTSRD"), as part of the DARPA CRASH research programme.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * This file contains the driver for the SAF1761 series USB OTG
36 * Datasheet is available from:
37 * http://www.nxp.com/products/automotive/multimedia/usb/SAF1761BE.html
40 #ifdef USB_GLOBAL_INCLUDE_FILE
41 #include USB_GLOBAL_INCLUDE_FILE
43 #include <sys/stdint.h>
44 #include <sys/stddef.h>
45 #include <sys/param.h>
46 #include <sys/queue.h>
47 #include <sys/types.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
51 #include <sys/module.h>
53 #include <sys/mutex.h>
54 #include <sys/condvar.h>
55 #include <sys/sysctl.h>
57 #include <sys/unistd.h>
58 #include <sys/callout.h>
59 #include <sys/malloc.h>
61 #include <sys/libkern.h>
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #define USB_DEBUG_VAR saf1761_otg_debug
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #endif /* USB_GLOBAL_INCLUDE_FILE */
81 #include <dev/usb/controller/saf1761_otg.h>
82 #include <dev/usb/controller/saf1761_otg_reg.h>
84 #define SAF1761_OTG_BUS2SC(bus) \
85 ((struct saf1761_otg_softc *)(((uint8_t *)(bus)) - \
86 ((uint8_t *)&(((struct saf1761_otg_softc *)0)->sc_bus))))
88 #define SAF1761_OTG_PC2UDEV(pc) \
89 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
91 #define SAF1761_DCINTERRUPT_THREAD_IRQ \
92 (SOTG_DCINTERRUPT_IEVBUS | SOTG_DCINTERRUPT_IEBRST | \
93 SOTG_DCINTERRUPT_IERESM | SOTG_DCINTERRUPT_IESUSP)
96 static int saf1761_otg_debug = 0;
97 static int saf1761_otg_forcefs = 0;
100 SYSCTL_NODE(_hw_usb, OID_AUTO, saf1761_otg, CTLFLAG_RW, 0,
103 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, debug, CTLFLAG_RWTUN,
104 &saf1761_otg_debug, 0, "SAF1761 DCI debug level");
105 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, forcefs, CTLFLAG_RWTUN,
106 &saf1761_otg_forcefs, 0, "SAF1761 DCI force FULL speed");
109 #define SAF1761_OTG_INTR_ENDPT 1
113 static const struct usb_bus_methods saf1761_otg_bus_methods;
114 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods;
115 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods;
116 static const struct usb_pipe_methods saf1761_otg_host_isoc_methods;
118 static saf1761_otg_cmd_t saf1761_host_setup_tx;
119 static saf1761_otg_cmd_t saf1761_host_bulk_data_rx;
120 static saf1761_otg_cmd_t saf1761_host_bulk_data_tx;
121 static saf1761_otg_cmd_t saf1761_host_intr_data_rx;
122 static saf1761_otg_cmd_t saf1761_host_intr_data_tx;
123 static saf1761_otg_cmd_t saf1761_host_isoc_data_rx;
124 static saf1761_otg_cmd_t saf1761_host_isoc_data_tx;
125 static saf1761_otg_cmd_t saf1761_device_setup_rx;
126 static saf1761_otg_cmd_t saf1761_device_data_rx;
127 static saf1761_otg_cmd_t saf1761_device_data_tx;
128 static saf1761_otg_cmd_t saf1761_device_data_tx_sync;
129 static void saf1761_otg_device_done(struct usb_xfer *, usb_error_t);
130 static void saf1761_otg_do_poll(struct usb_bus *);
131 static void saf1761_otg_standard_done(struct usb_xfer *);
132 static void saf1761_otg_intr_set(struct usb_xfer *, uint8_t);
133 static void saf1761_otg_root_intr(struct saf1761_otg_softc *);
134 static void saf1761_otg_enable_psof(struct saf1761_otg_softc *, uint8_t);
137 * Here is a list of what the SAF1761 chip can support. The main
138 * limitation is that the sum of the buffer sizes must be less than
141 static const struct usb_hw_ep_profile saf1761_otg_ep_profile[] = {
144 .max_in_frame_size = 64,
145 .max_out_frame_size = 64,
147 .support_control = 1,
150 .max_in_frame_size = SOTG_HS_MAX_PACKET_SIZE,
151 .max_out_frame_size = SOTG_HS_MAX_PACKET_SIZE,
153 .support_interrupt = 1,
155 .support_isochronous = 1,
162 saf1761_otg_get_hw_ep_profile(struct usb_device *udev,
163 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
166 *ppf = saf1761_otg_ep_profile + 0;
167 } else if (ep_addr < 8) {
168 *ppf = saf1761_otg_ep_profile + 1;
175 saf1761_otg_pull_up(struct saf1761_otg_softc *sc)
177 /* activate pullup on D+, if possible */
179 if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) {
182 sc->sc_flags.d_pulled_up = 1;
187 saf1761_otg_pull_down(struct saf1761_otg_softc *sc)
189 /* release pullup on D+, if possible */
191 if (sc->sc_flags.d_pulled_up) {
194 sc->sc_flags.d_pulled_up = 0;
199 saf1761_otg_wakeup_peer(struct saf1761_otg_softc *sc)
203 if (!(sc->sc_flags.status_suspend))
208 temp = SAF1761_READ_LE_4(sc, SOTG_MODE);
209 SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp | SOTG_MODE_SNDRSU);
210 SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp & ~SOTG_MODE_SNDRSU);
212 /* Wait 8ms for remote wakeup to complete. */
213 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
217 saf1761_host_channel_alloc(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
222 if (td->channel < SOTG_HOST_CHANNEL_MAX)
225 /* check if device is suspended */
226 if (SAF1761_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
227 return (1); /* busy - cannot transfer data */
229 switch (td->ep_type) {
231 map = ~(sc->sc_host_intr_map |
232 sc->sc_host_intr_busy_map[0] |
233 sc->sc_host_intr_busy_map[1]);
234 /* find first set bit */
238 sc->sc_host_intr_map |= (1U << x);
239 td->channel = 32 + x;
242 map = ~(sc->sc_host_isoc_map |
243 sc->sc_host_isoc_busy_map[0] |
244 sc->sc_host_isoc_busy_map[1]);
245 /* find first set bit */
249 sc->sc_host_isoc_map |= (1U << x);
253 map = ~(sc->sc_host_async_map |
254 sc->sc_host_async_busy_map[0] |
255 sc->sc_host_async_busy_map[1]);
256 /* find first set bit */
260 sc->sc_host_async_map |= (1U << x);
261 td->channel = 64 + x;
268 saf1761_host_channel_free(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
272 if (td->channel >= SOTG_HOST_CHANNEL_MAX)
275 switch (td->ep_type) {
277 x = td->channel - 32;
278 td->channel = SOTG_HOST_CHANNEL_MAX;
279 sc->sc_host_intr_map &= ~(1U << x);
280 sc->sc_host_intr_suspend_map &= ~(1U << x);
281 sc->sc_host_intr_busy_map[0] |= (1U << x);
282 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
283 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
287 td->channel = SOTG_HOST_CHANNEL_MAX;
288 sc->sc_host_isoc_map &= ~(1U << x);
289 sc->sc_host_isoc_suspend_map &= ~(1U << x);
290 sc->sc_host_isoc_busy_map[0] |= (1U << x);
291 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
292 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
295 x = td->channel - 64;
296 td->channel = SOTG_HOST_CHANNEL_MAX;
297 sc->sc_host_async_map &= ~(1U << x);
298 sc->sc_host_async_suspend_map &= ~(1U << x);
299 sc->sc_host_async_busy_map[0] |= (1U << x);
300 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
301 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
304 saf1761_otg_enable_psof(sc, 1);
308 saf1761_peek_host_status_le_4(struct saf1761_otg_softc *sc, uint32_t offset)
314 SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
315 SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
316 retval = SAF1761_READ_LE_4(sc, offset);
320 DPRINTF("STAUS is zero at offset 0x%x\n", offset);
328 saf1761_read_host_memory(struct saf1761_otg_softc *sc,
329 struct saf1761_otg_td *td, uint32_t len)
331 struct usb_page_search buf_res;
338 offset = SOTG_DATA_ADDR(td->channel);
339 SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
340 SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
342 /* optimised read first */
344 usbd_get_page(td->pc, td->offset, &buf_res);
346 /* get correct length */
347 if (buf_res.length > len)
348 buf_res.length = len;
350 /* check buffer alignment */
351 if (((uintptr_t)buf_res.buffer) & 3)
354 count = buf_res.length & ~3;
358 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
359 offset, buf_res.buffer, count / 4);
364 /* update remainder and offset */
365 td->remainder -= count;
370 /* use bounce buffer */
371 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
372 offset, sc->sc_bounce_buffer, (len + 3) / 4);
373 usbd_copy_in(td->pc, td->offset,
374 sc->sc_bounce_buffer, len);
376 /* update remainder and offset */
377 td->remainder -= len;
383 saf1761_write_host_memory(struct saf1761_otg_softc *sc,
384 struct saf1761_otg_td *td, uint32_t len)
386 struct usb_page_search buf_res;
393 offset = SOTG_DATA_ADDR(td->channel);
395 /* optimised write first */
397 usbd_get_page(td->pc, td->offset, &buf_res);
399 /* get correct length */
400 if (buf_res.length > len)
401 buf_res.length = len;
403 /* check buffer alignment */
404 if (((uintptr_t)buf_res.buffer) & 3)
407 count = buf_res.length & ~3;
411 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
412 offset, buf_res.buffer, count / 4);
417 /* update remainder and offset */
418 td->remainder -= count;
422 /* use bounce buffer */
423 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
424 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
425 offset, sc->sc_bounce_buffer, (len + 3) / 4);
427 /* update remainder and offset */
428 td->remainder -= len;
434 saf1761_host_setup_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
441 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
442 pdt_addr = SOTG_PTD(td->channel);
444 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
446 DPRINTFN(5, "STATUS=0x%08x\n", status);
448 if (status & SOTG_PTD_DW3_ACTIVE) {
450 } else if (status & SOTG_PTD_DW3_HALTED) {
455 if (saf1761_host_channel_alloc(sc, td))
460 if (count != td->remainder) {
465 saf1761_write_host_memory(sc, td, count);
467 pdt_addr = SOTG_PTD(td->channel);
469 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
470 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
471 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
472 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
474 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
475 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
477 temp = SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8;
478 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
480 temp = td->dw1_value | (2 << 10) /* SETUP PID */ | (td->ep_index >> 1);
481 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
483 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
484 (td->max_packet_size << 18) /* wMaxPacketSize */ |
485 (count << 3) /* transfer count */ |
487 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
490 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
491 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
495 return (1); /* busy */
497 saf1761_host_channel_free(sc, td);
498 return (0); /* complete */
502 saf1761_host_bulk_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
507 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
512 pdt_addr = SOTG_PTD(td->channel);
514 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
516 DPRINTFN(5, "STATUS=0x%08x\n", status);
518 if (status & SOTG_PTD_DW3_ACTIVE) {
520 } else if (status & SOTG_PTD_DW3_HALTED) {
521 if (!(status & SOTG_PTD_DW3_ERRORS))
526 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
527 count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
529 count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
532 /* verify the packet byte count */
533 if (count != td->max_packet_size) {
534 if (count < td->max_packet_size) {
535 /* we have a short packet */
539 /* invalid USB packet */
546 /* verify the packet byte count */
547 if (count > td->remainder) {
548 /* invalid USB packet */
553 saf1761_read_host_memory(sc, td, count);
555 /* check if we are complete */
556 if ((td->remainder == 0) || got_short) {
559 /* else need to receive a zero length packet */
561 saf1761_host_channel_free(sc, td);
563 if (saf1761_host_channel_alloc(sc, td))
566 /* set toggle, if any */
567 if (td->set_toggle) {
572 /* receive one more packet */
574 pdt_addr = SOTG_PTD(td->channel);
576 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
577 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
578 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
579 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
581 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
583 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
585 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
586 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
588 temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
589 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
591 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
592 (td->max_packet_size << 18) /* wMaxPacketSize */ |
593 (td->max_packet_size << 3) /* transfer count */ |
595 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
598 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
599 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
601 return (1); /* busy */
603 saf1761_host_channel_free(sc, td);
604 return (0); /* complete */
608 saf1761_host_bulk_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
614 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
617 pdt_addr = SOTG_PTD(td->channel);
619 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
621 DPRINTFN(5, "STATUS=0x%08x\n", status);
623 if (status & SOTG_PTD_DW3_ACTIVE) {
625 } else if (status & SOTG_PTD_DW3_HALTED) {
626 if (!(status & SOTG_PTD_DW3_ERRORS))
631 /* check remainder */
632 if (td->remainder == 0) {
635 /* else we need to transmit a short packet */
637 saf1761_host_channel_free(sc, td);
639 if (saf1761_host_channel_alloc(sc, td))
642 count = td->max_packet_size;
643 if (td->remainder < count) {
644 /* we have a short packet */
646 count = td->remainder;
649 saf1761_write_host_memory(sc, td, count);
651 /* set toggle, if any */
652 if (td->set_toggle) {
657 /* send one more packet */
659 pdt_addr = SOTG_PTD(td->channel);
661 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
662 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
663 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
664 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
666 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
668 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
670 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
671 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
673 temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
674 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
676 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
677 (td->max_packet_size << 18) /* wMaxPacketSize */ |
678 (count << 3) /* transfer count */ |
680 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
683 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
684 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
688 return (1); /* busy */
690 saf1761_host_channel_free(sc, td);
691 return (0); /* complete */
695 saf1761_host_intr_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
700 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
705 pdt_addr = SOTG_PTD(td->channel);
707 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
709 DPRINTFN(5, "STATUS=0x%08x\n", status);
711 if (status & SOTG_PTD_DW3_ACTIVE) {
713 } else if (status & SOTG_PTD_DW3_HALTED) {
714 if (!(status & SOTG_PTD_DW3_ERRORS))
719 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
720 count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
722 count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
725 /* verify the packet byte count */
726 if (count != td->max_packet_size) {
727 if (count < td->max_packet_size) {
728 /* we have a short packet */
732 /* invalid USB packet */
739 /* verify the packet byte count */
740 if (count > td->remainder) {
741 /* invalid USB packet */
746 saf1761_read_host_memory(sc, td, count);
748 /* check if we are complete */
749 if ((td->remainder == 0) || got_short) {
752 /* else need to receive a zero length packet */
754 saf1761_host_channel_free(sc, td);
756 if (saf1761_host_channel_alloc(sc, td))
759 /* set toggle, if any */
760 if (td->set_toggle) {
765 /* receive one more packet */
767 pdt_addr = SOTG_PTD(td->channel);
769 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
770 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
772 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
773 temp = (0xFC << td->uframe) & 0xFF; /* complete split */
777 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
779 temp = (1U << td->uframe); /* start mask or start split */
780 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
782 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
783 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
785 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
786 (td->interval & 0xF8);
787 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
789 temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
790 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
792 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
793 (td->max_packet_size << 18) /* wMaxPacketSize */ |
794 (td->max_packet_size << 3) /* transfer count */ |
796 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
799 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
800 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
802 return (1); /* busy */
804 saf1761_host_channel_free(sc, td);
805 return (0); /* complete */
809 saf1761_host_intr_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
815 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
818 pdt_addr = SOTG_PTD(td->channel);
820 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
822 DPRINTFN(5, "STATUS=0x%08x\n", status);
824 if (status & SOTG_PTD_DW3_ACTIVE) {
826 } else if (status & SOTG_PTD_DW3_HALTED) {
827 if (!(status & SOTG_PTD_DW3_ERRORS))
833 /* check remainder */
834 if (td->remainder == 0) {
837 /* else we need to transmit a short packet */
839 saf1761_host_channel_free(sc, td);
841 if (saf1761_host_channel_alloc(sc, td))
844 count = td->max_packet_size;
845 if (td->remainder < count) {
846 /* we have a short packet */
848 count = td->remainder;
851 saf1761_write_host_memory(sc, td, count);
853 /* set toggle, if any */
854 if (td->set_toggle) {
859 /* send one more packet */
861 pdt_addr = SOTG_PTD(td->channel);
863 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
864 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
866 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
867 temp = (0xFC << td->uframe) & 0xFF; /* complete split */
871 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
873 temp = (1U << td->uframe); /* start mask or start split */
874 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
876 temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
877 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
879 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
880 (td->interval & 0xF8);
881 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
883 temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
884 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
886 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
887 (td->max_packet_size << 18) /* wMaxPacketSize */ |
888 (count << 3) /* transfer count */ |
890 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
893 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
894 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
898 return (1); /* busy */
900 saf1761_host_channel_free(sc, td);
901 return (0); /* complete */
905 saf1761_host_isoc_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
910 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
914 pdt_addr = SOTG_PTD(td->channel);
916 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
918 DPRINTFN(5, "STATUS=0x%08x\n", status);
920 if (status & SOTG_PTD_DW3_ACTIVE) {
922 } else if (status & SOTG_PTD_DW3_HALTED) {
925 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
926 count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
928 count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
930 /* verify the packet byte count */
931 if (count != td->max_packet_size) {
932 if (count < td->max_packet_size) {
933 /* we have a short packet */
936 /* invalid USB packet */
942 /* verify the packet byte count */
943 if (count > td->remainder) {
944 /* invalid USB packet */
949 saf1761_read_host_memory(sc, td, count);
953 if (saf1761_host_channel_alloc(sc, td))
956 /* receive one more packet */
958 pdt_addr = SOTG_PTD(td->channel);
960 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
961 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
963 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
964 temp = (0xFC << (td->uframe & 7)) & 0xFF; /* complete split */
968 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
970 temp = (1U << (td->uframe & 7)); /* start mask or start split */
971 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
973 temp = SOTG_PTD_DW3_ACTIVE | SOTG_PTD_DW3_CERR_3;
974 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
976 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
978 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
980 temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
981 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
983 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
984 (td->max_packet_size << 18) /* wMaxPacketSize */ |
985 (td->max_packet_size << 3) /* transfer count */ |
987 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
990 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
991 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
993 return (1); /* busy */
995 saf1761_host_channel_free(sc, td);
996 return (0); /* complete */
1000 saf1761_host_isoc_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1006 if (td->channel < SOTG_HOST_CHANNEL_MAX) {
1009 pdt_addr = SOTG_PTD(td->channel);
1011 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
1013 DPRINTFN(5, "STATUS=0x%08x\n", status);
1015 if (status & SOTG_PTD_DW3_ACTIVE) {
1017 } else if (status & SOTG_PTD_DW3_HALTED) {
1022 if (saf1761_host_channel_alloc(sc, td))
1025 count = td->max_packet_size;
1026 if (td->remainder < count) {
1027 /* we have a short packet */
1029 count = td->remainder;
1032 saf1761_write_host_memory(sc, td, count);
1034 /* send one more packet */
1036 pdt_addr = SOTG_PTD(td->channel);
1038 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
1039 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
1040 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
1042 temp = (1U << (td->uframe & 7)); /* start mask or start split */
1043 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
1045 temp = SOTG_PTD_DW3_ACTIVE | SOTG_PTD_DW3_CERR_3;
1046 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
1048 temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
1049 (td->uframe & 0xF8);
1050 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
1052 temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
1053 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
1055 temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
1056 (count << 18) /* wMaxPacketSize */ |
1057 (count << 3) /* transfer count */ |
1059 SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
1062 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
1063 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
1065 return (1); /* busy */
1067 saf1761_host_channel_free(sc, td);
1068 return (0); /* complete */
1072 saf1761_otg_set_address(struct saf1761_otg_softc *sc, uint8_t addr)
1074 DPRINTFN(5, "addr=%d\n", addr);
1076 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, addr | SOTG_ADDRESS_ENABLE);
1081 saf1761_read_device_fifo(struct saf1761_otg_softc *sc,
1082 struct saf1761_otg_td *td, uint32_t len)
1084 struct usb_page_search buf_res;
1087 /* optimised read first */
1089 usbd_get_page(td->pc, td->offset, &buf_res);
1091 /* get correct length */
1092 if (buf_res.length > len)
1093 buf_res.length = len;
1095 /* check buffer alignment */
1096 if (((uintptr_t)buf_res.buffer) & 3)
1099 count = buf_res.length & ~3;
1103 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1104 SOTG_DATA_PORT, buf_res.buffer, count / 4);
1108 /* update remainder and offset */
1109 td->remainder -= count;
1110 td->offset += count;
1114 /* use bounce buffer */
1115 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1116 SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
1117 usbd_copy_in(td->pc, td->offset,
1118 sc->sc_bounce_buffer, len);
1120 /* update remainder and offset */
1121 td->remainder -= len;
1127 saf1761_write_device_fifo(struct saf1761_otg_softc *sc,
1128 struct saf1761_otg_td *td, uint32_t len)
1130 struct usb_page_search buf_res;
1133 /* optimised write first */
1135 usbd_get_page(td->pc, td->offset, &buf_res);
1137 /* get correct length */
1138 if (buf_res.length > len)
1139 buf_res.length = len;
1141 /* check buffer alignment */
1142 if (((uintptr_t)buf_res.buffer) & 3)
1145 count = buf_res.length & ~3;
1149 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1150 SOTG_DATA_PORT, buf_res.buffer, count / 4);
1154 /* update remainder and offset */
1155 td->remainder -= count;
1156 td->offset += count;
1159 /* use bounce buffer */
1160 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
1161 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1162 SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
1164 /* update remainder and offset */
1165 td->remainder -= len;
1171 saf1761_device_setup_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1173 struct usb_device_request req;
1176 /* select the correct endpoint */
1177 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1179 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1181 /* check buffer status */
1182 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1185 /* get buffer length */
1186 count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1188 DPRINTFN(5, "count=%u rem=%u\n", count, td->remainder);
1190 /* clear did stall */
1194 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
1196 /* verify data length */
1197 if (count != td->remainder) {
1198 DPRINTFN(0, "Invalid SETUP packet "
1199 "length, %d bytes\n", count);
1202 if (count != sizeof(req)) {
1203 DPRINTFN(0, "Unsupported SETUP packet "
1204 "length, %d bytes\n", count);
1208 saf1761_read_device_fifo(sc, td, sizeof(req));
1210 /* extract SETUP packet again */
1211 usbd_copy_out(td->pc, 0, &req, sizeof(req));
1213 /* sneak peek the set address request */
1214 if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1215 (req.bRequest == UR_SET_ADDRESS)) {
1216 sc->sc_dv_addr = req.wValue[0] & 0x7F;
1217 DPRINTF("Set address %d\n", sc->sc_dv_addr);
1219 sc->sc_dv_addr = 0xFF;
1221 return (0); /* complete */
1224 /* abort any ongoing transfer */
1225 if (!td->did_stall) {
1226 DPRINTFN(5, "stalling\n");
1229 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
1233 return (1); /* not complete */
1237 saf1761_device_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1240 uint8_t got_short = 0;
1242 if (td->ep_index == 0) {
1243 /* select the correct endpoint */
1244 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1246 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1248 /* check buffer status */
1249 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1251 if (td->remainder == 0) {
1253 * We are actually complete and have
1254 * received the next SETUP:
1256 DPRINTFN(5, "faking complete\n");
1257 return (0); /* complete */
1259 DPRINTFN(5, "SETUP packet while receiving data\n");
1261 * USB Host Aborted the transfer.
1264 return (0); /* complete */
1267 /* select the correct endpoint */
1268 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1269 (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1270 SOTG_EP_INDEX_DIR_OUT);
1272 /* enable data stage */
1273 if (td->set_toggle) {
1275 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1278 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1280 /* check buffer status */
1281 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1282 return (1); /* not complete */
1284 /* get buffer length */
1285 count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1287 DPRINTFN(5, "rem=%u count=0x%04x\n", td->remainder, count);
1289 /* verify the packet byte count */
1290 if (count != td->max_packet_size) {
1291 if (count < td->max_packet_size) {
1292 /* we have a short packet */
1296 /* invalid USB packet */
1298 return (0); /* we are complete */
1301 /* verify the packet byte count */
1302 if (count > td->remainder) {
1303 /* invalid USB packet */
1305 return (0); /* we are complete */
1308 saf1761_read_device_fifo(sc, td, count);
1310 /* check if we are complete */
1311 if ((td->remainder == 0) || got_short) {
1312 if (td->short_pkt) {
1313 /* we are complete */
1316 /* else need to receive a zero length packet */
1318 return (1); /* not complete */
1322 saf1761_device_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1326 if (td->ep_index == 0) {
1327 /* select the correct endpoint */
1328 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1330 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1332 /* check buffer status */
1333 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1334 DPRINTFN(5, "SETUP abort\n");
1336 * USB Host Aborted the transfer.
1339 return (0); /* complete */
1342 /* select the correct endpoint */
1343 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1344 (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1345 SOTG_EP_INDEX_DIR_IN);
1347 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1349 /* check buffer status */
1350 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1351 return (1); /* not complete */
1353 /* enable data stage */
1354 if (td->set_toggle) {
1356 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1359 DPRINTFN(5, "rem=%u\n", td->remainder);
1361 count = td->max_packet_size;
1362 if (td->remainder < count) {
1363 /* we have a short packet */
1365 count = td->remainder;
1368 saf1761_write_device_fifo(sc, td, count);
1370 if (td->ep_index == 0) {
1371 if (count < SOTG_FS_MAX_PACKET_SIZE) {
1372 /* set end of packet */
1373 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1376 if (count < SOTG_HS_MAX_PACKET_SIZE) {
1377 /* set end of packet */
1378 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1382 /* check remainder */
1383 if (td->remainder == 0) {
1384 if (td->short_pkt) {
1385 return (0); /* complete */
1387 /* else we need to transmit a short packet */
1389 return (1); /* not complete */
1393 saf1761_device_data_tx_sync(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1397 if (td->ep_index == 0) {
1398 /* select the correct endpoint */
1399 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1401 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1403 /* check buffer status */
1404 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1405 DPRINTFN(5, "Faking complete\n");
1406 return (0); /* complete */
1409 /* select the correct endpoint */
1410 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1411 (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1412 SOTG_EP_INDEX_DIR_IN);
1414 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1416 /* check buffer status */
1417 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1418 return (1); /* busy */
1420 if (sc->sc_dv_addr != 0xFF) {
1421 /* write function address */
1422 saf1761_otg_set_address(sc, sc->sc_dv_addr);
1424 return (0); /* complete */
1428 saf1761_otg_xfer_do_fifo(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1430 struct saf1761_otg_td *td;
1435 td = xfer->td_transfer_cache;
1440 if ((td->func) (sc, td)) {
1441 /* operation in progress */
1444 if (((void *)td) == xfer->td_transfer_last) {
1447 if (td->error_any) {
1449 } else if (td->remainder > 0) {
1451 * We had a short transfer. If there is no alternate
1452 * next, stop processing !
1454 if (!td->alt_next) {
1459 * Fetch the next transfer descriptor.
1461 toggle = td->toggle;
1463 td->toggle = toggle;
1464 xfer->td_transfer_cache = td;
1469 /* compute all actual lengths */
1470 xfer->td_transfer_cache = NULL;
1471 sc->sc_xfer_complete = 1;
1475 saf1761_otg_xfer_do_complete(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1477 struct saf1761_otg_td *td;
1481 td = xfer->td_transfer_cache;
1483 /* compute all actual lengths */
1484 saf1761_otg_standard_done(xfer);
1491 saf1761_otg_interrupt_poll_locked(struct saf1761_otg_softc *sc)
1493 struct usb_xfer *xfer;
1495 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
1496 saf1761_otg_xfer_do_fifo(sc, xfer);
1500 saf1761_otg_enable_psof(struct saf1761_otg_softc *sc, uint8_t on)
1503 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IEPSOF;
1505 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IEPSOF;
1507 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1511 saf1761_otg_wait_suspend(struct saf1761_otg_softc *sc, uint8_t on)
1514 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IESUSP;
1515 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IERESM;
1517 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IESUSP;
1518 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IERESM;
1520 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1524 saf1761_otg_update_vbus(struct saf1761_otg_softc *sc)
1528 /* read fresh status */
1529 status = SAF1761_READ_LE_4(sc, SOTG_STATUS);
1531 DPRINTFN(4, "STATUS=0x%04x\n", status);
1533 if ((status & SOTG_STATUS_VBUS_VLD) &&
1534 (status & SOTG_STATUS_ID)) {
1535 /* VBUS present and device mode */
1536 if (!sc->sc_flags.status_vbus) {
1537 sc->sc_flags.status_vbus = 1;
1539 /* complete root HUB interrupt endpoint */
1540 saf1761_otg_root_intr(sc);
1543 /* VBUS not-present or host mode */
1544 if (sc->sc_flags.status_vbus) {
1545 sc->sc_flags.status_vbus = 0;
1546 sc->sc_flags.status_bus_reset = 0;
1547 sc->sc_flags.status_suspend = 0;
1548 sc->sc_flags.change_suspend = 0;
1549 sc->sc_flags.change_connect = 1;
1551 /* complete root HUB interrupt endpoint */
1552 saf1761_otg_root_intr(sc);
1558 saf1761_otg_interrupt_complete_locked(struct saf1761_otg_softc *sc)
1560 struct usb_xfer *xfer;
1562 /* scan for completion events */
1563 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1564 if (saf1761_otg_xfer_do_complete(sc, xfer))
1570 saf1761_otg_filter_interrupt(void *arg)
1572 struct saf1761_otg_softc *sc = arg;
1573 int retval = FILTER_HANDLED;
1577 USB_BUS_SPIN_LOCK(&sc->sc_bus);
1579 hcstat = SAF1761_READ_LE_4(sc, SOTG_HCINTERRUPT);
1580 /* acknowledge all host controller interrupts */
1581 SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT, hcstat);
1583 status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT);
1584 /* acknowledge all device controller interrupts */
1585 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT,
1586 status & ~SAF1761_DCINTERRUPT_THREAD_IRQ);
1588 (void) SAF1761_READ_LE_4(sc, SOTG_ATL_PTD_DONE_PTD);
1589 (void) SAF1761_READ_LE_4(sc, SOTG_INT_PTD_DONE_PTD);
1590 (void) SAF1761_READ_LE_4(sc, SOTG_ISO_PTD_DONE_PTD);
1592 if (status & SOTG_DCINTERRUPT_IEPSOF) {
1593 if ((sc->sc_host_async_busy_map[1] | sc->sc_host_async_busy_map[0] |
1594 sc->sc_host_intr_busy_map[1] | sc->sc_host_intr_busy_map[0] |
1595 sc->sc_host_isoc_busy_map[1] | sc->sc_host_isoc_busy_map[0]) != 0) {
1596 /* busy waiting is active */
1597 retval = FILTER_SCHEDULE_THREAD;
1599 sc->sc_host_async_busy_map[1] = sc->sc_host_async_busy_map[0];
1600 sc->sc_host_async_busy_map[0] = 0;
1602 sc->sc_host_intr_busy_map[1] = sc->sc_host_intr_busy_map[0];
1603 sc->sc_host_intr_busy_map[0] = 0;
1605 sc->sc_host_isoc_busy_map[1] = sc->sc_host_isoc_busy_map[0];
1606 sc->sc_host_isoc_busy_map[0] = 0;
1608 /* busy waiting is not active */
1609 saf1761_otg_enable_psof(sc, 0);
1613 if (status & SAF1761_DCINTERRUPT_THREAD_IRQ)
1614 retval = FILTER_SCHEDULE_THREAD;
1616 /* poll FIFOs, if any */
1617 saf1761_otg_interrupt_poll_locked(sc);
1619 if (sc->sc_xfer_complete != 0)
1620 retval = FILTER_SCHEDULE_THREAD;
1622 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1628 saf1761_otg_interrupt(void *arg)
1630 struct saf1761_otg_softc *sc = arg;
1633 USB_BUS_LOCK(&sc->sc_bus);
1634 USB_BUS_SPIN_LOCK(&sc->sc_bus);
1636 status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT) &
1637 SAF1761_DCINTERRUPT_THREAD_IRQ;
1639 /* acknowledge all device controller interrupts */
1640 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT, status);
1642 DPRINTF("DCINTERRUPT=0x%08x SOF=0x%08x "
1643 "FRINDEX=0x%08x\n", status,
1644 SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM),
1645 SAF1761_READ_LE_4(sc, SOTG_FRINDEX));
1647 /* update VBUS and ID bits, if any */
1648 if (status & SOTG_DCINTERRUPT_IEVBUS)
1649 saf1761_otg_update_vbus(sc);
1651 if (status & SOTG_DCINTERRUPT_IEBRST) {
1653 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1654 SOTG_UNLOCK_DEVICE_CODE);
1656 /* Enable device address */
1657 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS,
1658 SOTG_ADDRESS_ENABLE);
1660 sc->sc_flags.status_bus_reset = 1;
1661 sc->sc_flags.status_suspend = 0;
1662 sc->sc_flags.change_suspend = 0;
1663 sc->sc_flags.change_connect = 1;
1665 /* disable resume interrupt */
1666 saf1761_otg_wait_suspend(sc, 1);
1667 /* complete root HUB interrupt endpoint */
1668 saf1761_otg_root_intr(sc);
1671 * If "RESUME" and "SUSPEND" is set at the same time we
1672 * interpret that like "RESUME". Resume is set when there is
1673 * at least 3 milliseconds of inactivity on the USB BUS:
1675 if (status & SOTG_DCINTERRUPT_IERESM) {
1677 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1678 SOTG_UNLOCK_DEVICE_CODE);
1680 if (sc->sc_flags.status_suspend) {
1681 sc->sc_flags.status_suspend = 0;
1682 sc->sc_flags.change_suspend = 1;
1683 /* disable resume interrupt */
1684 saf1761_otg_wait_suspend(sc, 1);
1685 /* complete root HUB interrupt endpoint */
1686 saf1761_otg_root_intr(sc);
1688 } else if (status & SOTG_DCINTERRUPT_IESUSP) {
1689 if (!sc->sc_flags.status_suspend) {
1690 sc->sc_flags.status_suspend = 1;
1691 sc->sc_flags.change_suspend = 1;
1692 /* enable resume interrupt */
1693 saf1761_otg_wait_suspend(sc, 0);
1694 /* complete root HUB interrupt endpoint */
1695 saf1761_otg_root_intr(sc);
1699 if (sc->sc_xfer_complete != 0) {
1700 sc->sc_xfer_complete = 0;
1702 /* complete FIFOs, if any */
1703 saf1761_otg_interrupt_complete_locked(sc);
1705 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1706 USB_BUS_UNLOCK(&sc->sc_bus);
1710 saf1761_otg_setup_standard_chain_sub(struct saf1761_otg_std_temp *temp)
1712 struct saf1761_otg_td *td;
1714 /* get current Transfer Descriptor */
1718 /* prepare for next TD */
1719 temp->td_next = td->obj_next;
1721 /* fill out the Transfer Descriptor */
1722 td->func = temp->func;
1724 td->offset = temp->offset;
1725 td->remainder = temp->len;
1727 td->error_stall = 0;
1729 td->did_stall = temp->did_stall;
1730 td->short_pkt = temp->short_pkt;
1731 td->alt_next = temp->setup_alt_next;
1732 td->channel = SOTG_HOST_CHANNEL_MAX;
1736 saf1761_otg_setup_standard_chain(struct usb_xfer *xfer)
1738 struct saf1761_otg_std_temp temp;
1739 struct saf1761_otg_softc *sc;
1740 struct saf1761_otg_td *td;
1746 uint8_t uframe_start;
1747 uint8_t uframe_interval;
1749 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1750 xfer->address, UE_GET_ADDR(xfer->endpointno),
1751 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1753 temp.max_frame_size = xfer->max_frame_size;
1755 td = xfer->td_start[0];
1756 xfer->td_transfer_first = td;
1757 xfer->td_transfer_cache = td;
1763 temp.td_next = xfer->td_start[0];
1765 temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
1766 xfer->flags_int.isochronous_xfr;
1767 temp.did_stall = !xfer->flags_int.control_stall;
1769 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
1771 sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1772 ep_no = (xfer->endpointno & UE_ADDR);
1773 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
1775 /* check if we should prepend a setup message */
1777 if (xfer->flags_int.control_xfr) {
1778 if (xfer->flags_int.control_hdr) {
1781 temp.func = &saf1761_host_setup_tx;
1783 temp.func = &saf1761_device_setup_rx;
1785 temp.len = xfer->frlengths[0];
1786 temp.pc = xfer->frbuffers + 0;
1787 temp.short_pkt = temp.len ? 1 : 0;
1788 /* check for last frame */
1789 if (xfer->nframes == 1) {
1790 /* no STATUS stage yet, SETUP is last */
1791 if (xfer->flags_int.control_act)
1792 temp.setup_alt_next = 0;
1794 saf1761_otg_setup_standard_chain_sub(&temp);
1802 uframe_interval = 0;
1804 if (x != xfer->nframes) {
1805 if (xfer->endpointno & UE_DIR_IN) {
1807 if (ep_type == UE_INTERRUPT) {
1808 temp.func = &saf1761_host_intr_data_rx;
1809 } else if (ep_type == UE_ISOCHRONOUS) {
1810 temp.func = &saf1761_host_isoc_data_rx;
1811 uframe_start = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) + 8) &
1812 (SOTG_FRINDEX_MASK & ~7);
1813 if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
1814 uframe_interval = 1U << xfer->fps_shift;
1816 uframe_interval = 8U;
1818 temp.func = &saf1761_host_bulk_data_rx;
1822 temp.func = &saf1761_device_data_tx;
1827 if (ep_type == UE_INTERRUPT) {
1828 temp.func = &saf1761_host_intr_data_tx;
1829 } else if (ep_type == UE_ISOCHRONOUS) {
1830 temp.func = &saf1761_host_isoc_data_tx;
1831 uframe_start = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) + 8) &
1832 (SOTG_FRINDEX_MASK & ~7);
1833 if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
1834 uframe_interval = 1U << xfer->fps_shift;
1836 uframe_interval = 8U;
1838 temp.func = &saf1761_host_bulk_data_tx;
1842 temp.func = &saf1761_device_data_rx;
1847 /* setup "pc" pointer */
1848 temp.pc = xfer->frbuffers + x;
1853 while (x != xfer->nframes) {
1855 /* DATA0 / DATA1 message */
1857 temp.len = xfer->frlengths[x];
1861 if (x == xfer->nframes) {
1862 if (xfer->flags_int.control_xfr) {
1863 if (xfer->flags_int.control_act) {
1864 temp.setup_alt_next = 0;
1867 temp.setup_alt_next = 0;
1870 if (temp.len == 0) {
1872 /* make sure that we send an USB packet */
1878 /* regular data transfer */
1880 temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1883 saf1761_otg_setup_standard_chain_sub(&temp);
1885 if (xfer->flags_int.isochronous_xfr) {
1886 temp.offset += temp.len;
1888 /* stamp the starting point for this transaction */
1889 temp.td->uframe = uframe_start;
1891 /* advance to next */
1892 uframe_start += uframe_interval;
1894 /* get next Page Cache pointer */
1895 temp.pc = xfer->frbuffers + x;
1899 /* check for control transfer */
1900 if (xfer->flags_int.control_xfr) {
1901 /* always setup a valid "pc" pointer for status and sync */
1902 temp.pc = xfer->frbuffers + 0;
1905 temp.setup_alt_next = 0;
1907 /* check if we should append a status stage */
1908 if (!xfer->flags_int.control_act) {
1911 * Send a DATA1 message and invert the current
1912 * endpoint direction.
1914 if (xfer->endpointno & UE_DIR_IN) {
1916 temp.func = &saf1761_host_bulk_data_tx;
1919 temp.func = &saf1761_device_data_rx;
1924 temp.func = &saf1761_host_bulk_data_rx;
1927 temp.func = &saf1761_device_data_tx;
1934 saf1761_otg_setup_standard_chain_sub(&temp);
1936 /* data toggle should be DATA1 */
1941 /* we need a SYNC point after TX */
1942 temp.func = &saf1761_device_data_tx_sync;
1943 saf1761_otg_setup_standard_chain_sub(&temp);
1948 temp.pc = xfer->frbuffers + 0;
1951 temp.setup_alt_next = 0;
1953 /* we need a SYNC point after TX */
1954 temp.func = &saf1761_device_data_tx_sync;
1955 saf1761_otg_setup_standard_chain_sub(&temp);
1959 /* must have at least one frame! */
1961 xfer->td_transfer_last = td;
1964 /* get first again */
1965 td = xfer->td_transfer_first;
1966 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
1971 saf1761_otg_timeout(void *arg)
1973 struct usb_xfer *xfer = arg;
1975 DPRINTF("xfer=%p\n", xfer);
1977 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1979 /* transfer is transferred */
1980 saf1761_otg_device_done(xfer, USB_ERR_TIMEOUT);
1984 saf1761_otg_intr_set(struct usb_xfer *xfer, uint8_t set)
1986 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1987 uint8_t ep_no = (xfer->endpointno & UE_ADDR);
1990 DPRINTFN(15, "endpoint=%d set=%d\n", xfer->endpointno, set);
1993 mask = SOTG_DCINTERRUPT_IEPRX(0) |
1994 SOTG_DCINTERRUPT_IEPTX(0) |
1995 SOTG_DCINTERRUPT_IEP0SETUP;
1996 } else if (xfer->endpointno & UE_DIR_IN) {
1997 mask = SOTG_DCINTERRUPT_IEPTX(ep_no);
1999 mask = SOTG_DCINTERRUPT_IEPRX(ep_no);
2003 sc->sc_intr_enable |= mask;
2005 sc->sc_intr_enable &= ~mask;
2007 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
2011 saf1761_otg_start_standard_chain(struct usb_xfer *xfer)
2013 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2017 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2020 saf1761_otg_xfer_do_fifo(sc, xfer);
2022 if (saf1761_otg_xfer_do_complete(sc, xfer) == 0) {
2024 * Only enable the endpoint interrupt when we are
2025 * actually waiting for data, hence we are dealing
2026 * with level triggered interrupts !
2028 saf1761_otg_intr_set(xfer, 1);
2030 /* put transfer on interrupt queue */
2031 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2033 /* start timeout, if any */
2034 if (xfer->timeout != 0) {
2035 usbd_transfer_timeout_ms(xfer,
2036 &saf1761_otg_timeout, xfer->timeout);
2039 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2043 saf1761_otg_root_intr(struct saf1761_otg_softc *sc)
2047 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2049 /* set port bit - we only have one port */
2050 sc->sc_hub_idata[0] = 0x02;
2052 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2053 sizeof(sc->sc_hub_idata));
2057 saf1761_otg_standard_done_sub(struct usb_xfer *xfer)
2059 struct saf1761_otg_td *td;
2065 td = xfer->td_transfer_cache;
2068 len = td->remainder;
2070 /* store last data toggle */
2071 xfer->endpoint->toggle_next = td->toggle;
2073 if (xfer->aframes != xfer->nframes) {
2075 * Verify the length and subtract
2076 * the remainder from "frlengths[]":
2078 if (len > xfer->frlengths[xfer->aframes]) {
2081 xfer->frlengths[xfer->aframes] -= len;
2084 /* Check for transfer error */
2085 if (td->error_any) {
2086 /* the transfer is finished */
2087 error = (td->error_stall ?
2088 USB_ERR_STALLED : USB_ERR_IOERROR);
2092 /* Check for short transfer */
2094 if (xfer->flags_int.short_frames_ok ||
2095 xfer->flags_int.isochronous_xfr) {
2096 /* follow alt next */
2103 /* the transfer is finished */
2111 /* this USB frame is complete */
2117 /* update transfer cache */
2119 xfer->td_transfer_cache = td;
2125 saf1761_otg_standard_done(struct usb_xfer *xfer)
2127 usb_error_t err = 0;
2129 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2130 xfer, xfer->endpoint);
2134 xfer->td_transfer_cache = xfer->td_transfer_first;
2136 if (xfer->flags_int.control_xfr) {
2138 if (xfer->flags_int.control_hdr) {
2140 err = saf1761_otg_standard_done_sub(xfer);
2144 if (xfer->td_transfer_cache == NULL) {
2148 while (xfer->aframes != xfer->nframes) {
2150 err = saf1761_otg_standard_done_sub(xfer);
2153 if (xfer->td_transfer_cache == NULL) {
2158 if (xfer->flags_int.control_xfr &&
2159 !xfer->flags_int.control_act) {
2161 err = saf1761_otg_standard_done_sub(xfer);
2164 saf1761_otg_device_done(xfer, err);
2167 /*------------------------------------------------------------------------*
2168 * saf1761_otg_device_done
2170 * NOTE: this function can be called more than one time on the
2171 * same USB transfer!
2172 *------------------------------------------------------------------------*/
2174 saf1761_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
2176 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2178 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2180 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2181 xfer, xfer->endpoint, error);
2183 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2185 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
2186 saf1761_otg_intr_set(xfer, 0);
2188 struct saf1761_otg_td *td;
2190 td = xfer->td_transfer_cache;
2193 saf1761_host_channel_free(sc, td);
2196 /* dequeue transfer and start next transfer */
2197 usbd_transfer_done(xfer, error);
2199 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2203 saf1761_otg_xfer_stall(struct usb_xfer *xfer)
2205 saf1761_otg_device_done(xfer, USB_ERR_STALLED);
2209 saf1761_otg_set_stall(struct usb_device *udev,
2210 struct usb_endpoint *ep, uint8_t *did_stall)
2212 struct saf1761_otg_softc *sc;
2217 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2220 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2225 DPRINTFN(5, "endpoint=%p\n", ep);
2228 sc = SAF1761_OTG_BUS2SC(udev->bus);
2230 ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2231 ep_dir = (ep->edesc->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT));
2232 ep_type = (ep->edesc->bmAttributes & UE_XFERTYPE);
2234 if (ep_type == UE_CONTROL) {
2235 /* should not happen */
2238 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2240 /* select the correct endpoint */
2241 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2242 (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2243 ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2244 SOTG_EP_INDEX_DIR_OUT));
2247 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
2249 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2253 saf1761_otg_clear_stall_sub_locked(struct saf1761_otg_softc *sc,
2254 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2256 if (ep_type == UE_CONTROL) {
2257 /* clearing stall is not needed */
2260 /* select the correct endpoint */
2261 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2262 (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2263 ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2264 SOTG_EP_INDEX_DIR_OUT));
2266 /* disable endpoint */
2267 SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, 0);
2268 /* enable endpoint again - will clear data toggle */
2269 SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, ep_type | SOTG_EP_TYPE_ENABLE);
2272 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_CLBUF);
2274 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
2278 saf1761_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
2280 struct saf1761_otg_softc *sc;
2281 struct usb_endpoint_descriptor *ed;
2283 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2285 DPRINTFN(5, "endpoint=%p\n", ep);
2288 if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2293 sc = SAF1761_OTG_BUS2SC(udev->bus);
2295 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2297 /* get endpoint descriptor */
2300 /* reset endpoint */
2301 saf1761_otg_clear_stall_sub_locked(sc,
2302 (ed->bEndpointAddress & UE_ADDR),
2303 (ed->bmAttributes & UE_XFERTYPE),
2304 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
2306 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2310 saf1761_otg_init(struct saf1761_otg_softc *sc)
2312 const struct usb_hw_ep_profile *pf;
2317 /* set up the bus structure */
2318 sc->sc_bus.usbrev = USB_REV_2_0;
2319 sc->sc_bus.methods = &saf1761_otg_bus_methods;
2321 USB_BUS_LOCK(&sc->sc_bus);
2323 /* Reset Host controller, including HW mode */
2324 SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_ALL);
2328 /* Reset Host controller, including HW mode */
2329 SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_HC);
2334 SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, 0);
2339 /* Enable interrupts */
2340 sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN |
2341 SOTG_HW_MODE_CTRL_COMN_INT;
2344 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE, SOTG_UNLOCK_DEVICE_CODE);
2347 * Set correct hardware mode, must be written twice if bus
2350 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2351 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2353 SAF1761_WRITE_LE_4(sc, SOTG_DCSCRATCH, 0xdeadbeef);
2354 SAF1761_WRITE_LE_4(sc, SOTG_HCSCRATCH, 0xdeadbeef);
2356 DPRINTF("DCID=0x%08x VEND_PROD=0x%08x HWMODE=0x%08x SCRATCH=0x%08x,0x%08x\n",
2357 SAF1761_READ_LE_4(sc, SOTG_DCCHIP_ID),
2358 SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID),
2359 SAF1761_READ_LE_4(sc, SOTG_HW_MODE_CTRL),
2360 SAF1761_READ_LE_4(sc, SOTG_DCSCRATCH),
2361 SAF1761_READ_LE_4(sc, SOTG_HCSCRATCH));
2363 /* reset device controller */
2364 SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_SFRESET);
2365 SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2370 /* reset host controller */
2371 SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_HCRESET);
2373 /* wait for reset to clear */
2374 for (x = 0; x != 10; x++) {
2375 if ((SAF1761_READ_LE_4(sc, SOTG_USBCMD) & SOTG_USBCMD_HCRESET) == 0)
2377 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
2380 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode |
2381 SOTG_HW_MODE_CTRL_ALL_ATX_RESET);
2386 SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2392 saf1761_otg_pull_down(sc);
2394 /* wait 10ms for pulldown to stabilise */
2395 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2399 saf1761_otg_get_hw_ep_profile(NULL, &pf, x);
2403 /* select the correct endpoint */
2404 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2405 (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2406 SOTG_EP_INDEX_DIR_IN);
2408 /* select the maximum packet size */
2409 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_in_frame_size);
2411 /* select the correct endpoint */
2412 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2413 (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2414 SOTG_EP_INDEX_DIR_OUT);
2416 /* select the maximum packet size */
2417 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_out_frame_size);
2420 /* enable interrupts */
2421 SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_GLINTENA |
2422 SOTG_MODE_CLKAON | SOTG_MODE_WKUPCS);
2424 sc->sc_interrupt_cfg |=
2425 SOTG_INTERRUPT_CFG_CDBGMOD |
2426 SOTG_INTERRUPT_CFG_DDBGMODIN |
2427 SOTG_INTERRUPT_CFG_DDBGMODOUT;
2429 /* set default values */
2430 SAF1761_WRITE_LE_4(sc, SOTG_INTERRUPT_CFG, sc->sc_interrupt_cfg);
2432 /* enable VBUS and ID interrupt */
2433 SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2434 SOTG_IRQ_ENABLE_CLR(0xFFFF));
2435 SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2436 SOTG_IRQ_ENABLE_SET(SOTG_IRQ_ID | SOTG_IRQ_VBUS_VLD));
2438 /* enable interrupts */
2439 sc->sc_intr_enable = SOTG_DCINTERRUPT_IEVBUS |
2440 SOTG_DCINTERRUPT_IEBRST | SOTG_DCINTERRUPT_IESUSP;
2441 SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
2444 * Connect ATX port 1 to device controller, select external
2445 * charge pump and driver VBUS to +5V:
2447 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2448 SOTG_CTRL_CLR(0xFFFF));
2449 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2450 SOTG_CTRL_SET(SOTG_CTRL_SW_SEL_HC_DC |
2451 SOTG_CTRL_BDIS_ACON_EN | SOTG_CTRL_SEL_CP_EXT |
2452 SOTG_CTRL_VBUS_DRV));
2454 /* disable device address */
2455 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, 0);
2457 /* enable host controller clock and preserve reserved bits */
2458 x = SAF1761_READ_LE_4(sc, SOTG_POWER_DOWN);
2459 SAF1761_WRITE_LE_4(sc, SOTG_POWER_DOWN, x | SOTG_POWER_DOWN_HC_CLK_EN);
2461 /* wait 10ms for clock */
2462 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2464 /* enable configuration flag */
2465 SAF1761_WRITE_LE_4(sc, SOTG_CONFIGFLAG, SOTG_CONFIGFLAG_ENABLE);
2467 /* clear RAM block */
2468 for (x = 0x400; x != 0x10000; x += 4)
2469 SAF1761_WRITE_LE_4(sc, x, 0);
2472 SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_RS);
2474 DPRINTF("USBCMD=0x%08x\n", SAF1761_READ_LE_4(sc, SOTG_USBCMD));
2476 /* make HC scan all PTDs */
2477 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_LAST_PTD, (1 << 31));
2478 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_LAST_PTD, (1 << 31));
2479 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_LAST_PTD, (1 << 31));
2481 /* skip all PTDs by default */
2482 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD, -1U);
2483 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD, -1U);
2484 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD, -1U);
2486 /* activate all PTD types */
2487 SAF1761_WRITE_LE_4(sc, SOTG_HCBUFFERSTATUS,
2488 SOTG_HCBUFFERSTATUS_ISO_BUF_FILL |
2489 SOTG_HCBUFFERSTATUS_INT_BUF_FILL |
2490 SOTG_HCBUFFERSTATUS_ATL_BUF_FILL);
2492 /* we don't use the AND mask */
2493 SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_AND, 0);
2494 SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_AND, 0);
2495 SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_AND, 0);
2497 /* enable all PTD OR interrupts by default */
2498 SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_OR, -1U);
2499 SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_OR, -1U);
2500 SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_OR, -1U);
2502 /* enable HC interrupts */
2503 SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT_ENABLE,
2504 SOTG_HCINTERRUPT_OTG_IRQ |
2505 SOTG_HCINTERRUPT_ISO_IRQ |
2506 SOTG_HCINTERRUPT_ALT_IRQ |
2507 SOTG_HCINTERRUPT_INT_IRQ);
2509 /* poll initial VBUS status */
2510 saf1761_otg_update_vbus(sc);
2512 USB_BUS_UNLOCK(&sc->sc_bus);
2514 /* catch any lost interrupts */
2516 saf1761_otg_do_poll(&sc->sc_bus);
2518 return (0); /* success */
2522 saf1761_otg_uninit(struct saf1761_otg_softc *sc)
2524 USB_BUS_LOCK(&sc->sc_bus);
2526 /* disable all interrupts */
2527 SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2529 sc->sc_flags.port_powered = 0;
2530 sc->sc_flags.status_vbus = 0;
2531 sc->sc_flags.status_bus_reset = 0;
2532 sc->sc_flags.status_suspend = 0;
2533 sc->sc_flags.change_suspend = 0;
2534 sc->sc_flags.change_connect = 1;
2536 saf1761_otg_pull_down(sc);
2537 USB_BUS_UNLOCK(&sc->sc_bus);
2541 saf1761_otg_suspend(struct saf1761_otg_softc *sc)
2547 saf1761_otg_resume(struct saf1761_otg_softc *sc)
2553 saf1761_otg_do_poll(struct usb_bus *bus)
2555 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
2557 USB_BUS_LOCK(&sc->sc_bus);
2558 USB_BUS_SPIN_LOCK(&sc->sc_bus);
2559 saf1761_otg_interrupt_poll_locked(sc);
2560 saf1761_otg_interrupt_complete_locked(sc);
2561 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2562 USB_BUS_UNLOCK(&sc->sc_bus);
2565 /*------------------------------------------------------------------------*
2566 * saf1761_otg control support
2567 * saf1761_otg interrupt support
2568 * saf1761_otg bulk support
2569 *------------------------------------------------------------------------*/
2571 saf1761_otg_device_non_isoc_open(struct usb_xfer *xfer)
2577 saf1761_otg_device_non_isoc_close(struct usb_xfer *xfer)
2579 saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2583 saf1761_otg_device_non_isoc_enter(struct usb_xfer *xfer)
2589 saf1761_otg_device_non_isoc_start(struct usb_xfer *xfer)
2592 saf1761_otg_setup_standard_chain(xfer);
2593 saf1761_otg_start_standard_chain(xfer);
2596 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods =
2598 .open = saf1761_otg_device_non_isoc_open,
2599 .close = saf1761_otg_device_non_isoc_close,
2600 .enter = saf1761_otg_device_non_isoc_enter,
2601 .start = saf1761_otg_device_non_isoc_start,
2604 /*------------------------------------------------------------------------*
2605 * saf1761_otg device side isochronous support
2606 *------------------------------------------------------------------------*/
2608 saf1761_otg_device_isoc_open(struct usb_xfer *xfer)
2614 saf1761_otg_device_isoc_close(struct usb_xfer *xfer)
2616 saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2620 saf1761_otg_device_isoc_enter(struct usb_xfer *xfer)
2622 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2626 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2627 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2629 /* get the current frame index - we don't need the high bits */
2631 nframes = SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM);
2634 * check if the frame index is within the window where the
2635 * frames will be inserted
2637 temp = (nframes - xfer->endpoint->isoc_next) & SOTG_FRAME_NUM_SOFR_MASK;
2639 if ((xfer->endpoint->is_synced == 0) ||
2640 (temp < xfer->nframes)) {
2642 * If there is data underflow or the pipe queue is
2643 * empty we schedule the transfer a few frames ahead
2644 * of the current frame position. Else two isochronous
2645 * transfers might overlap.
2647 xfer->endpoint->isoc_next = (nframes + 3) & SOTG_FRAME_NUM_SOFR_MASK;
2648 xfer->endpoint->is_synced = 1;
2649 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2652 * compute how many milliseconds the insertion is ahead of the
2653 * current frame position:
2655 temp = (xfer->endpoint->isoc_next - nframes) & SOTG_FRAME_NUM_SOFR_MASK;
2658 * pre-compute when the isochronous transfer will be finished:
2660 xfer->isoc_time_complete =
2661 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2664 /* compute frame number for next insertion */
2665 xfer->endpoint->isoc_next += xfer->nframes;
2668 saf1761_otg_setup_standard_chain(xfer);
2672 saf1761_otg_device_isoc_start(struct usb_xfer *xfer)
2674 /* start TD chain */
2675 saf1761_otg_start_standard_chain(xfer);
2678 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods =
2680 .open = saf1761_otg_device_isoc_open,
2681 .close = saf1761_otg_device_isoc_close,
2682 .enter = saf1761_otg_device_isoc_enter,
2683 .start = saf1761_otg_device_isoc_start,
2686 /*------------------------------------------------------------------------*
2687 * saf1761_otg host side isochronous support
2688 *------------------------------------------------------------------------*/
2690 saf1761_otg_host_isoc_open(struct usb_xfer *xfer)
2696 saf1761_otg_host_isoc_close(struct usb_xfer *xfer)
2698 saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2702 saf1761_otg_host_isoc_enter(struct usb_xfer *xfer)
2704 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2708 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2709 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2711 /* get the current frame index - we don't need the high bits */
2713 nframes = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) & SOTG_FRINDEX_MASK) >> 3;
2716 * check if the frame index is within the window where the
2717 * frames will be inserted
2719 temp = (nframes - xfer->endpoint->isoc_next) & (SOTG_FRINDEX_MASK >> 3);
2721 if ((xfer->endpoint->is_synced == 0) ||
2722 (temp < xfer->nframes)) {
2724 * If there is data underflow or the pipe queue is
2725 * empty we schedule the transfer a few frames ahead
2726 * of the current frame position. Else two isochronous
2727 * transfers might overlap.
2729 xfer->endpoint->isoc_next = (nframes + 3) & (SOTG_FRINDEX_MASK >> 3);
2730 xfer->endpoint->is_synced = 1;
2731 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2734 * compute how many milliseconds the insertion is ahead of the
2735 * current frame position:
2737 temp = (xfer->endpoint->isoc_next - nframes) & (SOTG_FRINDEX_MASK >> 3);
2740 * pre-compute when the isochronous transfer will be finished:
2742 xfer->isoc_time_complete =
2743 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2746 /* compute frame number for next insertion */
2747 xfer->endpoint->isoc_next += xfer->nframes;
2750 saf1761_otg_setup_standard_chain(xfer);
2754 saf1761_otg_host_isoc_start(struct usb_xfer *xfer)
2756 /* start TD chain */
2757 saf1761_otg_start_standard_chain(xfer);
2760 static const struct usb_pipe_methods saf1761_otg_host_isoc_methods =
2762 .open = saf1761_otg_host_isoc_open,
2763 .close = saf1761_otg_host_isoc_close,
2764 .enter = saf1761_otg_host_isoc_enter,
2765 .start = saf1761_otg_host_isoc_start,
2768 /*------------------------------------------------------------------------*
2769 * saf1761_otg root control support
2770 *------------------------------------------------------------------------*
2771 * Simulate a hardware HUB by handling all the necessary requests.
2772 *------------------------------------------------------------------------*/
2774 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2776 static const struct usb_device_descriptor saf1761_otg_devd = {
2777 .bLength = sizeof(struct usb_device_descriptor),
2778 .bDescriptorType = UDESC_DEVICE,
2779 HSETW(.idVendor, 0x04cc),
2780 HSETW(.idProduct, 0x1761),
2781 .bcdUSB = {0x00, 0x02},
2782 .bDeviceClass = UDCLASS_HUB,
2783 .bDeviceSubClass = UDSUBCLASS_HUB,
2784 .bDeviceProtocol = UDPROTO_FSHUB,
2785 .bMaxPacketSize = 64,
2786 .bcdDevice = {0x00, 0x01},
2789 .bNumConfigurations = 1,
2792 static const struct usb_device_qualifier saf1761_otg_odevd = {
2793 .bLength = sizeof(struct usb_device_qualifier),
2794 .bDescriptorType = UDESC_DEVICE_QUALIFIER,
2795 .bcdUSB = {0x00, 0x02},
2796 .bDeviceClass = UDCLASS_HUB,
2797 .bDeviceSubClass = UDSUBCLASS_HUB,
2798 .bDeviceProtocol = UDPROTO_FSHUB,
2799 .bMaxPacketSize0 = 0,
2800 .bNumConfigurations = 0,
2803 static const struct saf1761_otg_config_desc saf1761_otg_confd = {
2805 .bLength = sizeof(struct usb_config_descriptor),
2806 .bDescriptorType = UDESC_CONFIG,
2807 .wTotalLength[0] = sizeof(saf1761_otg_confd),
2809 .bConfigurationValue = 1,
2810 .iConfiguration = 0,
2811 .bmAttributes = UC_SELF_POWERED,
2815 .bLength = sizeof(struct usb_interface_descriptor),
2816 .bDescriptorType = UDESC_INTERFACE,
2818 .bInterfaceClass = UICLASS_HUB,
2819 .bInterfaceSubClass = UISUBCLASS_HUB,
2820 .bInterfaceProtocol = 0,
2824 .bLength = sizeof(struct usb_endpoint_descriptor),
2825 .bDescriptorType = UDESC_ENDPOINT,
2826 .bEndpointAddress = (UE_DIR_IN | SAF1761_OTG_INTR_ENDPT),
2827 .bmAttributes = UE_INTERRUPT,
2828 .wMaxPacketSize[0] = 8,
2833 static const struct usb_hub_descriptor_min saf1761_otg_hubd = {
2834 .bDescLength = sizeof(saf1761_otg_hubd),
2835 .bDescriptorType = UDESC_HUB,
2836 .bNbrPorts = SOTG_NUM_PORTS,
2837 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
2838 .bPwrOn2PwrGood = 50,
2839 .bHubContrCurrent = 0,
2840 .DeviceRemovable = {0}, /* port is removable */
2843 #define STRING_VENDOR \
2846 #define STRING_PRODUCT \
2847 "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
2849 USB_MAKE_STRING_DESC(STRING_VENDOR, saf1761_otg_vendor);
2850 USB_MAKE_STRING_DESC(STRING_PRODUCT, saf1761_otg_product);
2853 saf1761_otg_roothub_exec(struct usb_device *udev,
2854 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2856 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(udev->bus);
2865 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2868 ptr = (const void *)&sc->sc_hub_temp;
2872 value = UGETW(req->wValue);
2873 index = UGETW(req->wIndex);
2875 /* demultiplex the control request */
2877 switch (req->bmRequestType) {
2878 case UT_READ_DEVICE:
2879 switch (req->bRequest) {
2880 case UR_GET_DESCRIPTOR:
2881 goto tr_handle_get_descriptor;
2883 goto tr_handle_get_config;
2885 goto tr_handle_get_status;
2891 case UT_WRITE_DEVICE:
2892 switch (req->bRequest) {
2893 case UR_SET_ADDRESS:
2894 goto tr_handle_set_address;
2896 goto tr_handle_set_config;
2897 case UR_CLEAR_FEATURE:
2898 goto tr_valid; /* nop */
2899 case UR_SET_DESCRIPTOR:
2900 goto tr_valid; /* nop */
2901 case UR_SET_FEATURE:
2907 case UT_WRITE_ENDPOINT:
2908 switch (req->bRequest) {
2909 case UR_CLEAR_FEATURE:
2910 switch (UGETW(req->wValue)) {
2911 case UF_ENDPOINT_HALT:
2912 goto tr_handle_clear_halt;
2913 case UF_DEVICE_REMOTE_WAKEUP:
2914 goto tr_handle_clear_wakeup;
2919 case UR_SET_FEATURE:
2920 switch (UGETW(req->wValue)) {
2921 case UF_ENDPOINT_HALT:
2922 goto tr_handle_set_halt;
2923 case UF_DEVICE_REMOTE_WAKEUP:
2924 goto tr_handle_set_wakeup;
2929 case UR_SYNCH_FRAME:
2930 goto tr_valid; /* nop */
2936 case UT_READ_ENDPOINT:
2937 switch (req->bRequest) {
2939 goto tr_handle_get_ep_status;
2945 case UT_WRITE_INTERFACE:
2946 switch (req->bRequest) {
2947 case UR_SET_INTERFACE:
2948 goto tr_handle_set_interface;
2949 case UR_CLEAR_FEATURE:
2950 goto tr_valid; /* nop */
2951 case UR_SET_FEATURE:
2957 case UT_READ_INTERFACE:
2958 switch (req->bRequest) {
2959 case UR_GET_INTERFACE:
2960 goto tr_handle_get_interface;
2962 goto tr_handle_get_iface_status;
2968 case UT_WRITE_CLASS_INTERFACE:
2969 case UT_WRITE_VENDOR_INTERFACE:
2973 case UT_READ_CLASS_INTERFACE:
2974 case UT_READ_VENDOR_INTERFACE:
2978 case UT_WRITE_CLASS_DEVICE:
2979 switch (req->bRequest) {
2980 case UR_CLEAR_FEATURE:
2982 case UR_SET_DESCRIPTOR:
2983 case UR_SET_FEATURE:
2990 case UT_WRITE_CLASS_OTHER:
2991 switch (req->bRequest) {
2992 case UR_CLEAR_FEATURE:
2993 if (index == SOTG_HOST_PORT_NUM)
2994 goto tr_handle_clear_port_feature_host;
2995 else if (index == SOTG_DEVICE_PORT_NUM)
2996 goto tr_handle_clear_port_feature_device;
2999 case UR_SET_FEATURE:
3000 if (index == SOTG_HOST_PORT_NUM)
3001 goto tr_handle_set_port_feature_host;
3002 else if (index == SOTG_DEVICE_PORT_NUM)
3003 goto tr_handle_set_port_feature_device;
3006 case UR_CLEAR_TT_BUFFER:
3016 case UT_READ_CLASS_OTHER:
3017 switch (req->bRequest) {
3018 case UR_GET_TT_STATE:
3019 goto tr_handle_get_tt_state;
3021 if (index == SOTG_HOST_PORT_NUM)
3022 goto tr_handle_get_port_status_host;
3023 else if (index == SOTG_DEVICE_PORT_NUM)
3024 goto tr_handle_get_port_status_device;
3032 case UT_READ_CLASS_DEVICE:
3033 switch (req->bRequest) {
3034 case UR_GET_DESCRIPTOR:
3035 goto tr_handle_get_class_descriptor;
3037 goto tr_handle_get_class_status;
3048 tr_handle_get_descriptor:
3049 switch (value >> 8) {
3053 len = sizeof(saf1761_otg_devd);
3054 ptr = (const void *)&saf1761_otg_devd;
3056 case UDESC_DEVICE_QUALIFIER:
3059 len = sizeof(saf1761_otg_odevd);
3060 ptr = (const void *)&saf1761_otg_odevd;
3065 len = sizeof(saf1761_otg_confd);
3066 ptr = (const void *)&saf1761_otg_confd;
3069 switch (value & 0xff) {
3070 case 0: /* Language table */
3071 len = sizeof(usb_string_lang_en);
3072 ptr = (const void *)&usb_string_lang_en;
3075 case 1: /* Vendor */
3076 len = sizeof(saf1761_otg_vendor);
3077 ptr = (const void *)&saf1761_otg_vendor;
3080 case 2: /* Product */
3081 len = sizeof(saf1761_otg_product);
3082 ptr = (const void *)&saf1761_otg_product;
3093 tr_handle_get_config:
3095 sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3098 tr_handle_get_status:
3100 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3103 tr_handle_set_address:
3107 sc->sc_rt_addr = value;
3110 tr_handle_set_config:
3113 sc->sc_conf = value;
3116 tr_handle_get_interface:
3118 sc->sc_hub_temp.wValue[0] = 0;
3121 tr_handle_get_tt_state:
3122 tr_handle_get_class_status:
3123 tr_handle_get_iface_status:
3124 tr_handle_get_ep_status:
3126 USETW(sc->sc_hub_temp.wValue, 0);
3130 tr_handle_set_interface:
3131 tr_handle_set_wakeup:
3132 tr_handle_clear_wakeup:
3133 tr_handle_clear_halt:
3136 tr_handle_clear_port_feature_device:
3137 DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
3140 case UHF_PORT_SUSPEND:
3141 saf1761_otg_wakeup_peer(sc);
3144 case UHF_PORT_ENABLE:
3145 sc->sc_flags.port_enabled = 0;
3149 case UHF_PORT_INDICATOR:
3150 case UHF_C_PORT_ENABLE:
3151 case UHF_C_PORT_OVER_CURRENT:
3152 case UHF_C_PORT_RESET:
3155 case UHF_PORT_POWER:
3156 sc->sc_flags.port_powered = 0;
3157 saf1761_otg_pull_down(sc);
3159 case UHF_C_PORT_CONNECTION:
3160 sc->sc_flags.change_connect = 0;
3162 case UHF_C_PORT_SUSPEND:
3163 sc->sc_flags.change_suspend = 0;
3166 err = USB_ERR_IOERROR;
3171 tr_handle_clear_port_feature_host:
3172 DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
3174 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3177 case UHF_PORT_ENABLE:
3178 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PED);
3180 case UHF_PORT_SUSPEND:
3181 if ((temp & SOTG_PORTSC1_SUSP) && (!(temp & SOTG_PORTSC1_FPR)))
3182 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_FPR);
3184 /* wait 20ms for resume sequence to complete */
3185 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3187 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~(SOTG_PORTSC1_SUSP |
3188 SOTG_PORTSC1_FPR | SOTG_PORTSC1_LS /* High Speed */ ));
3190 /* 4ms settle time */
3191 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3193 case UHF_PORT_INDICATOR:
3194 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PIC);
3197 case UHF_C_PORT_ENABLE:
3198 case UHF_C_PORT_OVER_CURRENT:
3199 case UHF_C_PORT_RESET:
3200 case UHF_C_PORT_SUSPEND:
3203 case UHF_PORT_POWER:
3204 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PP);
3206 case UHF_C_PORT_CONNECTION:
3207 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_ECSC);
3210 err = USB_ERR_IOERROR;
3215 tr_handle_set_port_feature_device:
3216 DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
3219 case UHF_PORT_ENABLE:
3220 sc->sc_flags.port_enabled = 1;
3222 case UHF_PORT_SUSPEND:
3223 case UHF_PORT_RESET:
3225 case UHF_PORT_INDICATOR:
3228 case UHF_PORT_POWER:
3229 sc->sc_flags.port_powered = 1;
3232 err = USB_ERR_IOERROR;
3237 tr_handle_set_port_feature_host:
3238 DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
3240 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3243 case UHF_PORT_ENABLE:
3244 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PED);
3246 case UHF_PORT_SUSPEND:
3247 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_SUSP);
3249 case UHF_PORT_RESET:
3250 DPRINTFN(6, "reset port %d\n", index);
3252 /* Start reset sequence. */
3253 temp &= ~(SOTG_PORTSC1_PED | SOTG_PORTSC1_PR);
3255 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PR);
3257 /* Wait for reset to complete. */
3258 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3259 USB_MS_TO_TICKS(usb_port_root_reset_delay));
3261 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp);
3263 /* Wait for HC to complete reset. */
3264 usb_pause_mtx(&sc->sc_bus.bus_mtx, USB_MS_TO_TICKS(2));
3266 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3268 DPRINTF("After reset, status=0x%08x\n", temp);
3269 if (temp & SOTG_PORTSC1_PR) {
3270 device_printf(sc->sc_bus.bdev, "port reset timeout\n");
3271 err = USB_ERR_TIMEOUT;
3274 if (!(temp & SOTG_PORTSC1_PED)) {
3275 /* Not a high speed device, give up ownership.*/
3276 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PO);
3280 DPRINTF("port %d reset, status = 0x%08x\n", index, temp);
3282 case UHF_PORT_POWER:
3283 DPRINTFN(3, "set port power %d\n", index);
3284 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PP);
3288 DPRINTFN(3, "set port test %d\n", index);
3291 case UHF_PORT_INDICATOR:
3292 DPRINTFN(3, "set port ind %d\n", index);
3293 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PIC);
3296 err = USB_ERR_IOERROR;
3301 tr_handle_get_port_status_device:
3303 DPRINTFN(9, "UR_GET_PORT_STATUS on port %d\n", index);
3305 if (sc->sc_flags.status_vbus) {
3306 saf1761_otg_pull_up(sc);
3308 saf1761_otg_pull_down(sc);
3311 /* Select FULL-speed and Device Side Mode */
3313 value = UPS_PORT_MODE_DEVICE;
3315 if (sc->sc_flags.port_powered)
3316 value |= UPS_PORT_POWER;
3318 if (sc->sc_flags.port_enabled)
3319 value |= UPS_PORT_ENABLED;
3321 if (sc->sc_flags.status_vbus &&
3322 sc->sc_flags.status_bus_reset)
3323 value |= UPS_CURRENT_CONNECT_STATUS;
3325 if (sc->sc_flags.status_suspend)
3326 value |= UPS_SUSPEND;
3328 USETW(sc->sc_hub_temp.ps.wPortStatus, value);
3332 if (sc->sc_flags.change_connect)
3333 value |= UPS_C_CONNECT_STATUS;
3335 if (sc->sc_flags.change_suspend)
3336 value |= UPS_C_SUSPEND;
3338 USETW(sc->sc_hub_temp.ps.wPortChange, value);
3339 len = sizeof(sc->sc_hub_temp.ps);
3342 tr_handle_get_port_status_host:
3344 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3346 DPRINTFN(9, "UR_GET_PORT_STATUS on port %d = 0x%08x\n", index, temp);
3350 if (temp & SOTG_PORTSC1_ECCS)
3351 i |= UPS_CURRENT_CONNECT_STATUS;
3352 if (temp & SOTG_PORTSC1_PED)
3353 i |= UPS_PORT_ENABLED;
3354 if ((temp & SOTG_PORTSC1_SUSP) && !(temp & SOTG_PORTSC1_FPR))
3356 if (temp & SOTG_PORTSC1_PR)
3358 if (temp & SOTG_PORTSC1_PP)
3359 i |= UPS_PORT_POWER;
3361 USETW(sc->sc_hub_temp.ps.wPortStatus, i);
3364 if (temp & SOTG_PORTSC1_ECSC)
3365 i |= UPS_C_CONNECT_STATUS;
3366 if (temp & SOTG_PORTSC1_FPR)
3369 i |= UPS_C_PORT_RESET;
3370 USETW(sc->sc_hub_temp.ps.wPortChange, i);
3371 len = sizeof(sc->sc_hub_temp.ps);
3374 tr_handle_get_class_descriptor:
3377 ptr = (const void *)&saf1761_otg_hubd;
3378 len = sizeof(saf1761_otg_hubd);
3382 err = USB_ERR_STALLED;
3390 saf1761_otg_xfer_setup(struct usb_setup_params *parm)
3392 struct saf1761_otg_softc *sc;
3393 struct usb_xfer *xfer;
3401 sc = SAF1761_OTG_BUS2SC(parm->udev->bus);
3402 xfer = parm->curr_xfer;
3405 * NOTE: This driver does not use any of the parameters that
3406 * are computed from the following values. Just set some
3407 * reasonable dummies:
3409 parm->hc_max_packet_size = 0x500;
3410 parm->hc_max_packet_count = 1;
3411 parm->hc_max_frame_size = 0x500;
3413 usbd_transfer_setup_sub(parm);
3416 * Compute maximum number of TDs:
3418 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
3420 if (ep_type == UE_CONTROL) {
3422 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
3425 ntd = xfer->nframes + 1 /* SYNC */ ;
3429 * check if "usbd_transfer_setup_sub" set an error
3435 * allocate transfer descriptors
3439 ep_no = xfer->endpointno & UE_ADDR;
3442 * Check profile stuff
3444 if (parm->udev->flags.usb_mode == USB_MODE_DEVICE) {
3445 const struct usb_hw_ep_profile *pf;
3447 saf1761_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
3450 /* should not happen */
3451 parm->err = USB_ERR_INVAL;
3456 dw1 = (xfer->address << 3) | (ep_type << 12);
3458 switch (parm->udev->speed) {
3459 case USB_SPEED_FULL:
3461 /* check if root HUB port is running High Speed */
3462 if (parm->udev->parent_hs_hub != NULL) {
3463 dw1 |= SOTG_PTD_DW1_ENABLE_SPLIT;
3464 dw1 |= (parm->udev->hs_port_no << 18);
3465 dw1 |= (parm->udev->hs_hub_addr << 25);
3466 if (parm->udev->speed == USB_SPEED_LOW)
3475 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
3477 for (n = 0; n != ntd; n++) {
3479 struct saf1761_otg_td *td;
3483 td = USB_ADD_BYTES(parm->buf, parm->size[0]);
3486 td->max_packet_size = xfer->max_packet_size;
3487 td->ep_index = ep_no;
3488 td->ep_type = ep_type;
3489 td->dw1_value = dw1;
3492 if (ep_type == UE_INTERRUPT) {
3493 if (xfer->interval > 32)
3494 td->interval = (32 / 2) << 3;
3496 td->interval = (xfer->interval / 2) << 3;
3500 td->obj_next = last_obj;
3504 parm->size[0] += sizeof(*td);
3507 xfer->td_start[0] = last_obj;
3511 saf1761_otg_xfer_unsetup(struct usb_xfer *xfer)
3516 saf1761_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3517 struct usb_endpoint *ep)
3521 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3523 edesc->bEndpointAddress, udev->flags.usb_mode);
3525 if (udev->parent_hub == NULL) {
3526 /* root HUB has special endpoint handling */
3530 /* Verify wMaxPacketSize */
3531 mps = UGETW(edesc->wMaxPacketSize);
3532 if (udev->speed == USB_SPEED_HIGH) {
3533 if ((mps >> 11) & 3) {
3534 DPRINTF("A packet multiplier different from "
3535 "1 is not supported\n");
3539 if (mps > SOTG_HS_MAX_PACKET_SIZE) {
3540 DPRINTF("Packet size %d bigger than %d\n",
3541 (int)mps, SOTG_HS_MAX_PACKET_SIZE);
3544 if (udev->flags.usb_mode == USB_MODE_DEVICE) {
3545 if (udev->speed != USB_SPEED_FULL &&
3546 udev->speed != USB_SPEED_HIGH) {
3550 switch (edesc->bmAttributes & UE_XFERTYPE) {
3551 case UE_ISOCHRONOUS:
3552 ep->methods = &saf1761_otg_device_isoc_methods;
3555 ep->methods = &saf1761_otg_non_isoc_methods;
3559 switch (edesc->bmAttributes & UE_XFERTYPE) {
3560 case UE_ISOCHRONOUS:
3561 ep->methods = &saf1761_otg_host_isoc_methods;
3564 ep->methods = &saf1761_otg_non_isoc_methods;
3571 saf1761_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3573 struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
3576 case USB_HW_POWER_SUSPEND:
3577 saf1761_otg_suspend(sc);
3579 case USB_HW_POWER_SHUTDOWN:
3580 saf1761_otg_uninit(sc);
3582 case USB_HW_POWER_RESUME:
3583 saf1761_otg_resume(sc);
3591 saf1761_otg_device_resume(struct usb_device *udev)
3593 struct saf1761_otg_softc *sc;
3594 struct saf1761_otg_td *td;
3595 struct usb_xfer *xfer;
3600 if (udev->flags.usb_mode != USB_MODE_HOST)
3603 sc = SAF1761_OTG_BUS2SC(udev->bus);
3605 USB_BUS_LOCK(&sc->sc_bus);
3606 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3608 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3610 if (xfer->xroot->udev != udev)
3613 td = xfer->td_transfer_cache;
3614 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3617 switch (td->ep_type) {
3619 x = td->channel - 32;
3620 sc->sc_host_intr_suspend_map &= ~(1U << x);
3621 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3622 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3624 case UE_ISOCHRONOUS:
3626 sc->sc_host_isoc_suspend_map &= ~(1U << x);
3627 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3628 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3631 x = td->channel - 64;
3632 sc->sc_host_async_suspend_map &= ~(1U << x);
3633 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3634 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3639 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3640 USB_BUS_UNLOCK(&sc->sc_bus);
3642 /* poll all transfers again to restart resumed ones */
3643 saf1761_otg_do_poll(&sc->sc_bus);
3647 saf1761_otg_device_suspend(struct usb_device *udev)
3649 struct saf1761_otg_softc *sc;
3650 struct saf1761_otg_td *td;
3651 struct usb_xfer *xfer;
3656 if (udev->flags.usb_mode != USB_MODE_HOST)
3659 sc = SAF1761_OTG_BUS2SC(udev->bus);
3661 USB_BUS_LOCK(&sc->sc_bus);
3662 USB_BUS_SPIN_LOCK(&sc->sc_bus);
3664 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3666 if (xfer->xroot->udev != udev)
3669 td = xfer->td_transfer_cache;
3670 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3673 switch (td->ep_type) {
3675 x = td->channel - 32;
3676 sc->sc_host_intr_suspend_map |= (1U << x);
3677 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3678 (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3680 case UE_ISOCHRONOUS:
3682 sc->sc_host_isoc_suspend_map |= (1U << x);
3683 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3684 (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3687 x = td->channel - 64;
3688 sc->sc_host_async_suspend_map |= (1U << x);
3689 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3690 (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3695 USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3696 USB_BUS_UNLOCK(&sc->sc_bus);
3699 static const struct usb_bus_methods saf1761_otg_bus_methods =
3701 .endpoint_init = &saf1761_otg_ep_init,
3702 .xfer_setup = &saf1761_otg_xfer_setup,
3703 .xfer_unsetup = &saf1761_otg_xfer_unsetup,
3704 .get_hw_ep_profile = &saf1761_otg_get_hw_ep_profile,
3705 .xfer_stall = &saf1761_otg_xfer_stall,
3706 .set_stall = &saf1761_otg_set_stall,
3707 .clear_stall = &saf1761_otg_clear_stall,
3708 .roothub_exec = &saf1761_otg_roothub_exec,
3709 .xfer_poll = &saf1761_otg_do_poll,
3710 .set_hw_power_sleep = saf1761_otg_set_hw_power_sleep,
3711 .device_resume = &saf1761_otg_device_resume,
3712 .device_suspend = &saf1761_otg_device_suspend,