sys/dev/usb/controller/saf1761_otg.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
   4  * All rights reserved.
   5  *
   6  * This software was developed by SRI International and the University of
   7  * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
   8  * ("CTSRD"), as part of the DARPA CRASH research programme.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * This file contains the driver for the SAF1761 series USB OTG
  34  * controller.
  35  *
  36  * Datasheet is available from:
  37  * http://www.nxp.com/products/automotive/multimedia/usb/SAF1761BE.html
  38  */
  39
  40 #ifdef USB_GLOBAL_INCLUDE_FILE
  41 #include USB_GLOBAL_INCLUDE_FILE
  42 #else
  43 #include <sys/stdint.h>
  44 #include <sys/stddef.h>
  45 #include <sys/param.h>
  46 #include <sys/queue.h>
  47 #include <sys/types.h>
  48 #include <sys/systm.h>
  49 #include <sys/kernel.h>
  50 #include <sys/bus.h>
  51 #include <sys/module.h>
  52 #include <sys/lock.h>
  53 #include <sys/mutex.h>
  54 #include <sys/condvar.h>
  55 #include <sys/sysctl.h>
  56 #include <sys/sx.h>
  57 #include <sys/unistd.h>
  58 #include <sys/callout.h>
  59 #include <sys/malloc.h>
  60 #include <sys/priv.h>
  61
  62 #include <dev/usb/usb.h>
  63 #include <dev/usb/usbdi.h>
  64
  65 #define USB_DEBUG_VAR saf1761_otg_debug
  66
  67 #include <dev/usb/usb_core.h>
  68 #include <dev/usb/usb_debug.h>
  69 #include <dev/usb/usb_busdma.h>
  70 #include <dev/usb/usb_process.h>
  71 #include <dev/usb/usb_transfer.h>
  72 #include <dev/usb/usb_device.h>
  73 #include <dev/usb/usb_hub.h>
  74 #include <dev/usb/usb_util.h>
  75
  76 #include <dev/usb/usb_controller.h>
  77 #include <dev/usb/usb_bus.h>
  78 #endif                                  /* USB_GLOBAL_INCLUDE_FILE */
  79
  80 #include <dev/usb/controller/saf1761_otg.h>
  81 #include <dev/usb/controller/saf1761_otg_reg.h>
  82
  83 #define SAF1761_OTG_BUS2SC(bus) \
  84    ((struct saf1761_otg_softc *)(((uint8_t *)(bus)) - \
  85     ((uint8_t *)&(((struct saf1761_otg_softc *)0)->sc_bus))))
  86
  87 #define SAF1761_OTG_PC2UDEV(pc) \
  88    (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
  89
  90 #define SAF1761_DCINTERRUPT_THREAD_IRQ                  \
  91   (SOTG_DCINTERRUPT_IEVBUS | SOTG_DCINTERRUPT_IEBRST |  \
  92   SOTG_DCINTERRUPT_IERESM | SOTG_DCINTERRUPT_IESUSP)
  93
  94 #ifdef USB_DEBUG
  95 static int saf1761_otg_debug = 0;
  96 static int saf1761_otg_forcefs = 0;
  97
  98 static
  99 SYSCTL_NODE(_hw_usb, OID_AUTO, saf1761_otg, CTLFLAG_RW, 0,
 100     "USB SAF1761 DCI");
 101
 102 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, debug, CTLFLAG_RW,
 103     &saf1761_otg_debug, 0, "SAF1761 DCI debug level");
 104 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, forcefs, CTLFLAG_RW,
 105     &saf1761_otg_forcefs, 0, "SAF1761 DCI force FULL speed");
 106 #endif
 107
 108 #define SAF1761_OTG_INTR_ENDPT 1
 109
 110 /* prototypes */
 111
 112 static const struct usb_bus_methods saf1761_otg_bus_methods;
 113 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods;
 114 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods;
 115
 116 static saf1761_otg_cmd_t saf1761_host_setup_tx;
 117 static saf1761_otg_cmd_t saf1761_host_bulk_data_rx;
 118 static saf1761_otg_cmd_t saf1761_host_bulk_data_tx;
 119 static saf1761_otg_cmd_t saf1761_host_intr_data_rx;
 120 static saf1761_otg_cmd_t saf1761_host_intr_data_tx;
 121 static saf1761_otg_cmd_t saf1761_host_isoc_data_rx;
 122 static saf1761_otg_cmd_t saf1761_host_isoc_data_tx;
 123 static saf1761_otg_cmd_t saf1761_device_setup_rx;
 124 static saf1761_otg_cmd_t saf1761_device_data_rx;
 125 static saf1761_otg_cmd_t saf1761_device_data_tx;
 126 static saf1761_otg_cmd_t saf1761_device_data_tx_sync;
 127 static void saf1761_otg_device_done(struct usb_xfer *, usb_error_t);
 128 static void saf1761_otg_do_poll(struct usb_bus *);
 129 static void saf1761_otg_standard_done(struct usb_xfer *);
 130 static void saf1761_otg_intr_set(struct usb_xfer *, uint8_t);
 131 static void saf1761_otg_root_intr(struct saf1761_otg_softc *);
 132
 133 /*
 134  * Here is a list of what the SAF1761 chip can support. The main
 135  * limitation is that the sum of the buffer sizes must be less than
 136  * 8192 bytes.
 137  */
 138 static const struct usb_hw_ep_profile saf1761_otg_ep_profile[] = {
 139
 140         [0] = {
 141                 .max_in_frame_size = 64,
 142                 .max_out_frame_size = 64,
 143                 .is_simplex = 0,
 144                 .support_control = 1,
 145         },
 146         [1] = {
 147                 .max_in_frame_size = SOTG_HS_MAX_PACKET_SIZE,
 148                 .max_out_frame_size = SOTG_HS_MAX_PACKET_SIZE,
 149                 .is_simplex = 0,
 150                 .support_interrupt = 1,
 151                 .support_bulk = 1,
 152                 .support_isochronous = 1,
 153                 .support_in = 1,
 154                 .support_out = 1,
 155         },
 156 };
 157
 158 static void
 159 saf1761_otg_get_hw_ep_profile(struct usb_device *udev,
 160     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 161 {
 162         if (ep_addr == 0) {
 163                 *ppf = saf1761_otg_ep_profile + 0;
 164         } else if (ep_addr < 8) {
 165                 *ppf = saf1761_otg_ep_profile + 1;
 166         } else {
 167                 *ppf = NULL;
 168         }
 169 }
 170
 171 static void
 172 saf1761_otg_pull_up(struct saf1761_otg_softc *sc)
 173 {
 174         /* activate pullup on D+, if possible */
 175
 176         if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) {
 177                 DPRINTF("\n");
 178
 179                 sc->sc_flags.d_pulled_up = 1;
 180         }
 181 }
 182
 183 static void
 184 saf1761_otg_pull_down(struct saf1761_otg_softc *sc)
 185 {
 186         /* release pullup on D+, if possible */
 187
 188         if (sc->sc_flags.d_pulled_up) {
 189                 DPRINTF("\n");
 190
 191                 sc->sc_flags.d_pulled_up = 0;
 192         }
 193 }
 194
 195 static void
 196 saf1761_otg_wakeup_peer(struct saf1761_otg_softc *sc)
 197 {
 198         uint16_t temp;
 199
 200         if (!(sc->sc_flags.status_suspend))
 201                 return;
 202
 203         DPRINTFN(5, "\n");
 204
 205         temp = SAF1761_READ_LE_4(sc, SOTG_MODE);
 206         SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp | SOTG_MODE_SNDRSU);
 207         SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp & ~SOTG_MODE_SNDRSU);
 208
 209         /* Wait 8ms for remote wakeup to complete. */
 210         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 211 }
 212
 213 static uint8_t
 214 saf1761_host_channel_alloc(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 215 {
 216         uint32_t x;
 217
 218         if (td->channel < SOTG_HOST_CHANNEL_MAX)
 219                 return (0);
 220
 221         /* check if device is suspended */
 222         if (SAF1761_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
 223                 return (1);             /* busy - cannot transfer data */
 224
 225         switch (td->ep_type) {
 226         case UE_INTERRUPT:
 227                 for (x = 0; x != 32; x++) {
 228                         if (sc->sc_host_intr_map & (1 << x))
 229                                 continue;
 230                         sc->sc_host_intr_map |= (1 << x);
 231                         td->channel = 32 + x;
 232                         return (0);
 233                 }
 234                 break;
 235         case UE_ISOCHRONOUS:
 236                 for (x = 0; x != 32; x++) {
 237                         if (sc->sc_host_isoc_map & (1 << x))
 238                                 continue;
 239                         sc->sc_host_isoc_map |= (1 << x);
 240                         td->channel = x;
 241                         return (0);
 242                 }
 243                 break;
 244         default:
 245                 for (x = 0; x != 32; x++) {
 246                         if (sc->sc_host_async_map & (1 << x))
 247                                 continue;
 248                         sc->sc_host_async_map |= (1 << x);
 249                         td->channel = 64 + x;
 250                         return (0);
 251                 }
 252                 break;
 253         }
 254         return (1);
 255 }
 256
 257 static void
 258 saf1761_host_channel_free(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 259 {
 260         uint32_t x;
 261
 262         if (td->channel >= SOTG_HOST_CHANNEL_MAX)
 263                 return;
 264
 265         switch (td->ep_type) {
 266         case UE_INTERRUPT:
 267                 x = td->channel - 32;
 268                 td->channel = SOTG_HOST_CHANNEL_MAX;
 269                 sc->sc_host_intr_map &= ~(1 << x);
 270                 sc->sc_host_intr_suspend_map &= ~(1 << x);
 271                 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 272                     (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 273                 break;
 274         case UE_ISOCHRONOUS:
 275                 x = td->channel;
 276                 td->channel = SOTG_HOST_CHANNEL_MAX;
 277                 sc->sc_host_isoc_map &= ~(1 << x);
 278                 sc->sc_host_isoc_suspend_map &= ~(1 << x);
 279                 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
 280                     (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
 281                 break;
 282         default:
 283                 x = td->channel - 64;
 284                 td->channel = SOTG_HOST_CHANNEL_MAX;
 285                 sc->sc_host_async_map &= ~(1 << x);
 286                 sc->sc_host_async_suspend_map &= ~(1 << x);
 287                 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 288                     (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 289                 break;
 290         }
 291 }
 292
 293 static uint32_t
 294 saf1761_peek_host_status_le_4(struct saf1761_otg_softc *sc, uint32_t offset)
 295 {
 296         uint32_t x = 0;
 297         while (1) {
 298                 uint32_t retval;
 299
 300                 SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
 301                 SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
 302                 retval = SAF1761_READ_LE_4(sc, offset);
 303                 if (retval != 0)
 304                         return (retval);
 305                 if (++x == 8) {
 306                         DPRINTF("STAUS is zero at offset 0x%x\n", offset);
 307                         break;
 308                 }
 309         }
 310         return (0);
 311 }
 312
 313 static void
 314 saf1761_read_host_memory(struct saf1761_otg_softc *sc,
 315     struct saf1761_otg_td *td, uint32_t len)
 316 {
 317         struct usb_page_search buf_res;
 318         uint32_t offset;
 319         uint32_t count;
 320
 321         if (len == 0)
 322                 return;
 323
 324         offset = SOTG_DATA_ADDR(td->channel);
 325         SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
 326         SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
 327
 328         /* optimised read first */
 329         while (len > 0) {
 330                 usbd_get_page(td->pc, td->offset, &buf_res);
 331
 332                 /* get correct length */
 333                 if (buf_res.length > len)
 334                         buf_res.length = len;
 335
 336                 /* check buffer alignment */
 337                 if (((uintptr_t)buf_res.buffer) & 3)
 338                         break;
 339
 340                 count = buf_res.length & ~3;
 341                 if (count == 0)
 342                         break;
 343
 344                 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 345                     offset, buf_res.buffer, count / 4);
 346
 347                 len -= count;
 348                 offset += count;
 349
 350                 /* update remainder and offset */
 351                 td->remainder -= count;
 352                 td->offset += count;
 353         }
 354
 355         if (len > 0) {
 356                 /* use bounce buffer */
 357                 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 358                     offset, sc->sc_bounce_buffer, (len + 3) / 4);
 359                 usbd_copy_in(td->pc, td->offset,
 360                     sc->sc_bounce_buffer, len);
 361
 362                 /* update remainder and offset */
 363                 td->remainder -= len;
 364                 td->offset += len;
 365         }
 366 }
 367
 368 static void
 369 saf1761_write_host_memory(struct saf1761_otg_softc *sc,
 370     struct saf1761_otg_td *td, uint32_t len)
 371 {
 372         struct usb_page_search buf_res;
 373         uint32_t offset;
 374         uint32_t count;
 375
 376         if (len == 0)
 377                 return;
 378
 379         offset = SOTG_DATA_ADDR(td->channel);
 380
 381         /* optimised write first */
 382         while (len > 0) {
 383                 usbd_get_page(td->pc, td->offset, &buf_res);
 384
 385                 /* get correct length */
 386                 if (buf_res.length > len)
 387                         buf_res.length = len;
 388
 389                 /* check buffer alignment */
 390                 if (((uintptr_t)buf_res.buffer) & 3)
 391                         break;
 392
 393                 count = buf_res.length & ~3;
 394                 if (count == 0)
 395                         break;
 396
 397                 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 398                     offset, buf_res.buffer, count / 4);
 399
 400                 len -= count;
 401                 offset += count;
 402
 403                 /* update remainder and offset */
 404                 td->remainder -= count;
 405                 td->offset += count;
 406         }
 407         if (len > 0) {
 408                 /* use bounce buffer */
 409                 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
 410                 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 411                     offset, sc->sc_bounce_buffer, (len + 3) / 4);
 412
 413                 /* update remainder and offset */
 414                 td->remainder -= len;
 415                 td->offset += len;
 416         }
 417 }
 418
 419 static uint8_t
 420 saf1761_host_setup_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 421 {
 422         uint32_t pdt_addr;
 423         uint32_t status;
 424         uint32_t count;
 425         uint32_t temp;
 426
 427         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 428                 pdt_addr = SOTG_PTD(td->channel);
 429
 430                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 431
 432                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 433
 434                 if (status & SOTG_PTD_DW3_ACTIVE) {
 435                         goto busy;
 436                 } else if (status & SOTG_PTD_DW3_HALTED) {
 437                         td->error_any = 1;
 438                 }
 439                 goto complete;
 440         }
 441         if (saf1761_host_channel_alloc(sc, td))
 442                 goto busy;
 443
 444         count = 8;
 445
 446         if (count != td->remainder) {
 447                 td->error_any = 1;
 448                 goto complete;
 449         }
 450
 451         saf1761_write_host_memory(sc, td, count);
 452
 453         pdt_addr = SOTG_PTD(td->channel);
 454
 455         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 456         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 457         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 458         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 459
 460         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 461         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 462
 463         temp = SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8;
 464         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 465
 466         temp = td->dw1_value | (2 << 10) /* SETUP PID */ | (td->ep_index >> 1);
 467         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 468
 469         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 470             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 471             (count << 3) /* transfer count */ |
 472             SOTG_PTD_DW0_VALID;
 473         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 474
 475         /* activate PTD */
 476         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 477             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 478
 479         td->toggle = 1;
 480 busy:
 481         return (1);     /* busy */
 482 complete:
 483         saf1761_host_channel_free(sc, td);
 484         return (0);     /* complete */
 485 }
 486
 487 static uint8_t
 488 saf1761_host_bulk_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 489 {
 490         uint32_t pdt_addr;
 491         uint32_t temp;
 492
 493         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 494                 uint32_t status;
 495                 uint32_t count;
 496                 uint8_t got_short;
 497
 498                 pdt_addr = SOTG_PTD(td->channel);
 499
 500                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 501
 502                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 503
 504                 if (status & SOTG_PTD_DW3_ACTIVE) {
 505                         goto busy;
 506                 } else if (status & SOTG_PTD_DW3_HALTED) {
 507                         if (!(status & SOTG_PTD_DW3_ERRORS))
 508                                 td->error_stall = 1;
 509                         td->error_any = 1;
 510                         goto complete;
 511                 }
 512                 count = (status & SOTG_PTD_DW3_XFER_COUNT);
 513                 got_short = 0;
 514
 515                 /* verify the packet byte count */
 516                 if (count != td->max_packet_size) {
 517                         if (count < td->max_packet_size) {
 518                                 /* we have a short packet */
 519                                 td->short_pkt = 1;
 520                                 got_short = 1;
 521                         } else {
 522                                 /* invalid USB packet */
 523                                 td->error_any = 1;
 524                                 goto complete;
 525                         }
 526                 }
 527                 td->toggle ^= 1;
 528
 529                 /* verify the packet byte count */
 530                 if (count > td->remainder) {
 531                         /* invalid USB packet */
 532                         td->error_any = 1;
 533                         goto complete;
 534                 }
 535
 536                 saf1761_read_host_memory(sc, td, count);
 537
 538                 /* check if we are complete */
 539                 if ((td->remainder == 0) || got_short) {
 540                         if (td->short_pkt)
 541                                 goto complete;
 542                         /* else need to receive a zero length packet */
 543                 }
 544                 saf1761_host_channel_free(sc, td);
 545         }
 546         if (saf1761_host_channel_alloc(sc, td))
 547                 goto busy;
 548
 549         /* set toggle, if any */
 550         if (td->set_toggle) {
 551                 td->set_toggle = 0;
 552                 td->toggle = 1;
 553         }
 554
 555         /* receive one more packet */
 556
 557         pdt_addr = SOTG_PTD(td->channel);
 558
 559         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 560         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 561         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 562         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 563
 564         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
 565             SOTG_PTD_DW3_CERR_2;
 566         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 567
 568         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
 569         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 570
 571         temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
 572         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 573
 574         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 575             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 576             (td->max_packet_size << 3) /* transfer count */ |
 577             SOTG_PTD_DW0_VALID;
 578         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 579
 580         /* activate PTD */
 581         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 582             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 583 busy:
 584         return (1);     /* busy */
 585 complete:
 586         saf1761_host_channel_free(sc, td);
 587         return (0);     /* complete */
 588 }
 589
 590 static uint8_t
 591 saf1761_host_bulk_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 592 {
 593         uint32_t pdt_addr;
 594         uint32_t temp;
 595         uint32_t count;
 596
 597         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 598                 uint32_t status;
 599
 600                 pdt_addr = SOTG_PTD(td->channel);
 601
 602                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 603
 604                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 605
 606                 if (status & SOTG_PTD_DW3_ACTIVE) {
 607                         goto busy;
 608                 } else if (status & SOTG_PTD_DW3_HALTED) {
 609                         if (!(status & SOTG_PTD_DW3_ERRORS))
 610                                 td->error_stall = 1;
 611                         td->error_any = 1;
 612                         goto complete;
 613                 }
 614                 /* check remainder */
 615                 if (td->remainder == 0) {
 616                         if (td->short_pkt)
 617                                 goto complete;
 618                         /* else we need to transmit a short packet */
 619                 }
 620                 saf1761_host_channel_free(sc, td);
 621         }
 622         if (saf1761_host_channel_alloc(sc, td))
 623                 goto busy;
 624
 625         count = td->max_packet_size;
 626         if (td->remainder < count) {
 627                 /* we have a short packet */
 628                 td->short_pkt = 1;
 629                 count = td->remainder;
 630         }
 631
 632         saf1761_write_host_memory(sc, td, count);
 633
 634         /* set toggle, if any */
 635         if (td->set_toggle) {
 636                 td->set_toggle = 0;
 637                 td->toggle = 1;
 638         }
 639
 640         /* send one more packet */
 641
 642         pdt_addr = SOTG_PTD(td->channel);
 643
 644         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 645         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 646         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 647         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 648
 649         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
 650             SOTG_PTD_DW3_CERR_2;
 651         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 652
 653         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
 654         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 655
 656         temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
 657         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 658
 659         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 660             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 661             (count << 3) /* transfer count */ |
 662             SOTG_PTD_DW0_VALID;
 663         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 664
 665         /* activate PTD */
 666         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 667             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 668
 669         td->toggle ^= 1;
 670 busy:
 671         return (1);     /* busy */
 672 complete:
 673         saf1761_host_channel_free(sc, td);
 674         return (0);     /* complete */
 675 }
 676
 677 static uint8_t
 678 saf1761_host_intr_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 679 {
 680         uint32_t pdt_addr;
 681         uint32_t temp;
 682
 683         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 684                 uint32_t status;
 685                 uint32_t count;
 686                 uint8_t got_short;
 687
 688                 pdt_addr = SOTG_PTD(td->channel);
 689
 690                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 691
 692                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 693
 694                 if (status & SOTG_PTD_DW3_ACTIVE) {
 695                         goto busy;
 696                 } else if (status & SOTG_PTD_DW3_HALTED) {
 697                         if (!(status & SOTG_PTD_DW3_ERRORS))
 698                                 td->error_stall = 1;
 699                         td->error_any = 1;
 700                         goto complete;
 701                 }
 702                 count = (status & SOTG_PTD_DW3_XFER_COUNT);
 703                 got_short = 0;
 704
 705                 /* verify the packet byte count */
 706                 if (count != td->max_packet_size) {
 707                         if (count < td->max_packet_size) {
 708                                 /* we have a short packet */
 709                                 td->short_pkt = 1;
 710                                 got_short = 1;
 711                         } else {
 712                                 /* invalid USB packet */
 713                                 td->error_any = 1;
 714                                 goto complete;
 715                         }
 716                 }
 717                 td->toggle ^= 1;
 718
 719                 /* verify the packet byte count */
 720                 if (count > td->remainder) {
 721                         /* invalid USB packet */
 722                         td->error_any = 1;
 723                         goto complete;
 724                 }
 725
 726                 saf1761_read_host_memory(sc, td, count);
 727
 728                 /* check if we are complete */
 729                 if ((td->remainder == 0) || got_short) {
 730                         if (td->short_pkt)
 731                                 goto complete;
 732                         /* else need to receive a zero length packet */
 733                 }
 734                 saf1761_host_channel_free(sc, td);
 735         }
 736         if (saf1761_host_channel_alloc(sc, td))
 737                 goto busy;
 738
 739         /* set toggle, if any */
 740         if (td->set_toggle) {
 741                 td->set_toggle = 0;
 742                 td->toggle = 1;
 743         }
 744
 745         /* receive one more packet */
 746
 747         pdt_addr = SOTG_PTD(td->channel);
 748
 749         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 750         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 751
 752         temp = (0xFC << td->uframe) & 0xFF;     /* complete split */
 753         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
 754
 755         temp = (1U << td->uframe);              /* start split */
 756         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
 757
 758         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 759         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 760
 761         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) | (td->interval & 0xF8);
 762         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 763
 764         temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
 765         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 766
 767         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 768             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 769             (td->max_packet_size << 3) /* transfer count */ |
 770             SOTG_PTD_DW0_VALID;
 771         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 772
 773         /* activate PTD */
 774         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 775             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 776 busy:
 777         return (1);     /* busy */
 778 complete:
 779         saf1761_host_channel_free(sc, td);
 780         return (0);     /* complete */
 781 }
 782
 783 static uint8_t
 784 saf1761_host_intr_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 785 {
 786         uint32_t pdt_addr;
 787         uint32_t temp;
 788         uint32_t count;
 789
 790         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 791                 uint32_t status;
 792
 793                 pdt_addr = SOTG_PTD(td->channel);
 794
 795                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 796
 797                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 798
 799                 if (status & SOTG_PTD_DW3_ACTIVE) {
 800                         goto busy;
 801                 } else if (status & SOTG_PTD_DW3_HALTED) {
 802                         if (!(status & SOTG_PTD_DW3_ERRORS))
 803                                 td->error_stall = 1;
 804                         td->error_any = 1;
 805                         goto complete;
 806                 }
 807
 808                 /* check remainder */
 809                 if (td->remainder == 0) {
 810                         if (td->short_pkt)
 811                                 goto complete;
 812                         /* else we need to transmit a short packet */
 813                 }
 814                 saf1761_host_channel_free(sc, td);
 815         }
 816         if (saf1761_host_channel_alloc(sc, td))
 817                 goto busy;
 818
 819         count = td->max_packet_size;
 820         if (td->remainder < count) {
 821                 /* we have a short packet */
 822                 td->short_pkt = 1;
 823                 count = td->remainder;
 824         }
 825
 826         saf1761_write_host_memory(sc, td, count);
 827
 828         /* set toggle, if any */
 829         if (td->set_toggle) {
 830                 td->set_toggle = 0;
 831                 td->toggle = 1;
 832         }
 833
 834         /* send one more packet */
 835
 836         pdt_addr = SOTG_PTD(td->channel);
 837
 838         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 839         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 840
 841         temp = (0xFC << td->uframe) & 0xFF;     /* complete split */
 842         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
 843
 844         temp = (1U << td->uframe);              /* start split */
 845         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
 846
 847         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 848         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 849
 850         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) | (td->interval & 0xF8);
 851         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 852
 853         temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
 854         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 855
 856         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 857             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 858             (count << 3) /* transfer count */ |
 859             SOTG_PTD_DW0_VALID;
 860         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 861
 862         /* activate PTD */
 863         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 864             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 865
 866         td->toggle ^= 1;
 867 busy:
 868         return (1);     /* busy */
 869 complete:
 870         saf1761_host_channel_free(sc, td);
 871         return (0);     /* complete */
 872 }
 873
 874 static uint8_t
 875 saf1761_host_isoc_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 876 {
 877         /* activate PTD */
 878         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
 879             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
 880
 881         return (1);     /* busy */
 882 }
 883
 884 static uint8_t
 885 saf1761_host_isoc_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 886 {
 887         /* activate PTD */
 888         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
 889             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
 890
 891         return (1);     /* busy */
 892 }
 893
 894 static void
 895 saf1761_otg_set_address(struct saf1761_otg_softc *sc, uint8_t addr)
 896 {
 897         DPRINTFN(5, "addr=%d\n", addr);
 898
 899         SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, addr | SOTG_ADDRESS_ENABLE);
 900 }
 901
 902
 903 static void
 904 saf1761_read_device_fifo(struct saf1761_otg_softc *sc,
 905     struct saf1761_otg_td *td, uint32_t len)
 906 {
 907         struct usb_page_search buf_res;
 908         uint32_t count;
 909
 910         /* optimised read first */
 911         while (len > 0) {
 912                 usbd_get_page(td->pc, td->offset, &buf_res);
 913
 914                 /* get correct length */
 915                 if (buf_res.length > len)
 916                         buf_res.length = len;
 917
 918                 /* check buffer alignment */
 919                 if (((uintptr_t)buf_res.buffer) & 3)
 920                         break;
 921
 922                 count = buf_res.length & ~3;
 923                 if (count == 0)
 924                         break;
 925
 926                 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 927                     SOTG_DATA_PORT, buf_res.buffer, count / 4);
 928
 929                 len -= count;
 930
 931                 /* update remainder and offset */
 932                 td->remainder -= count;
 933                 td->offset += count;
 934         }
 935
 936         if (len > 0) {
 937                 /* use bounce buffer */
 938                 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 939                     SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
 940                 usbd_copy_in(td->pc, td->offset,
 941                     sc->sc_bounce_buffer, len);
 942
 943                 /* update remainder and offset */
 944                 td->remainder -= len;
 945                 td->offset += len;
 946         }
 947 }
 948
 949 static void
 950 saf1761_write_device_fifo(struct saf1761_otg_softc *sc,
 951     struct saf1761_otg_td *td, uint32_t len)
 952 {
 953         struct usb_page_search buf_res;
 954         uint32_t count;
 955
 956         /* optimised write first */
 957         while (len > 0) {
 958                 usbd_get_page(td->pc, td->offset, &buf_res);
 959
 960                 /* get correct length */
 961                 if (buf_res.length > len)
 962                         buf_res.length = len;
 963
 964                 /* check buffer alignment */
 965                 if (((uintptr_t)buf_res.buffer) & 3)
 966                         break;
 967
 968                 count = buf_res.length & ~3;
 969                 if (count == 0)
 970                         break;
 971
 972                 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 973                     SOTG_DATA_PORT, buf_res.buffer, count / 4);
 974
 975                 len -= count;
 976
 977                 /* update remainder and offset */
 978                 td->remainder -= count;
 979                 td->offset += count;
 980         }
 981         if (len > 0) {
 982                 /* use bounce buffer */
 983                 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
 984                 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 985                     SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
 986
 987                 /* update remainder and offset */
 988                 td->remainder -= len;
 989                 td->offset += len;
 990         }
 991 }
 992
 993 static uint8_t
 994 saf1761_device_setup_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 995 {
 996         struct usb_device_request req;
 997         uint32_t count;
 998
 999         /* select the correct endpoint */
1000         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1001
1002         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1003
1004         /* check buffer status */
1005         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1006                 goto busy;
1007
1008         /* get buffer length */
1009         count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1010
1011         DPRINTFN(5, "count=%u rem=%u\n", count, td->remainder);
1012
1013         /* clear did stall */
1014         td->did_stall = 0;
1015
1016         /* clear stall */
1017         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
1018
1019         /* verify data length */
1020         if (count != td->remainder) {
1021                 DPRINTFN(0, "Invalid SETUP packet "
1022                     "length, %d bytes\n", count);
1023                 goto busy;
1024         }
1025         if (count != sizeof(req)) {
1026                 DPRINTFN(0, "Unsupported SETUP packet "
1027                     "length, %d bytes\n", count);
1028                 goto busy;
1029         }
1030         /* receive data */
1031         saf1761_read_device_fifo(sc, td, sizeof(req));
1032
1033         /* extract SETUP packet again */
1034         usbd_copy_out(td->pc, 0, &req, sizeof(req));
1035
1036         /* sneak peek the set address request */
1037         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1038             (req.bRequest == UR_SET_ADDRESS)) {
1039                 sc->sc_dv_addr = req.wValue[0] & 0x7F;
1040                 DPRINTF("Set address %d\n", sc->sc_dv_addr);
1041         } else {
1042                 sc->sc_dv_addr = 0xFF;
1043         }
1044         return (0);                     /* complete */
1045
1046 busy:
1047         /* abort any ongoing transfer */
1048         if (!td->did_stall) {
1049                 DPRINTFN(5, "stalling\n");
1050
1051                 /* set stall */
1052                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
1053
1054                 td->did_stall = 1;
1055         }
1056         return (1);                     /* not complete */
1057 }
1058
1059 static uint8_t
1060 saf1761_device_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1061 {
1062         uint32_t count;
1063         uint8_t got_short = 0;
1064
1065         if (td->ep_index == 0) {
1066                 /* select the correct endpoint */
1067                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1068
1069                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1070
1071                 /* check buffer status */
1072                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1073
1074                         if (td->remainder == 0) {
1075                                 /*
1076                                  * We are actually complete and have
1077                                  * received the next SETUP:
1078                                  */
1079                                 DPRINTFN(5, "faking complete\n");
1080                                 return (0);     /* complete */
1081                         }
1082                         DPRINTFN(5, "SETUP packet while receiving data\n");
1083                         /*
1084                          * USB Host Aborted the transfer.
1085                          */
1086                         td->error_any = 1;
1087                         return (0);     /* complete */
1088                 }
1089         }
1090         /* select the correct endpoint */
1091         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1092             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1093             SOTG_EP_INDEX_DIR_OUT);
1094
1095         /* enable data stage */
1096         if (td->set_toggle) {
1097                 td->set_toggle = 0;
1098                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1099         }
1100
1101         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1102
1103         /* check buffer status */
1104         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1105                 return (1);             /* not complete */
1106
1107         /* get buffer length */
1108         count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1109
1110         DPRINTFN(5, "rem=%u count=0x%04x\n", td->remainder, count);
1111
1112         /* verify the packet byte count */
1113         if (count != td->max_packet_size) {
1114                 if (count < td->max_packet_size) {
1115                         /* we have a short packet */
1116                         td->short_pkt = 1;
1117                         got_short = 1;
1118                 } else {
1119                         /* invalid USB packet */
1120                         td->error_any = 1;
1121                         return (0);     /* we are complete */
1122                 }
1123         }
1124         /* verify the packet byte count */
1125         if (count > td->remainder) {
1126                 /* invalid USB packet */
1127                 td->error_any = 1;
1128                 return (0);             /* we are complete */
1129         }
1130         /* receive data */
1131         saf1761_read_device_fifo(sc, td, count);
1132
1133         /* check if we are complete */
1134         if ((td->remainder == 0) || got_short) {
1135                 if (td->short_pkt) {
1136                         /* we are complete */
1137                         return (0);
1138                 }
1139                 /* else need to receive a zero length packet */
1140         }
1141         return (1);                     /* not complete */
1142 }
1143
1144 static uint8_t
1145 saf1761_device_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1146 {
1147         uint32_t count;
1148
1149         if (td->ep_index == 0) {
1150                 /* select the correct endpoint */
1151                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1152
1153                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1154
1155                 /* check buffer status */
1156                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1157                         DPRINTFN(5, "SETUP abort\n");
1158                         /*
1159                          * USB Host Aborted the transfer.
1160                          */
1161                         td->error_any = 1;
1162                         return (0);     /* complete */
1163                 }
1164         }
1165         /* select the correct endpoint */
1166         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1167             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1168             SOTG_EP_INDEX_DIR_IN);
1169
1170         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1171
1172         /* check buffer status */
1173         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1174                 return (1);             /* not complete */
1175
1176         /* enable data stage */
1177         if (td->set_toggle) {
1178                 td->set_toggle = 0;
1179                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1180         }
1181
1182         DPRINTFN(5, "rem=%u\n", td->remainder);
1183
1184         count = td->max_packet_size;
1185         if (td->remainder < count) {
1186                 /* we have a short packet */
1187                 td->short_pkt = 1;
1188                 count = td->remainder;
1189         }
1190         /* transmit data */
1191         saf1761_write_device_fifo(sc, td, count);
1192
1193         if (td->ep_index == 0) {
1194                 if (count < SOTG_FS_MAX_PACKET_SIZE) {
1195                         /* set end of packet */
1196                         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1197                 }
1198         } else {
1199                 if (count < SOTG_HS_MAX_PACKET_SIZE) {
1200                         /* set end of packet */
1201                         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1202                 }
1203         }
1204
1205         /* check remainder */
1206         if (td->remainder == 0) {
1207                 if (td->short_pkt) {
1208                         return (0);     /* complete */
1209                 }
1210                 /* else we need to transmit a short packet */
1211         }
1212         return (1);                     /* not complete */
1213 }
1214
1215 static uint8_t
1216 saf1761_device_data_tx_sync(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1217 {
1218         uint32_t count;
1219
1220         if (td->ep_index == 0) {
1221                 /* select the correct endpoint */
1222                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1223
1224                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1225
1226                 /* check buffer status */
1227                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1228                         DPRINTFN(5, "Faking complete\n");
1229                         return (0);     /* complete */
1230                 }
1231         }
1232         /* select the correct endpoint */
1233         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1234             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1235             SOTG_EP_INDEX_DIR_IN);
1236
1237         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1238
1239         /* check buffer status */
1240         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1241                 return (1);             /* busy */
1242
1243         if (sc->sc_dv_addr != 0xFF) {
1244                 /* write function address */
1245                 saf1761_otg_set_address(sc, sc->sc_dv_addr);
1246         }
1247         return (0);                     /* complete */
1248 }
1249
1250 static void
1251 saf1761_otg_xfer_do_fifo(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1252 {
1253         struct saf1761_otg_td *td;
1254         uint8_t toggle;
1255
1256         DPRINTFN(9, "\n");
1257
1258         td = xfer->td_transfer_cache;
1259         if (td == NULL)
1260                 return;
1261
1262         while (1) {
1263                 if ((td->func) (sc, td)) {
1264                         /* operation in progress */
1265                         break;
1266                 }
1267                 if (((void *)td) == xfer->td_transfer_last) {
1268                         goto done;
1269                 }
1270                 if (td->error_any) {
1271                         goto done;
1272                 } else if (td->remainder > 0) {
1273                         /*
1274                          * We had a short transfer. If there is no alternate
1275                          * next, stop processing !
1276                          */
1277                         if (!td->alt_next) {
1278                                 goto done;
1279                         }
1280                 }
1281                 /*
1282                  * Fetch the next transfer descriptor.
1283                  */
1284                 toggle = td->toggle;
1285                 td = td->obj_next;
1286                 td->toggle = toggle;
1287                 xfer->td_transfer_cache = td;
1288         }
1289         return;
1290
1291 done:
1292         /* compute all actual lengths */
1293         xfer->td_transfer_cache = NULL;
1294         sc->sc_xfer_complete = 1;
1295 }
1296
1297 static uint8_t
1298 saf1761_otg_xfer_do_complete(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1299 {
1300         struct saf1761_otg_td *td;
1301
1302         DPRINTFN(9, "\n");
1303
1304         td = xfer->td_transfer_cache;
1305         if (td == NULL) {
1306                 /* compute all actual lengths */
1307                 saf1761_otg_standard_done(xfer);
1308                 return (1);
1309         }
1310         return (0);
1311 }
1312
1313 static void
1314 saf1761_otg_interrupt_poll_locked(struct saf1761_otg_softc *sc)
1315 {
1316         struct usb_xfer *xfer;
1317
1318         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
1319                 saf1761_otg_xfer_do_fifo(sc, xfer);
1320 }
1321
1322 static void
1323 saf1761_otg_wait_suspend(struct saf1761_otg_softc *sc, uint8_t on)
1324 {
1325         if (on) {
1326                 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IESUSP;
1327                 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IERESM;
1328         } else {
1329                 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IESUSP;
1330                 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IERESM;
1331         }
1332         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1333 }
1334
1335 static void
1336 saf1761_otg_update_vbus(struct saf1761_otg_softc *sc)
1337 {
1338         uint16_t status;
1339
1340         /* read fresh status */
1341         status = SAF1761_READ_LE_4(sc, SOTG_STATUS);
1342
1343         DPRINTFN(4, "STATUS=0x%04x\n", status);
1344
1345         if ((status & SOTG_STATUS_VBUS_VLD) &&
1346             (status & SOTG_STATUS_ID)) {
1347                 /* VBUS present and device mode */
1348                 if (!sc->sc_flags.status_vbus) {
1349                         sc->sc_flags.status_vbus = 1;
1350
1351                         /* complete root HUB interrupt endpoint */
1352                         saf1761_otg_root_intr(sc);
1353                 }
1354         } else {
1355                 /* VBUS not-present or host mode */
1356                 if (sc->sc_flags.status_vbus) {
1357                         sc->sc_flags.status_vbus = 0;
1358                         sc->sc_flags.status_bus_reset = 0;
1359                         sc->sc_flags.status_suspend = 0;
1360                         sc->sc_flags.change_suspend = 0;
1361                         sc->sc_flags.change_connect = 1;
1362
1363                         /* complete root HUB interrupt endpoint */
1364                         saf1761_otg_root_intr(sc);
1365                 }
1366         }
1367 }
1368
1369 static void
1370 saf1761_otg_interrupt_complete_locked(struct saf1761_otg_softc *sc)
1371 {
1372         struct usb_xfer *xfer;
1373 repeat:
1374         /* scan for completion events */
1375         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1376                 if (saf1761_otg_xfer_do_complete(sc, xfer))
1377                         goto repeat;
1378         }
1379 }
1380
1381 int
1382 saf1761_otg_filter_interrupt(void *arg)
1383 {
1384         struct saf1761_otg_softc *sc = arg;
1385         int retval = FILTER_HANDLED;
1386         uint32_t hcstat;
1387         uint32_t status;
1388
1389         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1390
1391         hcstat = SAF1761_READ_LE_4(sc, SOTG_HCINTERRUPT);
1392         /* acknowledge all host controller interrupts */
1393         SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT, hcstat);
1394
1395         status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT);
1396         /* acknowledge all device controller interrupts */
1397         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT,
1398             status & ~SAF1761_DCINTERRUPT_THREAD_IRQ);
1399
1400         (void) SAF1761_READ_LE_4(sc, SOTG_ATL_PTD_DONE_PTD);
1401         (void) SAF1761_READ_LE_4(sc, SOTG_INT_PTD_DONE_PTD);
1402         (void) SAF1761_READ_LE_4(sc, SOTG_ISO_PTD_DONE_PTD);
1403
1404         if (status & SAF1761_DCINTERRUPT_THREAD_IRQ)
1405                 retval = FILTER_SCHEDULE_THREAD;
1406
1407         /* poll FIFOs, if any */
1408         saf1761_otg_interrupt_poll_locked(sc);
1409
1410         if (sc->sc_xfer_complete != 0)
1411                 retval = FILTER_SCHEDULE_THREAD;
1412
1413         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1414
1415         return (retval);
1416 }
1417
1418 void
1419 saf1761_otg_interrupt(void *arg)
1420 {
1421         struct saf1761_otg_softc *sc = arg;
1422         uint32_t status;
1423
1424         USB_BUS_LOCK(&sc->sc_bus);
1425         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1426
1427         status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT) &
1428             SAF1761_DCINTERRUPT_THREAD_IRQ;
1429
1430         /* acknowledge all device controller interrupts */
1431         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT, status);
1432
1433         DPRINTF("DCINTERRUPT=0x%08x SOF=0x%08x "
1434             "FRINDEX=0x%08x\n", status,
1435             SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM),
1436             SAF1761_READ_LE_4(sc, SOTG_FRINDEX));
1437
1438         /* update VBUS and ID bits, if any */
1439         if (status & SOTG_DCINTERRUPT_IEVBUS)
1440                 saf1761_otg_update_vbus(sc);
1441
1442         if (status & SOTG_DCINTERRUPT_IEBRST) {
1443                 /* unlock device */
1444                 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1445                     SOTG_UNLOCK_DEVICE_CODE);
1446
1447                 /* Enable device address */
1448                 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS,
1449                     SOTG_ADDRESS_ENABLE);
1450
1451                 sc->sc_flags.status_bus_reset = 1;
1452                 sc->sc_flags.status_suspend = 0;
1453                 sc->sc_flags.change_suspend = 0;
1454                 sc->sc_flags.change_connect = 1;
1455
1456                 /* disable resume interrupt */
1457                 saf1761_otg_wait_suspend(sc, 1);
1458                 /* complete root HUB interrupt endpoint */
1459                 saf1761_otg_root_intr(sc);
1460         }
1461         /*
1462          * If "RESUME" and "SUSPEND" is set at the same time we
1463          * interpret that like "RESUME". Resume is set when there is
1464          * at least 3 milliseconds of inactivity on the USB BUS:
1465          */
1466         if (status & SOTG_DCINTERRUPT_IERESM) {
1467                 /* unlock device */
1468                 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1469                     SOTG_UNLOCK_DEVICE_CODE);
1470
1471                 if (sc->sc_flags.status_suspend) {
1472                         sc->sc_flags.status_suspend = 0;
1473                         sc->sc_flags.change_suspend = 1;
1474                         /* disable resume interrupt */
1475                         saf1761_otg_wait_suspend(sc, 1);
1476                         /* complete root HUB interrupt endpoint */
1477                         saf1761_otg_root_intr(sc);
1478                 }
1479         } else if (status & SOTG_DCINTERRUPT_IESUSP) {
1480                 if (!sc->sc_flags.status_suspend) {
1481                         sc->sc_flags.status_suspend = 1;
1482                         sc->sc_flags.change_suspend = 1;
1483                         /* enable resume interrupt */
1484                         saf1761_otg_wait_suspend(sc, 0);
1485                         /* complete root HUB interrupt endpoint */
1486                         saf1761_otg_root_intr(sc);
1487                 }
1488         }
1489
1490         if (sc->sc_xfer_complete != 0) {
1491                 sc->sc_xfer_complete = 0;
1492
1493                 /* complete FIFOs, if any */
1494                 saf1761_otg_interrupt_complete_locked(sc);
1495         }
1496         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1497         USB_BUS_UNLOCK(&sc->sc_bus);
1498 }
1499
1500 static void
1501 saf1761_otg_setup_standard_chain_sub(struct saf1761_otg_std_temp *temp)
1502 {
1503         struct saf1761_otg_td *td;
1504
1505         /* get current Transfer Descriptor */
1506         td = temp->td_next;
1507         temp->td = td;
1508
1509         /* prepare for next TD */
1510         temp->td_next = td->obj_next;
1511
1512         /* fill out the Transfer Descriptor */
1513         td->func = temp->func;
1514         td->pc = temp->pc;
1515         td->offset = temp->offset;
1516         td->remainder = temp->len;
1517         td->error_any = 0;
1518         td->error_stall = 0;
1519         td->set_toggle = 0;
1520         td->did_stall = temp->did_stall;
1521         td->short_pkt = temp->short_pkt;
1522         td->alt_next = temp->setup_alt_next;
1523         td->channel = SOTG_HOST_CHANNEL_MAX;
1524 }
1525
1526 static void
1527 saf1761_otg_setup_standard_chain(struct usb_xfer *xfer)
1528 {
1529         struct saf1761_otg_std_temp temp;
1530         struct saf1761_otg_softc *sc;
1531         struct saf1761_otg_td *td;
1532         uint32_t x;
1533         uint8_t ep_no;
1534         uint8_t ep_type;
1535         uint8_t need_sync;
1536         uint8_t is_host;
1537
1538         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1539             xfer->address, UE_GET_ADDR(xfer->endpointno),
1540             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1541
1542         temp.max_frame_size = xfer->max_frame_size;
1543
1544         td = xfer->td_start[0];
1545         xfer->td_transfer_first = td;
1546         xfer->td_transfer_cache = td;
1547
1548         /* setup temp */
1549
1550         temp.pc = NULL;
1551         temp.td = NULL;
1552         temp.td_next = xfer->td_start[0];
1553         temp.offset = 0;
1554         temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
1555             xfer->flags_int.isochronous_xfr;
1556         temp.did_stall = !xfer->flags_int.control_stall;
1557
1558         is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
1559
1560         sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1561         ep_no = (xfer->endpointno & UE_ADDR);
1562         ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
1563
1564         /* check if we should prepend a setup message */
1565
1566         if (xfer->flags_int.control_xfr) {
1567                 if (xfer->flags_int.control_hdr) {
1568
1569                         if (is_host)
1570                                 temp.func = &saf1761_host_setup_tx;
1571                         else
1572                                 temp.func = &saf1761_device_setup_rx;
1573
1574                         temp.len = xfer->frlengths[0];
1575                         temp.pc = xfer->frbuffers + 0;
1576                         temp.short_pkt = temp.len ? 1 : 0;
1577                         /* check for last frame */
1578                         if (xfer->nframes == 1) {
1579                                 /* no STATUS stage yet, SETUP is last */
1580                                 if (xfer->flags_int.control_act)
1581                                         temp.setup_alt_next = 0;
1582                         }
1583                         saf1761_otg_setup_standard_chain_sub(&temp);
1584                 }
1585                 x = 1;
1586         } else {
1587                 x = 0;
1588         }
1589
1590         if (x != xfer->nframes) {
1591                 if (xfer->endpointno & UE_DIR_IN) {
1592                         if (is_host) {
1593                                 if (ep_type == UE_INTERRUPT)
1594                                         temp.func = &saf1761_host_intr_data_rx;
1595                                 else if (ep_type == UE_ISOCHRONOUS)
1596                                         temp.func = &saf1761_host_isoc_data_rx;
1597                                 else
1598                                         temp.func = &saf1761_host_bulk_data_rx;
1599                                 need_sync = 0;
1600                         } else {
1601                                 temp.func = &saf1761_device_data_tx;
1602                                 need_sync = 1;
1603                         }
1604                 } else {
1605                         if (is_host) {
1606                                 if (ep_type == UE_INTERRUPT)
1607                                         temp.func = &saf1761_host_intr_data_tx;
1608                                 else if (ep_type == UE_ISOCHRONOUS)
1609                                         temp.func = &saf1761_host_isoc_data_tx;
1610                                 else
1611                                         temp.func = &saf1761_host_bulk_data_tx;
1612                                 need_sync = 0;
1613                         } else {
1614                                 temp.func = &saf1761_device_data_rx;
1615                                 need_sync = 0;
1616                         }
1617                 }
1618
1619                 /* setup "pc" pointer */
1620                 temp.pc = xfer->frbuffers + x;
1621         } else {
1622                 need_sync = 0;
1623         }
1624
1625         while (x != xfer->nframes) {
1626
1627                 /* DATA0 / DATA1 message */
1628
1629                 temp.len = xfer->frlengths[x];
1630
1631                 x++;
1632
1633                 if (x == xfer->nframes) {
1634                         if (xfer->flags_int.control_xfr) {
1635                                 if (xfer->flags_int.control_act) {
1636                                         temp.setup_alt_next = 0;
1637                                 }
1638                         } else {
1639                                 temp.setup_alt_next = 0;
1640                         }
1641                 }
1642                 if (temp.len == 0) {
1643
1644                         /* make sure that we send an USB packet */
1645
1646                         temp.short_pkt = 0;
1647
1648                 } else {
1649
1650                         /* regular data transfer */
1651
1652                         temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1653                 }
1654
1655                 saf1761_otg_setup_standard_chain_sub(&temp);
1656
1657                 if (xfer->flags_int.isochronous_xfr) {
1658                         temp.offset += temp.len;
1659                 } else {
1660                         /* get next Page Cache pointer */
1661                         temp.pc = xfer->frbuffers + x;
1662                 }
1663         }
1664
1665         /* check for control transfer */
1666         if (xfer->flags_int.control_xfr) {
1667                 /* always setup a valid "pc" pointer for status and sync */
1668                 temp.pc = xfer->frbuffers + 0;
1669                 temp.len = 0;
1670                 temp.short_pkt = 0;
1671                 temp.setup_alt_next = 0;
1672
1673                 /* check if we should append a status stage */
1674                 if (!xfer->flags_int.control_act) {
1675
1676                         /*
1677                          * Send a DATA1 message and invert the current
1678                          * endpoint direction.
1679                          */
1680                         if (xfer->endpointno & UE_DIR_IN) {
1681                                 if (is_host) {
1682                                         temp.func = &saf1761_host_bulk_data_tx;
1683                                         need_sync = 0;
1684                                 } else {
1685                                         temp.func = &saf1761_device_data_rx;
1686                                         need_sync = 0;
1687                                 }
1688                         } else {
1689                                 if (is_host) {
1690                                         temp.func = &saf1761_host_bulk_data_rx;
1691                                         need_sync = 0;
1692                                 } else {
1693                                         temp.func = &saf1761_device_data_tx;
1694                                         need_sync = 1;
1695                                 }
1696                         }
1697                         temp.len = 0;
1698                         temp.short_pkt = 0;
1699
1700                         saf1761_otg_setup_standard_chain_sub(&temp);
1701
1702                         /* data toggle should be DATA1 */
1703                         td = temp.td;
1704                         td->set_toggle = 1;
1705
1706                         if (need_sync) {
1707                                 /* we need a SYNC point after TX */
1708                                 temp.func = &saf1761_device_data_tx_sync;
1709                                 saf1761_otg_setup_standard_chain_sub(&temp);
1710                         }
1711                 }
1712         } else {
1713                 if (need_sync) {
1714                         temp.pc = xfer->frbuffers + 0;
1715                         temp.len = 0;
1716                         temp.short_pkt = 0;
1717                         temp.setup_alt_next = 0;
1718
1719                         /* we need a SYNC point after TX */
1720                         temp.func = &saf1761_device_data_tx_sync;
1721                         saf1761_otg_setup_standard_chain_sub(&temp);
1722                 }
1723         }
1724
1725         /* must have at least one frame! */
1726         td = temp.td;
1727         xfer->td_transfer_last = td;
1728
1729         if (is_host) {
1730                 /* get first again */
1731                 td = xfer->td_transfer_first;
1732                 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
1733         }
1734 }
1735
1736 static void
1737 saf1761_otg_timeout(void *arg)
1738 {
1739         struct usb_xfer *xfer = arg;
1740
1741         DPRINTF("xfer=%p\n", xfer);
1742
1743         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1744
1745         /* transfer is transferred */
1746         saf1761_otg_device_done(xfer, USB_ERR_TIMEOUT);
1747 }
1748
1749 static void
1750 saf1761_otg_intr_set(struct usb_xfer *xfer, uint8_t set)
1751 {
1752         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1753         uint8_t ep_no = (xfer->endpointno & UE_ADDR);
1754         uint32_t mask;
1755
1756         DPRINTFN(15, "endpoint=%d set=%d\n", xfer->endpointno, set);
1757
1758         if (ep_no == 0) {
1759                 mask = SOTG_DCINTERRUPT_IEPRX(0) |
1760                     SOTG_DCINTERRUPT_IEPTX(0) |
1761                     SOTG_DCINTERRUPT_IEP0SETUP;
1762         } else if (xfer->endpointno & UE_DIR_IN) {
1763                 mask = SOTG_DCINTERRUPT_IEPTX(ep_no);
1764         } else {
1765                 mask = SOTG_DCINTERRUPT_IEPRX(ep_no);
1766         }
1767
1768         if (set)
1769                 sc->sc_intr_enable |= mask;
1770         else
1771                 sc->sc_intr_enable &= ~mask;
1772
1773         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1774 }
1775
1776 static void
1777 saf1761_otg_start_standard_chain(struct usb_xfer *xfer)
1778 {
1779         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1780
1781         DPRINTFN(9, "\n");
1782
1783         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1784
1785         /* poll one time */
1786         saf1761_otg_xfer_do_fifo(sc, xfer);
1787
1788         if (xfer->td_transfer_cache != NULL) {
1789                 /*
1790                  * Only enable the endpoint interrupt when we are
1791                  * actually waiting for data, hence we are dealing
1792                  * with level triggered interrupts !
1793                  */
1794                 saf1761_otg_intr_set(xfer, 1);
1795
1796                 /* put transfer on interrupt queue */
1797                 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1798
1799                 /* start timeout, if any */
1800                 if (xfer->timeout != 0) {
1801                         usbd_transfer_timeout_ms(xfer,
1802                             &saf1761_otg_timeout, xfer->timeout);
1803                 }
1804         } else {
1805                 /* catch completion, if any */
1806                 saf1761_otg_interrupt_complete_locked(sc);
1807         }
1808         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1809 }
1810
1811 static void
1812 saf1761_otg_root_intr(struct saf1761_otg_softc *sc)
1813 {
1814         DPRINTFN(9, "\n");
1815
1816         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1817
1818         /* set port bit - we only have one port */
1819         sc->sc_hub_idata[0] = 0x02;
1820
1821         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1822             sizeof(sc->sc_hub_idata));
1823 }
1824
1825 static usb_error_t
1826 saf1761_otg_standard_done_sub(struct usb_xfer *xfer)
1827 {
1828         struct saf1761_otg_td *td;
1829         uint32_t len;
1830         usb_error_t error;
1831
1832         DPRINTFN(9, "\n");
1833
1834         td = xfer->td_transfer_cache;
1835
1836         do {
1837                 len = td->remainder;
1838
1839                 /* store last data toggle */
1840                 xfer->endpoint->toggle_next = td->toggle;
1841
1842                 if (xfer->aframes != xfer->nframes) {
1843                         /*
1844                          * Verify the length and subtract
1845                          * the remainder from "frlengths[]":
1846                          */
1847                         if (len > xfer->frlengths[xfer->aframes]) {
1848                                 td->error_any = 1;
1849                         } else {
1850                                 xfer->frlengths[xfer->aframes] -= len;
1851                         }
1852                 }
1853                 /* Check for transfer error */
1854                 if (td->error_any) {
1855                         /* the transfer is finished */
1856                         error = (td->error_stall ?
1857                             USB_ERR_STALLED : USB_ERR_IOERROR);
1858                         td = NULL;
1859                         break;
1860                 }
1861                 /* Check for short transfer */
1862                 if (len > 0) {
1863                         if (xfer->flags_int.short_frames_ok ||
1864                             xfer->flags_int.isochronous_xfr) {
1865                                 /* follow alt next */
1866                                 if (td->alt_next) {
1867                                         td = td->obj_next;
1868                                 } else {
1869                                         td = NULL;
1870                                 }
1871                         } else {
1872                                 /* the transfer is finished */
1873                                 td = NULL;
1874                         }
1875                         error = 0;
1876                         break;
1877                 }
1878                 td = td->obj_next;
1879
1880                 /* this USB frame is complete */
1881                 error = 0;
1882                 break;
1883
1884         } while (0);
1885
1886         /* update transfer cache */
1887
1888         xfer->td_transfer_cache = td;
1889
1890         return (error);
1891 }
1892
1893 static void
1894 saf1761_otg_standard_done(struct usb_xfer *xfer)
1895 {
1896         usb_error_t err = 0;
1897
1898         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1899             xfer, xfer->endpoint);
1900
1901         /* reset scanner */
1902
1903         xfer->td_transfer_cache = xfer->td_transfer_first;
1904
1905         if (xfer->flags_int.control_xfr) {
1906
1907                 if (xfer->flags_int.control_hdr) {
1908
1909                         err = saf1761_otg_standard_done_sub(xfer);
1910                 }
1911                 xfer->aframes = 1;
1912
1913                 if (xfer->td_transfer_cache == NULL) {
1914                         goto done;
1915                 }
1916         }
1917         while (xfer->aframes != xfer->nframes) {
1918
1919                 err = saf1761_otg_standard_done_sub(xfer);
1920                 xfer->aframes++;
1921
1922                 if (xfer->td_transfer_cache == NULL) {
1923                         goto done;
1924                 }
1925         }
1926
1927         if (xfer->flags_int.control_xfr &&
1928             !xfer->flags_int.control_act) {
1929
1930                 err = saf1761_otg_standard_done_sub(xfer);
1931         }
1932 done:
1933         saf1761_otg_device_done(xfer, err);
1934 }
1935
1936 /*------------------------------------------------------------------------*
1937  *      saf1761_otg_device_done
1938  *
1939  * NOTE: this function can be called more than one time on the
1940  * same USB transfer!
1941  *------------------------------------------------------------------------*/
1942 static void
1943 saf1761_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
1944 {
1945         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1946
1947         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1948
1949         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1950             xfer, xfer->endpoint, error);
1951
1952         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1953
1954         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1955                 saf1761_otg_intr_set(xfer, 0);
1956         } else {
1957                 struct saf1761_otg_td *td;
1958
1959                 td = xfer->td_transfer_first;
1960
1961                 if (td != NULL)
1962                         saf1761_host_channel_free(sc, td);
1963         }
1964
1965         /* dequeue transfer and start next transfer */
1966         usbd_transfer_done(xfer, error);
1967
1968         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1969 }
1970
1971 static void
1972 saf1761_otg_xfer_stall(struct usb_xfer *xfer)
1973 {
1974         saf1761_otg_device_done(xfer, USB_ERR_STALLED);
1975 }
1976
1977 static void
1978 saf1761_otg_set_stall(struct usb_device *udev,
1979     struct usb_endpoint *ep, uint8_t *did_stall)
1980 {
1981         struct saf1761_otg_softc *sc;
1982         uint8_t ep_no;
1983         uint8_t ep_type;
1984         uint8_t ep_dir;
1985
1986         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1987
1988         /* check mode */
1989         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1990                 /* not supported */
1991                 return;
1992         }
1993
1994         DPRINTFN(5, "endpoint=%p\n", ep);
1995
1996         /* set STALL bit */
1997         sc = SAF1761_OTG_BUS2SC(udev->bus);
1998
1999         ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2000         ep_dir = (ep->edesc->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT));
2001         ep_type = (ep->edesc->bmAttributes & UE_XFERTYPE);
2002
2003         if (ep_type == UE_CONTROL) {
2004                 /* should not happen */
2005                 return;
2006         }
2007         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2008
2009         /* select the correct endpoint */
2010         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2011             (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2012             ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2013             SOTG_EP_INDEX_DIR_OUT));
2014
2015         /* set stall */
2016         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
2017
2018         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2019 }
2020
2021 static void
2022 saf1761_otg_clear_stall_sub_locked(struct saf1761_otg_softc *sc,
2023     uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2024 {
2025         if (ep_type == UE_CONTROL) {
2026                 /* clearing stall is not needed */
2027                 return;
2028         }
2029         /* select the correct endpoint */
2030         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2031             (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2032             ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2033             SOTG_EP_INDEX_DIR_OUT));
2034
2035         /* disable endpoint */
2036         SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, 0);
2037         /* enable endpoint again - will clear data toggle */
2038         SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, ep_type | SOTG_EP_TYPE_ENABLE);
2039
2040         /* clear buffer */
2041         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_CLBUF);
2042         /* clear stall */
2043         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
2044 }
2045
2046 static void
2047 saf1761_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
2048 {
2049         struct saf1761_otg_softc *sc;
2050         struct usb_endpoint_descriptor *ed;
2051
2052         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2053
2054         DPRINTFN(5, "endpoint=%p\n", ep);
2055
2056         /* check mode */
2057         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2058                 /* not supported */
2059                 return;
2060         }
2061         /* get softc */
2062         sc = SAF1761_OTG_BUS2SC(udev->bus);
2063
2064         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2065
2066         /* get endpoint descriptor */
2067         ed = ep->edesc;
2068
2069         /* reset endpoint */
2070         saf1761_otg_clear_stall_sub_locked(sc,
2071             (ed->bEndpointAddress & UE_ADDR),
2072             (ed->bmAttributes & UE_XFERTYPE),
2073             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
2074
2075         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2076 }
2077
2078 usb_error_t
2079 saf1761_otg_init(struct saf1761_otg_softc *sc)
2080 {
2081         const struct usb_hw_ep_profile *pf;
2082         uint32_t x;
2083
2084         DPRINTF("\n");
2085
2086         /* set up the bus structure */
2087         sc->sc_bus.usbrev = USB_REV_2_0;
2088         sc->sc_bus.methods = &saf1761_otg_bus_methods;
2089
2090         USB_BUS_LOCK(&sc->sc_bus);
2091
2092         /* Reset Host controller, including HW mode */
2093         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_ALL);
2094
2095         DELAY(1000);
2096
2097         /* Reset Host controller, including HW mode */
2098         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_HC);
2099
2100         /* wait a bit */
2101         DELAY(1000);
2102
2103         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, 0);
2104
2105         /* wait a bit */
2106         DELAY(1000);
2107
2108         /* Enable interrupts */
2109         sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN |
2110             SOTG_HW_MODE_CTRL_COMN_INT;
2111
2112         /* unlock device */
2113         SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE, SOTG_UNLOCK_DEVICE_CODE);
2114
2115         /*
2116          * Set correct hardware mode, must be written twice if bus
2117          * width is changed:
2118          */
2119         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2120         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2121
2122         SAF1761_WRITE_LE_4(sc, SOTG_DCSCRATCH, 0xdeadbeef);
2123         SAF1761_WRITE_LE_4(sc, SOTG_HCSCRATCH, 0xdeadbeef);
2124
2125         DPRINTF("DCID=0x%08x VEND_PROD=0x%08x HWMODE=0x%08x SCRATCH=0x%08x,0x%08x\n",
2126             SAF1761_READ_LE_4(sc, SOTG_DCCHIP_ID),
2127             SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID),
2128             SAF1761_READ_LE_4(sc, SOTG_HW_MODE_CTRL),
2129             SAF1761_READ_LE_4(sc, SOTG_DCSCRATCH),
2130             SAF1761_READ_LE_4(sc, SOTG_HCSCRATCH));
2131
2132         /* reset device controller */
2133         SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_SFRESET);
2134         SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2135
2136         /* wait a bit */
2137         DELAY(1000);
2138
2139         /* reset host controller */
2140         SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_HCRESET);
2141
2142         /* wait for reset to clear */
2143         for (x = 0; x != 10; x++) {
2144                 if ((SAF1761_READ_LE_4(sc, SOTG_USBCMD) & SOTG_USBCMD_HCRESET) == 0)
2145                         break;
2146                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
2147         }
2148
2149         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode |
2150             SOTG_HW_MODE_CTRL_ALL_ATX_RESET);
2151
2152         /* wait a bit */
2153         DELAY(1000);
2154
2155         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2156
2157         /* wait a bit */
2158         DELAY(1000);
2159
2160         /* do a pulldown */
2161         saf1761_otg_pull_down(sc);
2162
2163         /* wait 10ms for pulldown to stabilise */
2164         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2165
2166         for (x = 1;; x++) {
2167
2168                 saf1761_otg_get_hw_ep_profile(NULL, &pf, x);
2169                 if (pf == NULL)
2170                         break;
2171
2172                 /* select the correct endpoint */
2173                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2174                     (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2175                     SOTG_EP_INDEX_DIR_IN);
2176
2177                 /* select the maximum packet size */
2178                 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_in_frame_size);
2179
2180                 /* select the correct endpoint */
2181                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2182                     (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2183                     SOTG_EP_INDEX_DIR_OUT);
2184
2185                 /* select the maximum packet size */
2186                 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_out_frame_size);
2187         }
2188
2189         /* enable interrupts */
2190         SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_GLINTENA |
2191             SOTG_MODE_CLKAON | SOTG_MODE_WKUPCS);
2192
2193         sc->sc_interrupt_cfg |=
2194             SOTG_INTERRUPT_CFG_CDBGMOD |
2195             SOTG_INTERRUPT_CFG_DDBGMODIN |
2196             SOTG_INTERRUPT_CFG_DDBGMODOUT;
2197
2198         /* set default values */
2199         SAF1761_WRITE_LE_4(sc, SOTG_INTERRUPT_CFG, sc->sc_interrupt_cfg);
2200
2201         /* enable VBUS and ID interrupt */
2202         SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2203             SOTG_IRQ_ENABLE_CLR(0xFFFF));
2204         SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2205             SOTG_IRQ_ENABLE_SET(SOTG_IRQ_ID | SOTG_IRQ_VBUS_VLD));
2206
2207         /* enable interrupts */
2208         sc->sc_intr_enable = SOTG_DCINTERRUPT_IEVBUS |
2209             SOTG_DCINTERRUPT_IEBRST | SOTG_DCINTERRUPT_IESUSP;
2210         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
2211
2212         /*
2213          * Connect ATX port 1 to device controller, select external
2214          * charge pump and driver VBUS to +5V:
2215          */
2216         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2217             SOTG_CTRL_CLR(0xFFFF));
2218         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2219             SOTG_CTRL_SET(SOTG_CTRL_SW_SEL_HC_DC |
2220             SOTG_CTRL_BDIS_ACON_EN | SOTG_CTRL_SEL_CP_EXT |
2221             SOTG_CTRL_VBUS_DRV));
2222
2223         /* disable device address */
2224         SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, 0);
2225
2226         /* enable host controller clock and preserve reserved bits */
2227         x = SAF1761_READ_LE_4(sc, SOTG_POWER_DOWN);
2228         SAF1761_WRITE_LE_4(sc, SOTG_POWER_DOWN, x | SOTG_POWER_DOWN_HC_CLK_EN);
2229
2230         /* wait 10ms for clock */
2231         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2232
2233         /* enable configuration flag */
2234         SAF1761_WRITE_LE_4(sc, SOTG_CONFIGFLAG, SOTG_CONFIGFLAG_ENABLE);
2235
2236         /* clear RAM block */
2237         for (x = 0x400; x != 0x10000; x += 4)
2238                 SAF1761_WRITE_LE_4(sc, x, 0);
2239
2240         /* start the HC */
2241         SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_RS);
2242
2243         DPRINTF("USBCMD=0x%08x\n", SAF1761_READ_LE_4(sc, SOTG_USBCMD));
2244
2245         /* make HC scan all PTDs */
2246         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_LAST_PTD, (1 << 31));
2247         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_LAST_PTD, (1 << 31));
2248         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_LAST_PTD, (1 << 31));
2249
2250         /* skip all PTDs by default */
2251         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD, -1U);
2252         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD, -1U);
2253         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD, -1U);
2254
2255         /* activate all PTD types */
2256         SAF1761_WRITE_LE_4(sc, SOTG_HCBUFFERSTATUS,
2257             SOTG_HCBUFFERSTATUS_ISO_BUF_FILL |
2258             SOTG_HCBUFFERSTATUS_INT_BUF_FILL |
2259             SOTG_HCBUFFERSTATUS_ATL_BUF_FILL);
2260
2261         /* we don't use the AND mask */
2262         SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_AND, 0);
2263         SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_AND, 0);
2264         SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_AND, 0);
2265
2266         /* enable all PTD OR interrupts by default */
2267         SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_OR, -1U);
2268         SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_OR, -1U);
2269         SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_OR, -1U);
2270
2271         /* enable HC interrupts */
2272         SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT_ENABLE,
2273             SOTG_HCINTERRUPT_OTG_IRQ |
2274             SOTG_HCINTERRUPT_ISO_IRQ |
2275             SOTG_HCINTERRUPT_ALT_IRQ |
2276             SOTG_HCINTERRUPT_INT_IRQ);
2277
2278         /* poll initial VBUS status */
2279         saf1761_otg_update_vbus(sc);
2280
2281         USB_BUS_UNLOCK(&sc->sc_bus);
2282
2283         /* catch any lost interrupts */
2284
2285         saf1761_otg_do_poll(&sc->sc_bus);
2286
2287         return (0);                     /* success */
2288 }
2289
2290 void
2291 saf1761_otg_uninit(struct saf1761_otg_softc *sc)
2292 {
2293         USB_BUS_LOCK(&sc->sc_bus);
2294
2295         /* disable all interrupts */
2296         SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2297
2298         sc->sc_flags.port_powered = 0;
2299         sc->sc_flags.status_vbus = 0;
2300         sc->sc_flags.status_bus_reset = 0;
2301         sc->sc_flags.status_suspend = 0;
2302         sc->sc_flags.change_suspend = 0;
2303         sc->sc_flags.change_connect = 1;
2304
2305         saf1761_otg_pull_down(sc);
2306         USB_BUS_UNLOCK(&sc->sc_bus);
2307 }
2308
2309 static void
2310 saf1761_otg_suspend(struct saf1761_otg_softc *sc)
2311 {
2312         /* TODO */
2313 }
2314
2315 static void
2316 saf1761_otg_resume(struct saf1761_otg_softc *sc)
2317 {
2318         /* TODO */
2319 }
2320
2321 static void
2322 saf1761_otg_do_poll(struct usb_bus *bus)
2323 {
2324         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
2325
2326         USB_BUS_LOCK(&sc->sc_bus);
2327         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2328         saf1761_otg_interrupt_poll_locked(sc);
2329         saf1761_otg_interrupt_complete_locked(sc);
2330         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2331         USB_BUS_UNLOCK(&sc->sc_bus);
2332 }
2333
2334 /*------------------------------------------------------------------------*
2335  * saf1761_otg control support
2336  * saf1761_otg interrupt support
2337  * saf1761_otg bulk support
2338  *------------------------------------------------------------------------*/
2339 static void
2340 saf1761_otg_device_non_isoc_open(struct usb_xfer *xfer)
2341 {
2342         return;
2343 }
2344
2345 static void
2346 saf1761_otg_device_non_isoc_close(struct usb_xfer *xfer)
2347 {
2348         saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2349 }
2350
2351 static void
2352 saf1761_otg_device_non_isoc_enter(struct usb_xfer *xfer)
2353 {
2354         return;
2355 }
2356
2357 static void
2358 saf1761_otg_device_non_isoc_start(struct usb_xfer *xfer)
2359 {
2360         /* setup TDs */
2361         saf1761_otg_setup_standard_chain(xfer);
2362         saf1761_otg_start_standard_chain(xfer);
2363 }
2364
2365 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods =
2366 {
2367         .open = saf1761_otg_device_non_isoc_open,
2368         .close = saf1761_otg_device_non_isoc_close,
2369         .enter = saf1761_otg_device_non_isoc_enter,
2370         .start = saf1761_otg_device_non_isoc_start,
2371 };
2372
2373 /*------------------------------------------------------------------------*
2374  * saf1761_otg isochronous support
2375  *------------------------------------------------------------------------*/
2376 static void
2377 saf1761_otg_device_isoc_open(struct usb_xfer *xfer)
2378 {
2379         return;
2380 }
2381
2382 static void
2383 saf1761_otg_device_isoc_close(struct usb_xfer *xfer)
2384 {
2385         saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2386 }
2387
2388 static void
2389 saf1761_otg_device_isoc_enter(struct usb_xfer *xfer)
2390 {
2391         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2392         uint32_t temp;
2393         uint32_t nframes;
2394
2395         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2396             xfer, xfer->endpoint->isoc_next, xfer->nframes);
2397
2398         /* get the current frame index - we don't need the high bits */
2399
2400         nframes = SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM);
2401
2402         /*
2403          * check if the frame index is within the window where the
2404          * frames will be inserted
2405          */
2406         temp = (nframes - xfer->endpoint->isoc_next) & SOTG_FRAME_NUM_SOFR_MASK;
2407
2408         if ((xfer->endpoint->is_synced == 0) ||
2409             (temp < xfer->nframes)) {
2410                 /*
2411                  * If there is data underflow or the pipe queue is
2412                  * empty we schedule the transfer a few frames ahead
2413                  * of the current frame position. Else two isochronous
2414                  * transfers might overlap.
2415                  */
2416                 xfer->endpoint->isoc_next = (nframes + 3) & SOTG_FRAME_NUM_SOFR_MASK;
2417                 xfer->endpoint->is_synced = 1;
2418                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2419         }
2420         /*
2421          * compute how many milliseconds the insertion is ahead of the
2422          * current frame position:
2423          */
2424         temp = (xfer->endpoint->isoc_next - nframes) & SOTG_FRAME_NUM_SOFR_MASK;
2425
2426         /*
2427          * pre-compute when the isochronous transfer will be finished:
2428          */
2429         xfer->isoc_time_complete =
2430             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2431             xfer->nframes;
2432
2433         /* compute frame number for next insertion */
2434         xfer->endpoint->isoc_next += xfer->nframes;
2435
2436         /* setup TDs */
2437         saf1761_otg_setup_standard_chain(xfer);
2438 }
2439
2440 static void
2441 saf1761_otg_device_isoc_start(struct usb_xfer *xfer)
2442 {
2443         /* start TD chain */
2444         saf1761_otg_start_standard_chain(xfer);
2445 }
2446
2447 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods =
2448 {
2449         .open = saf1761_otg_device_isoc_open,
2450         .close = saf1761_otg_device_isoc_close,
2451         .enter = saf1761_otg_device_isoc_enter,
2452         .start = saf1761_otg_device_isoc_start,
2453 };
2454
2455 /*------------------------------------------------------------------------*
2456  * saf1761_otg root control support
2457  *------------------------------------------------------------------------*
2458  * Simulate a hardware HUB by handling all the necessary requests.
2459  *------------------------------------------------------------------------*/
2460
2461 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2462
2463 static const struct usb_device_descriptor saf1761_otg_devd = {
2464         .bLength = sizeof(struct usb_device_descriptor),
2465         .bDescriptorType = UDESC_DEVICE,
2466         HSETW(.idVendor, 0x04cc),
2467         HSETW(.idProduct, 0x1761),
2468         .bcdUSB = {0x00, 0x02},
2469         .bDeviceClass = UDCLASS_HUB,
2470         .bDeviceSubClass = UDSUBCLASS_HUB,
2471         .bDeviceProtocol = UDPROTO_FSHUB,
2472         .bMaxPacketSize = 64,
2473         .bcdDevice = {0x00, 0x01},
2474         .iManufacturer = 1,
2475         .iProduct = 2,
2476         .bNumConfigurations = 1,
2477 };
2478
2479 static const struct usb_device_qualifier saf1761_otg_odevd = {
2480         .bLength = sizeof(struct usb_device_qualifier),
2481         .bDescriptorType = UDESC_DEVICE_QUALIFIER,
2482         .bcdUSB = {0x00, 0x02},
2483         .bDeviceClass = UDCLASS_HUB,
2484         .bDeviceSubClass = UDSUBCLASS_HUB,
2485         .bDeviceProtocol = UDPROTO_FSHUB,
2486         .bMaxPacketSize0 = 0,
2487         .bNumConfigurations = 0,
2488 };
2489
2490 static const struct saf1761_otg_config_desc saf1761_otg_confd = {
2491         .confd = {
2492                 .bLength = sizeof(struct usb_config_descriptor),
2493                 .bDescriptorType = UDESC_CONFIG,
2494                 .wTotalLength[0] = sizeof(saf1761_otg_confd),
2495                 .bNumInterface = 1,
2496                 .bConfigurationValue = 1,
2497                 .iConfiguration = 0,
2498                 .bmAttributes = UC_SELF_POWERED,
2499                 .bMaxPower = 0,
2500         },
2501         .ifcd = {
2502                 .bLength = sizeof(struct usb_interface_descriptor),
2503                 .bDescriptorType = UDESC_INTERFACE,
2504                 .bNumEndpoints = 1,
2505                 .bInterfaceClass = UICLASS_HUB,
2506                 .bInterfaceSubClass = UISUBCLASS_HUB,
2507                 .bInterfaceProtocol = 0,
2508         },
2509
2510         .endpd = {
2511                 .bLength = sizeof(struct usb_endpoint_descriptor),
2512                 .bDescriptorType = UDESC_ENDPOINT,
2513                 .bEndpointAddress = (UE_DIR_IN | SAF1761_OTG_INTR_ENDPT),
2514                 .bmAttributes = UE_INTERRUPT,
2515                 .wMaxPacketSize[0] = 8,
2516                 .bInterval = 255,
2517         },
2518 };
2519
2520 static const struct usb_hub_descriptor_min saf1761_otg_hubd = {
2521         .bDescLength = sizeof(saf1761_otg_hubd),
2522         .bDescriptorType = UDESC_HUB,
2523         .bNbrPorts = SOTG_NUM_PORTS,
2524         HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
2525         .bPwrOn2PwrGood = 50,
2526         .bHubContrCurrent = 0,
2527         .DeviceRemovable = {0},         /* port is removable */
2528 };
2529
2530 #define STRING_VENDOR \
2531   "N\0X\0P"
2532
2533 #define STRING_PRODUCT \
2534   "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
2535
2536 USB_MAKE_STRING_DESC(STRING_VENDOR, saf1761_otg_vendor);
2537 USB_MAKE_STRING_DESC(STRING_PRODUCT, saf1761_otg_product);
2538
2539 static usb_error_t
2540 saf1761_otg_roothub_exec(struct usb_device *udev,
2541     struct usb_device_request *req, const void **pptr, uint16_t *plength)
2542 {
2543         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(udev->bus);
2544         const void *ptr;
2545         uint16_t len;
2546         uint16_t value;
2547         uint16_t index;
2548         uint32_t temp;
2549         uint32_t i;
2550         usb_error_t err;
2551
2552         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2553
2554         /* buffer reset */
2555         ptr = (const void *)&sc->sc_hub_temp;
2556         len = 0;
2557         err = 0;
2558
2559         value = UGETW(req->wValue);
2560         index = UGETW(req->wIndex);
2561
2562         /* demultiplex the control request */
2563
2564         switch (req->bmRequestType) {
2565         case UT_READ_DEVICE:
2566                 switch (req->bRequest) {
2567                 case UR_GET_DESCRIPTOR:
2568                         goto tr_handle_get_descriptor;
2569                 case UR_GET_CONFIG:
2570                         goto tr_handle_get_config;
2571                 case UR_GET_STATUS:
2572                         goto tr_handle_get_status;
2573                 default:
2574                         goto tr_stalled;
2575                 }
2576                 break;
2577
2578         case UT_WRITE_DEVICE:
2579                 switch (req->bRequest) {
2580                 case UR_SET_ADDRESS:
2581                         goto tr_handle_set_address;
2582                 case UR_SET_CONFIG:
2583                         goto tr_handle_set_config;
2584                 case UR_CLEAR_FEATURE:
2585                         goto tr_valid;  /* nop */
2586                 case UR_SET_DESCRIPTOR:
2587                         goto tr_valid;  /* nop */
2588                 case UR_SET_FEATURE:
2589                 default:
2590                         goto tr_stalled;
2591                 }
2592                 break;
2593
2594         case UT_WRITE_ENDPOINT:
2595                 switch (req->bRequest) {
2596                 case UR_CLEAR_FEATURE:
2597                         switch (UGETW(req->wValue)) {
2598                         case UF_ENDPOINT_HALT:
2599                                 goto tr_handle_clear_halt;
2600                         case UF_DEVICE_REMOTE_WAKEUP:
2601                                 goto tr_handle_clear_wakeup;
2602                         default:
2603                                 goto tr_stalled;
2604                         }
2605                         break;
2606                 case UR_SET_FEATURE:
2607                         switch (UGETW(req->wValue)) {
2608                         case UF_ENDPOINT_HALT:
2609                                 goto tr_handle_set_halt;
2610                         case UF_DEVICE_REMOTE_WAKEUP:
2611                                 goto tr_handle_set_wakeup;
2612                         default:
2613                                 goto tr_stalled;
2614                         }
2615                         break;
2616                 case UR_SYNCH_FRAME:
2617                         goto tr_valid;  /* nop */
2618                 default:
2619                         goto tr_stalled;
2620                 }
2621                 break;
2622
2623         case UT_READ_ENDPOINT:
2624                 switch (req->bRequest) {
2625                 case UR_GET_STATUS:
2626                         goto tr_handle_get_ep_status;
2627                 default:
2628                         goto tr_stalled;
2629                 }
2630                 break;
2631
2632         case UT_WRITE_INTERFACE:
2633                 switch (req->bRequest) {
2634                 case UR_SET_INTERFACE:
2635                         goto tr_handle_set_interface;
2636                 case UR_CLEAR_FEATURE:
2637                         goto tr_valid;  /* nop */
2638                 case UR_SET_FEATURE:
2639                 default:
2640                         goto tr_stalled;
2641                 }
2642                 break;
2643
2644         case UT_READ_INTERFACE:
2645                 switch (req->bRequest) {
2646                 case UR_GET_INTERFACE:
2647                         goto tr_handle_get_interface;
2648                 case UR_GET_STATUS:
2649                         goto tr_handle_get_iface_status;
2650                 default:
2651                         goto tr_stalled;
2652                 }
2653                 break;
2654
2655         case UT_WRITE_CLASS_INTERFACE:
2656         case UT_WRITE_VENDOR_INTERFACE:
2657                 /* XXX forward */
2658                 break;
2659
2660         case UT_READ_CLASS_INTERFACE:
2661         case UT_READ_VENDOR_INTERFACE:
2662                 /* XXX forward */
2663                 break;
2664
2665         case UT_WRITE_CLASS_DEVICE:
2666                 switch (req->bRequest) {
2667                 case UR_CLEAR_FEATURE:
2668                         goto tr_valid;
2669                 case UR_SET_DESCRIPTOR:
2670                 case UR_SET_FEATURE:
2671                         break;
2672                 default:
2673                         goto tr_stalled;
2674                 }
2675                 break;
2676
2677         case UT_WRITE_CLASS_OTHER:
2678                 switch (req->bRequest) {
2679                 case UR_CLEAR_FEATURE:
2680                         if (index == SOTG_HOST_PORT_NUM)
2681                                 goto tr_handle_clear_port_feature_host;
2682                         else if (index == SOTG_DEVICE_PORT_NUM)
2683                                 goto tr_handle_clear_port_feature_device;
2684                         else
2685                                 goto tr_stalled;
2686                 case UR_SET_FEATURE:
2687                         if (index == SOTG_HOST_PORT_NUM)
2688                                 goto tr_handle_set_port_feature_host;
2689                         else if (index == SOTG_DEVICE_PORT_NUM)
2690                                 goto tr_handle_set_port_feature_device;
2691                         else
2692                                 goto tr_stalled;
2693                 case UR_CLEAR_TT_BUFFER:
2694                 case UR_RESET_TT:
2695                 case UR_STOP_TT:
2696                         goto tr_valid;
2697
2698                 default:
2699                         goto tr_stalled;
2700                 }
2701                 break;
2702
2703         case UT_READ_CLASS_OTHER:
2704                 switch (req->bRequest) {
2705                 case UR_GET_TT_STATE:
2706                         goto tr_handle_get_tt_state;
2707                 case UR_GET_STATUS:
2708                         if (index == SOTG_HOST_PORT_NUM)
2709                                 goto tr_handle_get_port_status_host;
2710                         else if (index == SOTG_DEVICE_PORT_NUM)
2711                                 goto tr_handle_get_port_status_device;
2712                         else
2713                                 goto tr_stalled;
2714                 default:
2715                         goto tr_stalled;
2716                 }
2717                 break;
2718
2719         case UT_READ_CLASS_DEVICE:
2720                 switch (req->bRequest) {
2721                 case UR_GET_DESCRIPTOR:
2722                         goto tr_handle_get_class_descriptor;
2723                 case UR_GET_STATUS:
2724                         goto tr_handle_get_class_status;
2725
2726                 default:
2727                         goto tr_stalled;
2728                 }
2729                 break;
2730         default:
2731                 goto tr_stalled;
2732         }
2733         goto tr_valid;
2734
2735 tr_handle_get_descriptor:
2736         switch (value >> 8) {
2737         case UDESC_DEVICE:
2738                 if (value & 0xff)
2739                         goto tr_stalled;
2740                 len = sizeof(saf1761_otg_devd);
2741                 ptr = (const void *)&saf1761_otg_devd;
2742                 goto tr_valid;
2743         case UDESC_DEVICE_QUALIFIER:
2744                 if (value & 0xff)
2745                         goto tr_stalled;
2746                 len = sizeof(saf1761_otg_odevd);
2747                 ptr = (const void *)&saf1761_otg_odevd;
2748                 goto tr_valid;
2749         case UDESC_CONFIG:
2750                 if (value & 0xff)
2751                         goto tr_stalled;
2752                 len = sizeof(saf1761_otg_confd);
2753                 ptr = (const void *)&saf1761_otg_confd;
2754                 goto tr_valid;
2755         case UDESC_STRING:
2756                 switch (value & 0xff) {
2757                 case 0:         /* Language table */
2758                         len = sizeof(usb_string_lang_en);
2759                         ptr = (const void *)&usb_string_lang_en;
2760                         goto tr_valid;
2761
2762                 case 1:         /* Vendor */
2763                         len = sizeof(saf1761_otg_vendor);
2764                         ptr = (const void *)&saf1761_otg_vendor;
2765                         goto tr_valid;
2766
2767                 case 2:         /* Product */
2768                         len = sizeof(saf1761_otg_product);
2769                         ptr = (const void *)&saf1761_otg_product;
2770                         goto tr_valid;
2771                 default:
2772                         break;
2773                 }
2774                 break;
2775         default:
2776                 goto tr_stalled;
2777         }
2778         goto tr_stalled;
2779
2780 tr_handle_get_config:
2781         len = 1;
2782         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
2783         goto tr_valid;
2784
2785 tr_handle_get_status:
2786         len = 2;
2787         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
2788         goto tr_valid;
2789
2790 tr_handle_set_address:
2791         if (value & 0xFF00)
2792                 goto tr_stalled;
2793
2794         sc->sc_rt_addr = value;
2795         goto tr_valid;
2796
2797 tr_handle_set_config:
2798         if (value >= 2)
2799                 goto tr_stalled;
2800         sc->sc_conf = value;
2801         goto tr_valid;
2802
2803 tr_handle_get_interface:
2804         len = 1;
2805         sc->sc_hub_temp.wValue[0] = 0;
2806         goto tr_valid;
2807
2808 tr_handle_get_tt_state:
2809 tr_handle_get_class_status:
2810 tr_handle_get_iface_status:
2811 tr_handle_get_ep_status:
2812         len = 2;
2813         USETW(sc->sc_hub_temp.wValue, 0);
2814         goto tr_valid;
2815
2816 tr_handle_set_halt:
2817 tr_handle_set_interface:
2818 tr_handle_set_wakeup:
2819 tr_handle_clear_wakeup:
2820 tr_handle_clear_halt:
2821         goto tr_valid;
2822
2823 tr_handle_clear_port_feature_device:
2824         DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
2825
2826         switch (value) {
2827         case UHF_PORT_SUSPEND:
2828                 saf1761_otg_wakeup_peer(sc);
2829                 break;
2830
2831         case UHF_PORT_ENABLE:
2832                 sc->sc_flags.port_enabled = 0;
2833                 break;
2834
2835         case UHF_PORT_TEST:
2836         case UHF_PORT_INDICATOR:
2837         case UHF_C_PORT_ENABLE:
2838         case UHF_C_PORT_OVER_CURRENT:
2839         case UHF_C_PORT_RESET:
2840                 /* nops */
2841                 break;
2842         case UHF_PORT_POWER:
2843                 sc->sc_flags.port_powered = 0;
2844                 saf1761_otg_pull_down(sc);
2845                 break;
2846         case UHF_C_PORT_CONNECTION:
2847                 sc->sc_flags.change_connect = 0;
2848                 break;
2849         case UHF_C_PORT_SUSPEND:
2850                 sc->sc_flags.change_suspend = 0;
2851                 break;
2852         default:
2853                 err = USB_ERR_IOERROR;
2854                 goto tr_valid;
2855         }
2856         goto tr_valid;
2857
2858 tr_handle_clear_port_feature_host:
2859         DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
2860
2861         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
2862
2863         switch (value) {
2864         case UHF_PORT_ENABLE:
2865                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PED);
2866                 break;
2867         case UHF_PORT_SUSPEND:
2868                 if ((temp & SOTG_PORTSC1_SUSP) && (!(temp & SOTG_PORTSC1_FPR)))
2869                         SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_FPR);
2870
2871                 /* wait 20ms for resume sequence to complete */
2872                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
2873
2874                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~(SOTG_PORTSC1_SUSP |
2875                     SOTG_PORTSC1_FPR | SOTG_PORTSC1_LS /* High Speed */ ));
2876
2877                 /* 4ms settle time */
2878                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
2879                 break;
2880         case UHF_PORT_INDICATOR:
2881                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PIC);
2882                 break;
2883         case UHF_PORT_TEST:
2884         case UHF_C_PORT_ENABLE:
2885         case UHF_C_PORT_OVER_CURRENT:
2886         case UHF_C_PORT_RESET:
2887         case UHF_C_PORT_SUSPEND:
2888                 /* NOPs */
2889                 break;
2890         case UHF_PORT_POWER:
2891                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PP);
2892                 break;
2893         case UHF_C_PORT_CONNECTION:
2894                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_ECSC);
2895                 break;
2896         default:
2897                 err = USB_ERR_IOERROR;
2898                 goto tr_valid;
2899         }
2900         goto tr_valid;
2901
2902 tr_handle_set_port_feature_device:
2903         DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
2904
2905         switch (value) {
2906         case UHF_PORT_ENABLE:
2907                 sc->sc_flags.port_enabled = 1;
2908                 break;
2909         case UHF_PORT_SUSPEND:
2910         case UHF_PORT_RESET:
2911         case UHF_PORT_TEST:
2912         case UHF_PORT_INDICATOR:
2913                 /* nops */
2914                 break;
2915         case UHF_PORT_POWER:
2916                 sc->sc_flags.port_powered = 1;
2917                 break;
2918         default:
2919                 err = USB_ERR_IOERROR;
2920                 goto tr_valid;
2921         }
2922         goto tr_valid;
2923
2924 tr_handle_set_port_feature_host:
2925         DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
2926
2927         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
2928
2929         switch (value) {
2930         case UHF_PORT_ENABLE:
2931                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PED);
2932                 break;
2933         case UHF_PORT_SUSPEND:
2934                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_SUSP);
2935                 break;
2936         case UHF_PORT_RESET:
2937                 DPRINTFN(6, "reset port %d\n", index);
2938
2939                 /* Start reset sequence. */
2940                 temp &= ~(SOTG_PORTSC1_PED | SOTG_PORTSC1_PR);
2941
2942                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PR);
2943
2944                 /* Wait for reset to complete. */
2945                 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2946                     USB_MS_TO_TICKS(usb_port_root_reset_delay));
2947
2948                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp);
2949
2950                 /* Wait for HC to complete reset. */
2951                 usb_pause_mtx(&sc->sc_bus.bus_mtx, USB_MS_TO_TICKS(2));
2952
2953                 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
2954
2955                 DPRINTF("After reset, status=0x%08x\n", temp);
2956                 if (temp & SOTG_PORTSC1_PR) {
2957                         device_printf(sc->sc_bus.bdev, "port reset timeout\n");
2958                         err = USB_ERR_TIMEOUT;
2959                         goto tr_valid;
2960                 }
2961                 if (!(temp & SOTG_PORTSC1_PED)) {
2962                         /* Not a high speed device, give up ownership.*/
2963                         SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PO);
2964                         break;
2965                 }
2966                 sc->sc_isreset = 1;
2967                 DPRINTF("port %d reset, status = 0x%08x\n", index, temp);
2968                 break;
2969         case UHF_PORT_POWER:
2970                 DPRINTFN(3, "set port power %d\n", index);
2971                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PP);
2972                 break;
2973
2974         case UHF_PORT_TEST:
2975                 DPRINTFN(3, "set port test %d\n", index);
2976                 break;
2977
2978         case UHF_PORT_INDICATOR:
2979                 DPRINTFN(3, "set port ind %d\n", index);
2980                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PIC);
2981                 break;
2982         default:
2983                 err = USB_ERR_IOERROR;
2984                 goto tr_valid;
2985         }
2986         goto tr_valid;
2987
2988 tr_handle_get_port_status_device:
2989
2990         DPRINTFN(9, "UR_GET_PORT_STATUS on port %d\n", index);
2991
2992         if (sc->sc_flags.status_vbus) {
2993                 saf1761_otg_pull_up(sc);
2994         } else {
2995                 saf1761_otg_pull_down(sc);
2996         }
2997
2998         /* Select FULL-speed and Device Side Mode */
2999
3000         value = UPS_PORT_MODE_DEVICE;
3001
3002         if (sc->sc_flags.port_powered)
3003                 value |= UPS_PORT_POWER;
3004
3005         if (sc->sc_flags.port_enabled)
3006                 value |= UPS_PORT_ENABLED;
3007
3008         if (sc->sc_flags.status_vbus &&
3009             sc->sc_flags.status_bus_reset)
3010                 value |= UPS_CURRENT_CONNECT_STATUS;
3011
3012         if (sc->sc_flags.status_suspend)
3013                 value |= UPS_SUSPEND;
3014
3015         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
3016
3017         value = 0;
3018
3019         if (sc->sc_flags.change_connect)
3020                 value |= UPS_C_CONNECT_STATUS;
3021
3022         if (sc->sc_flags.change_suspend)
3023                 value |= UPS_C_SUSPEND;
3024
3025         USETW(sc->sc_hub_temp.ps.wPortChange, value);
3026         len = sizeof(sc->sc_hub_temp.ps);
3027         goto tr_valid;
3028
3029 tr_handle_get_port_status_host:
3030
3031         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3032
3033         DPRINTFN(9, "UR_GET_PORT_STATUS on port %d = 0x%08x\n", index, temp);
3034
3035         i = UPS_HIGH_SPEED;
3036
3037         if (temp & SOTG_PORTSC1_ECCS)
3038                 i |= UPS_CURRENT_CONNECT_STATUS;
3039         if (temp & SOTG_PORTSC1_PED)
3040                 i |= UPS_PORT_ENABLED;
3041         if ((temp & SOTG_PORTSC1_SUSP) && !(temp & SOTG_PORTSC1_FPR))
3042                 i |= UPS_SUSPEND;
3043         if (temp & SOTG_PORTSC1_PR)
3044                 i |= UPS_RESET;
3045         if (temp & SOTG_PORTSC1_PP)
3046                 i |= UPS_PORT_POWER;
3047
3048         USETW(sc->sc_hub_temp.ps.wPortStatus, i);
3049         i = 0;
3050
3051         if (temp & SOTG_PORTSC1_ECSC)
3052                 i |= UPS_C_CONNECT_STATUS;
3053         if (temp & SOTG_PORTSC1_FPR)
3054                 i |= UPS_C_SUSPEND;
3055         if (sc->sc_isreset)
3056                 i |= UPS_C_PORT_RESET;
3057         USETW(sc->sc_hub_temp.ps.wPortChange, i);
3058         len = sizeof(sc->sc_hub_temp.ps);
3059         goto tr_valid;
3060
3061 tr_handle_get_class_descriptor:
3062         if (value & 0xFF)
3063                 goto tr_stalled;
3064         ptr = (const void *)&saf1761_otg_hubd;
3065         len = sizeof(saf1761_otg_hubd);
3066         goto tr_valid;
3067
3068 tr_stalled:
3069         err = USB_ERR_STALLED;
3070 tr_valid:
3071         *plength = len;
3072         *pptr = ptr;
3073         return (err);
3074 }
3075
3076 static void
3077 saf1761_otg_xfer_setup(struct usb_setup_params *parm)
3078 {
3079         struct saf1761_otg_softc *sc;
3080         struct usb_xfer *xfer;
3081         void *last_obj;
3082         uint32_t dw1;
3083         uint32_t ntd;
3084         uint32_t n;
3085         uint8_t ep_no;
3086         uint8_t ep_type;
3087
3088         sc = SAF1761_OTG_BUS2SC(parm->udev->bus);
3089         xfer = parm->curr_xfer;
3090
3091         /*
3092          * NOTE: This driver does not use any of the parameters that
3093          * are computed from the following values. Just set some
3094          * reasonable dummies:
3095          */
3096         parm->hc_max_packet_size = 0x500;
3097         parm->hc_max_packet_count = 1;
3098         parm->hc_max_frame_size = 0x500;
3099
3100         usbd_transfer_setup_sub(parm);
3101
3102         /*
3103          * Compute maximum number of TDs:
3104          */
3105         ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
3106
3107         if (ep_type == UE_CONTROL) {
3108
3109                 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
3110
3111         } else {
3112                 ntd = xfer->nframes + 1 /* SYNC */ ;
3113         }
3114
3115         /*
3116          * check if "usbd_transfer_setup_sub" set an error
3117          */
3118         if (parm->err)
3119                 return;
3120
3121         /*
3122          * allocate transfer descriptors
3123          */
3124         last_obj = NULL;
3125
3126         ep_no = xfer->endpointno & UE_ADDR;
3127
3128         /*
3129          * Check profile stuff
3130          */
3131         if (parm->udev->flags.usb_mode == USB_MODE_DEVICE) {
3132                 const struct usb_hw_ep_profile *pf;
3133
3134                 saf1761_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
3135
3136                 if (pf == NULL) {
3137                         /* should not happen */
3138                         parm->err = USB_ERR_INVAL;
3139                         return;
3140                 }
3141         }
3142
3143         dw1 = (xfer->address << 3) | (ep_type << 12);
3144
3145         switch (parm->udev->speed) {
3146         case USB_SPEED_FULL:
3147         case USB_SPEED_LOW:
3148                 /* check if root HUB port is running High Speed */
3149                 if (parm->udev->parent_hs_hub != NULL) {
3150                         dw1 |= SOTG_PTD_DW1_ENABLE_SPLIT;
3151                         dw1 |= (parm->udev->hs_port_no << 18);
3152                         dw1 |= (parm->udev->hs_hub_addr << 25);
3153                         if (parm->udev->speed == USB_SPEED_LOW)
3154                                 dw1 |= (1 << 17);
3155                 }
3156                 break;
3157         default:
3158                 break;
3159         }
3160
3161         /* align data */
3162         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
3163
3164         for (n = 0; n != ntd; n++) {
3165
3166                 struct saf1761_otg_td *td;
3167
3168                 if (parm->buf) {
3169
3170                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
3171
3172                         /* init TD */
3173                         td->max_packet_size = xfer->max_packet_size;
3174                         td->ep_index = ep_no;
3175                         td->ep_type = ep_type;
3176                         td->dw1_value = dw1;
3177                         td->uframe = 0;
3178                         if (ep_type == UE_INTERRUPT) {
3179                                 if (xfer->interval > 32)
3180                                         td->interval = (32 / 2) << 3;
3181                                 else
3182                                         td->interval = (xfer->interval / 2) << 3;
3183                         } else {
3184                                 td->interval = 0;
3185                         }
3186                         td->obj_next = last_obj;
3187
3188                         last_obj = td;
3189                 }
3190                 parm->size[0] += sizeof(*td);
3191         }
3192
3193         xfer->td_start[0] = last_obj;
3194 }
3195
3196 static void
3197 saf1761_otg_xfer_unsetup(struct usb_xfer *xfer)
3198 {
3199 }
3200
3201 static void
3202 saf1761_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3203     struct usb_endpoint *ep)
3204 {
3205         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3206             ep, udev->address,
3207             edesc->bEndpointAddress, udev->flags.usb_mode);
3208
3209         if (udev->parent_hub == NULL) {
3210                 /* root HUB has special endpoint handling */
3211                 return;
3212         }
3213
3214         if (udev->flags.usb_mode == USB_MODE_DEVICE) {
3215                 if (udev->speed != USB_SPEED_FULL &&
3216                     udev->speed != USB_SPEED_HIGH) {
3217                         /* not supported */
3218                         return;
3219                 }
3220                 switch (edesc->bmAttributes & UE_XFERTYPE) {
3221                 case UE_ISOCHRONOUS:
3222                         ep->methods = &saf1761_otg_device_isoc_methods;
3223                         break;
3224                 default:
3225                         ep->methods = &saf1761_otg_non_isoc_methods;
3226                         break;
3227                 }
3228         } else {
3229                 switch (edesc->bmAttributes & UE_XFERTYPE) {
3230                 case UE_CONTROL:
3231                 case UE_BULK:
3232                 case UE_INTERRUPT:
3233                         ep->methods = &saf1761_otg_non_isoc_methods;
3234                         break;
3235                 default:
3236                         /* TODO */
3237                         break;
3238                 }
3239         }
3240 }
3241
3242 static void
3243 saf1761_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3244 {
3245         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
3246
3247         switch (state) {
3248         case USB_HW_POWER_SUSPEND:
3249                 saf1761_otg_suspend(sc);
3250                 break;
3251         case USB_HW_POWER_SHUTDOWN:
3252                 saf1761_otg_uninit(sc);
3253                 break;
3254         case USB_HW_POWER_RESUME:
3255                 saf1761_otg_resume(sc);
3256                 break;
3257         default:
3258                 break;
3259         }
3260 }
3261
3262 static void
3263 saf1761_otg_device_resume(struct usb_device *udev)
3264 {
3265         struct saf1761_otg_softc *sc;
3266         struct saf1761_otg_td *td;
3267         struct usb_xfer *xfer;
3268         uint8_t x;
3269
3270         DPRINTF("\n");
3271
3272         if (udev->flags.usb_mode != USB_MODE_HOST)
3273                 return;
3274
3275         sc = SAF1761_OTG_BUS2SC(udev->bus);
3276
3277         USB_BUS_LOCK(&sc->sc_bus);
3278         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3279
3280         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3281
3282                 if (xfer->xroot->udev != udev)
3283                         continue;
3284
3285                 td = xfer->td_transfer_cache;
3286                 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3287                         continue;
3288
3289                 switch (td->ep_type) {
3290                 case UE_INTERRUPT:
3291                         x = td->channel - 32;
3292                         sc->sc_host_intr_suspend_map &= ~(1 << x);
3293                         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3294                             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3295                         break;
3296                 case UE_ISOCHRONOUS:
3297                         x = td->channel;
3298                         sc->sc_host_isoc_suspend_map &= ~(1 << x);
3299                         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3300                             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3301                         break;
3302                 default:
3303                         x = td->channel - 64;
3304                         sc->sc_host_async_suspend_map &= ~(1 << x);
3305                         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3306                             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3307                         break;
3308                 }
3309         }
3310
3311         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3312         USB_BUS_UNLOCK(&sc->sc_bus);
3313
3314         /* poll all transfers again to restart resumed ones */
3315         saf1761_otg_do_poll(&sc->sc_bus);
3316 }
3317
3318 static void
3319 saf1761_otg_device_suspend(struct usb_device *udev)
3320 {
3321         struct saf1761_otg_softc *sc;
3322         struct saf1761_otg_td *td;
3323         struct usb_xfer *xfer;
3324         uint8_t x;
3325
3326         DPRINTF("\n");
3327
3328         if (udev->flags.usb_mode != USB_MODE_HOST)
3329                 return;
3330
3331         sc = SAF1761_OTG_BUS2SC(udev->bus);
3332
3333         USB_BUS_LOCK(&sc->sc_bus);
3334         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3335
3336         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3337
3338                 if (xfer->xroot->udev != udev)
3339                         continue;
3340
3341                 td = xfer->td_transfer_cache;
3342                 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3343                         continue;
3344
3345                 switch (td->ep_type) {
3346                 case UE_INTERRUPT:
3347                         x = td->channel - 32;
3348                         sc->sc_host_intr_suspend_map |= (1 << x);
3349                         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3350                             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3351                         break;
3352                 case UE_ISOCHRONOUS:
3353                         x = td->channel;
3354                         sc->sc_host_isoc_suspend_map |= (1 << x);
3355                         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3356                             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3357                         break;
3358                 default:
3359                         x = td->channel - 64;
3360                         sc->sc_host_async_suspend_map |= (1 << x);
3361                         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3362                             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3363                         break;
3364                 }
3365         }
3366
3367         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3368         USB_BUS_UNLOCK(&sc->sc_bus);
3369 }
3370
3371 static const struct usb_bus_methods saf1761_otg_bus_methods =
3372 {
3373         .endpoint_init = &saf1761_otg_ep_init,
3374         .xfer_setup = &saf1761_otg_xfer_setup,
3375         .xfer_unsetup = &saf1761_otg_xfer_unsetup,
3376         .get_hw_ep_profile = &saf1761_otg_get_hw_ep_profile,
3377         .xfer_stall = &saf1761_otg_xfer_stall,
3378         .set_stall = &saf1761_otg_set_stall,
3379         .clear_stall = &saf1761_otg_clear_stall,
3380         .roothub_exec = &saf1761_otg_roothub_exec,
3381         .xfer_poll = &saf1761_otg_do_poll,
3382         .set_hw_power_sleep = saf1761_otg_set_hw_power_sleep,
3383         .device_resume = &saf1761_otg_device_resume,
3384         .device_suspend = &saf1761_otg_device_suspend,
3385 };