sys/dev/usb/controller/saf1761_otg.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
   4  * All rights reserved.
   5  *
   6  * This software was developed by SRI International and the University of
   7  * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
   8  * ("CTSRD"), as part of the DARPA CRASH research programme.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * This file contains the driver for the SAF1761 series USB OTG
  34  * controller.
  35  *
  36  * Datasheet is available from:
  37  * http://www.nxp.com/products/automotive/multimedia/usb/SAF1761BE.html
  38  */
  39
  40 #ifdef USB_GLOBAL_INCLUDE_FILE
  41 #include USB_GLOBAL_INCLUDE_FILE
  42 #else
  43 #include <sys/stdint.h>
  44 #include <sys/stddef.h>
  45 #include <sys/param.h>
  46 #include <sys/queue.h>
  47 #include <sys/types.h>
  48 #include <sys/systm.h>
  49 #include <sys/kernel.h>
  50 #include <sys/bus.h>
  51 #include <sys/module.h>
  52 #include <sys/lock.h>
  53 #include <sys/mutex.h>
  54 #include <sys/condvar.h>
  55 #include <sys/sysctl.h>
  56 #include <sys/sx.h>
  57 #include <sys/unistd.h>
  58 #include <sys/callout.h>
  59 #include <sys/malloc.h>
  60 #include <sys/priv.h>
  61
  62 #include <dev/usb/usb.h>
  63 #include <dev/usb/usbdi.h>
  64
  65 #define USB_DEBUG_VAR saf1761_otg_debug
  66
  67 #include <dev/usb/usb_core.h>
  68 #include <dev/usb/usb_debug.h>
  69 #include <dev/usb/usb_busdma.h>
  70 #include <dev/usb/usb_process.h>
  71 #include <dev/usb/usb_transfer.h>
  72 #include <dev/usb/usb_device.h>
  73 #include <dev/usb/usb_hub.h>
  74 #include <dev/usb/usb_util.h>
  75
  76 #include <dev/usb/usb_controller.h>
  77 #include <dev/usb/usb_bus.h>
  78 #endif                                  /* USB_GLOBAL_INCLUDE_FILE */
  79
  80 #include <dev/usb/controller/saf1761_otg.h>
  81 #include <dev/usb/controller/saf1761_otg_reg.h>
  82
  83 #define SAF1761_OTG_BUS2SC(bus) \
  84    ((struct saf1761_otg_softc *)(((uint8_t *)(bus)) - \
  85     ((uint8_t *)&(((struct saf1761_otg_softc *)0)->sc_bus))))
  86
  87 #define SAF1761_OTG_PC2UDEV(pc) \
  88    (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
  89
  90 #define SAF1761_DCINTERRUPT_THREAD_IRQ                  \
  91   (SOTG_DCINTERRUPT_IEVBUS | SOTG_DCINTERRUPT_IEBRST |  \
  92   SOTG_DCINTERRUPT_IERESM | SOTG_DCINTERRUPT_IESUSP)
  93
  94 #ifdef USB_DEBUG
  95 static int saf1761_otg_debug = 0;
  96 static int saf1761_otg_forcefs = 0;
  97
  98 static
  99 SYSCTL_NODE(_hw_usb, OID_AUTO, saf1761_otg, CTLFLAG_RW, 0,
 100     "USB SAF1761 DCI");
 101
 102 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, debug, CTLFLAG_RW,
 103     &saf1761_otg_debug, 0, "SAF1761 DCI debug level");
 104 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, forcefs, CTLFLAG_RW,
 105     &saf1761_otg_forcefs, 0, "SAF1761 DCI force FULL speed");
 106 #endif
 107
 108 #define SAF1761_OTG_INTR_ENDPT 1
 109
 110 /* prototypes */
 111
 112 static const struct usb_bus_methods saf1761_otg_bus_methods;
 113 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods;
 114 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods;
 115 static const struct usb_pipe_methods saf1761_otg_host_isoc_methods;
 116
 117 static saf1761_otg_cmd_t saf1761_host_setup_tx;
 118 static saf1761_otg_cmd_t saf1761_host_bulk_data_rx;
 119 static saf1761_otg_cmd_t saf1761_host_bulk_data_tx;
 120 static saf1761_otg_cmd_t saf1761_host_intr_data_rx;
 121 static saf1761_otg_cmd_t saf1761_host_intr_data_tx;
 122 static saf1761_otg_cmd_t saf1761_host_isoc_data_rx;
 123 static saf1761_otg_cmd_t saf1761_host_isoc_data_tx;
 124 static saf1761_otg_cmd_t saf1761_device_setup_rx;
 125 static saf1761_otg_cmd_t saf1761_device_data_rx;
 126 static saf1761_otg_cmd_t saf1761_device_data_tx;
 127 static saf1761_otg_cmd_t saf1761_device_data_tx_sync;
 128 static void saf1761_otg_device_done(struct usb_xfer *, usb_error_t);
 129 static void saf1761_otg_do_poll(struct usb_bus *);
 130 static void saf1761_otg_standard_done(struct usb_xfer *);
 131 static void saf1761_otg_intr_set(struct usb_xfer *, uint8_t);
 132 static void saf1761_otg_root_intr(struct saf1761_otg_softc *);
 133
 134 /*
 135  * Here is a list of what the SAF1761 chip can support. The main
 136  * limitation is that the sum of the buffer sizes must be less than
 137  * 8192 bytes.
 138  */
 139 static const struct usb_hw_ep_profile saf1761_otg_ep_profile[] = {
 140
 141         [0] = {
 142                 .max_in_frame_size = 64,
 143                 .max_out_frame_size = 64,
 144                 .is_simplex = 0,
 145                 .support_control = 1,
 146         },
 147         [1] = {
 148                 .max_in_frame_size = SOTG_HS_MAX_PACKET_SIZE,
 149                 .max_out_frame_size = SOTG_HS_MAX_PACKET_SIZE,
 150                 .is_simplex = 0,
 151                 .support_interrupt = 1,
 152                 .support_bulk = 1,
 153                 .support_isochronous = 1,
 154                 .support_in = 1,
 155                 .support_out = 1,
 156         },
 157 };
 158
 159 static void
 160 saf1761_otg_get_hw_ep_profile(struct usb_device *udev,
 161     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 162 {
 163         if (ep_addr == 0) {
 164                 *ppf = saf1761_otg_ep_profile + 0;
 165         } else if (ep_addr < 8) {
 166                 *ppf = saf1761_otg_ep_profile + 1;
 167         } else {
 168                 *ppf = NULL;
 169         }
 170 }
 171
 172 static void
 173 saf1761_otg_pull_up(struct saf1761_otg_softc *sc)
 174 {
 175         /* activate pullup on D+, if possible */
 176
 177         if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) {
 178                 DPRINTF("\n");
 179
 180                 sc->sc_flags.d_pulled_up = 1;
 181         }
 182 }
 183
 184 static void
 185 saf1761_otg_pull_down(struct saf1761_otg_softc *sc)
 186 {
 187         /* release pullup on D+, if possible */
 188
 189         if (sc->sc_flags.d_pulled_up) {
 190                 DPRINTF("\n");
 191
 192                 sc->sc_flags.d_pulled_up = 0;
 193         }
 194 }
 195
 196 static void
 197 saf1761_otg_wakeup_peer(struct saf1761_otg_softc *sc)
 198 {
 199         uint16_t temp;
 200
 201         if (!(sc->sc_flags.status_suspend))
 202                 return;
 203
 204         DPRINTFN(5, "\n");
 205
 206         temp = SAF1761_READ_LE_4(sc, SOTG_MODE);
 207         SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp | SOTG_MODE_SNDRSU);
 208         SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp & ~SOTG_MODE_SNDRSU);
 209
 210         /* Wait 8ms for remote wakeup to complete. */
 211         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 212 }
 213
 214 static uint8_t
 215 saf1761_host_channel_alloc(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 216 {
 217         uint32_t x;
 218
 219         if (td->channel < SOTG_HOST_CHANNEL_MAX)
 220                 return (0);
 221
 222         /* check if device is suspended */
 223         if (SAF1761_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
 224                 return (1);             /* busy - cannot transfer data */
 225
 226         switch (td->ep_type) {
 227         case UE_INTERRUPT:
 228                 for (x = 0; x != 32; x++) {
 229                         if (sc->sc_host_intr_map & (1 << x))
 230                                 continue;
 231                         sc->sc_host_intr_map |= (1 << x);
 232                         td->channel = 32 + x;
 233                         return (0);
 234                 }
 235                 break;
 236         case UE_ISOCHRONOUS:
 237                 for (x = 0; x != 32; x++) {
 238                         if (sc->sc_host_isoc_map & (1 << x))
 239                                 continue;
 240                         sc->sc_host_isoc_map |= (1 << x);
 241                         td->channel = x;
 242                         return (0);
 243                 }
 244                 break;
 245         default:
 246                 for (x = 0; x != 32; x++) {
 247                         if (sc->sc_host_async_map & (1 << x))
 248                                 continue;
 249                         sc->sc_host_async_map |= (1 << x);
 250                         td->channel = 64 + x;
 251                         return (0);
 252                 }
 253                 break;
 254         }
 255         return (1);
 256 }
 257
 258 static void
 259 saf1761_host_channel_free(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 260 {
 261         uint32_t x;
 262
 263         if (td->channel >= SOTG_HOST_CHANNEL_MAX)
 264                 return;
 265
 266         switch (td->ep_type) {
 267         case UE_INTERRUPT:
 268                 x = td->channel - 32;
 269                 td->channel = SOTG_HOST_CHANNEL_MAX;
 270                 sc->sc_host_intr_map &= ~(1 << x);
 271                 sc->sc_host_intr_suspend_map &= ~(1 << x);
 272                 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 273                     (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 274                 break;
 275         case UE_ISOCHRONOUS:
 276                 x = td->channel;
 277                 td->channel = SOTG_HOST_CHANNEL_MAX;
 278                 sc->sc_host_isoc_map &= ~(1 << x);
 279                 sc->sc_host_isoc_suspend_map &= ~(1 << x);
 280                 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
 281                     (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
 282                 break;
 283         default:
 284                 x = td->channel - 64;
 285                 td->channel = SOTG_HOST_CHANNEL_MAX;
 286                 sc->sc_host_async_map &= ~(1 << x);
 287                 sc->sc_host_async_suspend_map &= ~(1 << x);
 288                 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 289                     (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 290                 break;
 291         }
 292 }
 293
 294 static uint32_t
 295 saf1761_peek_host_status_le_4(struct saf1761_otg_softc *sc, uint32_t offset)
 296 {
 297         uint32_t x = 0;
 298         while (1) {
 299                 uint32_t retval;
 300
 301                 SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
 302                 SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
 303                 retval = SAF1761_READ_LE_4(sc, offset);
 304                 if (retval != 0)
 305                         return (retval);
 306                 if (++x == 8) {
 307                         DPRINTF("STAUS is zero at offset 0x%x\n", offset);
 308                         break;
 309                 }
 310         }
 311         return (0);
 312 }
 313
 314 static void
 315 saf1761_read_host_memory(struct saf1761_otg_softc *sc,
 316     struct saf1761_otg_td *td, uint32_t len)
 317 {
 318         struct usb_page_search buf_res;
 319         uint32_t offset;
 320         uint32_t count;
 321
 322         if (len == 0)
 323                 return;
 324
 325         offset = SOTG_DATA_ADDR(td->channel);
 326         SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
 327         SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
 328
 329         /* optimised read first */
 330         while (len > 0) {
 331                 usbd_get_page(td->pc, td->offset, &buf_res);
 332
 333                 /* get correct length */
 334                 if (buf_res.length > len)
 335                         buf_res.length = len;
 336
 337                 /* check buffer alignment */
 338                 if (((uintptr_t)buf_res.buffer) & 3)
 339                         break;
 340
 341                 count = buf_res.length & ~3;
 342                 if (count == 0)
 343                         break;
 344
 345                 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 346                     offset, buf_res.buffer, count / 4);
 347
 348                 len -= count;
 349                 offset += count;
 350
 351                 /* update remainder and offset */
 352                 td->remainder -= count;
 353                 td->offset += count;
 354         }
 355
 356         if (len > 0) {
 357                 /* use bounce buffer */
 358                 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 359                     offset, sc->sc_bounce_buffer, (len + 3) / 4);
 360                 usbd_copy_in(td->pc, td->offset,
 361                     sc->sc_bounce_buffer, len);
 362
 363                 /* update remainder and offset */
 364                 td->remainder -= len;
 365                 td->offset += len;
 366         }
 367 }
 368
 369 static void
 370 saf1761_write_host_memory(struct saf1761_otg_softc *sc,
 371     struct saf1761_otg_td *td, uint32_t len)
 372 {
 373         struct usb_page_search buf_res;
 374         uint32_t offset;
 375         uint32_t count;
 376
 377         if (len == 0)
 378                 return;
 379
 380         offset = SOTG_DATA_ADDR(td->channel);
 381
 382         /* optimised write first */
 383         while (len > 0) {
 384                 usbd_get_page(td->pc, td->offset, &buf_res);
 385
 386                 /* get correct length */
 387                 if (buf_res.length > len)
 388                         buf_res.length = len;
 389
 390                 /* check buffer alignment */
 391                 if (((uintptr_t)buf_res.buffer) & 3)
 392                         break;
 393
 394                 count = buf_res.length & ~3;
 395                 if (count == 0)
 396                         break;
 397
 398                 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 399                     offset, buf_res.buffer, count / 4);
 400
 401                 len -= count;
 402                 offset += count;
 403
 404                 /* update remainder and offset */
 405                 td->remainder -= count;
 406                 td->offset += count;
 407         }
 408         if (len > 0) {
 409                 /* use bounce buffer */
 410                 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
 411                 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 412                     offset, sc->sc_bounce_buffer, (len + 3) / 4);
 413
 414                 /* update remainder and offset */
 415                 td->remainder -= len;
 416                 td->offset += len;
 417         }
 418 }
 419
 420 static uint8_t
 421 saf1761_host_setup_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 422 {
 423         uint32_t pdt_addr;
 424         uint32_t status;
 425         uint32_t count;
 426         uint32_t temp;
 427
 428         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 429                 pdt_addr = SOTG_PTD(td->channel);
 430
 431                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 432
 433                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 434
 435                 if (status & SOTG_PTD_DW3_ACTIVE) {
 436                         goto busy;
 437                 } else if (status & SOTG_PTD_DW3_HALTED) {
 438                         td->error_any = 1;
 439                 }
 440                 goto complete;
 441         }
 442         if (saf1761_host_channel_alloc(sc, td))
 443                 goto busy;
 444
 445         count = 8;
 446
 447         if (count != td->remainder) {
 448                 td->error_any = 1;
 449                 goto complete;
 450         }
 451
 452         saf1761_write_host_memory(sc, td, count);
 453
 454         pdt_addr = SOTG_PTD(td->channel);
 455
 456         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 457         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 458         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 459         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 460
 461         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 462         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 463
 464         temp = SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8;
 465         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 466
 467         temp = td->dw1_value | (2 << 10) /* SETUP PID */ | (td->ep_index >> 1);
 468         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 469
 470         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 471             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 472             (count << 3) /* transfer count */ |
 473             SOTG_PTD_DW0_VALID;
 474         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 475
 476         /* activate PTD */
 477         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 478             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 479
 480         td->toggle = 1;
 481 busy:
 482         return (1);     /* busy */
 483 complete:
 484         saf1761_host_channel_free(sc, td);
 485         return (0);     /* complete */
 486 }
 487
 488 static uint8_t
 489 saf1761_host_bulk_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 490 {
 491         uint32_t pdt_addr;
 492         uint32_t temp;
 493
 494         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 495                 uint32_t status;
 496                 uint32_t count;
 497                 uint8_t got_short;
 498
 499                 pdt_addr = SOTG_PTD(td->channel);
 500
 501                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 502
 503                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 504
 505                 if (status & SOTG_PTD_DW3_ACTIVE) {
 506                         goto busy;
 507                 } else if (status & SOTG_PTD_DW3_HALTED) {
 508                         if (!(status & SOTG_PTD_DW3_ERRORS))
 509                                 td->error_stall = 1;
 510                         td->error_any = 1;
 511                         goto complete;
 512                 }
 513                 count = (status & SOTG_PTD_DW3_XFER_COUNT);
 514                 got_short = 0;
 515
 516                 /* verify the packet byte count */
 517                 if (count != td->max_packet_size) {
 518                         if (count < td->max_packet_size) {
 519                                 /* we have a short packet */
 520                                 td->short_pkt = 1;
 521                                 got_short = 1;
 522                         } else {
 523                                 /* invalid USB packet */
 524                                 td->error_any = 1;
 525                                 goto complete;
 526                         }
 527                 }
 528                 td->toggle ^= 1;
 529
 530                 /* verify the packet byte count */
 531                 if (count > td->remainder) {
 532                         /* invalid USB packet */
 533                         td->error_any = 1;
 534                         goto complete;
 535                 }
 536
 537                 saf1761_read_host_memory(sc, td, count);
 538
 539                 /* check if we are complete */
 540                 if ((td->remainder == 0) || got_short) {
 541                         if (td->short_pkt)
 542                                 goto complete;
 543                         /* else need to receive a zero length packet */
 544                 }
 545                 saf1761_host_channel_free(sc, td);
 546         }
 547         if (saf1761_host_channel_alloc(sc, td))
 548                 goto busy;
 549
 550         /* set toggle, if any */
 551         if (td->set_toggle) {
 552                 td->set_toggle = 0;
 553                 td->toggle = 1;
 554         }
 555
 556         /* receive one more packet */
 557
 558         pdt_addr = SOTG_PTD(td->channel);
 559
 560         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 561         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 562         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 563         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 564
 565         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
 566             SOTG_PTD_DW3_CERR_2;
 567         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 568
 569         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
 570         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 571
 572         temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
 573         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 574
 575         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 576             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 577             (td->max_packet_size << 3) /* transfer count */ |
 578             SOTG_PTD_DW0_VALID;
 579         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 580
 581         /* activate PTD */
 582         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 583             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 584 busy:
 585         return (1);     /* busy */
 586 complete:
 587         saf1761_host_channel_free(sc, td);
 588         return (0);     /* complete */
 589 }
 590
 591 static uint8_t
 592 saf1761_host_bulk_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 593 {
 594         uint32_t pdt_addr;
 595         uint32_t temp;
 596         uint32_t count;
 597
 598         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 599                 uint32_t status;
 600
 601                 pdt_addr = SOTG_PTD(td->channel);
 602
 603                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 604
 605                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 606
 607                 if (status & SOTG_PTD_DW3_ACTIVE) {
 608                         goto busy;
 609                 } else if (status & SOTG_PTD_DW3_HALTED) {
 610                         if (!(status & SOTG_PTD_DW3_ERRORS))
 611                                 td->error_stall = 1;
 612                         td->error_any = 1;
 613                         goto complete;
 614                 }
 615                 /* check remainder */
 616                 if (td->remainder == 0) {
 617                         if (td->short_pkt)
 618                                 goto complete;
 619                         /* else we need to transmit a short packet */
 620                 }
 621                 saf1761_host_channel_free(sc, td);
 622         }
 623         if (saf1761_host_channel_alloc(sc, td))
 624                 goto busy;
 625
 626         count = td->max_packet_size;
 627         if (td->remainder < count) {
 628                 /* we have a short packet */
 629                 td->short_pkt = 1;
 630                 count = td->remainder;
 631         }
 632
 633         saf1761_write_host_memory(sc, td, count);
 634
 635         /* set toggle, if any */
 636         if (td->set_toggle) {
 637                 td->set_toggle = 0;
 638                 td->toggle = 1;
 639         }
 640
 641         /* send one more packet */
 642
 643         pdt_addr = SOTG_PTD(td->channel);
 644
 645         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 646         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 647         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 648         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 649
 650         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
 651             SOTG_PTD_DW3_CERR_2;
 652         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 653
 654         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
 655         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 656
 657         temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
 658         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 659
 660         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 661             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 662             (count << 3) /* transfer count */ |
 663             SOTG_PTD_DW0_VALID;
 664         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 665
 666         /* activate PTD */
 667         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 668             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 669
 670         td->toggle ^= 1;
 671 busy:
 672         return (1);     /* busy */
 673 complete:
 674         saf1761_host_channel_free(sc, td);
 675         return (0);     /* complete */
 676 }
 677
 678 static uint8_t
 679 saf1761_host_intr_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 680 {
 681         uint32_t pdt_addr;
 682         uint32_t temp;
 683
 684         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 685                 uint32_t status;
 686                 uint32_t count;
 687                 uint8_t got_short;
 688
 689                 pdt_addr = SOTG_PTD(td->channel);
 690
 691                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 692
 693                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 694
 695                 if (status & SOTG_PTD_DW3_ACTIVE) {
 696                         goto busy;
 697                 } else if (status & SOTG_PTD_DW3_HALTED) {
 698                         if (!(status & SOTG_PTD_DW3_ERRORS))
 699                                 td->error_stall = 1;
 700                         td->error_any = 1;
 701                         goto complete;
 702                 }
 703                 count = (status & SOTG_PTD_DW3_XFER_COUNT);
 704                 got_short = 0;
 705
 706                 /* verify the packet byte count */
 707                 if (count != td->max_packet_size) {
 708                         if (count < td->max_packet_size) {
 709                                 /* we have a short packet */
 710                                 td->short_pkt = 1;
 711                                 got_short = 1;
 712                         } else {
 713                                 /* invalid USB packet */
 714                                 td->error_any = 1;
 715                                 goto complete;
 716                         }
 717                 }
 718                 td->toggle ^= 1;
 719
 720                 /* verify the packet byte count */
 721                 if (count > td->remainder) {
 722                         /* invalid USB packet */
 723                         td->error_any = 1;
 724                         goto complete;
 725                 }
 726
 727                 saf1761_read_host_memory(sc, td, count);
 728
 729                 /* check if we are complete */
 730                 if ((td->remainder == 0) || got_short) {
 731                         if (td->short_pkt)
 732                                 goto complete;
 733                         /* else need to receive a zero length packet */
 734                 }
 735                 saf1761_host_channel_free(sc, td);
 736         }
 737         if (saf1761_host_channel_alloc(sc, td))
 738                 goto busy;
 739
 740         /* set toggle, if any */
 741         if (td->set_toggle) {
 742                 td->set_toggle = 0;
 743                 td->toggle = 1;
 744         }
 745
 746         /* receive one more packet */
 747
 748         pdt_addr = SOTG_PTD(td->channel);
 749
 750         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 751         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 752
 753         temp = (0xFC << td->uframe) & 0xFF;     /* complete split */
 754         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
 755
 756         temp = (1U << td->uframe);              /* start split */
 757         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
 758
 759         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 760         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 761
 762         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
 763             (td->interval & 0xF8);
 764         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 765
 766         temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
 767         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 768
 769         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 770             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 771             (td->max_packet_size << 3) /* transfer count */ |
 772             SOTG_PTD_DW0_VALID;
 773         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 774
 775         /* activate PTD */
 776         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 777             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 778 busy:
 779         return (1);     /* busy */
 780 complete:
 781         saf1761_host_channel_free(sc, td);
 782         return (0);     /* complete */
 783 }
 784
 785 static uint8_t
 786 saf1761_host_intr_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 787 {
 788         uint32_t pdt_addr;
 789         uint32_t temp;
 790         uint32_t count;
 791
 792         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 793                 uint32_t status;
 794
 795                 pdt_addr = SOTG_PTD(td->channel);
 796
 797                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 798
 799                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 800
 801                 if (status & SOTG_PTD_DW3_ACTIVE) {
 802                         goto busy;
 803                 } else if (status & SOTG_PTD_DW3_HALTED) {
 804                         if (!(status & SOTG_PTD_DW3_ERRORS))
 805                                 td->error_stall = 1;
 806                         td->error_any = 1;
 807                         goto complete;
 808                 }
 809
 810                 /* check remainder */
 811                 if (td->remainder == 0) {
 812                         if (td->short_pkt)
 813                                 goto complete;
 814                         /* else we need to transmit a short packet */
 815                 }
 816                 saf1761_host_channel_free(sc, td);
 817         }
 818         if (saf1761_host_channel_alloc(sc, td))
 819                 goto busy;
 820
 821         count = td->max_packet_size;
 822         if (td->remainder < count) {
 823                 /* we have a short packet */
 824                 td->short_pkt = 1;
 825                 count = td->remainder;
 826         }
 827
 828         saf1761_write_host_memory(sc, td, count);
 829
 830         /* set toggle, if any */
 831         if (td->set_toggle) {
 832                 td->set_toggle = 0;
 833                 td->toggle = 1;
 834         }
 835
 836         /* send one more packet */
 837
 838         pdt_addr = SOTG_PTD(td->channel);
 839
 840         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 841         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 842
 843         temp = (0xFC << td->uframe) & 0xFF;     /* complete split */
 844         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
 845
 846         temp = (1U << td->uframe);              /* start split */
 847         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
 848
 849         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 850         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 851
 852         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
 853             (td->interval & 0xF8);
 854         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 855
 856         temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
 857         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 858
 859         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 860             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 861             (count << 3) /* transfer count */ |
 862             SOTG_PTD_DW0_VALID;
 863         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 864
 865         /* activate PTD */
 866         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 867             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 868
 869         td->toggle ^= 1;
 870 busy:
 871         return (1);     /* busy */
 872 complete:
 873         saf1761_host_channel_free(sc, td);
 874         return (0);     /* complete */
 875 }
 876
 877 static uint8_t
 878 saf1761_host_isoc_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 879 {
 880         uint32_t pdt_addr;
 881         uint32_t temp;
 882
 883         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 884                 uint32_t status;
 885                 uint32_t count;
 886
 887                 pdt_addr = SOTG_PTD(td->channel);
 888
 889                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 890
 891                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 892
 893                 if (status & SOTG_PTD_DW3_ACTIVE) {
 894                         goto busy;
 895                 } else if (status & SOTG_PTD_DW3_HALTED) {
 896                         goto complete;
 897                 }
 898                 count = (status & SOTG_PTD_DW3_XFER_COUNT);
 899
 900                 /* verify the packet byte count */
 901                 if (count != td->max_packet_size) {
 902                         if (count < td->max_packet_size) {
 903                                 /* we have a short packet */
 904                                 td->short_pkt = 1;
 905                         } else {
 906                                 /* invalid USB packet */
 907                                 td->error_any = 1;
 908                                 goto complete;
 909                         }
 910                 }
 911
 912                 /* verify the packet byte count */
 913                 if (count > td->remainder) {
 914                         /* invalid USB packet */
 915                         td->error_any = 1;
 916                         goto complete;
 917                 }
 918
 919                 saf1761_read_host_memory(sc, td, count);
 920                 goto complete;
 921         }
 922
 923         if (saf1761_host_channel_alloc(sc, td))
 924                 goto busy;
 925
 926         /* receive one more packet */
 927
 928         pdt_addr = SOTG_PTD(td->channel);
 929
 930         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 931         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 932
 933         temp = (0xFC << td->uframe) & 0xFF;     /* complete split */
 934         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
 935
 936         temp = (1U << td->uframe);              /* start split */
 937         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
 938
 939         temp = SOTG_PTD_DW3_ACTIVE | SOTG_PTD_DW3_CERR_3;
 940         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 941
 942         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
 943         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 944
 945         temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
 946         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 947
 948         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 949             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 950             (td->max_packet_size << 3) /* transfer count */ |
 951             SOTG_PTD_DW0_VALID;
 952         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 953
 954         /* activate PTD */
 955         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
 956             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
 957 busy:
 958         return (1);     /* busy */
 959 complete:
 960         saf1761_host_channel_free(sc, td);
 961         return (0);     /* complete */
 962 }
 963
 964 static uint8_t
 965 saf1761_host_isoc_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 966 {
 967         uint32_t pdt_addr;
 968         uint32_t temp;
 969         uint32_t count;
 970
 971         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 972                 uint32_t status;
 973
 974                 pdt_addr = SOTG_PTD(td->channel);
 975
 976                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 977
 978                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 979
 980                 if (status & SOTG_PTD_DW3_ACTIVE) {
 981                         goto busy;
 982                 } else if (status & SOTG_PTD_DW3_HALTED) {
 983                         goto complete;
 984                 }
 985
 986                 goto complete;
 987         }
 988         if (saf1761_host_channel_alloc(sc, td))
 989                 goto busy;
 990
 991         count = td->max_packet_size;
 992         if (td->remainder < count) {
 993                 /* we have a short packet */
 994                 td->short_pkt = 1;
 995                 count = td->remainder;
 996         }
 997
 998         saf1761_write_host_memory(sc, td, count);
 999
1000         /* send one more packet */
1001
1002         pdt_addr = SOTG_PTD(td->channel);
1003
1004         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
1005         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
1006         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
1007
1008         temp = (1U << td->uframe);              /* start split */
1009         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
1010
1011         temp = SOTG_PTD_DW3_ACTIVE | SOTG_PTD_DW3_CERR_3;
1012         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
1013
1014         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
1015         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
1016
1017         temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
1018         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
1019
1020         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
1021             (count << 18) /* wMaxPacketSize */ |
1022             (count << 3) /* transfer count */ |
1023             SOTG_PTD_DW0_VALID;
1024         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
1025
1026         /* activate PTD */
1027         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
1028             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
1029 busy:
1030         return (1);     /* busy */
1031 complete:
1032         saf1761_host_channel_free(sc, td);
1033         return (0);     /* complete */
1034 }
1035
1036 static void
1037 saf1761_otg_set_address(struct saf1761_otg_softc *sc, uint8_t addr)
1038 {
1039         DPRINTFN(5, "addr=%d\n", addr);
1040
1041         SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, addr | SOTG_ADDRESS_ENABLE);
1042 }
1043
1044
1045 static void
1046 saf1761_read_device_fifo(struct saf1761_otg_softc *sc,
1047     struct saf1761_otg_td *td, uint32_t len)
1048 {
1049         struct usb_page_search buf_res;
1050         uint32_t count;
1051
1052         /* optimised read first */
1053         while (len > 0) {
1054                 usbd_get_page(td->pc, td->offset, &buf_res);
1055
1056                 /* get correct length */
1057                 if (buf_res.length > len)
1058                         buf_res.length = len;
1059
1060                 /* check buffer alignment */
1061                 if (((uintptr_t)buf_res.buffer) & 3)
1062                         break;
1063
1064                 count = buf_res.length & ~3;
1065                 if (count == 0)
1066                         break;
1067
1068                 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1069                     SOTG_DATA_PORT, buf_res.buffer, count / 4);
1070
1071                 len -= count;
1072
1073                 /* update remainder and offset */
1074                 td->remainder -= count;
1075                 td->offset += count;
1076         }
1077
1078         if (len > 0) {
1079                 /* use bounce buffer */
1080                 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1081                     SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
1082                 usbd_copy_in(td->pc, td->offset,
1083                     sc->sc_bounce_buffer, len);
1084
1085                 /* update remainder and offset */
1086                 td->remainder -= len;
1087                 td->offset += len;
1088         }
1089 }
1090
1091 static void
1092 saf1761_write_device_fifo(struct saf1761_otg_softc *sc,
1093     struct saf1761_otg_td *td, uint32_t len)
1094 {
1095         struct usb_page_search buf_res;
1096         uint32_t count;
1097
1098         /* optimised write first */
1099         while (len > 0) {
1100                 usbd_get_page(td->pc, td->offset, &buf_res);
1101
1102                 /* get correct length */
1103                 if (buf_res.length > len)
1104                         buf_res.length = len;
1105
1106                 /* check buffer alignment */
1107                 if (((uintptr_t)buf_res.buffer) & 3)
1108                         break;
1109
1110                 count = buf_res.length & ~3;
1111                 if (count == 0)
1112                         break;
1113
1114                 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1115                     SOTG_DATA_PORT, buf_res.buffer, count / 4);
1116
1117                 len -= count;
1118
1119                 /* update remainder and offset */
1120                 td->remainder -= count;
1121                 td->offset += count;
1122         }
1123         if (len > 0) {
1124                 /* use bounce buffer */
1125                 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
1126                 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1127                     SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
1128
1129                 /* update remainder and offset */
1130                 td->remainder -= len;
1131                 td->offset += len;
1132         }
1133 }
1134
1135 static uint8_t
1136 saf1761_device_setup_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1137 {
1138         struct usb_device_request req;
1139         uint32_t count;
1140
1141         /* select the correct endpoint */
1142         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1143
1144         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1145
1146         /* check buffer status */
1147         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1148                 goto busy;
1149
1150         /* get buffer length */
1151         count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1152
1153         DPRINTFN(5, "count=%u rem=%u\n", count, td->remainder);
1154
1155         /* clear did stall */
1156         td->did_stall = 0;
1157
1158         /* clear stall */
1159         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
1160
1161         /* verify data length */
1162         if (count != td->remainder) {
1163                 DPRINTFN(0, "Invalid SETUP packet "
1164                     "length, %d bytes\n", count);
1165                 goto busy;
1166         }
1167         if (count != sizeof(req)) {
1168                 DPRINTFN(0, "Unsupported SETUP packet "
1169                     "length, %d bytes\n", count);
1170                 goto busy;
1171         }
1172         /* receive data */
1173         saf1761_read_device_fifo(sc, td, sizeof(req));
1174
1175         /* extract SETUP packet again */
1176         usbd_copy_out(td->pc, 0, &req, sizeof(req));
1177
1178         /* sneak peek the set address request */
1179         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1180             (req.bRequest == UR_SET_ADDRESS)) {
1181                 sc->sc_dv_addr = req.wValue[0] & 0x7F;
1182                 DPRINTF("Set address %d\n", sc->sc_dv_addr);
1183         } else {
1184                 sc->sc_dv_addr = 0xFF;
1185         }
1186         return (0);                     /* complete */
1187
1188 busy:
1189         /* abort any ongoing transfer */
1190         if (!td->did_stall) {
1191                 DPRINTFN(5, "stalling\n");
1192
1193                 /* set stall */
1194                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
1195
1196                 td->did_stall = 1;
1197         }
1198         return (1);                     /* not complete */
1199 }
1200
1201 static uint8_t
1202 saf1761_device_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1203 {
1204         uint32_t count;
1205         uint8_t got_short = 0;
1206
1207         if (td->ep_index == 0) {
1208                 /* select the correct endpoint */
1209                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1210
1211                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1212
1213                 /* check buffer status */
1214                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1215
1216                         if (td->remainder == 0) {
1217                                 /*
1218                                  * We are actually complete and have
1219                                  * received the next SETUP:
1220                                  */
1221                                 DPRINTFN(5, "faking complete\n");
1222                                 return (0);     /* complete */
1223                         }
1224                         DPRINTFN(5, "SETUP packet while receiving data\n");
1225                         /*
1226                          * USB Host Aborted the transfer.
1227                          */
1228                         td->error_any = 1;
1229                         return (0);     /* complete */
1230                 }
1231         }
1232         /* select the correct endpoint */
1233         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1234             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1235             SOTG_EP_INDEX_DIR_OUT);
1236
1237         /* enable data stage */
1238         if (td->set_toggle) {
1239                 td->set_toggle = 0;
1240                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1241         }
1242
1243         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1244
1245         /* check buffer status */
1246         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1247                 return (1);             /* not complete */
1248
1249         /* get buffer length */
1250         count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1251
1252         DPRINTFN(5, "rem=%u count=0x%04x\n", td->remainder, count);
1253
1254         /* verify the packet byte count */
1255         if (count != td->max_packet_size) {
1256                 if (count < td->max_packet_size) {
1257                         /* we have a short packet */
1258                         td->short_pkt = 1;
1259                         got_short = 1;
1260                 } else {
1261                         /* invalid USB packet */
1262                         td->error_any = 1;
1263                         return (0);     /* we are complete */
1264                 }
1265         }
1266         /* verify the packet byte count */
1267         if (count > td->remainder) {
1268                 /* invalid USB packet */
1269                 td->error_any = 1;
1270                 return (0);             /* we are complete */
1271         }
1272         /* receive data */
1273         saf1761_read_device_fifo(sc, td, count);
1274
1275         /* check if we are complete */
1276         if ((td->remainder == 0) || got_short) {
1277                 if (td->short_pkt) {
1278                         /* we are complete */
1279                         return (0);
1280                 }
1281                 /* else need to receive a zero length packet */
1282         }
1283         return (1);                     /* not complete */
1284 }
1285
1286 static uint8_t
1287 saf1761_device_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1288 {
1289         uint32_t count;
1290
1291         if (td->ep_index == 0) {
1292                 /* select the correct endpoint */
1293                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1294
1295                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1296
1297                 /* check buffer status */
1298                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1299                         DPRINTFN(5, "SETUP abort\n");
1300                         /*
1301                          * USB Host Aborted the transfer.
1302                          */
1303                         td->error_any = 1;
1304                         return (0);     /* complete */
1305                 }
1306         }
1307         /* select the correct endpoint */
1308         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1309             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1310             SOTG_EP_INDEX_DIR_IN);
1311
1312         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1313
1314         /* check buffer status */
1315         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1316                 return (1);             /* not complete */
1317
1318         /* enable data stage */
1319         if (td->set_toggle) {
1320                 td->set_toggle = 0;
1321                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1322         }
1323
1324         DPRINTFN(5, "rem=%u\n", td->remainder);
1325
1326         count = td->max_packet_size;
1327         if (td->remainder < count) {
1328                 /* we have a short packet */
1329                 td->short_pkt = 1;
1330                 count = td->remainder;
1331         }
1332         /* transmit data */
1333         saf1761_write_device_fifo(sc, td, count);
1334
1335         if (td->ep_index == 0) {
1336                 if (count < SOTG_FS_MAX_PACKET_SIZE) {
1337                         /* set end of packet */
1338                         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1339                 }
1340         } else {
1341                 if (count < SOTG_HS_MAX_PACKET_SIZE) {
1342                         /* set end of packet */
1343                         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1344                 }
1345         }
1346
1347         /* check remainder */
1348         if (td->remainder == 0) {
1349                 if (td->short_pkt) {
1350                         return (0);     /* complete */
1351                 }
1352                 /* else we need to transmit a short packet */
1353         }
1354         return (1);                     /* not complete */
1355 }
1356
1357 static uint8_t
1358 saf1761_device_data_tx_sync(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1359 {
1360         uint32_t count;
1361
1362         if (td->ep_index == 0) {
1363                 /* select the correct endpoint */
1364                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1365
1366                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1367
1368                 /* check buffer status */
1369                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1370                         DPRINTFN(5, "Faking complete\n");
1371                         return (0);     /* complete */
1372                 }
1373         }
1374         /* select the correct endpoint */
1375         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1376             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1377             SOTG_EP_INDEX_DIR_IN);
1378
1379         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1380
1381         /* check buffer status */
1382         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1383                 return (1);             /* busy */
1384
1385         if (sc->sc_dv_addr != 0xFF) {
1386                 /* write function address */
1387                 saf1761_otg_set_address(sc, sc->sc_dv_addr);
1388         }
1389         return (0);                     /* complete */
1390 }
1391
1392 static void
1393 saf1761_otg_xfer_do_fifo(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1394 {
1395         struct saf1761_otg_td *td;
1396         uint8_t toggle;
1397
1398         DPRINTFN(9, "\n");
1399
1400         td = xfer->td_transfer_cache;
1401         if (td == NULL)
1402                 return;
1403
1404         while (1) {
1405                 if ((td->func) (sc, td)) {
1406                         /* operation in progress */
1407                         break;
1408                 }
1409                 if (((void *)td) == xfer->td_transfer_last) {
1410                         goto done;
1411                 }
1412                 if (td->error_any) {
1413                         goto done;
1414                 } else if (td->remainder > 0) {
1415                         /*
1416                          * We had a short transfer. If there is no alternate
1417                          * next, stop processing !
1418                          */
1419                         if (!td->alt_next) {
1420                                 goto done;
1421                         }
1422                 }
1423                 /*
1424                  * Fetch the next transfer descriptor.
1425                  */
1426                 toggle = td->toggle;
1427                 td = td->obj_next;
1428                 td->toggle = toggle;
1429                 xfer->td_transfer_cache = td;
1430         }
1431         return;
1432
1433 done:
1434         /* compute all actual lengths */
1435         xfer->td_transfer_cache = NULL;
1436         sc->sc_xfer_complete = 1;
1437 }
1438
1439 static uint8_t
1440 saf1761_otg_xfer_do_complete(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1441 {
1442         struct saf1761_otg_td *td;
1443
1444         DPRINTFN(9, "\n");
1445
1446         td = xfer->td_transfer_cache;
1447         if (td == NULL) {
1448                 /* compute all actual lengths */
1449                 saf1761_otg_standard_done(xfer);
1450                 return (1);
1451         }
1452         return (0);
1453 }
1454
1455 static void
1456 saf1761_otg_interrupt_poll_locked(struct saf1761_otg_softc *sc)
1457 {
1458         struct usb_xfer *xfer;
1459
1460         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
1461                 saf1761_otg_xfer_do_fifo(sc, xfer);
1462 }
1463
1464 static void
1465 saf1761_otg_wait_suspend(struct saf1761_otg_softc *sc, uint8_t on)
1466 {
1467         if (on) {
1468                 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IESUSP;
1469                 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IERESM;
1470         } else {
1471                 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IESUSP;
1472                 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IERESM;
1473         }
1474         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1475 }
1476
1477 static void
1478 saf1761_otg_update_vbus(struct saf1761_otg_softc *sc)
1479 {
1480         uint16_t status;
1481
1482         /* read fresh status */
1483         status = SAF1761_READ_LE_4(sc, SOTG_STATUS);
1484
1485         DPRINTFN(4, "STATUS=0x%04x\n", status);
1486
1487         if ((status & SOTG_STATUS_VBUS_VLD) &&
1488             (status & SOTG_STATUS_ID)) {
1489                 /* VBUS present and device mode */
1490                 if (!sc->sc_flags.status_vbus) {
1491                         sc->sc_flags.status_vbus = 1;
1492
1493                         /* complete root HUB interrupt endpoint */
1494                         saf1761_otg_root_intr(sc);
1495                 }
1496         } else {
1497                 /* VBUS not-present or host mode */
1498                 if (sc->sc_flags.status_vbus) {
1499                         sc->sc_flags.status_vbus = 0;
1500                         sc->sc_flags.status_bus_reset = 0;
1501                         sc->sc_flags.status_suspend = 0;
1502                         sc->sc_flags.change_suspend = 0;
1503                         sc->sc_flags.change_connect = 1;
1504
1505                         /* complete root HUB interrupt endpoint */
1506                         saf1761_otg_root_intr(sc);
1507                 }
1508         }
1509 }
1510
1511 static void
1512 saf1761_otg_interrupt_complete_locked(struct saf1761_otg_softc *sc)
1513 {
1514         struct usb_xfer *xfer;
1515 repeat:
1516         /* scan for completion events */
1517         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1518                 if (saf1761_otg_xfer_do_complete(sc, xfer))
1519                         goto repeat;
1520         }
1521 }
1522
1523 int
1524 saf1761_otg_filter_interrupt(void *arg)
1525 {
1526         struct saf1761_otg_softc *sc = arg;
1527         int retval = FILTER_HANDLED;
1528         uint32_t hcstat;
1529         uint32_t status;
1530
1531         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1532
1533         hcstat = SAF1761_READ_LE_4(sc, SOTG_HCINTERRUPT);
1534         /* acknowledge all host controller interrupts */
1535         SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT, hcstat);
1536
1537         status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT);
1538         /* acknowledge all device controller interrupts */
1539         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT,
1540             status & ~SAF1761_DCINTERRUPT_THREAD_IRQ);
1541
1542         (void) SAF1761_READ_LE_4(sc, SOTG_ATL_PTD_DONE_PTD);
1543         (void) SAF1761_READ_LE_4(sc, SOTG_INT_PTD_DONE_PTD);
1544         (void) SAF1761_READ_LE_4(sc, SOTG_ISO_PTD_DONE_PTD);
1545
1546         if (status & SAF1761_DCINTERRUPT_THREAD_IRQ)
1547                 retval = FILTER_SCHEDULE_THREAD;
1548
1549         /* poll FIFOs, if any */
1550         saf1761_otg_interrupt_poll_locked(sc);
1551
1552         if (sc->sc_xfer_complete != 0)
1553                 retval = FILTER_SCHEDULE_THREAD;
1554
1555         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1556
1557         return (retval);
1558 }
1559
1560 void
1561 saf1761_otg_interrupt(void *arg)
1562 {
1563         struct saf1761_otg_softc *sc = arg;
1564         uint32_t status;
1565
1566         USB_BUS_LOCK(&sc->sc_bus);
1567         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1568
1569         status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT) &
1570             SAF1761_DCINTERRUPT_THREAD_IRQ;
1571
1572         /* acknowledge all device controller interrupts */
1573         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT, status);
1574
1575         DPRINTF("DCINTERRUPT=0x%08x SOF=0x%08x "
1576             "FRINDEX=0x%08x\n", status,
1577             SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM),
1578             SAF1761_READ_LE_4(sc, SOTG_FRINDEX));
1579
1580         /* update VBUS and ID bits, if any */
1581         if (status & SOTG_DCINTERRUPT_IEVBUS)
1582                 saf1761_otg_update_vbus(sc);
1583
1584         if (status & SOTG_DCINTERRUPT_IEBRST) {
1585                 /* unlock device */
1586                 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1587                     SOTG_UNLOCK_DEVICE_CODE);
1588
1589                 /* Enable device address */
1590                 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS,
1591                     SOTG_ADDRESS_ENABLE);
1592
1593                 sc->sc_flags.status_bus_reset = 1;
1594                 sc->sc_flags.status_suspend = 0;
1595                 sc->sc_flags.change_suspend = 0;
1596                 sc->sc_flags.change_connect = 1;
1597
1598                 /* disable resume interrupt */
1599                 saf1761_otg_wait_suspend(sc, 1);
1600                 /* complete root HUB interrupt endpoint */
1601                 saf1761_otg_root_intr(sc);
1602         }
1603         /*
1604          * If "RESUME" and "SUSPEND" is set at the same time we
1605          * interpret that like "RESUME". Resume is set when there is
1606          * at least 3 milliseconds of inactivity on the USB BUS:
1607          */
1608         if (status & SOTG_DCINTERRUPT_IERESM) {
1609                 /* unlock device */
1610                 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1611                     SOTG_UNLOCK_DEVICE_CODE);
1612
1613                 if (sc->sc_flags.status_suspend) {
1614                         sc->sc_flags.status_suspend = 0;
1615                         sc->sc_flags.change_suspend = 1;
1616                         /* disable resume interrupt */
1617                         saf1761_otg_wait_suspend(sc, 1);
1618                         /* complete root HUB interrupt endpoint */
1619                         saf1761_otg_root_intr(sc);
1620                 }
1621         } else if (status & SOTG_DCINTERRUPT_IESUSP) {
1622                 if (!sc->sc_flags.status_suspend) {
1623                         sc->sc_flags.status_suspend = 1;
1624                         sc->sc_flags.change_suspend = 1;
1625                         /* enable resume interrupt */
1626                         saf1761_otg_wait_suspend(sc, 0);
1627                         /* complete root HUB interrupt endpoint */
1628                         saf1761_otg_root_intr(sc);
1629                 }
1630         }
1631
1632         if (sc->sc_xfer_complete != 0) {
1633                 sc->sc_xfer_complete = 0;
1634
1635                 /* complete FIFOs, if any */
1636                 saf1761_otg_interrupt_complete_locked(sc);
1637         }
1638         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1639         USB_BUS_UNLOCK(&sc->sc_bus);
1640 }
1641
1642 static void
1643 saf1761_otg_setup_standard_chain_sub(struct saf1761_otg_std_temp *temp)
1644 {
1645         struct saf1761_otg_td *td;
1646
1647         /* get current Transfer Descriptor */
1648         td = temp->td_next;
1649         temp->td = td;
1650
1651         /* prepare for next TD */
1652         temp->td_next = td->obj_next;
1653
1654         /* fill out the Transfer Descriptor */
1655         td->func = temp->func;
1656         td->pc = temp->pc;
1657         td->offset = temp->offset;
1658         td->remainder = temp->len;
1659         td->error_any = 0;
1660         td->error_stall = 0;
1661         td->set_toggle = 0;
1662         td->did_stall = temp->did_stall;
1663         td->short_pkt = temp->short_pkt;
1664         td->alt_next = temp->setup_alt_next;
1665         td->channel = SOTG_HOST_CHANNEL_MAX;
1666 }
1667
1668 static void
1669 saf1761_otg_setup_standard_chain(struct usb_xfer *xfer)
1670 {
1671         struct saf1761_otg_std_temp temp;
1672         struct saf1761_otg_softc *sc;
1673         struct saf1761_otg_td *td;
1674         uint32_t x;
1675         uint8_t ep_no;
1676         uint8_t ep_type;
1677         uint8_t need_sync;
1678         uint8_t is_host;
1679
1680         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1681             xfer->address, UE_GET_ADDR(xfer->endpointno),
1682             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1683
1684         temp.max_frame_size = xfer->max_frame_size;
1685
1686         td = xfer->td_start[0];
1687         xfer->td_transfer_first = td;
1688         xfer->td_transfer_cache = td;
1689
1690         /* setup temp */
1691
1692         temp.pc = NULL;
1693         temp.td = NULL;
1694         temp.td_next = xfer->td_start[0];
1695         temp.offset = 0;
1696         temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
1697             xfer->flags_int.isochronous_xfr;
1698         temp.did_stall = !xfer->flags_int.control_stall;
1699
1700         is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
1701
1702         sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1703         ep_no = (xfer->endpointno & UE_ADDR);
1704         ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
1705
1706         /* check if we should prepend a setup message */
1707
1708         if (xfer->flags_int.control_xfr) {
1709                 if (xfer->flags_int.control_hdr) {
1710
1711                         if (is_host)
1712                                 temp.func = &saf1761_host_setup_tx;
1713                         else
1714                                 temp.func = &saf1761_device_setup_rx;
1715
1716                         temp.len = xfer->frlengths[0];
1717                         temp.pc = xfer->frbuffers + 0;
1718                         temp.short_pkt = temp.len ? 1 : 0;
1719                         /* check for last frame */
1720                         if (xfer->nframes == 1) {
1721                                 /* no STATUS stage yet, SETUP is last */
1722                                 if (xfer->flags_int.control_act)
1723                                         temp.setup_alt_next = 0;
1724                         }
1725                         saf1761_otg_setup_standard_chain_sub(&temp);
1726                 }
1727                 x = 1;
1728         } else {
1729                 x = 0;
1730         }
1731
1732         if (x != xfer->nframes) {
1733                 if (xfer->endpointno & UE_DIR_IN) {
1734                         if (is_host) {
1735                                 if (ep_type == UE_INTERRUPT)
1736                                         temp.func = &saf1761_host_intr_data_rx;
1737                                 else if (ep_type == UE_ISOCHRONOUS)
1738                                         temp.func = &saf1761_host_isoc_data_rx;
1739                                 else
1740                                         temp.func = &saf1761_host_bulk_data_rx;
1741                                 need_sync = 0;
1742                         } else {
1743                                 temp.func = &saf1761_device_data_tx;
1744                                 need_sync = 1;
1745                         }
1746                 } else {
1747                         if (is_host) {
1748                                 if (ep_type == UE_INTERRUPT)
1749                                         temp.func = &saf1761_host_intr_data_tx;
1750                                 else if (ep_type == UE_ISOCHRONOUS)
1751                                         temp.func = &saf1761_host_isoc_data_tx;
1752                                 else
1753                                         temp.func = &saf1761_host_bulk_data_tx;
1754                                 need_sync = 0;
1755                         } else {
1756                                 temp.func = &saf1761_device_data_rx;
1757                                 need_sync = 0;
1758                         }
1759                 }
1760
1761                 /* setup "pc" pointer */
1762                 temp.pc = xfer->frbuffers + x;
1763         } else {
1764                 need_sync = 0;
1765         }
1766
1767         while (x != xfer->nframes) {
1768
1769                 /* DATA0 / DATA1 message */
1770
1771                 temp.len = xfer->frlengths[x];
1772
1773                 x++;
1774
1775                 if (x == xfer->nframes) {
1776                         if (xfer->flags_int.control_xfr) {
1777                                 if (xfer->flags_int.control_act) {
1778                                         temp.setup_alt_next = 0;
1779                                 }
1780                         } else {
1781                                 temp.setup_alt_next = 0;
1782                         }
1783                 }
1784                 if (temp.len == 0) {
1785
1786                         /* make sure that we send an USB packet */
1787
1788                         temp.short_pkt = 0;
1789
1790                 } else {
1791
1792                         /* regular data transfer */
1793
1794                         temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1795                 }
1796
1797                 saf1761_otg_setup_standard_chain_sub(&temp);
1798
1799                 if (xfer->flags_int.isochronous_xfr) {
1800                         temp.offset += temp.len;
1801                 } else {
1802                         /* get next Page Cache pointer */
1803                         temp.pc = xfer->frbuffers + x;
1804                 }
1805         }
1806
1807         /* check for control transfer */
1808         if (xfer->flags_int.control_xfr) {
1809                 /* always setup a valid "pc" pointer for status and sync */
1810                 temp.pc = xfer->frbuffers + 0;
1811                 temp.len = 0;
1812                 temp.short_pkt = 0;
1813                 temp.setup_alt_next = 0;
1814
1815                 /* check if we should append a status stage */
1816                 if (!xfer->flags_int.control_act) {
1817
1818                         /*
1819                          * Send a DATA1 message and invert the current
1820                          * endpoint direction.
1821                          */
1822                         if (xfer->endpointno & UE_DIR_IN) {
1823                                 if (is_host) {
1824                                         temp.func = &saf1761_host_bulk_data_tx;
1825                                         need_sync = 0;
1826                                 } else {
1827                                         temp.func = &saf1761_device_data_rx;
1828                                         need_sync = 0;
1829                                 }
1830                         } else {
1831                                 if (is_host) {
1832                                         temp.func = &saf1761_host_bulk_data_rx;
1833                                         need_sync = 0;
1834                                 } else {
1835                                         temp.func = &saf1761_device_data_tx;
1836                                         need_sync = 1;
1837                                 }
1838                         }
1839                         temp.len = 0;
1840                         temp.short_pkt = 0;
1841
1842                         saf1761_otg_setup_standard_chain_sub(&temp);
1843
1844                         /* data toggle should be DATA1 */
1845                         td = temp.td;
1846                         td->set_toggle = 1;
1847
1848                         if (need_sync) {
1849                                 /* we need a SYNC point after TX */
1850                                 temp.func = &saf1761_device_data_tx_sync;
1851                                 saf1761_otg_setup_standard_chain_sub(&temp);
1852                         }
1853                 }
1854         } else {
1855                 if (need_sync) {
1856                         temp.pc = xfer->frbuffers + 0;
1857                         temp.len = 0;
1858                         temp.short_pkt = 0;
1859                         temp.setup_alt_next = 0;
1860
1861                         /* we need a SYNC point after TX */
1862                         temp.func = &saf1761_device_data_tx_sync;
1863                         saf1761_otg_setup_standard_chain_sub(&temp);
1864                 }
1865         }
1866
1867         /* must have at least one frame! */
1868         td = temp.td;
1869         xfer->td_transfer_last = td;
1870
1871         if (is_host) {
1872                 /* get first again */
1873                 td = xfer->td_transfer_first;
1874                 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
1875         }
1876 }
1877
1878 static void
1879 saf1761_otg_timeout(void *arg)
1880 {
1881         struct usb_xfer *xfer = arg;
1882
1883         DPRINTF("xfer=%p\n", xfer);
1884
1885         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1886
1887         /* transfer is transferred */
1888         saf1761_otg_device_done(xfer, USB_ERR_TIMEOUT);
1889 }
1890
1891 static void
1892 saf1761_otg_intr_set(struct usb_xfer *xfer, uint8_t set)
1893 {
1894         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1895         uint8_t ep_no = (xfer->endpointno & UE_ADDR);
1896         uint32_t mask;
1897
1898         DPRINTFN(15, "endpoint=%d set=%d\n", xfer->endpointno, set);
1899
1900         if (ep_no == 0) {
1901                 mask = SOTG_DCINTERRUPT_IEPRX(0) |
1902                     SOTG_DCINTERRUPT_IEPTX(0) |
1903                     SOTG_DCINTERRUPT_IEP0SETUP;
1904         } else if (xfer->endpointno & UE_DIR_IN) {
1905                 mask = SOTG_DCINTERRUPT_IEPTX(ep_no);
1906         } else {
1907                 mask = SOTG_DCINTERRUPT_IEPRX(ep_no);
1908         }
1909
1910         if (set)
1911                 sc->sc_intr_enable |= mask;
1912         else
1913                 sc->sc_intr_enable &= ~mask;
1914
1915         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1916 }
1917
1918 static void
1919 saf1761_otg_start_standard_chain(struct usb_xfer *xfer)
1920 {
1921         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1922
1923         DPRINTFN(9, "\n");
1924
1925         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1926
1927         /* poll one time */
1928         saf1761_otg_xfer_do_fifo(sc, xfer);
1929
1930         if (saf1761_otg_xfer_do_complete(sc, xfer) == 0) {
1931                 /*
1932                  * Only enable the endpoint interrupt when we are
1933                  * actually waiting for data, hence we are dealing
1934                  * with level triggered interrupts !
1935                  */
1936                 saf1761_otg_intr_set(xfer, 1);
1937
1938                 /* put transfer on interrupt queue */
1939                 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1940
1941                 /* start timeout, if any */
1942                 if (xfer->timeout != 0) {
1943                         usbd_transfer_timeout_ms(xfer,
1944                             &saf1761_otg_timeout, xfer->timeout);
1945                 }
1946         }
1947         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1948 }
1949
1950 static void
1951 saf1761_otg_root_intr(struct saf1761_otg_softc *sc)
1952 {
1953         DPRINTFN(9, "\n");
1954
1955         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1956
1957         /* set port bit - we only have one port */
1958         sc->sc_hub_idata[0] = 0x02;
1959
1960         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1961             sizeof(sc->sc_hub_idata));
1962 }
1963
1964 static usb_error_t
1965 saf1761_otg_standard_done_sub(struct usb_xfer *xfer)
1966 {
1967         struct saf1761_otg_td *td;
1968         uint32_t len;
1969         usb_error_t error;
1970
1971         DPRINTFN(9, "\n");
1972
1973         td = xfer->td_transfer_cache;
1974
1975         do {
1976                 len = td->remainder;
1977
1978                 /* store last data toggle */
1979                 xfer->endpoint->toggle_next = td->toggle;
1980
1981                 if (xfer->aframes != xfer->nframes) {
1982                         /*
1983                          * Verify the length and subtract
1984                          * the remainder from "frlengths[]":
1985                          */
1986                         if (len > xfer->frlengths[xfer->aframes]) {
1987                                 td->error_any = 1;
1988                         } else {
1989                                 xfer->frlengths[xfer->aframes] -= len;
1990                         }
1991                 }
1992                 /* Check for transfer error */
1993                 if (td->error_any) {
1994                         /* the transfer is finished */
1995                         error = (td->error_stall ?
1996                             USB_ERR_STALLED : USB_ERR_IOERROR);
1997                         td = NULL;
1998                         break;
1999                 }
2000                 /* Check for short transfer */
2001                 if (len > 0) {
2002                         if (xfer->flags_int.short_frames_ok ||
2003                             xfer->flags_int.isochronous_xfr) {
2004                                 /* follow alt next */
2005                                 if (td->alt_next) {
2006                                         td = td->obj_next;
2007                                 } else {
2008                                         td = NULL;
2009                                 }
2010                         } else {
2011                                 /* the transfer is finished */
2012                                 td = NULL;
2013                         }
2014                         error = 0;
2015                         break;
2016                 }
2017                 td = td->obj_next;
2018
2019                 /* this USB frame is complete */
2020                 error = 0;
2021                 break;
2022
2023         } while (0);
2024
2025         /* update transfer cache */
2026
2027         xfer->td_transfer_cache = td;
2028
2029         return (error);
2030 }
2031
2032 static void
2033 saf1761_otg_standard_done(struct usb_xfer *xfer)
2034 {
2035         usb_error_t err = 0;
2036
2037         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2038             xfer, xfer->endpoint);
2039
2040         /* reset scanner */
2041
2042         xfer->td_transfer_cache = xfer->td_transfer_first;
2043
2044         if (xfer->flags_int.control_xfr) {
2045
2046                 if (xfer->flags_int.control_hdr) {
2047
2048                         err = saf1761_otg_standard_done_sub(xfer);
2049                 }
2050                 xfer->aframes = 1;
2051
2052                 if (xfer->td_transfer_cache == NULL) {
2053                         goto done;
2054                 }
2055         }
2056         while (xfer->aframes != xfer->nframes) {
2057
2058                 err = saf1761_otg_standard_done_sub(xfer);
2059                 xfer->aframes++;
2060
2061                 if (xfer->td_transfer_cache == NULL) {
2062                         goto done;
2063                 }
2064         }
2065
2066         if (xfer->flags_int.control_xfr &&
2067             !xfer->flags_int.control_act) {
2068
2069                 err = saf1761_otg_standard_done_sub(xfer);
2070         }
2071 done:
2072         saf1761_otg_device_done(xfer, err);
2073 }
2074
2075 /*------------------------------------------------------------------------*
2076  *      saf1761_otg_device_done
2077  *
2078  * NOTE: this function can be called more than one time on the
2079  * same USB transfer!
2080  *------------------------------------------------------------------------*/
2081 static void
2082 saf1761_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
2083 {
2084         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2085
2086         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2087
2088         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2089             xfer, xfer->endpoint, error);
2090
2091         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2092
2093         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
2094                 saf1761_otg_intr_set(xfer, 0);
2095         } else {
2096                 struct saf1761_otg_td *td;
2097
2098                 td = xfer->td_transfer_cache;
2099
2100                 if (td != NULL)
2101                         saf1761_host_channel_free(sc, td);
2102         }
2103
2104         /* dequeue transfer and start next transfer */
2105         usbd_transfer_done(xfer, error);
2106
2107         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2108 }
2109
2110 static void
2111 saf1761_otg_xfer_stall(struct usb_xfer *xfer)
2112 {
2113         saf1761_otg_device_done(xfer, USB_ERR_STALLED);
2114 }
2115
2116 static void
2117 saf1761_otg_set_stall(struct usb_device *udev,
2118     struct usb_endpoint *ep, uint8_t *did_stall)
2119 {
2120         struct saf1761_otg_softc *sc;
2121         uint8_t ep_no;
2122         uint8_t ep_type;
2123         uint8_t ep_dir;
2124
2125         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2126
2127         /* check mode */
2128         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2129                 /* not supported */
2130                 return;
2131         }
2132
2133         DPRINTFN(5, "endpoint=%p\n", ep);
2134
2135         /* set STALL bit */
2136         sc = SAF1761_OTG_BUS2SC(udev->bus);
2137
2138         ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2139         ep_dir = (ep->edesc->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT));
2140         ep_type = (ep->edesc->bmAttributes & UE_XFERTYPE);
2141
2142         if (ep_type == UE_CONTROL) {
2143                 /* should not happen */
2144                 return;
2145         }
2146         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2147
2148         /* select the correct endpoint */
2149         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2150             (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2151             ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2152             SOTG_EP_INDEX_DIR_OUT));
2153
2154         /* set stall */
2155         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
2156
2157         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2158 }
2159
2160 static void
2161 saf1761_otg_clear_stall_sub_locked(struct saf1761_otg_softc *sc,
2162     uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2163 {
2164         if (ep_type == UE_CONTROL) {
2165                 /* clearing stall is not needed */
2166                 return;
2167         }
2168         /* select the correct endpoint */
2169         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2170             (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2171             ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2172             SOTG_EP_INDEX_DIR_OUT));
2173
2174         /* disable endpoint */
2175         SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, 0);
2176         /* enable endpoint again - will clear data toggle */
2177         SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, ep_type | SOTG_EP_TYPE_ENABLE);
2178
2179         /* clear buffer */
2180         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_CLBUF);
2181         /* clear stall */
2182         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
2183 }
2184
2185 static void
2186 saf1761_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
2187 {
2188         struct saf1761_otg_softc *sc;
2189         struct usb_endpoint_descriptor *ed;
2190
2191         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2192
2193         DPRINTFN(5, "endpoint=%p\n", ep);
2194
2195         /* check mode */
2196         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2197                 /* not supported */
2198                 return;
2199         }
2200         /* get softc */
2201         sc = SAF1761_OTG_BUS2SC(udev->bus);
2202
2203         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2204
2205         /* get endpoint descriptor */
2206         ed = ep->edesc;
2207
2208         /* reset endpoint */
2209         saf1761_otg_clear_stall_sub_locked(sc,
2210             (ed->bEndpointAddress & UE_ADDR),
2211             (ed->bmAttributes & UE_XFERTYPE),
2212             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
2213
2214         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2215 }
2216
2217 usb_error_t
2218 saf1761_otg_init(struct saf1761_otg_softc *sc)
2219 {
2220         const struct usb_hw_ep_profile *pf;
2221         uint32_t x;
2222
2223         DPRINTF("\n");
2224
2225         /* set up the bus structure */
2226         sc->sc_bus.usbrev = USB_REV_2_0;
2227         sc->sc_bus.methods = &saf1761_otg_bus_methods;
2228
2229         USB_BUS_LOCK(&sc->sc_bus);
2230
2231         /* Reset Host controller, including HW mode */
2232         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_ALL);
2233
2234         DELAY(1000);
2235
2236         /* Reset Host controller, including HW mode */
2237         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_HC);
2238
2239         /* wait a bit */
2240         DELAY(1000);
2241
2242         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, 0);
2243
2244         /* wait a bit */
2245         DELAY(1000);
2246
2247         /* Enable interrupts */
2248         sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN |
2249             SOTG_HW_MODE_CTRL_COMN_INT;
2250
2251         /* unlock device */
2252         SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE, SOTG_UNLOCK_DEVICE_CODE);
2253
2254         /*
2255          * Set correct hardware mode, must be written twice if bus
2256          * width is changed:
2257          */
2258         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2259         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2260
2261         SAF1761_WRITE_LE_4(sc, SOTG_DCSCRATCH, 0xdeadbeef);
2262         SAF1761_WRITE_LE_4(sc, SOTG_HCSCRATCH, 0xdeadbeef);
2263
2264         DPRINTF("DCID=0x%08x VEND_PROD=0x%08x HWMODE=0x%08x SCRATCH=0x%08x,0x%08x\n",
2265             SAF1761_READ_LE_4(sc, SOTG_DCCHIP_ID),
2266             SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID),
2267             SAF1761_READ_LE_4(sc, SOTG_HW_MODE_CTRL),
2268             SAF1761_READ_LE_4(sc, SOTG_DCSCRATCH),
2269             SAF1761_READ_LE_4(sc, SOTG_HCSCRATCH));
2270
2271         /* reset device controller */
2272         SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_SFRESET);
2273         SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2274
2275         /* wait a bit */
2276         DELAY(1000);
2277
2278         /* reset host controller */
2279         SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_HCRESET);
2280
2281         /* wait for reset to clear */
2282         for (x = 0; x != 10; x++) {
2283                 if ((SAF1761_READ_LE_4(sc, SOTG_USBCMD) & SOTG_USBCMD_HCRESET) == 0)
2284                         break;
2285                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
2286         }
2287
2288         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode |
2289             SOTG_HW_MODE_CTRL_ALL_ATX_RESET);
2290
2291         /* wait a bit */
2292         DELAY(1000);
2293
2294         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2295
2296         /* wait a bit */
2297         DELAY(1000);
2298
2299         /* do a pulldown */
2300         saf1761_otg_pull_down(sc);
2301
2302         /* wait 10ms for pulldown to stabilise */
2303         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2304
2305         for (x = 1;; x++) {
2306
2307                 saf1761_otg_get_hw_ep_profile(NULL, &pf, x);
2308                 if (pf == NULL)
2309                         break;
2310
2311                 /* select the correct endpoint */
2312                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2313                     (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2314                     SOTG_EP_INDEX_DIR_IN);
2315
2316                 /* select the maximum packet size */
2317                 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_in_frame_size);
2318
2319                 /* select the correct endpoint */
2320                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2321                     (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2322                     SOTG_EP_INDEX_DIR_OUT);
2323
2324                 /* select the maximum packet size */
2325                 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_out_frame_size);
2326         }
2327
2328         /* enable interrupts */
2329         SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_GLINTENA |
2330             SOTG_MODE_CLKAON | SOTG_MODE_WKUPCS);
2331
2332         sc->sc_interrupt_cfg |=
2333             SOTG_INTERRUPT_CFG_CDBGMOD |
2334             SOTG_INTERRUPT_CFG_DDBGMODIN |
2335             SOTG_INTERRUPT_CFG_DDBGMODOUT;
2336
2337         /* set default values */
2338         SAF1761_WRITE_LE_4(sc, SOTG_INTERRUPT_CFG, sc->sc_interrupt_cfg);
2339
2340         /* enable VBUS and ID interrupt */
2341         SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2342             SOTG_IRQ_ENABLE_CLR(0xFFFF));
2343         SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2344             SOTG_IRQ_ENABLE_SET(SOTG_IRQ_ID | SOTG_IRQ_VBUS_VLD));
2345
2346         /* enable interrupts */
2347         sc->sc_intr_enable = SOTG_DCINTERRUPT_IEVBUS |
2348             SOTG_DCINTERRUPT_IEBRST | SOTG_DCINTERRUPT_IESUSP;
2349         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
2350
2351         /*
2352          * Connect ATX port 1 to device controller, select external
2353          * charge pump and driver VBUS to +5V:
2354          */
2355         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2356             SOTG_CTRL_CLR(0xFFFF));
2357         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2358             SOTG_CTRL_SET(SOTG_CTRL_SW_SEL_HC_DC |
2359             SOTG_CTRL_BDIS_ACON_EN | SOTG_CTRL_SEL_CP_EXT |
2360             SOTG_CTRL_VBUS_DRV));
2361
2362         /* disable device address */
2363         SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, 0);
2364
2365         /* enable host controller clock and preserve reserved bits */
2366         x = SAF1761_READ_LE_4(sc, SOTG_POWER_DOWN);
2367         SAF1761_WRITE_LE_4(sc, SOTG_POWER_DOWN, x | SOTG_POWER_DOWN_HC_CLK_EN);
2368
2369         /* wait 10ms for clock */
2370         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2371
2372         /* enable configuration flag */
2373         SAF1761_WRITE_LE_4(sc, SOTG_CONFIGFLAG, SOTG_CONFIGFLAG_ENABLE);
2374
2375         /* clear RAM block */
2376         for (x = 0x400; x != 0x10000; x += 4)
2377                 SAF1761_WRITE_LE_4(sc, x, 0);
2378
2379         /* start the HC */
2380         SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_RS);
2381
2382         DPRINTF("USBCMD=0x%08x\n", SAF1761_READ_LE_4(sc, SOTG_USBCMD));
2383
2384         /* make HC scan all PTDs */
2385         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_LAST_PTD, (1 << 31));
2386         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_LAST_PTD, (1 << 31));
2387         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_LAST_PTD, (1 << 31));
2388
2389         /* skip all PTDs by default */
2390         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD, -1U);
2391         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD, -1U);
2392         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD, -1U);
2393
2394         /* activate all PTD types */
2395         SAF1761_WRITE_LE_4(sc, SOTG_HCBUFFERSTATUS,
2396             SOTG_HCBUFFERSTATUS_ISO_BUF_FILL |
2397             SOTG_HCBUFFERSTATUS_INT_BUF_FILL |
2398             SOTG_HCBUFFERSTATUS_ATL_BUF_FILL);
2399
2400         /* we don't use the AND mask */
2401         SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_AND, 0);
2402         SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_AND, 0);
2403         SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_AND, 0);
2404
2405         /* enable all PTD OR interrupts by default */
2406         SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_OR, -1U);
2407         SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_OR, -1U);
2408         SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_OR, -1U);
2409
2410         /* enable HC interrupts */
2411         SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT_ENABLE,
2412             SOTG_HCINTERRUPT_OTG_IRQ |
2413             SOTG_HCINTERRUPT_ISO_IRQ |
2414             SOTG_HCINTERRUPT_ALT_IRQ |
2415             SOTG_HCINTERRUPT_INT_IRQ);
2416
2417         /* poll initial VBUS status */
2418         saf1761_otg_update_vbus(sc);
2419
2420         USB_BUS_UNLOCK(&sc->sc_bus);
2421
2422         /* catch any lost interrupts */
2423
2424         saf1761_otg_do_poll(&sc->sc_bus);
2425
2426         return (0);                     /* success */
2427 }
2428
2429 void
2430 saf1761_otg_uninit(struct saf1761_otg_softc *sc)
2431 {
2432         USB_BUS_LOCK(&sc->sc_bus);
2433
2434         /* disable all interrupts */
2435         SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2436
2437         sc->sc_flags.port_powered = 0;
2438         sc->sc_flags.status_vbus = 0;
2439         sc->sc_flags.status_bus_reset = 0;
2440         sc->sc_flags.status_suspend = 0;
2441         sc->sc_flags.change_suspend = 0;
2442         sc->sc_flags.change_connect = 1;
2443
2444         saf1761_otg_pull_down(sc);
2445         USB_BUS_UNLOCK(&sc->sc_bus);
2446 }
2447
2448 static void
2449 saf1761_otg_suspend(struct saf1761_otg_softc *sc)
2450 {
2451         /* TODO */
2452 }
2453
2454 static void
2455 saf1761_otg_resume(struct saf1761_otg_softc *sc)
2456 {
2457         /* TODO */
2458 }
2459
2460 static void
2461 saf1761_otg_do_poll(struct usb_bus *bus)
2462 {
2463         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
2464
2465         USB_BUS_LOCK(&sc->sc_bus);
2466         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2467         saf1761_otg_interrupt_poll_locked(sc);
2468         saf1761_otg_interrupt_complete_locked(sc);
2469         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2470         USB_BUS_UNLOCK(&sc->sc_bus);
2471 }
2472
2473 /*------------------------------------------------------------------------*
2474  * saf1761_otg control support
2475  * saf1761_otg interrupt support
2476  * saf1761_otg bulk support
2477  *------------------------------------------------------------------------*/
2478 static void
2479 saf1761_otg_device_non_isoc_open(struct usb_xfer *xfer)
2480 {
2481         return;
2482 }
2483
2484 static void
2485 saf1761_otg_device_non_isoc_close(struct usb_xfer *xfer)
2486 {
2487         saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2488 }
2489
2490 static void
2491 saf1761_otg_device_non_isoc_enter(struct usb_xfer *xfer)
2492 {
2493         return;
2494 }
2495
2496 static void
2497 saf1761_otg_device_non_isoc_start(struct usb_xfer *xfer)
2498 {
2499         /* setup TDs */
2500         saf1761_otg_setup_standard_chain(xfer);
2501         saf1761_otg_start_standard_chain(xfer);
2502 }
2503
2504 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods =
2505 {
2506         .open = saf1761_otg_device_non_isoc_open,
2507         .close = saf1761_otg_device_non_isoc_close,
2508         .enter = saf1761_otg_device_non_isoc_enter,
2509         .start = saf1761_otg_device_non_isoc_start,
2510 };
2511
2512 /*------------------------------------------------------------------------*
2513  * saf1761_otg device side isochronous support
2514  *------------------------------------------------------------------------*/
2515 static void
2516 saf1761_otg_device_isoc_open(struct usb_xfer *xfer)
2517 {
2518         return;
2519 }
2520
2521 static void
2522 saf1761_otg_device_isoc_close(struct usb_xfer *xfer)
2523 {
2524         saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2525 }
2526
2527 static void
2528 saf1761_otg_device_isoc_enter(struct usb_xfer *xfer)
2529 {
2530         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2531         uint32_t temp;
2532         uint32_t nframes;
2533
2534         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2535             xfer, xfer->endpoint->isoc_next, xfer->nframes);
2536
2537         /* get the current frame index - we don't need the high bits */
2538
2539         nframes = SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM);
2540
2541         /*
2542          * check if the frame index is within the window where the
2543          * frames will be inserted
2544          */
2545         temp = (nframes - xfer->endpoint->isoc_next) & SOTG_FRAME_NUM_SOFR_MASK;
2546
2547         if ((xfer->endpoint->is_synced == 0) ||
2548             (temp < xfer->nframes)) {
2549                 /*
2550                  * If there is data underflow or the pipe queue is
2551                  * empty we schedule the transfer a few frames ahead
2552                  * of the current frame position. Else two isochronous
2553                  * transfers might overlap.
2554                  */
2555                 xfer->endpoint->isoc_next = (nframes + 3) & SOTG_FRAME_NUM_SOFR_MASK;
2556                 xfer->endpoint->is_synced = 1;
2557                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2558         }
2559         /*
2560          * compute how many milliseconds the insertion is ahead of the
2561          * current frame position:
2562          */
2563         temp = (xfer->endpoint->isoc_next - nframes) & SOTG_FRAME_NUM_SOFR_MASK;
2564
2565         /*
2566          * pre-compute when the isochronous transfer will be finished:
2567          */
2568         xfer->isoc_time_complete =
2569             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2570             xfer->nframes;
2571
2572         /* compute frame number for next insertion */
2573         xfer->endpoint->isoc_next += xfer->nframes;
2574
2575         /* setup TDs */
2576         saf1761_otg_setup_standard_chain(xfer);
2577 }
2578
2579 static void
2580 saf1761_otg_device_isoc_start(struct usb_xfer *xfer)
2581 {
2582         /* start TD chain */
2583         saf1761_otg_start_standard_chain(xfer);
2584 }
2585
2586 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods =
2587 {
2588         .open = saf1761_otg_device_isoc_open,
2589         .close = saf1761_otg_device_isoc_close,
2590         .enter = saf1761_otg_device_isoc_enter,
2591         .start = saf1761_otg_device_isoc_start,
2592 };
2593
2594 /*------------------------------------------------------------------------*
2595  * saf1761_otg host side isochronous support
2596  *------------------------------------------------------------------------*/
2597 static void
2598 saf1761_otg_host_isoc_open(struct usb_xfer *xfer)
2599 {
2600         return;
2601 }
2602
2603 static void
2604 saf1761_otg_host_isoc_close(struct usb_xfer *xfer)
2605 {
2606         saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2607 }
2608
2609 static void
2610 saf1761_otg_host_isoc_enter(struct usb_xfer *xfer)
2611 {
2612         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2613         uint32_t temp;
2614         uint32_t nframes;
2615
2616         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2617             xfer, xfer->endpoint->isoc_next, xfer->nframes);
2618
2619         /* get the current frame index - we don't need the high bits */
2620
2621         nframes = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) & SOTG_FRINDEX_MASK) >> 3;
2622
2623         /*
2624          * check if the frame index is within the window where the
2625          * frames will be inserted
2626          */
2627         temp = (nframes - xfer->endpoint->isoc_next) & (SOTG_FRINDEX_MASK >> 3);
2628
2629         if ((xfer->endpoint->is_synced == 0) ||
2630             (temp < xfer->nframes)) {
2631                 /*
2632                  * If there is data underflow or the pipe queue is
2633                  * empty we schedule the transfer a few frames ahead
2634                  * of the current frame position. Else two isochronous
2635                  * transfers might overlap.
2636                  */
2637                 xfer->endpoint->isoc_next = (nframes + 3) & (SOTG_FRINDEX_MASK >> 3);
2638                 xfer->endpoint->is_synced = 1;
2639                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2640         }
2641         /*
2642          * compute how many milliseconds the insertion is ahead of the
2643          * current frame position:
2644          */
2645         temp = (xfer->endpoint->isoc_next - nframes) & (SOTG_FRINDEX_MASK >> 3);
2646
2647         /*
2648          * pre-compute when the isochronous transfer will be finished:
2649          */
2650         xfer->isoc_time_complete =
2651             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2652             xfer->nframes;
2653
2654         /* compute frame number for next insertion */
2655         xfer->endpoint->isoc_next += xfer->nframes;
2656
2657         /* setup TDs */
2658         saf1761_otg_setup_standard_chain(xfer);
2659 }
2660
2661 static void
2662 saf1761_otg_host_isoc_start(struct usb_xfer *xfer)
2663 {
2664         /* start TD chain */
2665         saf1761_otg_start_standard_chain(xfer);
2666 }
2667
2668 static const struct usb_pipe_methods saf1761_otg_host_isoc_methods =
2669 {
2670         .open = saf1761_otg_host_isoc_open,
2671         .close = saf1761_otg_host_isoc_close,
2672         .enter = saf1761_otg_host_isoc_enter,
2673         .start = saf1761_otg_host_isoc_start,
2674 };
2675
2676 /*------------------------------------------------------------------------*
2677  * saf1761_otg root control support
2678  *------------------------------------------------------------------------*
2679  * Simulate a hardware HUB by handling all the necessary requests.
2680  *------------------------------------------------------------------------*/
2681
2682 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2683
2684 static const struct usb_device_descriptor saf1761_otg_devd = {
2685         .bLength = sizeof(struct usb_device_descriptor),
2686         .bDescriptorType = UDESC_DEVICE,
2687         HSETW(.idVendor, 0x04cc),
2688         HSETW(.idProduct, 0x1761),
2689         .bcdUSB = {0x00, 0x02},
2690         .bDeviceClass = UDCLASS_HUB,
2691         .bDeviceSubClass = UDSUBCLASS_HUB,
2692         .bDeviceProtocol = UDPROTO_FSHUB,
2693         .bMaxPacketSize = 64,
2694         .bcdDevice = {0x00, 0x01},
2695         .iManufacturer = 1,
2696         .iProduct = 2,
2697         .bNumConfigurations = 1,
2698 };
2699
2700 static const struct usb_device_qualifier saf1761_otg_odevd = {
2701         .bLength = sizeof(struct usb_device_qualifier),
2702         .bDescriptorType = UDESC_DEVICE_QUALIFIER,
2703         .bcdUSB = {0x00, 0x02},
2704         .bDeviceClass = UDCLASS_HUB,
2705         .bDeviceSubClass = UDSUBCLASS_HUB,
2706         .bDeviceProtocol = UDPROTO_FSHUB,
2707         .bMaxPacketSize0 = 0,
2708         .bNumConfigurations = 0,
2709 };
2710
2711 static const struct saf1761_otg_config_desc saf1761_otg_confd = {
2712         .confd = {
2713                 .bLength = sizeof(struct usb_config_descriptor),
2714                 .bDescriptorType = UDESC_CONFIG,
2715                 .wTotalLength[0] = sizeof(saf1761_otg_confd),
2716                 .bNumInterface = 1,
2717                 .bConfigurationValue = 1,
2718                 .iConfiguration = 0,
2719                 .bmAttributes = UC_SELF_POWERED,
2720                 .bMaxPower = 0,
2721         },
2722         .ifcd = {
2723                 .bLength = sizeof(struct usb_interface_descriptor),
2724                 .bDescriptorType = UDESC_INTERFACE,
2725                 .bNumEndpoints = 1,
2726                 .bInterfaceClass = UICLASS_HUB,
2727                 .bInterfaceSubClass = UISUBCLASS_HUB,
2728                 .bInterfaceProtocol = 0,
2729         },
2730
2731         .endpd = {
2732                 .bLength = sizeof(struct usb_endpoint_descriptor),
2733                 .bDescriptorType = UDESC_ENDPOINT,
2734                 .bEndpointAddress = (UE_DIR_IN | SAF1761_OTG_INTR_ENDPT),
2735                 .bmAttributes = UE_INTERRUPT,
2736                 .wMaxPacketSize[0] = 8,
2737                 .bInterval = 255,
2738         },
2739 };
2740
2741 static const struct usb_hub_descriptor_min saf1761_otg_hubd = {
2742         .bDescLength = sizeof(saf1761_otg_hubd),
2743         .bDescriptorType = UDESC_HUB,
2744         .bNbrPorts = SOTG_NUM_PORTS,
2745         HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
2746         .bPwrOn2PwrGood = 50,
2747         .bHubContrCurrent = 0,
2748         .DeviceRemovable = {0},         /* port is removable */
2749 };
2750
2751 #define STRING_VENDOR \
2752   "N\0X\0P"
2753
2754 #define STRING_PRODUCT \
2755   "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
2756
2757 USB_MAKE_STRING_DESC(STRING_VENDOR, saf1761_otg_vendor);
2758 USB_MAKE_STRING_DESC(STRING_PRODUCT, saf1761_otg_product);
2759
2760 static usb_error_t
2761 saf1761_otg_roothub_exec(struct usb_device *udev,
2762     struct usb_device_request *req, const void **pptr, uint16_t *plength)
2763 {
2764         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(udev->bus);
2765         const void *ptr;
2766         uint16_t len;
2767         uint16_t value;
2768         uint16_t index;
2769         uint32_t temp;
2770         uint32_t i;
2771         usb_error_t err;
2772
2773         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2774
2775         /* buffer reset */
2776         ptr = (const void *)&sc->sc_hub_temp;
2777         len = 0;
2778         err = 0;
2779
2780         value = UGETW(req->wValue);
2781         index = UGETW(req->wIndex);
2782
2783         /* demultiplex the control request */
2784
2785         switch (req->bmRequestType) {
2786         case UT_READ_DEVICE:
2787                 switch (req->bRequest) {
2788                 case UR_GET_DESCRIPTOR:
2789                         goto tr_handle_get_descriptor;
2790                 case UR_GET_CONFIG:
2791                         goto tr_handle_get_config;
2792                 case UR_GET_STATUS:
2793                         goto tr_handle_get_status;
2794                 default:
2795                         goto tr_stalled;
2796                 }
2797                 break;
2798
2799         case UT_WRITE_DEVICE:
2800                 switch (req->bRequest) {
2801                 case UR_SET_ADDRESS:
2802                         goto tr_handle_set_address;
2803                 case UR_SET_CONFIG:
2804                         goto tr_handle_set_config;
2805                 case UR_CLEAR_FEATURE:
2806                         goto tr_valid;  /* nop */
2807                 case UR_SET_DESCRIPTOR:
2808                         goto tr_valid;  /* nop */
2809                 case UR_SET_FEATURE:
2810                 default:
2811                         goto tr_stalled;
2812                 }
2813                 break;
2814
2815         case UT_WRITE_ENDPOINT:
2816                 switch (req->bRequest) {
2817                 case UR_CLEAR_FEATURE:
2818                         switch (UGETW(req->wValue)) {
2819                         case UF_ENDPOINT_HALT:
2820                                 goto tr_handle_clear_halt;
2821                         case UF_DEVICE_REMOTE_WAKEUP:
2822                                 goto tr_handle_clear_wakeup;
2823                         default:
2824                                 goto tr_stalled;
2825                         }
2826                         break;
2827                 case UR_SET_FEATURE:
2828                         switch (UGETW(req->wValue)) {
2829                         case UF_ENDPOINT_HALT:
2830                                 goto tr_handle_set_halt;
2831                         case UF_DEVICE_REMOTE_WAKEUP:
2832                                 goto tr_handle_set_wakeup;
2833                         default:
2834                                 goto tr_stalled;
2835                         }
2836                         break;
2837                 case UR_SYNCH_FRAME:
2838                         goto tr_valid;  /* nop */
2839                 default:
2840                         goto tr_stalled;
2841                 }
2842                 break;
2843
2844         case UT_READ_ENDPOINT:
2845                 switch (req->bRequest) {
2846                 case UR_GET_STATUS:
2847                         goto tr_handle_get_ep_status;
2848                 default:
2849                         goto tr_stalled;
2850                 }
2851                 break;
2852
2853         case UT_WRITE_INTERFACE:
2854                 switch (req->bRequest) {
2855                 case UR_SET_INTERFACE:
2856                         goto tr_handle_set_interface;
2857                 case UR_CLEAR_FEATURE:
2858                         goto tr_valid;  /* nop */
2859                 case UR_SET_FEATURE:
2860                 default:
2861                         goto tr_stalled;
2862                 }
2863                 break;
2864
2865         case UT_READ_INTERFACE:
2866                 switch (req->bRequest) {
2867                 case UR_GET_INTERFACE:
2868                         goto tr_handle_get_interface;
2869                 case UR_GET_STATUS:
2870                         goto tr_handle_get_iface_status;
2871                 default:
2872                         goto tr_stalled;
2873                 }
2874                 break;
2875
2876         case UT_WRITE_CLASS_INTERFACE:
2877         case UT_WRITE_VENDOR_INTERFACE:
2878                 /* XXX forward */
2879                 break;
2880
2881         case UT_READ_CLASS_INTERFACE:
2882         case UT_READ_VENDOR_INTERFACE:
2883                 /* XXX forward */
2884                 break;
2885
2886         case UT_WRITE_CLASS_DEVICE:
2887                 switch (req->bRequest) {
2888                 case UR_CLEAR_FEATURE:
2889                         goto tr_valid;
2890                 case UR_SET_DESCRIPTOR:
2891                 case UR_SET_FEATURE:
2892                         break;
2893                 default:
2894                         goto tr_stalled;
2895                 }
2896                 break;
2897
2898         case UT_WRITE_CLASS_OTHER:
2899                 switch (req->bRequest) {
2900                 case UR_CLEAR_FEATURE:
2901                         if (index == SOTG_HOST_PORT_NUM)
2902                                 goto tr_handle_clear_port_feature_host;
2903                         else if (index == SOTG_DEVICE_PORT_NUM)
2904                                 goto tr_handle_clear_port_feature_device;
2905                         else
2906                                 goto tr_stalled;
2907                 case UR_SET_FEATURE:
2908                         if (index == SOTG_HOST_PORT_NUM)
2909                                 goto tr_handle_set_port_feature_host;
2910                         else if (index == SOTG_DEVICE_PORT_NUM)
2911                                 goto tr_handle_set_port_feature_device;
2912                         else
2913                                 goto tr_stalled;
2914                 case UR_CLEAR_TT_BUFFER:
2915                 case UR_RESET_TT:
2916                 case UR_STOP_TT:
2917                         goto tr_valid;
2918
2919                 default:
2920                         goto tr_stalled;
2921                 }
2922                 break;
2923
2924         case UT_READ_CLASS_OTHER:
2925                 switch (req->bRequest) {
2926                 case UR_GET_TT_STATE:
2927                         goto tr_handle_get_tt_state;
2928                 case UR_GET_STATUS:
2929                         if (index == SOTG_HOST_PORT_NUM)
2930                                 goto tr_handle_get_port_status_host;
2931                         else if (index == SOTG_DEVICE_PORT_NUM)
2932                                 goto tr_handle_get_port_status_device;
2933                         else
2934                                 goto tr_stalled;
2935                 default:
2936                         goto tr_stalled;
2937                 }
2938                 break;
2939
2940         case UT_READ_CLASS_DEVICE:
2941                 switch (req->bRequest) {
2942                 case UR_GET_DESCRIPTOR:
2943                         goto tr_handle_get_class_descriptor;
2944                 case UR_GET_STATUS:
2945                         goto tr_handle_get_class_status;
2946
2947                 default:
2948                         goto tr_stalled;
2949                 }
2950                 break;
2951         default:
2952                 goto tr_stalled;
2953         }
2954         goto tr_valid;
2955
2956 tr_handle_get_descriptor:
2957         switch (value >> 8) {
2958         case UDESC_DEVICE:
2959                 if (value & 0xff)
2960                         goto tr_stalled;
2961                 len = sizeof(saf1761_otg_devd);
2962                 ptr = (const void *)&saf1761_otg_devd;
2963                 goto tr_valid;
2964         case UDESC_DEVICE_QUALIFIER:
2965                 if (value & 0xff)
2966                         goto tr_stalled;
2967                 len = sizeof(saf1761_otg_odevd);
2968                 ptr = (const void *)&saf1761_otg_odevd;
2969                 goto tr_valid;
2970         case UDESC_CONFIG:
2971                 if (value & 0xff)
2972                         goto tr_stalled;
2973                 len = sizeof(saf1761_otg_confd);
2974                 ptr = (const void *)&saf1761_otg_confd;
2975                 goto tr_valid;
2976         case UDESC_STRING:
2977                 switch (value & 0xff) {
2978                 case 0:         /* Language table */
2979                         len = sizeof(usb_string_lang_en);
2980                         ptr = (const void *)&usb_string_lang_en;
2981                         goto tr_valid;
2982
2983                 case 1:         /* Vendor */
2984                         len = sizeof(saf1761_otg_vendor);
2985                         ptr = (const void *)&saf1761_otg_vendor;
2986                         goto tr_valid;
2987
2988                 case 2:         /* Product */
2989                         len = sizeof(saf1761_otg_product);
2990                         ptr = (const void *)&saf1761_otg_product;
2991                         goto tr_valid;
2992                 default:
2993                         break;
2994                 }
2995                 break;
2996         default:
2997                 goto tr_stalled;
2998         }
2999         goto tr_stalled;
3000
3001 tr_handle_get_config:
3002         len = 1;
3003         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3004         goto tr_valid;
3005
3006 tr_handle_get_status:
3007         len = 2;
3008         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3009         goto tr_valid;
3010
3011 tr_handle_set_address:
3012         if (value & 0xFF00)
3013                 goto tr_stalled;
3014
3015         sc->sc_rt_addr = value;
3016         goto tr_valid;
3017
3018 tr_handle_set_config:
3019         if (value >= 2)
3020                 goto tr_stalled;
3021         sc->sc_conf = value;
3022         goto tr_valid;
3023
3024 tr_handle_get_interface:
3025         len = 1;
3026         sc->sc_hub_temp.wValue[0] = 0;
3027         goto tr_valid;
3028
3029 tr_handle_get_tt_state:
3030 tr_handle_get_class_status:
3031 tr_handle_get_iface_status:
3032 tr_handle_get_ep_status:
3033         len = 2;
3034         USETW(sc->sc_hub_temp.wValue, 0);
3035         goto tr_valid;
3036
3037 tr_handle_set_halt:
3038 tr_handle_set_interface:
3039 tr_handle_set_wakeup:
3040 tr_handle_clear_wakeup:
3041 tr_handle_clear_halt:
3042         goto tr_valid;
3043
3044 tr_handle_clear_port_feature_device:
3045         DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
3046
3047         switch (value) {
3048         case UHF_PORT_SUSPEND:
3049                 saf1761_otg_wakeup_peer(sc);
3050                 break;
3051
3052         case UHF_PORT_ENABLE:
3053                 sc->sc_flags.port_enabled = 0;
3054                 break;
3055
3056         case UHF_PORT_TEST:
3057         case UHF_PORT_INDICATOR:
3058         case UHF_C_PORT_ENABLE:
3059         case UHF_C_PORT_OVER_CURRENT:
3060         case UHF_C_PORT_RESET:
3061                 /* nops */
3062                 break;
3063         case UHF_PORT_POWER:
3064                 sc->sc_flags.port_powered = 0;
3065                 saf1761_otg_pull_down(sc);
3066                 break;
3067         case UHF_C_PORT_CONNECTION:
3068                 sc->sc_flags.change_connect = 0;
3069                 break;
3070         case UHF_C_PORT_SUSPEND:
3071                 sc->sc_flags.change_suspend = 0;
3072                 break;
3073         default:
3074                 err = USB_ERR_IOERROR;
3075                 goto tr_valid;
3076         }
3077         goto tr_valid;
3078
3079 tr_handle_clear_port_feature_host:
3080         DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
3081
3082         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3083
3084         switch (value) {
3085         case UHF_PORT_ENABLE:
3086                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PED);
3087                 break;
3088         case UHF_PORT_SUSPEND:
3089                 if ((temp & SOTG_PORTSC1_SUSP) && (!(temp & SOTG_PORTSC1_FPR)))
3090                         SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_FPR);
3091
3092                 /* wait 20ms for resume sequence to complete */
3093                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3094
3095                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~(SOTG_PORTSC1_SUSP |
3096                     SOTG_PORTSC1_FPR | SOTG_PORTSC1_LS /* High Speed */ ));
3097
3098                 /* 4ms settle time */
3099                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3100                 break;
3101         case UHF_PORT_INDICATOR:
3102                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PIC);
3103                 break;
3104         case UHF_PORT_TEST:
3105         case UHF_C_PORT_ENABLE:
3106         case UHF_C_PORT_OVER_CURRENT:
3107         case UHF_C_PORT_RESET:
3108         case UHF_C_PORT_SUSPEND:
3109                 /* NOPs */
3110                 break;
3111         case UHF_PORT_POWER:
3112                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PP);
3113                 break;
3114         case UHF_C_PORT_CONNECTION:
3115                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_ECSC);
3116                 break;
3117         default:
3118                 err = USB_ERR_IOERROR;
3119                 goto tr_valid;
3120         }
3121         goto tr_valid;
3122
3123 tr_handle_set_port_feature_device:
3124         DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
3125
3126         switch (value) {
3127         case UHF_PORT_ENABLE:
3128                 sc->sc_flags.port_enabled = 1;
3129                 break;
3130         case UHF_PORT_SUSPEND:
3131         case UHF_PORT_RESET:
3132         case UHF_PORT_TEST:
3133         case UHF_PORT_INDICATOR:
3134                 /* nops */
3135                 break;
3136         case UHF_PORT_POWER:
3137                 sc->sc_flags.port_powered = 1;
3138                 break;
3139         default:
3140                 err = USB_ERR_IOERROR;
3141                 goto tr_valid;
3142         }
3143         goto tr_valid;
3144
3145 tr_handle_set_port_feature_host:
3146         DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
3147
3148         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3149
3150         switch (value) {
3151         case UHF_PORT_ENABLE:
3152                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PED);
3153                 break;
3154         case UHF_PORT_SUSPEND:
3155                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_SUSP);
3156                 break;
3157         case UHF_PORT_RESET:
3158                 DPRINTFN(6, "reset port %d\n", index);
3159
3160                 /* Start reset sequence. */
3161                 temp &= ~(SOTG_PORTSC1_PED | SOTG_PORTSC1_PR);
3162
3163                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PR);
3164
3165                 /* Wait for reset to complete. */
3166                 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3167                     USB_MS_TO_TICKS(usb_port_root_reset_delay));
3168
3169                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp);
3170
3171                 /* Wait for HC to complete reset. */
3172                 usb_pause_mtx(&sc->sc_bus.bus_mtx, USB_MS_TO_TICKS(2));
3173
3174                 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3175
3176                 DPRINTF("After reset, status=0x%08x\n", temp);
3177                 if (temp & SOTG_PORTSC1_PR) {
3178                         device_printf(sc->sc_bus.bdev, "port reset timeout\n");
3179                         err = USB_ERR_TIMEOUT;
3180                         goto tr_valid;
3181                 }
3182                 if (!(temp & SOTG_PORTSC1_PED)) {
3183                         /* Not a high speed device, give up ownership.*/
3184                         SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PO);
3185                         break;
3186                 }
3187                 sc->sc_isreset = 1;
3188                 DPRINTF("port %d reset, status = 0x%08x\n", index, temp);
3189                 break;
3190         case UHF_PORT_POWER:
3191                 DPRINTFN(3, "set port power %d\n", index);
3192                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PP);
3193                 break;
3194
3195         case UHF_PORT_TEST:
3196                 DPRINTFN(3, "set port test %d\n", index);
3197                 break;
3198
3199         case UHF_PORT_INDICATOR:
3200                 DPRINTFN(3, "set port ind %d\n", index);
3201                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PIC);
3202                 break;
3203         default:
3204                 err = USB_ERR_IOERROR;
3205                 goto tr_valid;
3206         }
3207         goto tr_valid;
3208
3209 tr_handle_get_port_status_device:
3210
3211         DPRINTFN(9, "UR_GET_PORT_STATUS on port %d\n", index);
3212
3213         if (sc->sc_flags.status_vbus) {
3214                 saf1761_otg_pull_up(sc);
3215         } else {
3216                 saf1761_otg_pull_down(sc);
3217         }
3218
3219         /* Select FULL-speed and Device Side Mode */
3220
3221         value = UPS_PORT_MODE_DEVICE;
3222
3223         if (sc->sc_flags.port_powered)
3224                 value |= UPS_PORT_POWER;
3225
3226         if (sc->sc_flags.port_enabled)
3227                 value |= UPS_PORT_ENABLED;
3228
3229         if (sc->sc_flags.status_vbus &&
3230             sc->sc_flags.status_bus_reset)
3231                 value |= UPS_CURRENT_CONNECT_STATUS;
3232
3233         if (sc->sc_flags.status_suspend)
3234                 value |= UPS_SUSPEND;
3235
3236         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
3237
3238         value = 0;
3239
3240         if (sc->sc_flags.change_connect)
3241                 value |= UPS_C_CONNECT_STATUS;
3242
3243         if (sc->sc_flags.change_suspend)
3244                 value |= UPS_C_SUSPEND;
3245
3246         USETW(sc->sc_hub_temp.ps.wPortChange, value);
3247         len = sizeof(sc->sc_hub_temp.ps);
3248         goto tr_valid;
3249
3250 tr_handle_get_port_status_host:
3251
3252         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3253
3254         DPRINTFN(9, "UR_GET_PORT_STATUS on port %d = 0x%08x\n", index, temp);
3255
3256         i = UPS_HIGH_SPEED;
3257
3258         if (temp & SOTG_PORTSC1_ECCS)
3259                 i |= UPS_CURRENT_CONNECT_STATUS;
3260         if (temp & SOTG_PORTSC1_PED)
3261                 i |= UPS_PORT_ENABLED;
3262         if ((temp & SOTG_PORTSC1_SUSP) && !(temp & SOTG_PORTSC1_FPR))
3263                 i |= UPS_SUSPEND;
3264         if (temp & SOTG_PORTSC1_PR)
3265                 i |= UPS_RESET;
3266         if (temp & SOTG_PORTSC1_PP)
3267                 i |= UPS_PORT_POWER;
3268
3269         USETW(sc->sc_hub_temp.ps.wPortStatus, i);
3270         i = 0;
3271
3272         if (temp & SOTG_PORTSC1_ECSC)
3273                 i |= UPS_C_CONNECT_STATUS;
3274         if (temp & SOTG_PORTSC1_FPR)
3275                 i |= UPS_C_SUSPEND;
3276         if (sc->sc_isreset)
3277                 i |= UPS_C_PORT_RESET;
3278         USETW(sc->sc_hub_temp.ps.wPortChange, i);
3279         len = sizeof(sc->sc_hub_temp.ps);
3280         goto tr_valid;
3281
3282 tr_handle_get_class_descriptor:
3283         if (value & 0xFF)
3284                 goto tr_stalled;
3285         ptr = (const void *)&saf1761_otg_hubd;
3286         len = sizeof(saf1761_otg_hubd);
3287         goto tr_valid;
3288
3289 tr_stalled:
3290         err = USB_ERR_STALLED;
3291 tr_valid:
3292         *plength = len;
3293         *pptr = ptr;
3294         return (err);
3295 }
3296
3297 static void
3298 saf1761_otg_xfer_setup(struct usb_setup_params *parm)
3299 {
3300         struct saf1761_otg_softc *sc;
3301         struct usb_xfer *xfer;
3302         void *last_obj;
3303         uint32_t dw1;
3304         uint32_t ntd;
3305         uint32_t n;
3306         uint8_t ep_no;
3307         uint8_t ep_type;
3308
3309         sc = SAF1761_OTG_BUS2SC(parm->udev->bus);
3310         xfer = parm->curr_xfer;
3311
3312         /*
3313          * NOTE: This driver does not use any of the parameters that
3314          * are computed from the following values. Just set some
3315          * reasonable dummies:
3316          */
3317         parm->hc_max_packet_size = 0x500;
3318         parm->hc_max_packet_count = 1;
3319         parm->hc_max_frame_size = 0x500;
3320
3321         usbd_transfer_setup_sub(parm);
3322
3323         /*
3324          * Compute maximum number of TDs:
3325          */
3326         ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
3327
3328         if (ep_type == UE_CONTROL) {
3329
3330                 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
3331
3332         } else {
3333                 ntd = xfer->nframes + 1 /* SYNC */ ;
3334         }
3335
3336         /*
3337          * check if "usbd_transfer_setup_sub" set an error
3338          */
3339         if (parm->err)
3340                 return;
3341
3342         /*
3343          * allocate transfer descriptors
3344          */
3345         last_obj = NULL;
3346
3347         ep_no = xfer->endpointno & UE_ADDR;
3348
3349         /*
3350          * Check profile stuff
3351          */
3352         if (parm->udev->flags.usb_mode == USB_MODE_DEVICE) {
3353                 const struct usb_hw_ep_profile *pf;
3354
3355                 saf1761_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
3356
3357                 if (pf == NULL) {
3358                         /* should not happen */
3359                         parm->err = USB_ERR_INVAL;
3360                         return;
3361                 }
3362         }
3363
3364         dw1 = (xfer->address << 3) | (ep_type << 12);
3365
3366         switch (parm->udev->speed) {
3367         case USB_SPEED_FULL:
3368         case USB_SPEED_LOW:
3369                 /* check if root HUB port is running High Speed */
3370                 if (parm->udev->parent_hs_hub != NULL) {
3371                         dw1 |= SOTG_PTD_DW1_ENABLE_SPLIT;
3372                         dw1 |= (parm->udev->hs_port_no << 18);
3373                         dw1 |= (parm->udev->hs_hub_addr << 25);
3374                         if (parm->udev->speed == USB_SPEED_LOW)
3375                                 dw1 |= (1 << 17);
3376                 }
3377                 break;
3378         default:
3379                 break;
3380         }
3381
3382         /* align data */
3383         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
3384
3385         for (n = 0; n != ntd; n++) {
3386
3387                 struct saf1761_otg_td *td;
3388
3389                 if (parm->buf) {
3390
3391                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
3392
3393                         /* init TD */
3394                         td->max_packet_size = xfer->max_packet_size;
3395                         td->ep_index = ep_no;
3396                         td->ep_type = ep_type;
3397                         td->dw1_value = dw1;
3398                         if (ep_type == UE_ISOCHRONOUS) {
3399                                 if (parm->udev->speed == USB_SPEED_HIGH) {
3400                                         uint8_t uframe_index = (ntd - 1 - n);
3401                                         uframe_index <<= usbd_xfer_get_fps_shift(xfer);
3402                                         td->uframe = (uframe_index & 7);
3403                                 } else {
3404                                         td->uframe = 0;
3405                                 }
3406                         } else {
3407                                 td->uframe = 0;
3408                         }
3409                         if (ep_type == UE_INTERRUPT) {
3410                                 if (xfer->interval > 32)
3411                                         td->interval = (32 / 2) << 3;
3412                                 else
3413                                         td->interval = (xfer->interval / 2) << 3;
3414                         } else {
3415                                 td->interval = 0;
3416                         }
3417                         td->obj_next = last_obj;
3418
3419                         last_obj = td;
3420                 }
3421                 parm->size[0] += sizeof(*td);
3422         }
3423
3424         xfer->td_start[0] = last_obj;
3425 }
3426
3427 static void
3428 saf1761_otg_xfer_unsetup(struct usb_xfer *xfer)
3429 {
3430 }
3431
3432 static void
3433 saf1761_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3434     struct usb_endpoint *ep)
3435 {
3436         uint16_t mps;
3437
3438         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3439             ep, udev->address,
3440             edesc->bEndpointAddress, udev->flags.usb_mode);
3441
3442         if (udev->parent_hub == NULL) {
3443                 /* root HUB has special endpoint handling */
3444                 return;
3445         }
3446
3447         /* Verify wMaxPacketSize */
3448         mps = UGETW(edesc->wMaxPacketSize);
3449         if (udev->speed == USB_SPEED_HIGH) {
3450                 if ((mps >> 11) & 3) {
3451                         DPRINTF("A packet multiplier different from "
3452                             "1 is not supported\n");
3453                         return;
3454                 }
3455         }
3456         if (mps > SOTG_HS_MAX_PACKET_SIZE) {
3457                 DPRINTF("Packet size %d bigger than %d\n",
3458                     (int)mps, SOTG_HS_MAX_PACKET_SIZE);
3459                 return;
3460         }
3461         if (udev->flags.usb_mode == USB_MODE_DEVICE) {
3462                 if (udev->speed != USB_SPEED_FULL &&
3463                     udev->speed != USB_SPEED_HIGH) {
3464                         /* not supported */
3465                         return;
3466                 }
3467                 switch (edesc->bmAttributes & UE_XFERTYPE) {
3468                 case UE_ISOCHRONOUS:
3469                         ep->methods = &saf1761_otg_device_isoc_methods;
3470                         break;
3471                 default:
3472                         ep->methods = &saf1761_otg_non_isoc_methods;
3473                         break;
3474                 }
3475         } else {
3476                 switch (edesc->bmAttributes & UE_XFERTYPE) {
3477                 case UE_ISOCHRONOUS:
3478                         ep->methods = &saf1761_otg_host_isoc_methods;
3479                         break;
3480                 default:
3481                         ep->methods = &saf1761_otg_non_isoc_methods;
3482                         break;
3483                 }
3484         }
3485 }
3486
3487 static void
3488 saf1761_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3489 {
3490         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
3491
3492         switch (state) {
3493         case USB_HW_POWER_SUSPEND:
3494                 saf1761_otg_suspend(sc);
3495                 break;
3496         case USB_HW_POWER_SHUTDOWN:
3497                 saf1761_otg_uninit(sc);
3498                 break;
3499         case USB_HW_POWER_RESUME:
3500                 saf1761_otg_resume(sc);
3501                 break;
3502         default:
3503                 break;
3504         }
3505 }
3506
3507 static void
3508 saf1761_otg_device_resume(struct usb_device *udev)
3509 {
3510         struct saf1761_otg_softc *sc;
3511         struct saf1761_otg_td *td;
3512         struct usb_xfer *xfer;
3513         uint8_t x;
3514
3515         DPRINTF("\n");
3516
3517         if (udev->flags.usb_mode != USB_MODE_HOST)
3518                 return;
3519
3520         sc = SAF1761_OTG_BUS2SC(udev->bus);
3521
3522         USB_BUS_LOCK(&sc->sc_bus);
3523         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3524
3525         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3526
3527                 if (xfer->xroot->udev != udev)
3528                         continue;
3529
3530                 td = xfer->td_transfer_cache;
3531                 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3532                         continue;
3533
3534                 switch (td->ep_type) {
3535                 case UE_INTERRUPT:
3536                         x = td->channel - 32;
3537                         sc->sc_host_intr_suspend_map &= ~(1 << x);
3538                         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3539                             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3540                         break;
3541                 case UE_ISOCHRONOUS:
3542                         x = td->channel;
3543                         sc->sc_host_isoc_suspend_map &= ~(1 << x);
3544                         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3545                             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3546                         break;
3547                 default:
3548                         x = td->channel - 64;
3549                         sc->sc_host_async_suspend_map &= ~(1 << x);
3550                         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3551                             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3552                         break;
3553                 }
3554         }
3555
3556         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3557         USB_BUS_UNLOCK(&sc->sc_bus);
3558
3559         /* poll all transfers again to restart resumed ones */
3560         saf1761_otg_do_poll(&sc->sc_bus);
3561 }
3562
3563 static void
3564 saf1761_otg_device_suspend(struct usb_device *udev)
3565 {
3566         struct saf1761_otg_softc *sc;
3567         struct saf1761_otg_td *td;
3568         struct usb_xfer *xfer;
3569         uint8_t x;
3570
3571         DPRINTF("\n");
3572
3573         if (udev->flags.usb_mode != USB_MODE_HOST)
3574                 return;
3575
3576         sc = SAF1761_OTG_BUS2SC(udev->bus);
3577
3578         USB_BUS_LOCK(&sc->sc_bus);
3579         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3580
3581         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3582
3583                 if (xfer->xroot->udev != udev)
3584                         continue;
3585
3586                 td = xfer->td_transfer_cache;
3587                 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3588                         continue;
3589
3590                 switch (td->ep_type) {
3591                 case UE_INTERRUPT:
3592                         x = td->channel - 32;
3593                         sc->sc_host_intr_suspend_map |= (1 << x);
3594                         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3595                             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3596                         break;
3597                 case UE_ISOCHRONOUS:
3598                         x = td->channel;
3599                         sc->sc_host_isoc_suspend_map |= (1 << x);
3600                         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3601                             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3602                         break;
3603                 default:
3604                         x = td->channel - 64;
3605                         sc->sc_host_async_suspend_map |= (1 << x);
3606                         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3607                             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3608                         break;
3609                 }
3610         }
3611
3612         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3613         USB_BUS_UNLOCK(&sc->sc_bus);
3614 }
3615
3616 static const struct usb_bus_methods saf1761_otg_bus_methods =
3617 {
3618         .endpoint_init = &saf1761_otg_ep_init,
3619         .xfer_setup = &saf1761_otg_xfer_setup,
3620         .xfer_unsetup = &saf1761_otg_xfer_unsetup,
3621         .get_hw_ep_profile = &saf1761_otg_get_hw_ep_profile,
3622         .xfer_stall = &saf1761_otg_xfer_stall,
3623         .set_stall = &saf1761_otg_set_stall,
3624         .clear_stall = &saf1761_otg_clear_stall,
3625         .roothub_exec = &saf1761_otg_roothub_exec,
3626         .xfer_poll = &saf1761_otg_do_poll,
3627         .set_hw_power_sleep = saf1761_otg_set_hw_power_sleep,
3628         .device_resume = &saf1761_otg_device_resume,
3629         .device_suspend = &saf1761_otg_device_suspend,
3630 };