sys/dev/usb/controller/saf1761_otg.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
   4  * All rights reserved.
   5  *
   6  * This software was developed by SRI International and the University of
   7  * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
   8  * ("CTSRD"), as part of the DARPA CRASH research programme.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * This file contains the driver for the SAF1761 series USB OTG
  34  * controller.
  35  *
  36  * Datasheet is available from:
  37  * http://www.nxp.com/products/automotive/multimedia/usb/SAF1761BE.html
  38  */
  39
  40 #ifdef USB_GLOBAL_INCLUDE_FILE
  41 #include USB_GLOBAL_INCLUDE_FILE
  42 #else
  43 #include <sys/stdint.h>
  44 #include <sys/stddef.h>
  45 #include <sys/param.h>
  46 #include <sys/queue.h>
  47 #include <sys/types.h>
  48 #include <sys/systm.h>
  49 #include <sys/kernel.h>
  50 #include <sys/bus.h>
  51 #include <sys/module.h>
  52 #include <sys/lock.h>
  53 #include <sys/mutex.h>
  54 #include <sys/condvar.h>
  55 #include <sys/sysctl.h>
  56 #include <sys/sx.h>
  57 #include <sys/unistd.h>
  58 #include <sys/callout.h>
  59 #include <sys/malloc.h>
  60 #include <sys/priv.h>
  61 #include <sys/libkern.h>
  62
  63 #include <dev/usb/usb.h>
  64 #include <dev/usb/usbdi.h>
  65
  66 #define USB_DEBUG_VAR saf1761_otg_debug
  67
  68 #include <dev/usb/usb_core.h>
  69 #include <dev/usb/usb_debug.h>
  70 #include <dev/usb/usb_busdma.h>
  71 #include <dev/usb/usb_process.h>
  72 #include <dev/usb/usb_transfer.h>
  73 #include <dev/usb/usb_device.h>
  74 #include <dev/usb/usb_hub.h>
  75 #include <dev/usb/usb_util.h>
  76
  77 #include <dev/usb/usb_controller.h>
  78 #include <dev/usb/usb_bus.h>
  79 #endif                                  /* USB_GLOBAL_INCLUDE_FILE */
  80
  81 #include <dev/usb/controller/saf1761_otg.h>
  82 #include <dev/usb/controller/saf1761_otg_reg.h>
  83
  84 #define SAF1761_OTG_BUS2SC(bus) \
  85    ((struct saf1761_otg_softc *)(((uint8_t *)(bus)) - \
  86     ((uint8_t *)&(((struct saf1761_otg_softc *)0)->sc_bus))))
  87
  88 #define SAF1761_OTG_PC2UDEV(pc) \
  89    (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
  90
  91 #define SAF1761_DCINTERRUPT_THREAD_IRQ                  \
  92   (SOTG_DCINTERRUPT_IEVBUS | SOTG_DCINTERRUPT_IEBRST |  \
  93   SOTG_DCINTERRUPT_IERESM | SOTG_DCINTERRUPT_IESUSP)
  94
  95 #ifdef USB_DEBUG
  96 static int saf1761_otg_debug = 0;
  97 static int saf1761_otg_forcefs = 0;
  98
  99 static
 100 SYSCTL_NODE(_hw_usb, OID_AUTO, saf1761_otg, CTLFLAG_RW, 0,
 101     "USB SAF1761 DCI");
 102
 103 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, debug, CTLFLAG_RWTUN,
 104     &saf1761_otg_debug, 0, "SAF1761 DCI debug level");
 105 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, forcefs, CTLFLAG_RWTUN,
 106     &saf1761_otg_forcefs, 0, "SAF1761 DCI force FULL speed");
 107 #endif
 108
 109 #define SAF1761_OTG_INTR_ENDPT 1
 110
 111 /* prototypes */
 112
 113 static const struct usb_bus_methods saf1761_otg_bus_methods;
 114 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods;
 115 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods;
 116 static const struct usb_pipe_methods saf1761_otg_host_isoc_methods;
 117
 118 static saf1761_otg_cmd_t saf1761_host_setup_tx;
 119 static saf1761_otg_cmd_t saf1761_host_bulk_data_rx;
 120 static saf1761_otg_cmd_t saf1761_host_bulk_data_tx;
 121 static saf1761_otg_cmd_t saf1761_host_intr_data_rx;
 122 static saf1761_otg_cmd_t saf1761_host_intr_data_tx;
 123 static saf1761_otg_cmd_t saf1761_host_isoc_data_rx;
 124 static saf1761_otg_cmd_t saf1761_host_isoc_data_tx;
 125 static saf1761_otg_cmd_t saf1761_device_setup_rx;
 126 static saf1761_otg_cmd_t saf1761_device_data_rx;
 127 static saf1761_otg_cmd_t saf1761_device_data_tx;
 128 static saf1761_otg_cmd_t saf1761_device_data_tx_sync;
 129 static void saf1761_otg_device_done(struct usb_xfer *, usb_error_t);
 130 static void saf1761_otg_do_poll(struct usb_bus *);
 131 static void saf1761_otg_standard_done(struct usb_xfer *);
 132 static void saf1761_otg_intr_set(struct usb_xfer *, uint8_t);
 133 static void saf1761_otg_root_intr(struct saf1761_otg_softc *);
 134 static void saf1761_otg_enable_psof(struct saf1761_otg_softc *, uint8_t);
 135
 136 /*
 137  * Here is a list of what the SAF1761 chip can support. The main
 138  * limitation is that the sum of the buffer sizes must be less than
 139  * 8192 bytes.
 140  */
 141 static const struct usb_hw_ep_profile saf1761_otg_ep_profile[] = {
 142
 143         [0] = {
 144                 .max_in_frame_size = 64,
 145                 .max_out_frame_size = 64,
 146                 .is_simplex = 0,
 147                 .support_control = 1,
 148         },
 149         [1] = {
 150                 .max_in_frame_size = SOTG_HS_MAX_PACKET_SIZE,
 151                 .max_out_frame_size = SOTG_HS_MAX_PACKET_SIZE,
 152                 .is_simplex = 0,
 153                 .support_interrupt = 1,
 154                 .support_bulk = 1,
 155                 .support_isochronous = 1,
 156                 .support_in = 1,
 157                 .support_out = 1,
 158         },
 159 };
 160
 161 static void
 162 saf1761_otg_get_hw_ep_profile(struct usb_device *udev,
 163     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 164 {
 165         if (ep_addr == 0) {
 166                 *ppf = saf1761_otg_ep_profile + 0;
 167         } else if (ep_addr < 8) {
 168                 *ppf = saf1761_otg_ep_profile + 1;
 169         } else {
 170                 *ppf = NULL;
 171         }
 172 }
 173
 174 static void
 175 saf1761_otg_pull_up(struct saf1761_otg_softc *sc)
 176 {
 177         /* activate pullup on D+, if possible */
 178
 179         if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) {
 180                 DPRINTF("\n");
 181
 182                 sc->sc_flags.d_pulled_up = 1;
 183         }
 184 }
 185
 186 static void
 187 saf1761_otg_pull_down(struct saf1761_otg_softc *sc)
 188 {
 189         /* release pullup on D+, if possible */
 190
 191         if (sc->sc_flags.d_pulled_up) {
 192                 DPRINTF("\n");
 193
 194                 sc->sc_flags.d_pulled_up = 0;
 195         }
 196 }
 197
 198 static void
 199 saf1761_otg_wakeup_peer(struct saf1761_otg_softc *sc)
 200 {
 201         uint16_t temp;
 202
 203         if (!(sc->sc_flags.status_suspend))
 204                 return;
 205
 206         DPRINTFN(5, "\n");
 207
 208         temp = SAF1761_READ_LE_4(sc, SOTG_MODE);
 209         SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp | SOTG_MODE_SNDRSU);
 210         SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp & ~SOTG_MODE_SNDRSU);
 211
 212         /* Wait 8ms for remote wakeup to complete. */
 213         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 214 }
 215
 216 static uint8_t
 217 saf1761_host_channel_alloc(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 218 {
 219         uint32_t map;
 220         int x;
 221
 222         if (td->channel < SOTG_HOST_CHANNEL_MAX)
 223                 return (0);
 224
 225         /* check if device is suspended */
 226         if (SAF1761_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
 227                 return (1);             /* busy - cannot transfer data */
 228
 229         switch (td->ep_type) {
 230         case UE_INTERRUPT:
 231                 map = ~(sc->sc_host_intr_map |
 232                     sc->sc_host_intr_busy_map[0] |
 233                     sc->sc_host_intr_busy_map[1]);
 234                 /* find first set bit */
 235                 x = ffs(map) - 1;
 236                 if (x < 0 || x > 31)
 237                         break;
 238                 sc->sc_host_intr_map |= (1U << x);
 239                 td->channel = 32 + x;
 240                 return (0);
 241         case UE_ISOCHRONOUS:
 242                 map = ~(sc->sc_host_isoc_map |
 243                     sc->sc_host_isoc_busy_map[0] |
 244                     sc->sc_host_isoc_busy_map[1]);
 245                 /* find first set bit */
 246                 x = ffs(map) - 1;
 247                 if (x < 0 || x > 31)
 248                         break;
 249                 sc->sc_host_isoc_map |= (1U << x);
 250                 td->channel = x;
 251                 return (0);
 252         default:
 253                 map = ~(sc->sc_host_async_map |
 254                     sc->sc_host_async_busy_map[0] |
 255                     sc->sc_host_async_busy_map[1]);
 256                 /* find first set bit */
 257                 x = ffs(map) - 1;
 258                 if (x < 0 || x > 31)
 259                         break;
 260                 sc->sc_host_async_map |= (1U << x);
 261                 td->channel = 64 + x;
 262                 return (0);
 263         }
 264         return (1);
 265 }
 266
 267 static void
 268 saf1761_host_channel_free(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 269 {
 270         uint32_t x;
 271
 272         if (td->channel >= SOTG_HOST_CHANNEL_MAX)
 273                 return;
 274
 275         switch (td->ep_type) {
 276         case UE_INTERRUPT:
 277                 x = td->channel - 32;
 278                 td->channel = SOTG_HOST_CHANNEL_MAX;
 279                 sc->sc_host_intr_map &= ~(1U << x);
 280                 sc->sc_host_intr_suspend_map &= ~(1U << x);
 281                 sc->sc_host_intr_busy_map[0] |= (1U << x);
 282                 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 283                     (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 284                 break;
 285         case UE_ISOCHRONOUS:
 286                 x = td->channel;
 287                 td->channel = SOTG_HOST_CHANNEL_MAX;
 288                 sc->sc_host_isoc_map &= ~(1U << x);
 289                 sc->sc_host_isoc_suspend_map &= ~(1U << x);
 290                 sc->sc_host_isoc_busy_map[0] |= (1U << x);
 291                 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
 292                     (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
 293                 break;
 294         default:
 295                 x = td->channel - 64;
 296                 td->channel = SOTG_HOST_CHANNEL_MAX;
 297                 sc->sc_host_async_map &= ~(1U << x);
 298                 sc->sc_host_async_suspend_map &= ~(1U << x);
 299                 sc->sc_host_async_busy_map[0] |= (1U << x);
 300                 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 301                     (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 302                 break;
 303         }
 304         saf1761_otg_enable_psof(sc, 1);
 305 }
 306
 307 static uint32_t
 308 saf1761_peek_host_status_le_4(struct saf1761_otg_softc *sc, uint32_t offset)
 309 {
 310         uint32_t x = 0;
 311         while (1) {
 312                 uint32_t retval;
 313
 314                 SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
 315                 SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
 316                 retval = SAF1761_READ_LE_4(sc, offset);
 317                 if (retval != 0)
 318                         return (retval);
 319                 if (++x == 8) {
 320                         DPRINTF("STAUS is zero at offset 0x%x\n", offset);
 321                         break;
 322                 }
 323         }
 324         return (0);
 325 }
 326
 327 static void
 328 saf1761_read_host_memory(struct saf1761_otg_softc *sc,
 329     struct saf1761_otg_td *td, uint32_t len)
 330 {
 331         struct usb_page_search buf_res;
 332         uint32_t offset;
 333         uint32_t count;
 334
 335         if (len == 0)
 336                 return;
 337
 338         offset = SOTG_DATA_ADDR(td->channel);
 339         SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
 340         SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
 341
 342         /* optimised read first */
 343         while (len > 0) {
 344                 usbd_get_page(td->pc, td->offset, &buf_res);
 345
 346                 /* get correct length */
 347                 if (buf_res.length > len)
 348                         buf_res.length = len;
 349
 350                 /* check buffer alignment */
 351                 if (((uintptr_t)buf_res.buffer) & 3)
 352                         break;
 353
 354                 count = buf_res.length & ~3;
 355                 if (count == 0)
 356                         break;
 357
 358                 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 359                     offset, buf_res.buffer, count / 4);
 360
 361                 len -= count;
 362                 offset += count;
 363
 364                 /* update remainder and offset */
 365                 td->remainder -= count;
 366                 td->offset += count;
 367         }
 368
 369         if (len > 0) {
 370                 /* use bounce buffer */
 371                 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 372                     offset, sc->sc_bounce_buffer, (len + 3) / 4);
 373                 usbd_copy_in(td->pc, td->offset,
 374                     sc->sc_bounce_buffer, len);
 375
 376                 /* update remainder and offset */
 377                 td->remainder -= len;
 378                 td->offset += len;
 379         }
 380 }
 381
 382 static void
 383 saf1761_write_host_memory(struct saf1761_otg_softc *sc,
 384     struct saf1761_otg_td *td, uint32_t len)
 385 {
 386         struct usb_page_search buf_res;
 387         uint32_t offset;
 388         uint32_t count;
 389
 390         if (len == 0)
 391                 return;
 392
 393         offset = SOTG_DATA_ADDR(td->channel);
 394
 395         /* optimised write first */
 396         while (len > 0) {
 397                 usbd_get_page(td->pc, td->offset, &buf_res);
 398
 399                 /* get correct length */
 400                 if (buf_res.length > len)
 401                         buf_res.length = len;
 402
 403                 /* check buffer alignment */
 404                 if (((uintptr_t)buf_res.buffer) & 3)
 405                         break;
 406
 407                 count = buf_res.length & ~3;
 408                 if (count == 0)
 409                         break;
 410
 411                 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 412                     offset, buf_res.buffer, count / 4);
 413
 414                 len -= count;
 415                 offset += count;
 416
 417                 /* update remainder and offset */
 418                 td->remainder -= count;
 419                 td->offset += count;
 420         }
 421         if (len > 0) {
 422                 /* use bounce buffer */
 423                 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
 424                 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 425                     offset, sc->sc_bounce_buffer, (len + 3) / 4);
 426
 427                 /* update remainder and offset */
 428                 td->remainder -= len;
 429                 td->offset += len;
 430         }
 431 }
 432
 433 static uint8_t
 434 saf1761_host_setup_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 435 {
 436         uint32_t pdt_addr;
 437         uint32_t status;
 438         uint32_t count;
 439         uint32_t temp;
 440
 441         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 442                 pdt_addr = SOTG_PTD(td->channel);
 443
 444                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 445
 446                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 447
 448                 if (status & SOTG_PTD_DW3_ACTIVE) {
 449                         goto busy;
 450                 } else if (status & SOTG_PTD_DW3_HALTED) {
 451                         td->error_any = 1;
 452                 }
 453                 goto complete;
 454         }
 455         if (saf1761_host_channel_alloc(sc, td))
 456                 goto busy;
 457
 458         count = 8;
 459
 460         if (count != td->remainder) {
 461                 td->error_any = 1;
 462                 goto complete;
 463         }
 464
 465         saf1761_write_host_memory(sc, td, count);
 466
 467         pdt_addr = SOTG_PTD(td->channel);
 468
 469         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 470         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 471         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 472         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 473
 474         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 475         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 476
 477         temp = SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8;
 478         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 479
 480         temp = td->dw1_value | (2 << 10) /* SETUP PID */ | (td->ep_index >> 1);
 481         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 482
 483         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 484             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 485             (count << 3) /* transfer count */ |
 486             SOTG_PTD_DW0_VALID;
 487         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 488
 489         /* activate PTD */
 490         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 491             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 492
 493         td->toggle = 1;
 494 busy:
 495         return (1);     /* busy */
 496 complete:
 497         saf1761_host_channel_free(sc, td);
 498         return (0);     /* complete */
 499 }
 500
 501 static uint8_t
 502 saf1761_host_bulk_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 503 {
 504         uint32_t pdt_addr;
 505         uint32_t temp;
 506
 507         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 508                 uint32_t status;
 509                 uint32_t count;
 510                 uint8_t got_short;
 511
 512                 pdt_addr = SOTG_PTD(td->channel);
 513
 514                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 515
 516                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 517
 518                 if (status & SOTG_PTD_DW3_ACTIVE) {
 519                         goto busy;
 520                 } else if (status & SOTG_PTD_DW3_HALTED) {
 521                         if (!(status & SOTG_PTD_DW3_ERRORS))
 522                                 td->error_stall = 1;
 523                         td->error_any = 1;
 524                         goto complete;
 525                 }
 526                 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
 527                         count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
 528                 else
 529                         count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
 530                 got_short = 0;
 531
 532                 /* verify the packet byte count */
 533                 if (count != td->max_packet_size) {
 534                         if (count < td->max_packet_size) {
 535                                 /* we have a short packet */
 536                                 td->short_pkt = 1;
 537                                 got_short = 1;
 538                         } else {
 539                                 /* invalid USB packet */
 540                                 td->error_any = 1;
 541                                 goto complete;
 542                         }
 543                 }
 544                 td->toggle ^= 1;
 545
 546                 /* verify the packet byte count */
 547                 if (count > td->remainder) {
 548                         /* invalid USB packet */
 549                         td->error_any = 1;
 550                         goto complete;
 551                 }
 552
 553                 saf1761_read_host_memory(sc, td, count);
 554
 555                 /* check if we are complete */
 556                 if ((td->remainder == 0) || got_short) {
 557                         if (td->short_pkt)
 558                                 goto complete;
 559                         /* else need to receive a zero length packet */
 560                 }
 561                 saf1761_host_channel_free(sc, td);
 562         }
 563         if (saf1761_host_channel_alloc(sc, td))
 564                 goto busy;
 565
 566         /* set toggle, if any */
 567         if (td->set_toggle) {
 568                 td->set_toggle = 0;
 569                 td->toggle = 1;
 570         }
 571
 572         /* receive one more packet */
 573
 574         pdt_addr = SOTG_PTD(td->channel);
 575
 576         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 577         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 578         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 579         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 580
 581         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
 582             SOTG_PTD_DW3_CERR_2;
 583         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 584
 585         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
 586         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 587
 588         temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
 589         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 590
 591         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 592             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 593             (td->max_packet_size << 3) /* transfer count */ |
 594             SOTG_PTD_DW0_VALID;
 595         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 596
 597         /* activate PTD */
 598         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 599             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 600 busy:
 601         return (1);     /* busy */
 602 complete:
 603         saf1761_host_channel_free(sc, td);
 604         return (0);     /* complete */
 605 }
 606
 607 static uint8_t
 608 saf1761_host_bulk_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 609 {
 610         uint32_t pdt_addr;
 611         uint32_t temp;
 612         uint32_t count;
 613
 614         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 615                 uint32_t status;
 616
 617                 pdt_addr = SOTG_PTD(td->channel);
 618
 619                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 620
 621                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 622
 623                 if (status & SOTG_PTD_DW3_ACTIVE) {
 624                         goto busy;
 625                 } else if (status & SOTG_PTD_DW3_HALTED) {
 626                         if (!(status & SOTG_PTD_DW3_ERRORS))
 627                                 td->error_stall = 1;
 628                         td->error_any = 1;
 629                         goto complete;
 630                 }
 631                 /* check remainder */
 632                 if (td->remainder == 0) {
 633                         if (td->short_pkt)
 634                                 goto complete;
 635                         /* else we need to transmit a short packet */
 636                 }
 637                 saf1761_host_channel_free(sc, td);
 638         }
 639         if (saf1761_host_channel_alloc(sc, td))
 640                 goto busy;
 641
 642         count = td->max_packet_size;
 643         if (td->remainder < count) {
 644                 /* we have a short packet */
 645                 td->short_pkt = 1;
 646                 count = td->remainder;
 647         }
 648
 649         saf1761_write_host_memory(sc, td, count);
 650
 651         /* set toggle, if any */
 652         if (td->set_toggle) {
 653                 td->set_toggle = 0;
 654                 td->toggle = 1;
 655         }
 656
 657         /* send one more packet */
 658
 659         pdt_addr = SOTG_PTD(td->channel);
 660
 661         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 662         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 663         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 664         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 665
 666         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
 667             SOTG_PTD_DW3_CERR_2;
 668         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 669
 670         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
 671         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 672
 673         temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
 674         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 675
 676         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 677             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 678             (count << 3) /* transfer count */ |
 679             SOTG_PTD_DW0_VALID;
 680         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 681
 682         /* activate PTD */
 683         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 684             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 685
 686         td->toggle ^= 1;
 687 busy:
 688         return (1);     /* busy */
 689 complete:
 690         saf1761_host_channel_free(sc, td);
 691         return (0);     /* complete */
 692 }
 693
 694 static uint8_t
 695 saf1761_host_intr_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 696 {
 697         uint32_t pdt_addr;
 698         uint32_t temp;
 699
 700         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 701                 uint32_t status;
 702                 uint32_t count;
 703                 uint8_t got_short;
 704
 705                 pdt_addr = SOTG_PTD(td->channel);
 706
 707                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 708
 709                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 710
 711                 if (status & SOTG_PTD_DW3_ACTIVE) {
 712                         goto busy;
 713                 } else if (status & SOTG_PTD_DW3_HALTED) {
 714                         if (!(status & SOTG_PTD_DW3_ERRORS))
 715                                 td->error_stall = 1;
 716                         td->error_any = 1;
 717                         goto complete;
 718                 }
 719                 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
 720                         count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
 721                 else
 722                         count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
 723                 got_short = 0;
 724
 725                 /* verify the packet byte count */
 726                 if (count != td->max_packet_size) {
 727                         if (count < td->max_packet_size) {
 728                                 /* we have a short packet */
 729                                 td->short_pkt = 1;
 730                                 got_short = 1;
 731                         } else {
 732                                 /* invalid USB packet */
 733                                 td->error_any = 1;
 734                                 goto complete;
 735                         }
 736                 }
 737                 td->toggle ^= 1;
 738
 739                 /* verify the packet byte count */
 740                 if (count > td->remainder) {
 741                         /* invalid USB packet */
 742                         td->error_any = 1;
 743                         goto complete;
 744                 }
 745
 746                 saf1761_read_host_memory(sc, td, count);
 747
 748                 /* check if we are complete */
 749                 if ((td->remainder == 0) || got_short) {
 750                         if (td->short_pkt)
 751                                 goto complete;
 752                         /* else need to receive a zero length packet */
 753                 }
 754                 saf1761_host_channel_free(sc, td);
 755         }
 756         if (saf1761_host_channel_alloc(sc, td))
 757                 goto busy;
 758
 759         /* set toggle, if any */
 760         if (td->set_toggle) {
 761                 td->set_toggle = 0;
 762                 td->toggle = 1;
 763         }
 764
 765         /* receive one more packet */
 766
 767         pdt_addr = SOTG_PTD(td->channel);
 768
 769         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 770         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 771
 772         if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
 773                 temp = (0xFC << td->uframe) & 0xFF;     /* complete split */
 774         } else {
 775                 temp = 0;
 776         }
 777         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
 778
 779         temp = (1U << td->uframe);              /* start mask or start split */
 780         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
 781
 782         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 783         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 784
 785         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
 786             (td->interval & 0xF8);
 787         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 788
 789         temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
 790         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 791
 792         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 793             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 794             (td->max_packet_size << 3) /* transfer count */ |
 795             SOTG_PTD_DW0_VALID;
 796         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 797
 798         /* activate PTD */
 799         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 800             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 801 busy:
 802         return (1);     /* busy */
 803 complete:
 804         saf1761_host_channel_free(sc, td);
 805         return (0);     /* complete */
 806 }
 807
 808 static uint8_t
 809 saf1761_host_intr_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 810 {
 811         uint32_t pdt_addr;
 812         uint32_t temp;
 813         uint32_t count;
 814
 815         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 816                 uint32_t status;
 817
 818                 pdt_addr = SOTG_PTD(td->channel);
 819
 820                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 821
 822                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 823
 824                 if (status & SOTG_PTD_DW3_ACTIVE) {
 825                         goto busy;
 826                 } else if (status & SOTG_PTD_DW3_HALTED) {
 827                         if (!(status & SOTG_PTD_DW3_ERRORS))
 828                                 td->error_stall = 1;
 829                         td->error_any = 1;
 830                         goto complete;
 831                 }
 832
 833                 /* check remainder */
 834                 if (td->remainder == 0) {
 835                         if (td->short_pkt)
 836                                 goto complete;
 837                         /* else we need to transmit a short packet */
 838                 }
 839                 saf1761_host_channel_free(sc, td);
 840         }
 841         if (saf1761_host_channel_alloc(sc, td))
 842                 goto busy;
 843
 844         count = td->max_packet_size;
 845         if (td->remainder < count) {
 846                 /* we have a short packet */
 847                 td->short_pkt = 1;
 848                 count = td->remainder;
 849         }
 850
 851         saf1761_write_host_memory(sc, td, count);
 852
 853         /* set toggle, if any */
 854         if (td->set_toggle) {
 855                 td->set_toggle = 0;
 856                 td->toggle = 1;
 857         }
 858
 859         /* send one more packet */
 860
 861         pdt_addr = SOTG_PTD(td->channel);
 862
 863         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 864         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 865
 866         if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
 867                 temp = (0xFC << td->uframe) & 0xFF;     /* complete split */
 868         } else {
 869                 temp = 0;
 870         }
 871         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
 872
 873         temp = (1U << td->uframe);              /* start mask or start split */
 874         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
 875
 876         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 877         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 878
 879         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
 880             (td->interval & 0xF8);
 881         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 882
 883         temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
 884         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 885
 886         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 887             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 888             (count << 3) /* transfer count */ |
 889             SOTG_PTD_DW0_VALID;
 890         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 891
 892         /* activate PTD */
 893         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 894             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 895
 896         td->toggle ^= 1;
 897 busy:
 898         return (1);     /* busy */
 899 complete:
 900         saf1761_host_channel_free(sc, td);
 901         return (0);     /* complete */
 902 }
 903
 904 static uint8_t
 905 saf1761_host_isoc_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 906 {
 907         uint32_t pdt_addr;
 908         uint32_t temp;
 909
 910         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 911                 uint32_t status;
 912                 uint32_t count;
 913
 914                 pdt_addr = SOTG_PTD(td->channel);
 915
 916                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 917
 918                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 919
 920                 if (status & SOTG_PTD_DW3_ACTIVE) {
 921                         goto busy;
 922                 } else if (status & SOTG_PTD_DW3_HALTED) {
 923                         goto complete;
 924                 }
 925                 if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT)
 926                         count = (status & SOTG_PTD_DW3_XFER_COUNT_SPLIT);
 927                 else
 928                         count = (status & SOTG_PTD_DW3_XFER_COUNT_HS);
 929
 930                 /* verify the packet byte count */
 931                 if (count != td->max_packet_size) {
 932                         if (count < td->max_packet_size) {
 933                                 /* we have a short packet */
 934                                 td->short_pkt = 1;
 935                         } else {
 936                                 /* invalid USB packet */
 937                                 td->error_any = 1;
 938                                 goto complete;
 939                         }
 940                 }
 941
 942                 /* verify the packet byte count */
 943                 if (count > td->remainder) {
 944                         /* invalid USB packet */
 945                         td->error_any = 1;
 946                         goto complete;
 947                 }
 948
 949                 saf1761_read_host_memory(sc, td, count);
 950                 goto complete;
 951         }
 952
 953         if (saf1761_host_channel_alloc(sc, td))
 954                 goto busy;
 955
 956         /* receive one more packet */
 957
 958         pdt_addr = SOTG_PTD(td->channel);
 959
 960         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 961         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 962
 963         if (td->dw1_value & SOTG_PTD_DW1_ENABLE_SPLIT) {
 964                 temp = (0xFC << (td->uframe & 7)) & 0xFF;       /* complete split */
 965         } else {
 966                 temp = 0;
 967         }
 968         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
 969
 970         temp = (1U << (td->uframe & 7));        /* start mask or start split */
 971         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
 972
 973         temp = SOTG_PTD_DW3_ACTIVE | SOTG_PTD_DW3_CERR_3;
 974         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 975
 976         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
 977             (td->uframe & 0xF8);
 978         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 979
 980         temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
 981         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 982
 983         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 984             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 985             (td->max_packet_size << 3) /* transfer count */ |
 986             SOTG_PTD_DW0_VALID;
 987         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 988
 989         /* activate PTD */
 990         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
 991             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
 992 busy:
 993         return (1);     /* busy */
 994 complete:
 995         saf1761_host_channel_free(sc, td);
 996         return (0);     /* complete */
 997 }
 998
 999 static uint8_t
1000 saf1761_host_isoc_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1001 {
1002         uint32_t pdt_addr;
1003         uint32_t temp;
1004         uint32_t count;
1005
1006         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
1007                 uint32_t status;
1008
1009                 pdt_addr = SOTG_PTD(td->channel);
1010
1011                 status = saf1761_peek_host_status_le_4(sc, pdt_addr + SOTG_PTD_DW3);
1012
1013                 DPRINTFN(5, "STATUS=0x%08x\n", status);
1014
1015                 if (status & SOTG_PTD_DW3_ACTIVE) {
1016                         goto busy;
1017                 } else if (status & SOTG_PTD_DW3_HALTED) {
1018                         goto complete;
1019                 }
1020                 goto complete;
1021         }
1022         if (saf1761_host_channel_alloc(sc, td))
1023                 goto busy;
1024
1025         count = td->max_packet_size;
1026         if (td->remainder < count) {
1027                 /* we have a short packet */
1028                 td->short_pkt = 1;
1029                 count = td->remainder;
1030         }
1031
1032         saf1761_write_host_memory(sc, td, count);
1033
1034         /* send one more packet */
1035
1036         pdt_addr = SOTG_PTD(td->channel);
1037
1038         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
1039         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
1040         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
1041
1042         temp = (1U << (td->uframe & 7));        /* start mask or start split */
1043         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
1044
1045         temp = SOTG_PTD_DW3_ACTIVE | SOTG_PTD_DW3_CERR_3;
1046         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
1047
1048         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) |
1049             (td->uframe & 0xF8);
1050         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
1051
1052         temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
1053         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
1054
1055         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
1056             (count << 18) /* wMaxPacketSize */ |
1057             (count << 3) /* transfer count */ |
1058             SOTG_PTD_DW0_VALID;
1059         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
1060
1061         /* activate PTD */
1062         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
1063             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
1064 busy:
1065         return (1);     /* busy */
1066 complete:
1067         saf1761_host_channel_free(sc, td);
1068         return (0);     /* complete */
1069 }
1070
1071 static void
1072 saf1761_otg_set_address(struct saf1761_otg_softc *sc, uint8_t addr)
1073 {
1074         DPRINTFN(5, "addr=%d\n", addr);
1075
1076         SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, addr | SOTG_ADDRESS_ENABLE);
1077 }
1078
1079
1080 static void
1081 saf1761_read_device_fifo(struct saf1761_otg_softc *sc,
1082     struct saf1761_otg_td *td, uint32_t len)
1083 {
1084         struct usb_page_search buf_res;
1085         uint32_t count;
1086
1087         /* optimised read first */
1088         while (len > 0) {
1089                 usbd_get_page(td->pc, td->offset, &buf_res);
1090
1091                 /* get correct length */
1092                 if (buf_res.length > len)
1093                         buf_res.length = len;
1094
1095                 /* check buffer alignment */
1096                 if (((uintptr_t)buf_res.buffer) & 3)
1097                         break;
1098
1099                 count = buf_res.length & ~3;
1100                 if (count == 0)
1101                         break;
1102
1103                 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1104                     SOTG_DATA_PORT, buf_res.buffer, count / 4);
1105
1106                 len -= count;
1107
1108                 /* update remainder and offset */
1109                 td->remainder -= count;
1110                 td->offset += count;
1111         }
1112
1113         if (len > 0) {
1114                 /* use bounce buffer */
1115                 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1116                     SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
1117                 usbd_copy_in(td->pc, td->offset,
1118                     sc->sc_bounce_buffer, len);
1119
1120                 /* update remainder and offset */
1121                 td->remainder -= len;
1122                 td->offset += len;
1123         }
1124 }
1125
1126 static void
1127 saf1761_write_device_fifo(struct saf1761_otg_softc *sc,
1128     struct saf1761_otg_td *td, uint32_t len)
1129 {
1130         struct usb_page_search buf_res;
1131         uint32_t count;
1132
1133         /* optimised write first */
1134         while (len > 0) {
1135                 usbd_get_page(td->pc, td->offset, &buf_res);
1136
1137                 /* get correct length */
1138                 if (buf_res.length > len)
1139                         buf_res.length = len;
1140
1141                 /* check buffer alignment */
1142                 if (((uintptr_t)buf_res.buffer) & 3)
1143                         break;
1144
1145                 count = buf_res.length & ~3;
1146                 if (count == 0)
1147                         break;
1148
1149                 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1150                     SOTG_DATA_PORT, buf_res.buffer, count / 4);
1151
1152                 len -= count;
1153
1154                 /* update remainder and offset */
1155                 td->remainder -= count;
1156                 td->offset += count;
1157         }
1158         if (len > 0) {
1159                 /* use bounce buffer */
1160                 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
1161                 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
1162                     SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
1163
1164                 /* update remainder and offset */
1165                 td->remainder -= len;
1166                 td->offset += len;
1167         }
1168 }
1169
1170 static uint8_t
1171 saf1761_device_setup_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1172 {
1173         struct usb_device_request req;
1174         uint32_t count;
1175
1176         /* select the correct endpoint */
1177         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1178
1179         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1180
1181         /* check buffer status */
1182         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1183                 goto busy;
1184
1185         /* get buffer length */
1186         count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1187
1188         DPRINTFN(5, "count=%u rem=%u\n", count, td->remainder);
1189
1190         /* clear did stall */
1191         td->did_stall = 0;
1192
1193         /* clear stall */
1194         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
1195
1196         /* verify data length */
1197         if (count != td->remainder) {
1198                 DPRINTFN(0, "Invalid SETUP packet "
1199                     "length, %d bytes\n", count);
1200                 goto busy;
1201         }
1202         if (count != sizeof(req)) {
1203                 DPRINTFN(0, "Unsupported SETUP packet "
1204                     "length, %d bytes\n", count);
1205                 goto busy;
1206         }
1207         /* receive data */
1208         saf1761_read_device_fifo(sc, td, sizeof(req));
1209
1210         /* extract SETUP packet again */
1211         usbd_copy_out(td->pc, 0, &req, sizeof(req));
1212
1213         /* sneak peek the set address request */
1214         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1215             (req.bRequest == UR_SET_ADDRESS)) {
1216                 sc->sc_dv_addr = req.wValue[0] & 0x7F;
1217                 DPRINTF("Set address %d\n", sc->sc_dv_addr);
1218         } else {
1219                 sc->sc_dv_addr = 0xFF;
1220         }
1221         return (0);                     /* complete */
1222
1223 busy:
1224         /* abort any ongoing transfer */
1225         if (!td->did_stall) {
1226                 DPRINTFN(5, "stalling\n");
1227
1228                 /* set stall */
1229                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
1230
1231                 td->did_stall = 1;
1232         }
1233         return (1);                     /* not complete */
1234 }
1235
1236 static uint8_t
1237 saf1761_device_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1238 {
1239         uint32_t count;
1240         uint8_t got_short = 0;
1241
1242         if (td->ep_index == 0) {
1243                 /* select the correct endpoint */
1244                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1245
1246                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1247
1248                 /* check buffer status */
1249                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1250
1251                         if (td->remainder == 0) {
1252                                 /*
1253                                  * We are actually complete and have
1254                                  * received the next SETUP:
1255                                  */
1256                                 DPRINTFN(5, "faking complete\n");
1257                                 return (0);     /* complete */
1258                         }
1259                         DPRINTFN(5, "SETUP packet while receiving data\n");
1260                         /*
1261                          * USB Host Aborted the transfer.
1262                          */
1263                         td->error_any = 1;
1264                         return (0);     /* complete */
1265                 }
1266         }
1267         /* select the correct endpoint */
1268         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1269             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1270             SOTG_EP_INDEX_DIR_OUT);
1271
1272         /* enable data stage */
1273         if (td->set_toggle) {
1274                 td->set_toggle = 0;
1275                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1276         }
1277
1278         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1279
1280         /* check buffer status */
1281         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1282                 return (1);             /* not complete */
1283
1284         /* get buffer length */
1285         count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1286
1287         DPRINTFN(5, "rem=%u count=0x%04x\n", td->remainder, count);
1288
1289         /* verify the packet byte count */
1290         if (count != td->max_packet_size) {
1291                 if (count < td->max_packet_size) {
1292                         /* we have a short packet */
1293                         td->short_pkt = 1;
1294                         got_short = 1;
1295                 } else {
1296                         /* invalid USB packet */
1297                         td->error_any = 1;
1298                         return (0);     /* we are complete */
1299                 }
1300         }
1301         /* verify the packet byte count */
1302         if (count > td->remainder) {
1303                 /* invalid USB packet */
1304                 td->error_any = 1;
1305                 return (0);             /* we are complete */
1306         }
1307         /* receive data */
1308         saf1761_read_device_fifo(sc, td, count);
1309
1310         /* check if we are complete */
1311         if ((td->remainder == 0) || got_short) {
1312                 if (td->short_pkt) {
1313                         /* we are complete */
1314                         return (0);
1315                 }
1316                 /* else need to receive a zero length packet */
1317         }
1318         return (1);                     /* not complete */
1319 }
1320
1321 static uint8_t
1322 saf1761_device_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1323 {
1324         uint32_t count;
1325
1326         if (td->ep_index == 0) {
1327                 /* select the correct endpoint */
1328                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1329
1330                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1331
1332                 /* check buffer status */
1333                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1334                         DPRINTFN(5, "SETUP abort\n");
1335                         /*
1336                          * USB Host Aborted the transfer.
1337                          */
1338                         td->error_any = 1;
1339                         return (0);     /* complete */
1340                 }
1341         }
1342         /* select the correct endpoint */
1343         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1344             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1345             SOTG_EP_INDEX_DIR_IN);
1346
1347         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1348
1349         /* check buffer status */
1350         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1351                 return (1);             /* not complete */
1352
1353         /* enable data stage */
1354         if (td->set_toggle) {
1355                 td->set_toggle = 0;
1356                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1357         }
1358
1359         DPRINTFN(5, "rem=%u\n", td->remainder);
1360
1361         count = td->max_packet_size;
1362         if (td->remainder < count) {
1363                 /* we have a short packet */
1364                 td->short_pkt = 1;
1365                 count = td->remainder;
1366         }
1367         /* transmit data */
1368         saf1761_write_device_fifo(sc, td, count);
1369
1370         if (td->ep_index == 0) {
1371                 if (count < SOTG_FS_MAX_PACKET_SIZE) {
1372                         /* set end of packet */
1373                         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1374                 }
1375         } else {
1376                 if (count < SOTG_HS_MAX_PACKET_SIZE) {
1377                         /* set end of packet */
1378                         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1379                 }
1380         }
1381
1382         /* check remainder */
1383         if (td->remainder == 0) {
1384                 if (td->short_pkt) {
1385                         return (0);     /* complete */
1386                 }
1387                 /* else we need to transmit a short packet */
1388         }
1389         return (1);                     /* not complete */
1390 }
1391
1392 static uint8_t
1393 saf1761_device_data_tx_sync(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1394 {
1395         uint32_t count;
1396
1397         if (td->ep_index == 0) {
1398                 /* select the correct endpoint */
1399                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1400
1401                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1402
1403                 /* check buffer status */
1404                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1405                         DPRINTFN(5, "Faking complete\n");
1406                         return (0);     /* complete */
1407                 }
1408         }
1409         /* select the correct endpoint */
1410         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1411             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1412             SOTG_EP_INDEX_DIR_IN);
1413
1414         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1415
1416         /* check buffer status */
1417         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1418                 return (1);             /* busy */
1419
1420         if (sc->sc_dv_addr != 0xFF) {
1421                 /* write function address */
1422                 saf1761_otg_set_address(sc, sc->sc_dv_addr);
1423         }
1424         return (0);                     /* complete */
1425 }
1426
1427 static void
1428 saf1761_otg_xfer_do_fifo(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1429 {
1430         struct saf1761_otg_td *td;
1431         uint8_t toggle;
1432
1433         DPRINTFN(9, "\n");
1434
1435         td = xfer->td_transfer_cache;
1436         if (td == NULL)
1437                 return;
1438
1439         while (1) {
1440                 if ((td->func) (sc, td)) {
1441                         /* operation in progress */
1442                         break;
1443                 }
1444                 if (((void *)td) == xfer->td_transfer_last) {
1445                         goto done;
1446                 }
1447                 if (td->error_any) {
1448                         goto done;
1449                 } else if (td->remainder > 0) {
1450                         /*
1451                          * We had a short transfer. If there is no alternate
1452                          * next, stop processing !
1453                          */
1454                         if (!td->alt_next) {
1455                                 goto done;
1456                         }
1457                 }
1458                 /*
1459                  * Fetch the next transfer descriptor.
1460                  */
1461                 toggle = td->toggle;
1462                 td = td->obj_next;
1463                 td->toggle = toggle;
1464                 xfer->td_transfer_cache = td;
1465         }
1466         return;
1467
1468 done:
1469         /* compute all actual lengths */
1470         xfer->td_transfer_cache = NULL;
1471         sc->sc_xfer_complete = 1;
1472 }
1473
1474 static uint8_t
1475 saf1761_otg_xfer_do_complete(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1476 {
1477         struct saf1761_otg_td *td;
1478
1479         DPRINTFN(9, "\n");
1480
1481         td = xfer->td_transfer_cache;
1482         if (td == NULL) {
1483                 /* compute all actual lengths */
1484                 saf1761_otg_standard_done(xfer);
1485                 return (1);
1486         }
1487         return (0);
1488 }
1489
1490 static void
1491 saf1761_otg_interrupt_poll_locked(struct saf1761_otg_softc *sc)
1492 {
1493         struct usb_xfer *xfer;
1494
1495         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
1496                 saf1761_otg_xfer_do_fifo(sc, xfer);
1497 }
1498
1499 static void
1500 saf1761_otg_enable_psof(struct saf1761_otg_softc *sc, uint8_t on)
1501 {
1502         if (on) {
1503                 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IEPSOF;
1504         } else {
1505                 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IEPSOF;
1506         }
1507         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1508 }
1509
1510 static void
1511 saf1761_otg_wait_suspend(struct saf1761_otg_softc *sc, uint8_t on)
1512 {
1513         if (on) {
1514                 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IESUSP;
1515                 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IERESM;
1516         } else {
1517                 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IESUSP;
1518                 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IERESM;
1519         }
1520         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1521 }
1522
1523 static void
1524 saf1761_otg_update_vbus(struct saf1761_otg_softc *sc)
1525 {
1526         uint16_t status;
1527
1528         /* read fresh status */
1529         status = SAF1761_READ_LE_4(sc, SOTG_STATUS);
1530
1531         DPRINTFN(4, "STATUS=0x%04x\n", status);
1532
1533         if ((status & SOTG_STATUS_VBUS_VLD) &&
1534             (status & SOTG_STATUS_ID)) {
1535                 /* VBUS present and device mode */
1536                 if (!sc->sc_flags.status_vbus) {
1537                         sc->sc_flags.status_vbus = 1;
1538
1539                         /* complete root HUB interrupt endpoint */
1540                         saf1761_otg_root_intr(sc);
1541                 }
1542         } else {
1543                 /* VBUS not-present or host mode */
1544                 if (sc->sc_flags.status_vbus) {
1545                         sc->sc_flags.status_vbus = 0;
1546                         sc->sc_flags.status_bus_reset = 0;
1547                         sc->sc_flags.status_suspend = 0;
1548                         sc->sc_flags.change_suspend = 0;
1549                         sc->sc_flags.change_connect = 1;
1550
1551                         /* complete root HUB interrupt endpoint */
1552                         saf1761_otg_root_intr(sc);
1553                 }
1554         }
1555 }
1556
1557 static void
1558 saf1761_otg_interrupt_complete_locked(struct saf1761_otg_softc *sc)
1559 {
1560         struct usb_xfer *xfer;
1561 repeat:
1562         /* scan for completion events */
1563         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1564                 if (saf1761_otg_xfer_do_complete(sc, xfer))
1565                         goto repeat;
1566         }
1567 }
1568
1569 int
1570 saf1761_otg_filter_interrupt(void *arg)
1571 {
1572         struct saf1761_otg_softc *sc = arg;
1573         int retval = FILTER_HANDLED;
1574         uint32_t hcstat;
1575         uint32_t status;
1576
1577         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1578
1579         hcstat = SAF1761_READ_LE_4(sc, SOTG_HCINTERRUPT);
1580         /* acknowledge all host controller interrupts */
1581         SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT, hcstat);
1582
1583         status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT);
1584         /* acknowledge all device controller interrupts */
1585         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT,
1586             status & ~SAF1761_DCINTERRUPT_THREAD_IRQ);
1587
1588         (void) SAF1761_READ_LE_4(sc, SOTG_ATL_PTD_DONE_PTD);
1589         (void) SAF1761_READ_LE_4(sc, SOTG_INT_PTD_DONE_PTD);
1590         (void) SAF1761_READ_LE_4(sc, SOTG_ISO_PTD_DONE_PTD);
1591
1592         if (status & SOTG_DCINTERRUPT_IEPSOF) {
1593                 if ((sc->sc_host_async_busy_map[1] | sc->sc_host_async_busy_map[0] |
1594                      sc->sc_host_intr_busy_map[1] | sc->sc_host_intr_busy_map[0] |
1595                      sc->sc_host_isoc_busy_map[1] | sc->sc_host_isoc_busy_map[0]) != 0) {
1596                         /* busy waiting is active */
1597                         retval = FILTER_SCHEDULE_THREAD;
1598
1599                         sc->sc_host_async_busy_map[1] = sc->sc_host_async_busy_map[0];
1600                         sc->sc_host_async_busy_map[0] = 0;
1601
1602                         sc->sc_host_intr_busy_map[1] = sc->sc_host_intr_busy_map[0];
1603                         sc->sc_host_intr_busy_map[0] = 0;
1604
1605                         sc->sc_host_isoc_busy_map[1] = sc->sc_host_isoc_busy_map[0];
1606                         sc->sc_host_isoc_busy_map[0] = 0;
1607                 } else {
1608                         /* busy waiting is not active */
1609                         saf1761_otg_enable_psof(sc, 0);
1610                 }
1611         }
1612
1613         if (status & SAF1761_DCINTERRUPT_THREAD_IRQ)
1614                 retval = FILTER_SCHEDULE_THREAD;
1615
1616         /* poll FIFOs, if any */
1617         saf1761_otg_interrupt_poll_locked(sc);
1618
1619         if (sc->sc_xfer_complete != 0)
1620                 retval = FILTER_SCHEDULE_THREAD;
1621
1622         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1623
1624         return (retval);
1625 }
1626
1627 void
1628 saf1761_otg_interrupt(void *arg)
1629 {
1630         struct saf1761_otg_softc *sc = arg;
1631         uint32_t status;
1632
1633         USB_BUS_LOCK(&sc->sc_bus);
1634         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1635
1636         status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT) &
1637             SAF1761_DCINTERRUPT_THREAD_IRQ;
1638
1639         /* acknowledge all device controller interrupts */
1640         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT, status);
1641
1642         DPRINTF("DCINTERRUPT=0x%08x SOF=0x%08x "
1643             "FRINDEX=0x%08x\n", status,
1644             SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM),
1645             SAF1761_READ_LE_4(sc, SOTG_FRINDEX));
1646
1647         /* update VBUS and ID bits, if any */
1648         if (status & SOTG_DCINTERRUPT_IEVBUS)
1649                 saf1761_otg_update_vbus(sc);
1650
1651         if (status & SOTG_DCINTERRUPT_IEBRST) {
1652                 /* unlock device */
1653                 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1654                     SOTG_UNLOCK_DEVICE_CODE);
1655
1656                 /* Enable device address */
1657                 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS,
1658                     SOTG_ADDRESS_ENABLE);
1659
1660                 sc->sc_flags.status_bus_reset = 1;
1661                 sc->sc_flags.status_suspend = 0;
1662                 sc->sc_flags.change_suspend = 0;
1663                 sc->sc_flags.change_connect = 1;
1664
1665                 /* disable resume interrupt */
1666                 saf1761_otg_wait_suspend(sc, 1);
1667                 /* complete root HUB interrupt endpoint */
1668                 saf1761_otg_root_intr(sc);
1669         }
1670         /*
1671          * If "RESUME" and "SUSPEND" is set at the same time we
1672          * interpret that like "RESUME". Resume is set when there is
1673          * at least 3 milliseconds of inactivity on the USB BUS:
1674          */
1675         if (status & SOTG_DCINTERRUPT_IERESM) {
1676                 /* unlock device */
1677                 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1678                     SOTG_UNLOCK_DEVICE_CODE);
1679
1680                 if (sc->sc_flags.status_suspend) {
1681                         sc->sc_flags.status_suspend = 0;
1682                         sc->sc_flags.change_suspend = 1;
1683                         /* disable resume interrupt */
1684                         saf1761_otg_wait_suspend(sc, 1);
1685                         /* complete root HUB interrupt endpoint */
1686                         saf1761_otg_root_intr(sc);
1687                 }
1688         } else if (status & SOTG_DCINTERRUPT_IESUSP) {
1689                 if (!sc->sc_flags.status_suspend) {
1690                         sc->sc_flags.status_suspend = 1;
1691                         sc->sc_flags.change_suspend = 1;
1692                         /* enable resume interrupt */
1693                         saf1761_otg_wait_suspend(sc, 0);
1694                         /* complete root HUB interrupt endpoint */
1695                         saf1761_otg_root_intr(sc);
1696                 }
1697         }
1698
1699         if (sc->sc_xfer_complete != 0) {
1700                 sc->sc_xfer_complete = 0;
1701
1702                 /* complete FIFOs, if any */
1703                 saf1761_otg_interrupt_complete_locked(sc);
1704         }
1705         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1706         USB_BUS_UNLOCK(&sc->sc_bus);
1707 }
1708
1709 static void
1710 saf1761_otg_setup_standard_chain_sub(struct saf1761_otg_std_temp *temp)
1711 {
1712         struct saf1761_otg_td *td;
1713
1714         /* get current Transfer Descriptor */
1715         td = temp->td_next;
1716         temp->td = td;
1717
1718         /* prepare for next TD */
1719         temp->td_next = td->obj_next;
1720
1721         /* fill out the Transfer Descriptor */
1722         td->func = temp->func;
1723         td->pc = temp->pc;
1724         td->offset = temp->offset;
1725         td->remainder = temp->len;
1726         td->error_any = 0;
1727         td->error_stall = 0;
1728         td->set_toggle = 0;
1729         td->did_stall = temp->did_stall;
1730         td->short_pkt = temp->short_pkt;
1731         td->alt_next = temp->setup_alt_next;
1732         td->channel = SOTG_HOST_CHANNEL_MAX;
1733 }
1734
1735 static void
1736 saf1761_otg_setup_standard_chain(struct usb_xfer *xfer)
1737 {
1738         struct saf1761_otg_std_temp temp;
1739         struct saf1761_otg_softc *sc;
1740         struct saf1761_otg_td *td;
1741         uint32_t x;
1742         uint8_t ep_no;
1743         uint8_t ep_type;
1744         uint8_t need_sync;
1745         uint8_t is_host;
1746         uint8_t uframe_start;
1747         uint8_t uframe_interval;
1748
1749         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1750             xfer->address, UE_GET_ADDR(xfer->endpointno),
1751             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1752
1753         temp.max_frame_size = xfer->max_frame_size;
1754
1755         td = xfer->td_start[0];
1756         xfer->td_transfer_first = td;
1757         xfer->td_transfer_cache = td;
1758
1759         /* setup temp */
1760
1761         temp.pc = NULL;
1762         temp.td = NULL;
1763         temp.td_next = xfer->td_start[0];
1764         temp.offset = 0;
1765         temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
1766             xfer->flags_int.isochronous_xfr;
1767         temp.did_stall = !xfer->flags_int.control_stall;
1768
1769         is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
1770
1771         sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1772         ep_no = (xfer->endpointno & UE_ADDR);
1773         ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
1774
1775         /* check if we should prepend a setup message */
1776
1777         if (xfer->flags_int.control_xfr) {
1778                 if (xfer->flags_int.control_hdr) {
1779
1780                         if (is_host)
1781                                 temp.func = &saf1761_host_setup_tx;
1782                         else
1783                                 temp.func = &saf1761_device_setup_rx;
1784
1785                         temp.len = xfer->frlengths[0];
1786                         temp.pc = xfer->frbuffers + 0;
1787                         temp.short_pkt = temp.len ? 1 : 0;
1788                         /* check for last frame */
1789                         if (xfer->nframes == 1) {
1790                                 /* no STATUS stage yet, SETUP is last */
1791                                 if (xfer->flags_int.control_act)
1792                                         temp.setup_alt_next = 0;
1793                         }
1794                         saf1761_otg_setup_standard_chain_sub(&temp);
1795                 }
1796                 x = 1;
1797         } else {
1798                 x = 0;
1799         }
1800
1801         uframe_start = 0;
1802         uframe_interval = 0;
1803
1804         if (x != xfer->nframes) {
1805                 if (xfer->endpointno & UE_DIR_IN) {
1806                         if (is_host) {
1807                                 if (ep_type == UE_INTERRUPT) {
1808                                         temp.func = &saf1761_host_intr_data_rx;
1809                                 } else if (ep_type == UE_ISOCHRONOUS) {
1810                                         temp.func = &saf1761_host_isoc_data_rx;
1811                                         uframe_start = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) + 8) &
1812                                             (SOTG_FRINDEX_MASK & ~7);
1813                                         if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
1814                                                 uframe_interval = 1U << xfer->fps_shift;
1815                                         else
1816                                                 uframe_interval = 8U;
1817                                 } else {
1818                                         temp.func = &saf1761_host_bulk_data_rx;
1819                                 }
1820                                 need_sync = 0;
1821                         } else {
1822                                 temp.func = &saf1761_device_data_tx;
1823                                 need_sync = 1;
1824                         }
1825                 } else {
1826                         if (is_host) {
1827                                 if (ep_type == UE_INTERRUPT) {
1828                                         temp.func = &saf1761_host_intr_data_tx;
1829                                 } else if (ep_type == UE_ISOCHRONOUS) {
1830                                         temp.func = &saf1761_host_isoc_data_tx;
1831                                         uframe_start = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) + 8) &
1832                                             (SOTG_FRINDEX_MASK & ~7);
1833                                         if (xfer->xroot->udev->speed == USB_SPEED_HIGH)
1834                                                 uframe_interval = 1U << xfer->fps_shift;
1835                                         else
1836                                                 uframe_interval = 8U;
1837                                 } else {
1838                                         temp.func = &saf1761_host_bulk_data_tx;
1839                                 }
1840                                 need_sync = 0;
1841                         } else {
1842                                 temp.func = &saf1761_device_data_rx;
1843                                 need_sync = 0;
1844                         }
1845                 }
1846
1847                 /* setup "pc" pointer */
1848                 temp.pc = xfer->frbuffers + x;
1849         } else {
1850                 need_sync = 0;
1851         }
1852
1853         while (x != xfer->nframes) {
1854
1855                 /* DATA0 / DATA1 message */
1856
1857                 temp.len = xfer->frlengths[x];
1858
1859                 x++;
1860
1861                 if (x == xfer->nframes) {
1862                         if (xfer->flags_int.control_xfr) {
1863                                 if (xfer->flags_int.control_act) {
1864                                         temp.setup_alt_next = 0;
1865                                 }
1866                         } else {
1867                                 temp.setup_alt_next = 0;
1868                         }
1869                 }
1870                 if (temp.len == 0) {
1871
1872                         /* make sure that we send an USB packet */
1873
1874                         temp.short_pkt = 0;
1875
1876                 } else {
1877
1878                         /* regular data transfer */
1879
1880                         temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1881                 }
1882
1883                 saf1761_otg_setup_standard_chain_sub(&temp);
1884
1885                 if (xfer->flags_int.isochronous_xfr) {
1886                         temp.offset += temp.len;
1887
1888                         /* stamp the starting point for this transaction */
1889                         temp.td->uframe = uframe_start;
1890
1891                         /* advance to next */
1892                         uframe_start += uframe_interval;
1893                 } else {
1894                         /* get next Page Cache pointer */
1895                         temp.pc = xfer->frbuffers + x;
1896                 }
1897         }
1898
1899         /* check for control transfer */
1900         if (xfer->flags_int.control_xfr) {
1901                 /* always setup a valid "pc" pointer for status and sync */
1902                 temp.pc = xfer->frbuffers + 0;
1903                 temp.len = 0;
1904                 temp.short_pkt = 0;
1905                 temp.setup_alt_next = 0;
1906
1907                 /* check if we should append a status stage */
1908                 if (!xfer->flags_int.control_act) {
1909
1910                         /*
1911                          * Send a DATA1 message and invert the current
1912                          * endpoint direction.
1913                          */
1914                         if (xfer->endpointno & UE_DIR_IN) {
1915                                 if (is_host) {
1916                                         temp.func = &saf1761_host_bulk_data_tx;
1917                                         need_sync = 0;
1918                                 } else {
1919                                         temp.func = &saf1761_device_data_rx;
1920                                         need_sync = 0;
1921                                 }
1922                         } else {
1923                                 if (is_host) {
1924                                         temp.func = &saf1761_host_bulk_data_rx;
1925                                         need_sync = 0;
1926                                 } else {
1927                                         temp.func = &saf1761_device_data_tx;
1928                                         need_sync = 1;
1929                                 }
1930                         }
1931                         temp.len = 0;
1932                         temp.short_pkt = 0;
1933
1934                         saf1761_otg_setup_standard_chain_sub(&temp);
1935
1936                         /* data toggle should be DATA1 */
1937                         td = temp.td;
1938                         td->set_toggle = 1;
1939
1940                         if (need_sync) {
1941                                 /* we need a SYNC point after TX */
1942                                 temp.func = &saf1761_device_data_tx_sync;
1943                                 saf1761_otg_setup_standard_chain_sub(&temp);
1944                         }
1945                 }
1946         } else {
1947                 if (need_sync) {
1948                         temp.pc = xfer->frbuffers + 0;
1949                         temp.len = 0;
1950                         temp.short_pkt = 0;
1951                         temp.setup_alt_next = 0;
1952
1953                         /* we need a SYNC point after TX */
1954                         temp.func = &saf1761_device_data_tx_sync;
1955                         saf1761_otg_setup_standard_chain_sub(&temp);
1956                 }
1957         }
1958
1959         /* must have at least one frame! */
1960         td = temp.td;
1961         xfer->td_transfer_last = td;
1962
1963         if (is_host) {
1964                 /* get first again */
1965                 td = xfer->td_transfer_first;
1966                 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
1967         }
1968 }
1969
1970 static void
1971 saf1761_otg_timeout(void *arg)
1972 {
1973         struct usb_xfer *xfer = arg;
1974
1975         DPRINTF("xfer=%p\n", xfer);
1976
1977         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1978
1979         /* transfer is transferred */
1980         saf1761_otg_device_done(xfer, USB_ERR_TIMEOUT);
1981 }
1982
1983 static void
1984 saf1761_otg_intr_set(struct usb_xfer *xfer, uint8_t set)
1985 {
1986         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1987         uint8_t ep_no = (xfer->endpointno & UE_ADDR);
1988         uint32_t mask;
1989
1990         DPRINTFN(15, "endpoint=%d set=%d\n", xfer->endpointno, set);
1991
1992         if (ep_no == 0) {
1993                 mask = SOTG_DCINTERRUPT_IEPRX(0) |
1994                     SOTG_DCINTERRUPT_IEPTX(0) |
1995                     SOTG_DCINTERRUPT_IEP0SETUP;
1996         } else if (xfer->endpointno & UE_DIR_IN) {
1997                 mask = SOTG_DCINTERRUPT_IEPTX(ep_no);
1998         } else {
1999                 mask = SOTG_DCINTERRUPT_IEPRX(ep_no);
2000         }
2001
2002         if (set)
2003                 sc->sc_intr_enable |= mask;
2004         else
2005                 sc->sc_intr_enable &= ~mask;
2006
2007         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
2008 }
2009
2010 static void
2011 saf1761_otg_start_standard_chain(struct usb_xfer *xfer)
2012 {
2013         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2014
2015         DPRINTFN(9, "\n");
2016
2017         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2018
2019         /* poll one time */
2020         saf1761_otg_xfer_do_fifo(sc, xfer);
2021
2022         if (saf1761_otg_xfer_do_complete(sc, xfer) == 0) {
2023                 /*
2024                  * Only enable the endpoint interrupt when we are
2025                  * actually waiting for data, hence we are dealing
2026                  * with level triggered interrupts !
2027                  */
2028                 saf1761_otg_intr_set(xfer, 1);
2029
2030                 /* put transfer on interrupt queue */
2031                 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
2032
2033                 /* start timeout, if any */
2034                 if (xfer->timeout != 0) {
2035                         usbd_transfer_timeout_ms(xfer,
2036                             &saf1761_otg_timeout, xfer->timeout);
2037                 }
2038         }
2039         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2040 }
2041
2042 static void
2043 saf1761_otg_root_intr(struct saf1761_otg_softc *sc)
2044 {
2045         DPRINTFN(9, "\n");
2046
2047         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2048
2049         /* set port bit - we only have one port */
2050         sc->sc_hub_idata[0] = 0x02;
2051
2052         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2053             sizeof(sc->sc_hub_idata));
2054 }
2055
2056 static usb_error_t
2057 saf1761_otg_standard_done_sub(struct usb_xfer *xfer)
2058 {
2059         struct saf1761_otg_td *td;
2060         uint32_t len;
2061         usb_error_t error;
2062
2063         DPRINTFN(9, "\n");
2064
2065         td = xfer->td_transfer_cache;
2066
2067         do {
2068                 len = td->remainder;
2069
2070                 /* store last data toggle */
2071                 xfer->endpoint->toggle_next = td->toggle;
2072
2073                 if (xfer->aframes != xfer->nframes) {
2074                         /*
2075                          * Verify the length and subtract
2076                          * the remainder from "frlengths[]":
2077                          */
2078                         if (len > xfer->frlengths[xfer->aframes]) {
2079                                 td->error_any = 1;
2080                         } else {
2081                                 xfer->frlengths[xfer->aframes] -= len;
2082                         }
2083                 }
2084                 /* Check for transfer error */
2085                 if (td->error_any) {
2086                         /* the transfer is finished */
2087                         error = (td->error_stall ?
2088                             USB_ERR_STALLED : USB_ERR_IOERROR);
2089                         td = NULL;
2090                         break;
2091                 }
2092                 /* Check for short transfer */
2093                 if (len > 0) {
2094                         if (xfer->flags_int.short_frames_ok ||
2095                             xfer->flags_int.isochronous_xfr) {
2096                                 /* follow alt next */
2097                                 if (td->alt_next) {
2098                                         td = td->obj_next;
2099                                 } else {
2100                                         td = NULL;
2101                                 }
2102                         } else {
2103                                 /* the transfer is finished */
2104                                 td = NULL;
2105                         }
2106                         error = 0;
2107                         break;
2108                 }
2109                 td = td->obj_next;
2110
2111                 /* this USB frame is complete */
2112                 error = 0;
2113                 break;
2114
2115         } while (0);
2116
2117         /* update transfer cache */
2118
2119         xfer->td_transfer_cache = td;
2120
2121         return (error);
2122 }
2123
2124 static void
2125 saf1761_otg_standard_done(struct usb_xfer *xfer)
2126 {
2127         usb_error_t err = 0;
2128
2129         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2130             xfer, xfer->endpoint);
2131
2132         /* reset scanner */
2133
2134         xfer->td_transfer_cache = xfer->td_transfer_first;
2135
2136         if (xfer->flags_int.control_xfr) {
2137
2138                 if (xfer->flags_int.control_hdr) {
2139
2140                         err = saf1761_otg_standard_done_sub(xfer);
2141                 }
2142                 xfer->aframes = 1;
2143
2144                 if (xfer->td_transfer_cache == NULL) {
2145                         goto done;
2146                 }
2147         }
2148         while (xfer->aframes != xfer->nframes) {
2149
2150                 err = saf1761_otg_standard_done_sub(xfer);
2151                 xfer->aframes++;
2152
2153                 if (xfer->td_transfer_cache == NULL) {
2154                         goto done;
2155                 }
2156         }
2157
2158         if (xfer->flags_int.control_xfr &&
2159             !xfer->flags_int.control_act) {
2160
2161                 err = saf1761_otg_standard_done_sub(xfer);
2162         }
2163 done:
2164         saf1761_otg_device_done(xfer, err);
2165 }
2166
2167 /*------------------------------------------------------------------------*
2168  *      saf1761_otg_device_done
2169  *
2170  * NOTE: this function can be called more than one time on the
2171  * same USB transfer!
2172  *------------------------------------------------------------------------*/
2173 static void
2174 saf1761_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
2175 {
2176         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2177
2178         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
2179
2180         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2181             xfer, xfer->endpoint, error);
2182
2183         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2184
2185         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
2186                 saf1761_otg_intr_set(xfer, 0);
2187         } else {
2188                 struct saf1761_otg_td *td;
2189
2190                 td = xfer->td_transfer_cache;
2191
2192                 if (td != NULL)
2193                         saf1761_host_channel_free(sc, td);
2194         }
2195
2196         /* dequeue transfer and start next transfer */
2197         usbd_transfer_done(xfer, error);
2198
2199         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2200 }
2201
2202 static void
2203 saf1761_otg_xfer_stall(struct usb_xfer *xfer)
2204 {
2205         saf1761_otg_device_done(xfer, USB_ERR_STALLED);
2206 }
2207
2208 static void
2209 saf1761_otg_set_stall(struct usb_device *udev,
2210     struct usb_endpoint *ep, uint8_t *did_stall)
2211 {
2212         struct saf1761_otg_softc *sc;
2213         uint8_t ep_no;
2214         uint8_t ep_type;
2215         uint8_t ep_dir;
2216
2217         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2218
2219         /* check mode */
2220         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2221                 /* not supported */
2222                 return;
2223         }
2224
2225         DPRINTFN(5, "endpoint=%p\n", ep);
2226
2227         /* set STALL bit */
2228         sc = SAF1761_OTG_BUS2SC(udev->bus);
2229
2230         ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
2231         ep_dir = (ep->edesc->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT));
2232         ep_type = (ep->edesc->bmAttributes & UE_XFERTYPE);
2233
2234         if (ep_type == UE_CONTROL) {
2235                 /* should not happen */
2236                 return;
2237         }
2238         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2239
2240         /* select the correct endpoint */
2241         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2242             (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2243             ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2244             SOTG_EP_INDEX_DIR_OUT));
2245
2246         /* set stall */
2247         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
2248
2249         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2250 }
2251
2252 static void
2253 saf1761_otg_clear_stall_sub_locked(struct saf1761_otg_softc *sc,
2254     uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2255 {
2256         if (ep_type == UE_CONTROL) {
2257                 /* clearing stall is not needed */
2258                 return;
2259         }
2260         /* select the correct endpoint */
2261         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2262             (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2263             ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2264             SOTG_EP_INDEX_DIR_OUT));
2265
2266         /* disable endpoint */
2267         SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, 0);
2268         /* enable endpoint again - will clear data toggle */
2269         SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, ep_type | SOTG_EP_TYPE_ENABLE);
2270
2271         /* clear buffer */
2272         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_CLBUF);
2273         /* clear stall */
2274         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
2275 }
2276
2277 static void
2278 saf1761_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
2279 {
2280         struct saf1761_otg_softc *sc;
2281         struct usb_endpoint_descriptor *ed;
2282
2283         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2284
2285         DPRINTFN(5, "endpoint=%p\n", ep);
2286
2287         /* check mode */
2288         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2289                 /* not supported */
2290                 return;
2291         }
2292         /* get softc */
2293         sc = SAF1761_OTG_BUS2SC(udev->bus);
2294
2295         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2296
2297         /* get endpoint descriptor */
2298         ed = ep->edesc;
2299
2300         /* reset endpoint */
2301         saf1761_otg_clear_stall_sub_locked(sc,
2302             (ed->bEndpointAddress & UE_ADDR),
2303             (ed->bmAttributes & UE_XFERTYPE),
2304             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
2305
2306         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2307 }
2308
2309 usb_error_t
2310 saf1761_otg_init(struct saf1761_otg_softc *sc)
2311 {
2312         const struct usb_hw_ep_profile *pf;
2313         uint32_t x;
2314
2315         DPRINTF("\n");
2316
2317         /* set up the bus structure */
2318         sc->sc_bus.usbrev = USB_REV_2_0;
2319         sc->sc_bus.methods = &saf1761_otg_bus_methods;
2320
2321         USB_BUS_LOCK(&sc->sc_bus);
2322
2323         /* Reset Host controller, including HW mode */
2324         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_ALL);
2325
2326         DELAY(1000);
2327
2328         /* Reset Host controller, including HW mode */
2329         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_HC);
2330
2331         /* wait a bit */
2332         DELAY(1000);
2333
2334         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, 0);
2335
2336         /* wait a bit */
2337         DELAY(1000);
2338
2339         /* Enable interrupts */
2340         sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN |
2341             SOTG_HW_MODE_CTRL_COMN_INT;
2342
2343         /* unlock device */
2344         SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE, SOTG_UNLOCK_DEVICE_CODE);
2345
2346         /*
2347          * Set correct hardware mode, must be written twice if bus
2348          * width is changed:
2349          */
2350         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2351         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2352
2353         SAF1761_WRITE_LE_4(sc, SOTG_DCSCRATCH, 0xdeadbeef);
2354         SAF1761_WRITE_LE_4(sc, SOTG_HCSCRATCH, 0xdeadbeef);
2355
2356         DPRINTF("DCID=0x%08x VEND_PROD=0x%08x HWMODE=0x%08x SCRATCH=0x%08x,0x%08x\n",
2357             SAF1761_READ_LE_4(sc, SOTG_DCCHIP_ID),
2358             SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID),
2359             SAF1761_READ_LE_4(sc, SOTG_HW_MODE_CTRL),
2360             SAF1761_READ_LE_4(sc, SOTG_DCSCRATCH),
2361             SAF1761_READ_LE_4(sc, SOTG_HCSCRATCH));
2362
2363         /* reset device controller */
2364         SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_SFRESET);
2365         SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2366
2367         /* wait a bit */
2368         DELAY(1000);
2369
2370         /* reset host controller */
2371         SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_HCRESET);
2372
2373         /* wait for reset to clear */
2374         for (x = 0; x != 10; x++) {
2375                 if ((SAF1761_READ_LE_4(sc, SOTG_USBCMD) & SOTG_USBCMD_HCRESET) == 0)
2376                         break;
2377                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
2378         }
2379
2380         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode |
2381             SOTG_HW_MODE_CTRL_ALL_ATX_RESET);
2382
2383         /* wait a bit */
2384         DELAY(1000);
2385
2386         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2387
2388         /* wait a bit */
2389         DELAY(1000);
2390
2391         /* do a pulldown */
2392         saf1761_otg_pull_down(sc);
2393
2394         /* wait 10ms for pulldown to stabilise */
2395         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2396
2397         for (x = 1;; x++) {
2398
2399                 saf1761_otg_get_hw_ep_profile(NULL, &pf, x);
2400                 if (pf == NULL)
2401                         break;
2402
2403                 /* select the correct endpoint */
2404                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2405                     (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2406                     SOTG_EP_INDEX_DIR_IN);
2407
2408                 /* select the maximum packet size */
2409                 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_in_frame_size);
2410
2411                 /* select the correct endpoint */
2412                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2413                     (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2414                     SOTG_EP_INDEX_DIR_OUT);
2415
2416                 /* select the maximum packet size */
2417                 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_out_frame_size);
2418         }
2419
2420         /* enable interrupts */
2421         SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_GLINTENA |
2422             SOTG_MODE_CLKAON | SOTG_MODE_WKUPCS);
2423
2424         sc->sc_interrupt_cfg |=
2425             SOTG_INTERRUPT_CFG_CDBGMOD |
2426             SOTG_INTERRUPT_CFG_DDBGMODIN |
2427             SOTG_INTERRUPT_CFG_DDBGMODOUT;
2428
2429         /* set default values */
2430         SAF1761_WRITE_LE_4(sc, SOTG_INTERRUPT_CFG, sc->sc_interrupt_cfg);
2431
2432         /* enable VBUS and ID interrupt */
2433         SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2434             SOTG_IRQ_ENABLE_CLR(0xFFFF));
2435         SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2436             SOTG_IRQ_ENABLE_SET(SOTG_IRQ_ID | SOTG_IRQ_VBUS_VLD));
2437
2438         /* enable interrupts */
2439         sc->sc_intr_enable = SOTG_DCINTERRUPT_IEVBUS |
2440             SOTG_DCINTERRUPT_IEBRST | SOTG_DCINTERRUPT_IESUSP;
2441         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
2442
2443         /*
2444          * Connect ATX port 1 to device controller, select external
2445          * charge pump and driver VBUS to +5V:
2446          */
2447         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2448             SOTG_CTRL_CLR(0xFFFF));
2449         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2450             SOTG_CTRL_SET(SOTG_CTRL_SW_SEL_HC_DC |
2451             SOTG_CTRL_BDIS_ACON_EN | SOTG_CTRL_SEL_CP_EXT |
2452             SOTG_CTRL_VBUS_DRV));
2453
2454         /* disable device address */
2455         SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, 0);
2456
2457         /* enable host controller clock and preserve reserved bits */
2458         x = SAF1761_READ_LE_4(sc, SOTG_POWER_DOWN);
2459         SAF1761_WRITE_LE_4(sc, SOTG_POWER_DOWN, x | SOTG_POWER_DOWN_HC_CLK_EN);
2460
2461         /* wait 10ms for clock */
2462         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2463
2464         /* enable configuration flag */
2465         SAF1761_WRITE_LE_4(sc, SOTG_CONFIGFLAG, SOTG_CONFIGFLAG_ENABLE);
2466
2467         /* clear RAM block */
2468         for (x = 0x400; x != 0x10000; x += 4)
2469                 SAF1761_WRITE_LE_4(sc, x, 0);
2470
2471         /* start the HC */
2472         SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_RS);
2473
2474         DPRINTF("USBCMD=0x%08x\n", SAF1761_READ_LE_4(sc, SOTG_USBCMD));
2475
2476         /* make HC scan all PTDs */
2477         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_LAST_PTD, (1 << 31));
2478         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_LAST_PTD, (1 << 31));
2479         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_LAST_PTD, (1 << 31));
2480
2481         /* skip all PTDs by default */
2482         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD, -1U);
2483         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD, -1U);
2484         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD, -1U);
2485
2486         /* activate all PTD types */
2487         SAF1761_WRITE_LE_4(sc, SOTG_HCBUFFERSTATUS,
2488             SOTG_HCBUFFERSTATUS_ISO_BUF_FILL |
2489             SOTG_HCBUFFERSTATUS_INT_BUF_FILL |
2490             SOTG_HCBUFFERSTATUS_ATL_BUF_FILL);
2491
2492         /* we don't use the AND mask */
2493         SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_AND, 0);
2494         SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_AND, 0);
2495         SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_AND, 0);
2496
2497         /* enable all PTD OR interrupts by default */
2498         SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_OR, -1U);
2499         SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_OR, -1U);
2500         SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_OR, -1U);
2501
2502         /* enable HC interrupts */
2503         SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT_ENABLE,
2504             SOTG_HCINTERRUPT_OTG_IRQ |
2505             SOTG_HCINTERRUPT_ISO_IRQ |
2506             SOTG_HCINTERRUPT_ALT_IRQ |
2507             SOTG_HCINTERRUPT_INT_IRQ);
2508
2509         /* poll initial VBUS status */
2510         saf1761_otg_update_vbus(sc);
2511
2512         USB_BUS_UNLOCK(&sc->sc_bus);
2513
2514         /* catch any lost interrupts */
2515
2516         saf1761_otg_do_poll(&sc->sc_bus);
2517
2518         return (0);                     /* success */
2519 }
2520
2521 void
2522 saf1761_otg_uninit(struct saf1761_otg_softc *sc)
2523 {
2524         USB_BUS_LOCK(&sc->sc_bus);
2525
2526         /* disable all interrupts */
2527         SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2528
2529         sc->sc_flags.port_powered = 0;
2530         sc->sc_flags.status_vbus = 0;
2531         sc->sc_flags.status_bus_reset = 0;
2532         sc->sc_flags.status_suspend = 0;
2533         sc->sc_flags.change_suspend = 0;
2534         sc->sc_flags.change_connect = 1;
2535
2536         saf1761_otg_pull_down(sc);
2537         USB_BUS_UNLOCK(&sc->sc_bus);
2538 }
2539
2540 static void
2541 saf1761_otg_suspend(struct saf1761_otg_softc *sc)
2542 {
2543         /* TODO */
2544 }
2545
2546 static void
2547 saf1761_otg_resume(struct saf1761_otg_softc *sc)
2548 {
2549         /* TODO */
2550 }
2551
2552 static void
2553 saf1761_otg_do_poll(struct usb_bus *bus)
2554 {
2555         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
2556
2557         USB_BUS_LOCK(&sc->sc_bus);
2558         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2559         saf1761_otg_interrupt_poll_locked(sc);
2560         saf1761_otg_interrupt_complete_locked(sc);
2561         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2562         USB_BUS_UNLOCK(&sc->sc_bus);
2563 }
2564
2565 /*------------------------------------------------------------------------*
2566  * saf1761_otg control support
2567  * saf1761_otg interrupt support
2568  * saf1761_otg bulk support
2569  *------------------------------------------------------------------------*/
2570 static void
2571 saf1761_otg_device_non_isoc_open(struct usb_xfer *xfer)
2572 {
2573         return;
2574 }
2575
2576 static void
2577 saf1761_otg_device_non_isoc_close(struct usb_xfer *xfer)
2578 {
2579         saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2580 }
2581
2582 static void
2583 saf1761_otg_device_non_isoc_enter(struct usb_xfer *xfer)
2584 {
2585         return;
2586 }
2587
2588 static void
2589 saf1761_otg_device_non_isoc_start(struct usb_xfer *xfer)
2590 {
2591         /* setup TDs */
2592         saf1761_otg_setup_standard_chain(xfer);
2593         saf1761_otg_start_standard_chain(xfer);
2594 }
2595
2596 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods =
2597 {
2598         .open = saf1761_otg_device_non_isoc_open,
2599         .close = saf1761_otg_device_non_isoc_close,
2600         .enter = saf1761_otg_device_non_isoc_enter,
2601         .start = saf1761_otg_device_non_isoc_start,
2602 };
2603
2604 /*------------------------------------------------------------------------*
2605  * saf1761_otg device side isochronous support
2606  *------------------------------------------------------------------------*/
2607 static void
2608 saf1761_otg_device_isoc_open(struct usb_xfer *xfer)
2609 {
2610         return;
2611 }
2612
2613 static void
2614 saf1761_otg_device_isoc_close(struct usb_xfer *xfer)
2615 {
2616         saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2617 }
2618
2619 static void
2620 saf1761_otg_device_isoc_enter(struct usb_xfer *xfer)
2621 {
2622         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2623         uint32_t temp;
2624         uint32_t nframes;
2625
2626         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2627             xfer, xfer->endpoint->isoc_next, xfer->nframes);
2628
2629         /* get the current frame index - we don't need the high bits */
2630
2631         nframes = SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM);
2632
2633         /*
2634          * check if the frame index is within the window where the
2635          * frames will be inserted
2636          */
2637         temp = (nframes - xfer->endpoint->isoc_next) & SOTG_FRAME_NUM_SOFR_MASK;
2638
2639         if ((xfer->endpoint->is_synced == 0) ||
2640             (temp < xfer->nframes)) {
2641                 /*
2642                  * If there is data underflow or the pipe queue is
2643                  * empty we schedule the transfer a few frames ahead
2644                  * of the current frame position. Else two isochronous
2645                  * transfers might overlap.
2646                  */
2647                 xfer->endpoint->isoc_next = (nframes + 3) & SOTG_FRAME_NUM_SOFR_MASK;
2648                 xfer->endpoint->is_synced = 1;
2649                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2650         }
2651         /*
2652          * compute how many milliseconds the insertion is ahead of the
2653          * current frame position:
2654          */
2655         temp = (xfer->endpoint->isoc_next - nframes) & SOTG_FRAME_NUM_SOFR_MASK;
2656
2657         /*
2658          * pre-compute when the isochronous transfer will be finished:
2659          */
2660         xfer->isoc_time_complete =
2661             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2662             xfer->nframes;
2663
2664         /* compute frame number for next insertion */
2665         xfer->endpoint->isoc_next += xfer->nframes;
2666
2667         /* setup TDs */
2668         saf1761_otg_setup_standard_chain(xfer);
2669 }
2670
2671 static void
2672 saf1761_otg_device_isoc_start(struct usb_xfer *xfer)
2673 {
2674         /* start TD chain */
2675         saf1761_otg_start_standard_chain(xfer);
2676 }
2677
2678 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods =
2679 {
2680         .open = saf1761_otg_device_isoc_open,
2681         .close = saf1761_otg_device_isoc_close,
2682         .enter = saf1761_otg_device_isoc_enter,
2683         .start = saf1761_otg_device_isoc_start,
2684 };
2685
2686 /*------------------------------------------------------------------------*
2687  * saf1761_otg host side isochronous support
2688  *------------------------------------------------------------------------*/
2689 static void
2690 saf1761_otg_host_isoc_open(struct usb_xfer *xfer)
2691 {
2692         return;
2693 }
2694
2695 static void
2696 saf1761_otg_host_isoc_close(struct usb_xfer *xfer)
2697 {
2698         saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2699 }
2700
2701 static void
2702 saf1761_otg_host_isoc_enter(struct usb_xfer *xfer)
2703 {
2704         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2705         uint32_t temp;
2706         uint32_t nframes;
2707
2708         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2709             xfer, xfer->endpoint->isoc_next, xfer->nframes);
2710
2711         /* get the current frame index - we don't need the high bits */
2712
2713         nframes = (SAF1761_READ_LE_4(sc, SOTG_FRINDEX) & SOTG_FRINDEX_MASK) >> 3;
2714
2715         /*
2716          * check if the frame index is within the window where the
2717          * frames will be inserted
2718          */
2719         temp = (nframes - xfer->endpoint->isoc_next) & (SOTG_FRINDEX_MASK >> 3);
2720
2721         if ((xfer->endpoint->is_synced == 0) ||
2722             (temp < xfer->nframes)) {
2723                 /*
2724                  * If there is data underflow or the pipe queue is
2725                  * empty we schedule the transfer a few frames ahead
2726                  * of the current frame position. Else two isochronous
2727                  * transfers might overlap.
2728                  */
2729                 xfer->endpoint->isoc_next = (nframes + 3) & (SOTG_FRINDEX_MASK >> 3);
2730                 xfer->endpoint->is_synced = 1;
2731                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2732         }
2733         /*
2734          * compute how many milliseconds the insertion is ahead of the
2735          * current frame position:
2736          */
2737         temp = (xfer->endpoint->isoc_next - nframes) & (SOTG_FRINDEX_MASK >> 3);
2738
2739         /*
2740          * pre-compute when the isochronous transfer will be finished:
2741          */
2742         xfer->isoc_time_complete =
2743             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2744             xfer->nframes;
2745
2746         /* compute frame number for next insertion */
2747         xfer->endpoint->isoc_next += xfer->nframes;
2748
2749         /* setup TDs */
2750         saf1761_otg_setup_standard_chain(xfer);
2751 }
2752
2753 static void
2754 saf1761_otg_host_isoc_start(struct usb_xfer *xfer)
2755 {
2756         /* start TD chain */
2757         saf1761_otg_start_standard_chain(xfer);
2758 }
2759
2760 static const struct usb_pipe_methods saf1761_otg_host_isoc_methods =
2761 {
2762         .open = saf1761_otg_host_isoc_open,
2763         .close = saf1761_otg_host_isoc_close,
2764         .enter = saf1761_otg_host_isoc_enter,
2765         .start = saf1761_otg_host_isoc_start,
2766 };
2767
2768 /*------------------------------------------------------------------------*
2769  * saf1761_otg root control support
2770  *------------------------------------------------------------------------*
2771  * Simulate a hardware HUB by handling all the necessary requests.
2772  *------------------------------------------------------------------------*/
2773
2774 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2775
2776 static const struct usb_device_descriptor saf1761_otg_devd = {
2777         .bLength = sizeof(struct usb_device_descriptor),
2778         .bDescriptorType = UDESC_DEVICE,
2779         HSETW(.idVendor, 0x04cc),
2780         HSETW(.idProduct, 0x1761),
2781         .bcdUSB = {0x00, 0x02},
2782         .bDeviceClass = UDCLASS_HUB,
2783         .bDeviceSubClass = UDSUBCLASS_HUB,
2784         .bDeviceProtocol = UDPROTO_FSHUB,
2785         .bMaxPacketSize = 64,
2786         .bcdDevice = {0x00, 0x01},
2787         .iManufacturer = 1,
2788         .iProduct = 2,
2789         .bNumConfigurations = 1,
2790 };
2791
2792 static const struct usb_device_qualifier saf1761_otg_odevd = {
2793         .bLength = sizeof(struct usb_device_qualifier),
2794         .bDescriptorType = UDESC_DEVICE_QUALIFIER,
2795         .bcdUSB = {0x00, 0x02},
2796         .bDeviceClass = UDCLASS_HUB,
2797         .bDeviceSubClass = UDSUBCLASS_HUB,
2798         .bDeviceProtocol = UDPROTO_FSHUB,
2799         .bMaxPacketSize0 = 0,
2800         .bNumConfigurations = 0,
2801 };
2802
2803 static const struct saf1761_otg_config_desc saf1761_otg_confd = {
2804         .confd = {
2805                 .bLength = sizeof(struct usb_config_descriptor),
2806                 .bDescriptorType = UDESC_CONFIG,
2807                 .wTotalLength[0] = sizeof(saf1761_otg_confd),
2808                 .bNumInterface = 1,
2809                 .bConfigurationValue = 1,
2810                 .iConfiguration = 0,
2811                 .bmAttributes = UC_SELF_POWERED,
2812                 .bMaxPower = 0,
2813         },
2814         .ifcd = {
2815                 .bLength = sizeof(struct usb_interface_descriptor),
2816                 .bDescriptorType = UDESC_INTERFACE,
2817                 .bNumEndpoints = 1,
2818                 .bInterfaceClass = UICLASS_HUB,
2819                 .bInterfaceSubClass = UISUBCLASS_HUB,
2820                 .bInterfaceProtocol = 0,
2821         },
2822
2823         .endpd = {
2824                 .bLength = sizeof(struct usb_endpoint_descriptor),
2825                 .bDescriptorType = UDESC_ENDPOINT,
2826                 .bEndpointAddress = (UE_DIR_IN | SAF1761_OTG_INTR_ENDPT),
2827                 .bmAttributes = UE_INTERRUPT,
2828                 .wMaxPacketSize[0] = 8,
2829                 .bInterval = 255,
2830         },
2831 };
2832
2833 static const struct usb_hub_descriptor_min saf1761_otg_hubd = {
2834         .bDescLength = sizeof(saf1761_otg_hubd),
2835         .bDescriptorType = UDESC_HUB,
2836         .bNbrPorts = SOTG_NUM_PORTS,
2837         HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
2838         .bPwrOn2PwrGood = 50,
2839         .bHubContrCurrent = 0,
2840         .DeviceRemovable = {0},         /* port is removable */
2841 };
2842
2843 #define STRING_VENDOR \
2844   "N\0X\0P"
2845
2846 #define STRING_PRODUCT \
2847   "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
2848
2849 USB_MAKE_STRING_DESC(STRING_VENDOR, saf1761_otg_vendor);
2850 USB_MAKE_STRING_DESC(STRING_PRODUCT, saf1761_otg_product);
2851
2852 static usb_error_t
2853 saf1761_otg_roothub_exec(struct usb_device *udev,
2854     struct usb_device_request *req, const void **pptr, uint16_t *plength)
2855 {
2856         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(udev->bus);
2857         const void *ptr;
2858         uint16_t len;
2859         uint16_t value;
2860         uint16_t index;
2861         uint32_t temp;
2862         uint32_t i;
2863         usb_error_t err;
2864
2865         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2866
2867         /* buffer reset */
2868         ptr = (const void *)&sc->sc_hub_temp;
2869         len = 0;
2870         err = 0;
2871
2872         value = UGETW(req->wValue);
2873         index = UGETW(req->wIndex);
2874
2875         /* demultiplex the control request */
2876
2877         switch (req->bmRequestType) {
2878         case UT_READ_DEVICE:
2879                 switch (req->bRequest) {
2880                 case UR_GET_DESCRIPTOR:
2881                         goto tr_handle_get_descriptor;
2882                 case UR_GET_CONFIG:
2883                         goto tr_handle_get_config;
2884                 case UR_GET_STATUS:
2885                         goto tr_handle_get_status;
2886                 default:
2887                         goto tr_stalled;
2888                 }
2889                 break;
2890
2891         case UT_WRITE_DEVICE:
2892                 switch (req->bRequest) {
2893                 case UR_SET_ADDRESS:
2894                         goto tr_handle_set_address;
2895                 case UR_SET_CONFIG:
2896                         goto tr_handle_set_config;
2897                 case UR_CLEAR_FEATURE:
2898                         goto tr_valid;  /* nop */
2899                 case UR_SET_DESCRIPTOR:
2900                         goto tr_valid;  /* nop */
2901                 case UR_SET_FEATURE:
2902                 default:
2903                         goto tr_stalled;
2904                 }
2905                 break;
2906
2907         case UT_WRITE_ENDPOINT:
2908                 switch (req->bRequest) {
2909                 case UR_CLEAR_FEATURE:
2910                         switch (UGETW(req->wValue)) {
2911                         case UF_ENDPOINT_HALT:
2912                                 goto tr_handle_clear_halt;
2913                         case UF_DEVICE_REMOTE_WAKEUP:
2914                                 goto tr_handle_clear_wakeup;
2915                         default:
2916                                 goto tr_stalled;
2917                         }
2918                         break;
2919                 case UR_SET_FEATURE:
2920                         switch (UGETW(req->wValue)) {
2921                         case UF_ENDPOINT_HALT:
2922                                 goto tr_handle_set_halt;
2923                         case UF_DEVICE_REMOTE_WAKEUP:
2924                                 goto tr_handle_set_wakeup;
2925                         default:
2926                                 goto tr_stalled;
2927                         }
2928                         break;
2929                 case UR_SYNCH_FRAME:
2930                         goto tr_valid;  /* nop */
2931                 default:
2932                         goto tr_stalled;
2933                 }
2934                 break;
2935
2936         case UT_READ_ENDPOINT:
2937                 switch (req->bRequest) {
2938                 case UR_GET_STATUS:
2939                         goto tr_handle_get_ep_status;
2940                 default:
2941                         goto tr_stalled;
2942                 }
2943                 break;
2944
2945         case UT_WRITE_INTERFACE:
2946                 switch (req->bRequest) {
2947                 case UR_SET_INTERFACE:
2948                         goto tr_handle_set_interface;
2949                 case UR_CLEAR_FEATURE:
2950                         goto tr_valid;  /* nop */
2951                 case UR_SET_FEATURE:
2952                 default:
2953                         goto tr_stalled;
2954                 }
2955                 break;
2956
2957         case UT_READ_INTERFACE:
2958                 switch (req->bRequest) {
2959                 case UR_GET_INTERFACE:
2960                         goto tr_handle_get_interface;
2961                 case UR_GET_STATUS:
2962                         goto tr_handle_get_iface_status;
2963                 default:
2964                         goto tr_stalled;
2965                 }
2966                 break;
2967
2968         case UT_WRITE_CLASS_INTERFACE:
2969         case UT_WRITE_VENDOR_INTERFACE:
2970                 /* XXX forward */
2971                 break;
2972
2973         case UT_READ_CLASS_INTERFACE:
2974         case UT_READ_VENDOR_INTERFACE:
2975                 /* XXX forward */
2976                 break;
2977
2978         case UT_WRITE_CLASS_DEVICE:
2979                 switch (req->bRequest) {
2980                 case UR_CLEAR_FEATURE:
2981                         goto tr_valid;
2982                 case UR_SET_DESCRIPTOR:
2983                 case UR_SET_FEATURE:
2984                         break;
2985                 default:
2986                         goto tr_stalled;
2987                 }
2988                 break;
2989
2990         case UT_WRITE_CLASS_OTHER:
2991                 switch (req->bRequest) {
2992                 case UR_CLEAR_FEATURE:
2993                         if (index == SOTG_HOST_PORT_NUM)
2994                                 goto tr_handle_clear_port_feature_host;
2995                         else if (index == SOTG_DEVICE_PORT_NUM)
2996                                 goto tr_handle_clear_port_feature_device;
2997                         else
2998                                 goto tr_stalled;
2999                 case UR_SET_FEATURE:
3000                         if (index == SOTG_HOST_PORT_NUM)
3001                                 goto tr_handle_set_port_feature_host;
3002                         else if (index == SOTG_DEVICE_PORT_NUM)
3003                                 goto tr_handle_set_port_feature_device;
3004                         else
3005                                 goto tr_stalled;
3006                 case UR_CLEAR_TT_BUFFER:
3007                 case UR_RESET_TT:
3008                 case UR_STOP_TT:
3009                         goto tr_valid;
3010
3011                 default:
3012                         goto tr_stalled;
3013                 }
3014                 break;
3015
3016         case UT_READ_CLASS_OTHER:
3017                 switch (req->bRequest) {
3018                 case UR_GET_TT_STATE:
3019                         goto tr_handle_get_tt_state;
3020                 case UR_GET_STATUS:
3021                         if (index == SOTG_HOST_PORT_NUM)
3022                                 goto tr_handle_get_port_status_host;
3023                         else if (index == SOTG_DEVICE_PORT_NUM)
3024                                 goto tr_handle_get_port_status_device;
3025                         else
3026                                 goto tr_stalled;
3027                 default:
3028                         goto tr_stalled;
3029                 }
3030                 break;
3031
3032         case UT_READ_CLASS_DEVICE:
3033                 switch (req->bRequest) {
3034                 case UR_GET_DESCRIPTOR:
3035                         goto tr_handle_get_class_descriptor;
3036                 case UR_GET_STATUS:
3037                         goto tr_handle_get_class_status;
3038
3039                 default:
3040                         goto tr_stalled;
3041                 }
3042                 break;
3043         default:
3044                 goto tr_stalled;
3045         }
3046         goto tr_valid;
3047
3048 tr_handle_get_descriptor:
3049         switch (value >> 8) {
3050         case UDESC_DEVICE:
3051                 if (value & 0xff)
3052                         goto tr_stalled;
3053                 len = sizeof(saf1761_otg_devd);
3054                 ptr = (const void *)&saf1761_otg_devd;
3055                 goto tr_valid;
3056         case UDESC_DEVICE_QUALIFIER:
3057                 if (value & 0xff)
3058                         goto tr_stalled;
3059                 len = sizeof(saf1761_otg_odevd);
3060                 ptr = (const void *)&saf1761_otg_odevd;
3061                 goto tr_valid;
3062         case UDESC_CONFIG:
3063                 if (value & 0xff)
3064                         goto tr_stalled;
3065                 len = sizeof(saf1761_otg_confd);
3066                 ptr = (const void *)&saf1761_otg_confd;
3067                 goto tr_valid;
3068         case UDESC_STRING:
3069                 switch (value & 0xff) {
3070                 case 0:         /* Language table */
3071                         len = sizeof(usb_string_lang_en);
3072                         ptr = (const void *)&usb_string_lang_en;
3073                         goto tr_valid;
3074
3075                 case 1:         /* Vendor */
3076                         len = sizeof(saf1761_otg_vendor);
3077                         ptr = (const void *)&saf1761_otg_vendor;
3078                         goto tr_valid;
3079
3080                 case 2:         /* Product */
3081                         len = sizeof(saf1761_otg_product);
3082                         ptr = (const void *)&saf1761_otg_product;
3083                         goto tr_valid;
3084                 default:
3085                         break;
3086                 }
3087                 break;
3088         default:
3089                 goto tr_stalled;
3090         }
3091         goto tr_stalled;
3092
3093 tr_handle_get_config:
3094         len = 1;
3095         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
3096         goto tr_valid;
3097
3098 tr_handle_get_status:
3099         len = 2;
3100         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
3101         goto tr_valid;
3102
3103 tr_handle_set_address:
3104         if (value & 0xFF00)
3105                 goto tr_stalled;
3106
3107         sc->sc_rt_addr = value;
3108         goto tr_valid;
3109
3110 tr_handle_set_config:
3111         if (value >= 2)
3112                 goto tr_stalled;
3113         sc->sc_conf = value;
3114         goto tr_valid;
3115
3116 tr_handle_get_interface:
3117         len = 1;
3118         sc->sc_hub_temp.wValue[0] = 0;
3119         goto tr_valid;
3120
3121 tr_handle_get_tt_state:
3122 tr_handle_get_class_status:
3123 tr_handle_get_iface_status:
3124 tr_handle_get_ep_status:
3125         len = 2;
3126         USETW(sc->sc_hub_temp.wValue, 0);
3127         goto tr_valid;
3128
3129 tr_handle_set_halt:
3130 tr_handle_set_interface:
3131 tr_handle_set_wakeup:
3132 tr_handle_clear_wakeup:
3133 tr_handle_clear_halt:
3134         goto tr_valid;
3135
3136 tr_handle_clear_port_feature_device:
3137         DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
3138
3139         switch (value) {
3140         case UHF_PORT_SUSPEND:
3141                 saf1761_otg_wakeup_peer(sc);
3142                 break;
3143
3144         case UHF_PORT_ENABLE:
3145                 sc->sc_flags.port_enabled = 0;
3146                 break;
3147
3148         case UHF_PORT_TEST:
3149         case UHF_PORT_INDICATOR:
3150         case UHF_C_PORT_ENABLE:
3151         case UHF_C_PORT_OVER_CURRENT:
3152         case UHF_C_PORT_RESET:
3153                 /* nops */
3154                 break;
3155         case UHF_PORT_POWER:
3156                 sc->sc_flags.port_powered = 0;
3157                 saf1761_otg_pull_down(sc);
3158                 break;
3159         case UHF_C_PORT_CONNECTION:
3160                 sc->sc_flags.change_connect = 0;
3161                 break;
3162         case UHF_C_PORT_SUSPEND:
3163                 sc->sc_flags.change_suspend = 0;
3164                 break;
3165         default:
3166                 err = USB_ERR_IOERROR;
3167                 goto tr_valid;
3168         }
3169         goto tr_valid;
3170
3171 tr_handle_clear_port_feature_host:
3172         DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
3173
3174         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3175
3176         switch (value) {
3177         case UHF_PORT_ENABLE:
3178                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PED);
3179                 break;
3180         case UHF_PORT_SUSPEND:
3181                 if ((temp & SOTG_PORTSC1_SUSP) && (!(temp & SOTG_PORTSC1_FPR)))
3182                         SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_FPR);
3183
3184                 /* wait 20ms for resume sequence to complete */
3185                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3186
3187                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~(SOTG_PORTSC1_SUSP |
3188                     SOTG_PORTSC1_FPR | SOTG_PORTSC1_LS /* High Speed */ ));
3189
3190                 /* 4ms settle time */
3191                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3192                 break;
3193         case UHF_PORT_INDICATOR:
3194                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PIC);
3195                 break;
3196         case UHF_PORT_TEST:
3197         case UHF_C_PORT_ENABLE:
3198         case UHF_C_PORT_OVER_CURRENT:
3199         case UHF_C_PORT_RESET:
3200         case UHF_C_PORT_SUSPEND:
3201                 /* NOPs */
3202                 break;
3203         case UHF_PORT_POWER:
3204                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PP);
3205                 break;
3206         case UHF_C_PORT_CONNECTION:
3207                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_ECSC);
3208                 break;
3209         default:
3210                 err = USB_ERR_IOERROR;
3211                 goto tr_valid;
3212         }
3213         goto tr_valid;
3214
3215 tr_handle_set_port_feature_device:
3216         DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
3217
3218         switch (value) {
3219         case UHF_PORT_ENABLE:
3220                 sc->sc_flags.port_enabled = 1;
3221                 break;
3222         case UHF_PORT_SUSPEND:
3223         case UHF_PORT_RESET:
3224         case UHF_PORT_TEST:
3225         case UHF_PORT_INDICATOR:
3226                 /* nops */
3227                 break;
3228         case UHF_PORT_POWER:
3229                 sc->sc_flags.port_powered = 1;
3230                 break;
3231         default:
3232                 err = USB_ERR_IOERROR;
3233                 goto tr_valid;
3234         }
3235         goto tr_valid;
3236
3237 tr_handle_set_port_feature_host:
3238         DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
3239
3240         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3241
3242         switch (value) {
3243         case UHF_PORT_ENABLE:
3244                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PED);
3245                 break;
3246         case UHF_PORT_SUSPEND:
3247                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_SUSP);
3248                 break;
3249         case UHF_PORT_RESET:
3250                 DPRINTFN(6, "reset port %d\n", index);
3251
3252                 /* Start reset sequence. */
3253                 temp &= ~(SOTG_PORTSC1_PED | SOTG_PORTSC1_PR);
3254
3255                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PR);
3256
3257                 /* Wait for reset to complete. */
3258                 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3259                     USB_MS_TO_TICKS(usb_port_root_reset_delay));
3260
3261                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp);
3262
3263                 /* Wait for HC to complete reset. */
3264                 usb_pause_mtx(&sc->sc_bus.bus_mtx, USB_MS_TO_TICKS(2));
3265
3266                 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3267
3268                 DPRINTF("After reset, status=0x%08x\n", temp);
3269                 if (temp & SOTG_PORTSC1_PR) {
3270                         device_printf(sc->sc_bus.bdev, "port reset timeout\n");
3271                         err = USB_ERR_TIMEOUT;
3272                         goto tr_valid;
3273                 }
3274                 if (!(temp & SOTG_PORTSC1_PED)) {
3275                         /* Not a high speed device, give up ownership.*/
3276                         SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PO);
3277                         break;
3278                 }
3279                 sc->sc_isreset = 1;
3280                 DPRINTF("port %d reset, status = 0x%08x\n", index, temp);
3281                 break;
3282         case UHF_PORT_POWER:
3283                 DPRINTFN(3, "set port power %d\n", index);
3284                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PP);
3285                 break;
3286
3287         case UHF_PORT_TEST:
3288                 DPRINTFN(3, "set port test %d\n", index);
3289                 break;
3290
3291         case UHF_PORT_INDICATOR:
3292                 DPRINTFN(3, "set port ind %d\n", index);
3293                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PIC);
3294                 break;
3295         default:
3296                 err = USB_ERR_IOERROR;
3297                 goto tr_valid;
3298         }
3299         goto tr_valid;
3300
3301 tr_handle_get_port_status_device:
3302
3303         DPRINTFN(9, "UR_GET_PORT_STATUS on port %d\n", index);
3304
3305         if (sc->sc_flags.status_vbus) {
3306                 saf1761_otg_pull_up(sc);
3307         } else {
3308                 saf1761_otg_pull_down(sc);
3309         }
3310
3311         /* Select FULL-speed and Device Side Mode */
3312
3313         value = UPS_PORT_MODE_DEVICE;
3314
3315         if (sc->sc_flags.port_powered)
3316                 value |= UPS_PORT_POWER;
3317
3318         if (sc->sc_flags.port_enabled)
3319                 value |= UPS_PORT_ENABLED;
3320
3321         if (sc->sc_flags.status_vbus &&
3322             sc->sc_flags.status_bus_reset)
3323                 value |= UPS_CURRENT_CONNECT_STATUS;
3324
3325         if (sc->sc_flags.status_suspend)
3326                 value |= UPS_SUSPEND;
3327
3328         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
3329
3330         value = 0;
3331
3332         if (sc->sc_flags.change_connect)
3333                 value |= UPS_C_CONNECT_STATUS;
3334
3335         if (sc->sc_flags.change_suspend)
3336                 value |= UPS_C_SUSPEND;
3337
3338         USETW(sc->sc_hub_temp.ps.wPortChange, value);
3339         len = sizeof(sc->sc_hub_temp.ps);
3340         goto tr_valid;
3341
3342 tr_handle_get_port_status_host:
3343
3344         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3345
3346         DPRINTFN(9, "UR_GET_PORT_STATUS on port %d = 0x%08x\n", index, temp);
3347
3348         i = UPS_HIGH_SPEED;
3349
3350         if (temp & SOTG_PORTSC1_ECCS)
3351                 i |= UPS_CURRENT_CONNECT_STATUS;
3352         if (temp & SOTG_PORTSC1_PED)
3353                 i |= UPS_PORT_ENABLED;
3354         if ((temp & SOTG_PORTSC1_SUSP) && !(temp & SOTG_PORTSC1_FPR))
3355                 i |= UPS_SUSPEND;
3356         if (temp & SOTG_PORTSC1_PR)
3357                 i |= UPS_RESET;
3358         if (temp & SOTG_PORTSC1_PP)
3359                 i |= UPS_PORT_POWER;
3360
3361         USETW(sc->sc_hub_temp.ps.wPortStatus, i);
3362         i = 0;
3363
3364         if (temp & SOTG_PORTSC1_ECSC)
3365                 i |= UPS_C_CONNECT_STATUS;
3366         if (temp & SOTG_PORTSC1_FPR)
3367                 i |= UPS_C_SUSPEND;
3368         if (sc->sc_isreset)
3369                 i |= UPS_C_PORT_RESET;
3370         USETW(sc->sc_hub_temp.ps.wPortChange, i);
3371         len = sizeof(sc->sc_hub_temp.ps);
3372         goto tr_valid;
3373
3374 tr_handle_get_class_descriptor:
3375         if (value & 0xFF)
3376                 goto tr_stalled;
3377         ptr = (const void *)&saf1761_otg_hubd;
3378         len = sizeof(saf1761_otg_hubd);
3379         goto tr_valid;
3380
3381 tr_stalled:
3382         err = USB_ERR_STALLED;
3383 tr_valid:
3384         *plength = len;
3385         *pptr = ptr;
3386         return (err);
3387 }
3388
3389 static void
3390 saf1761_otg_xfer_setup(struct usb_setup_params *parm)
3391 {
3392         struct saf1761_otg_softc *sc;
3393         struct usb_xfer *xfer;
3394         void *last_obj;
3395         uint32_t dw1;
3396         uint32_t ntd;
3397         uint32_t n;
3398         uint8_t ep_no;
3399         uint8_t ep_type;
3400
3401         sc = SAF1761_OTG_BUS2SC(parm->udev->bus);
3402         xfer = parm->curr_xfer;
3403
3404         /*
3405          * NOTE: This driver does not use any of the parameters that
3406          * are computed from the following values. Just set some
3407          * reasonable dummies:
3408          */
3409         parm->hc_max_packet_size = 0x500;
3410         parm->hc_max_packet_count = 1;
3411         parm->hc_max_frame_size = 0x500;
3412
3413         usbd_transfer_setup_sub(parm);
3414
3415         /*
3416          * Compute maximum number of TDs:
3417          */
3418         ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
3419
3420         if (ep_type == UE_CONTROL) {
3421
3422                 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
3423
3424         } else {
3425                 ntd = xfer->nframes + 1 /* SYNC */ ;
3426         }
3427
3428         /*
3429          * check if "usbd_transfer_setup_sub" set an error
3430          */
3431         if (parm->err)
3432                 return;
3433
3434         /*
3435          * allocate transfer descriptors
3436          */
3437         last_obj = NULL;
3438
3439         ep_no = xfer->endpointno & UE_ADDR;
3440
3441         /*
3442          * Check profile stuff
3443          */
3444         if (parm->udev->flags.usb_mode == USB_MODE_DEVICE) {
3445                 const struct usb_hw_ep_profile *pf;
3446
3447                 saf1761_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
3448
3449                 if (pf == NULL) {
3450                         /* should not happen */
3451                         parm->err = USB_ERR_INVAL;
3452                         return;
3453                 }
3454         }
3455
3456         dw1 = (xfer->address << 3) | (ep_type << 12);
3457
3458         switch (parm->udev->speed) {
3459         case USB_SPEED_FULL:
3460         case USB_SPEED_LOW:
3461                 /* check if root HUB port is running High Speed */
3462                 if (parm->udev->parent_hs_hub != NULL) {
3463                         dw1 |= SOTG_PTD_DW1_ENABLE_SPLIT;
3464                         dw1 |= (parm->udev->hs_port_no << 18);
3465                         dw1 |= (parm->udev->hs_hub_addr << 25);
3466                         if (parm->udev->speed == USB_SPEED_LOW)
3467                                 dw1 |= (1 << 17);
3468                 }
3469                 break;
3470         default:
3471                 break;
3472         }
3473
3474         /* align data */
3475         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
3476
3477         for (n = 0; n != ntd; n++) {
3478
3479                 struct saf1761_otg_td *td;
3480
3481                 if (parm->buf) {
3482
3483                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
3484
3485                         /* init TD */
3486                         td->max_packet_size = xfer->max_packet_size;
3487                         td->ep_index = ep_no;
3488                         td->ep_type = ep_type;
3489                         td->dw1_value = dw1;
3490                         td->uframe = 0;
3491
3492                         if (ep_type == UE_INTERRUPT) {
3493                                 if (xfer->interval > 32)
3494                                         td->interval = (32 / 2) << 3;
3495                                 else
3496                                         td->interval = (xfer->interval / 2) << 3;
3497                         } else {
3498                                 td->interval = 0;
3499                         }
3500                         td->obj_next = last_obj;
3501
3502                         last_obj = td;
3503                 }
3504                 parm->size[0] += sizeof(*td);
3505         }
3506
3507         xfer->td_start[0] = last_obj;
3508 }
3509
3510 static void
3511 saf1761_otg_xfer_unsetup(struct usb_xfer *xfer)
3512 {
3513 }
3514
3515 static void
3516 saf1761_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3517     struct usb_endpoint *ep)
3518 {
3519         uint16_t mps;
3520
3521         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3522             ep, udev->address,
3523             edesc->bEndpointAddress, udev->flags.usb_mode);
3524
3525         if (udev->parent_hub == NULL) {
3526                 /* root HUB has special endpoint handling */
3527                 return;
3528         }
3529
3530         /* Verify wMaxPacketSize */
3531         mps = UGETW(edesc->wMaxPacketSize);
3532         if (udev->speed == USB_SPEED_HIGH) {
3533                 if ((mps >> 11) & 3) {
3534                         DPRINTF("A packet multiplier different from "
3535                             "1 is not supported\n");
3536                         return;
3537                 }
3538         }
3539         if (mps > SOTG_HS_MAX_PACKET_SIZE) {
3540                 DPRINTF("Packet size %d bigger than %d\n",
3541                     (int)mps, SOTG_HS_MAX_PACKET_SIZE);
3542                 return;
3543         }
3544         if (udev->flags.usb_mode == USB_MODE_DEVICE) {
3545                 if (udev->speed != USB_SPEED_FULL &&
3546                     udev->speed != USB_SPEED_HIGH) {
3547                         /* not supported */
3548                         return;
3549                 }
3550                 switch (edesc->bmAttributes & UE_XFERTYPE) {
3551                 case UE_ISOCHRONOUS:
3552                         ep->methods = &saf1761_otg_device_isoc_methods;
3553                         break;
3554                 default:
3555                         ep->methods = &saf1761_otg_non_isoc_methods;
3556                         break;
3557                 }
3558         } else {
3559                 switch (edesc->bmAttributes & UE_XFERTYPE) {
3560                 case UE_ISOCHRONOUS:
3561                         ep->methods = &saf1761_otg_host_isoc_methods;
3562                         break;
3563                 default:
3564                         ep->methods = &saf1761_otg_non_isoc_methods;
3565                         break;
3566                 }
3567         }
3568 }
3569
3570 static void
3571 saf1761_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3572 {
3573         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
3574
3575         switch (state) {
3576         case USB_HW_POWER_SUSPEND:
3577                 saf1761_otg_suspend(sc);
3578                 break;
3579         case USB_HW_POWER_SHUTDOWN:
3580                 saf1761_otg_uninit(sc);
3581                 break;
3582         case USB_HW_POWER_RESUME:
3583                 saf1761_otg_resume(sc);
3584                 break;
3585         default:
3586                 break;
3587         }
3588 }
3589
3590 static void
3591 saf1761_otg_device_resume(struct usb_device *udev)
3592 {
3593         struct saf1761_otg_softc *sc;
3594         struct saf1761_otg_td *td;
3595         struct usb_xfer *xfer;
3596         uint8_t x;
3597
3598         DPRINTF("\n");
3599
3600         if (udev->flags.usb_mode != USB_MODE_HOST)
3601                 return;
3602
3603         sc = SAF1761_OTG_BUS2SC(udev->bus);
3604
3605         USB_BUS_LOCK(&sc->sc_bus);
3606         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3607
3608         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3609
3610                 if (xfer->xroot->udev != udev)
3611                         continue;
3612
3613                 td = xfer->td_transfer_cache;
3614                 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3615                         continue;
3616
3617                 switch (td->ep_type) {
3618                 case UE_INTERRUPT:
3619                         x = td->channel - 32;
3620                         sc->sc_host_intr_suspend_map &= ~(1U << x);
3621                         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3622                             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3623                         break;
3624                 case UE_ISOCHRONOUS:
3625                         x = td->channel;
3626                         sc->sc_host_isoc_suspend_map &= ~(1U << x);
3627                         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3628                             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3629                         break;
3630                 default:
3631                         x = td->channel - 64;
3632                         sc->sc_host_async_suspend_map &= ~(1U << x);
3633                         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3634                             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3635                         break;
3636                 }
3637         }
3638
3639         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3640         USB_BUS_UNLOCK(&sc->sc_bus);
3641
3642         /* poll all transfers again to restart resumed ones */
3643         saf1761_otg_do_poll(&sc->sc_bus);
3644 }
3645
3646 static void
3647 saf1761_otg_device_suspend(struct usb_device *udev)
3648 {
3649         struct saf1761_otg_softc *sc;
3650         struct saf1761_otg_td *td;
3651         struct usb_xfer *xfer;
3652         uint8_t x;
3653
3654         DPRINTF("\n");
3655
3656         if (udev->flags.usb_mode != USB_MODE_HOST)
3657                 return;
3658
3659         sc = SAF1761_OTG_BUS2SC(udev->bus);
3660
3661         USB_BUS_LOCK(&sc->sc_bus);
3662         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3663
3664         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3665
3666                 if (xfer->xroot->udev != udev)
3667                         continue;
3668
3669                 td = xfer->td_transfer_cache;
3670                 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3671                         continue;
3672
3673                 switch (td->ep_type) {
3674                 case UE_INTERRUPT:
3675                         x = td->channel - 32;
3676                         sc->sc_host_intr_suspend_map |= (1U << x);
3677                         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3678                             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3679                         break;
3680                 case UE_ISOCHRONOUS:
3681                         x = td->channel;
3682                         sc->sc_host_isoc_suspend_map |= (1U << x);
3683                         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3684                             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3685                         break;
3686                 default:
3687                         x = td->channel - 64;
3688                         sc->sc_host_async_suspend_map |= (1U << x);
3689                         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3690                             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3691                         break;
3692                 }
3693         }
3694
3695         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3696         USB_BUS_UNLOCK(&sc->sc_bus);
3697 }
3698
3699 static const struct usb_bus_methods saf1761_otg_bus_methods =
3700 {
3701         .endpoint_init = &saf1761_otg_ep_init,
3702         .xfer_setup = &saf1761_otg_xfer_setup,
3703         .xfer_unsetup = &saf1761_otg_xfer_unsetup,
3704         .get_hw_ep_profile = &saf1761_otg_get_hw_ep_profile,
3705         .xfer_stall = &saf1761_otg_xfer_stall,
3706         .set_stall = &saf1761_otg_set_stall,
3707         .clear_stall = &saf1761_otg_clear_stall,
3708         .roothub_exec = &saf1761_otg_roothub_exec,
3709         .xfer_poll = &saf1761_otg_do_poll,
3710         .set_hw_power_sleep = saf1761_otg_set_hw_power_sleep,
3711         .device_resume = &saf1761_otg_device_resume,
3712         .device_suspend = &saf1761_otg_device_suspend,
3713 };