sys/dev/usb/controller/saf1761_otg.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2014 Hans Petter Selasky <hselasky@FreeBSD.org>
   4  * All rights reserved.
   5  *
   6  * This software was developed by SRI International and the University of
   7  * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
   8  * ("CTSRD"), as part of the DARPA CRASH research programme.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * This file contains the driver for the SAF1761 series USB OTG
  34  * controller.
  35  *
  36  * Datasheet is available from:
  37  * http://www.nxp.com/products/automotive/multimedia/usb/SAF1761BE.html
  38  */
  39
  40 #ifdef USB_GLOBAL_INCLUDE_FILE
  41 #include USB_GLOBAL_INCLUDE_FILE
  42 #else
  43 #include <sys/stdint.h>
  44 #include <sys/stddef.h>
  45 #include <sys/param.h>
  46 #include <sys/queue.h>
  47 #include <sys/types.h>
  48 #include <sys/systm.h>
  49 #include <sys/kernel.h>
  50 #include <sys/bus.h>
  51 #include <sys/module.h>
  52 #include <sys/lock.h>
  53 #include <sys/mutex.h>
  54 #include <sys/condvar.h>
  55 #include <sys/sysctl.h>
  56 #include <sys/sx.h>
  57 #include <sys/unistd.h>
  58 #include <sys/callout.h>
  59 #include <sys/malloc.h>
  60 #include <sys/priv.h>
  61
  62 #include <dev/usb/usb.h>
  63 #include <dev/usb/usbdi.h>
  64
  65 #define USB_DEBUG_VAR saf1761_otg_debug
  66
  67 #include <dev/usb/usb_core.h>
  68 #include <dev/usb/usb_debug.h>
  69 #include <dev/usb/usb_busdma.h>
  70 #include <dev/usb/usb_process.h>
  71 #include <dev/usb/usb_transfer.h>
  72 #include <dev/usb/usb_device.h>
  73 #include <dev/usb/usb_hub.h>
  74 #include <dev/usb/usb_util.h>
  75
  76 #include <dev/usb/usb_controller.h>
  77 #include <dev/usb/usb_bus.h>
  78 #endif                                  /* USB_GLOBAL_INCLUDE_FILE */
  79
  80 #include <dev/usb/controller/saf1761_otg.h>
  81 #include <dev/usb/controller/saf1761_otg_reg.h>
  82
  83 #define SAF1761_OTG_BUS2SC(bus) \
  84    ((struct saf1761_otg_softc *)(((uint8_t *)(bus)) - \
  85     ((uint8_t *)&(((struct saf1761_otg_softc *)0)->sc_bus))))
  86
  87 #define SAF1761_OTG_PC2UDEV(pc) \
  88    (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev)
  89
  90 #define SAF1761_DCINTERRUPT_THREAD_IRQ                  \
  91   (SOTG_DCINTERRUPT_IEVBUS | SOTG_DCINTERRUPT_IEBRST |  \
  92   SOTG_DCINTERRUPT_IERESM | SOTG_DCINTERRUPT_IESUSP)
  93
  94 #ifdef USB_DEBUG
  95 static int saf1761_otg_debug = 0;
  96 static int saf1761_otg_forcefs = 0;
  97
  98 static
  99 SYSCTL_NODE(_hw_usb, OID_AUTO, saf1761_otg, CTLFLAG_RW, 0,
 100     "USB SAF1761 DCI");
 101
 102 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, debug, CTLFLAG_RW,
 103     &saf1761_otg_debug, 0, "SAF1761 DCI debug level");
 104 SYSCTL_INT(_hw_usb_saf1761_otg, OID_AUTO, forcefs, CTLFLAG_RW,
 105     &saf1761_otg_forcefs, 0, "SAF1761 DCI force FULL speed");
 106 #endif
 107
 108 #define SAF1761_OTG_INTR_ENDPT 1
 109
 110 /* prototypes */
 111
 112 static const struct usb_bus_methods saf1761_otg_bus_methods;
 113 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods;
 114 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods;
 115
 116 static saf1761_otg_cmd_t saf1761_host_setup_tx;
 117 static saf1761_otg_cmd_t saf1761_host_bulk_data_rx;
 118 static saf1761_otg_cmd_t saf1761_host_bulk_data_tx;
 119 static saf1761_otg_cmd_t saf1761_host_intr_data_rx;
 120 static saf1761_otg_cmd_t saf1761_host_intr_data_tx;
 121 static saf1761_otg_cmd_t saf1761_host_isoc_data_rx;
 122 static saf1761_otg_cmd_t saf1761_host_isoc_data_tx;
 123 static saf1761_otg_cmd_t saf1761_device_setup_rx;
 124 static saf1761_otg_cmd_t saf1761_device_data_rx;
 125 static saf1761_otg_cmd_t saf1761_device_data_tx;
 126 static saf1761_otg_cmd_t saf1761_device_data_tx_sync;
 127 static void saf1761_otg_device_done(struct usb_xfer *, usb_error_t);
 128 static void saf1761_otg_do_poll(struct usb_bus *);
 129 static void saf1761_otg_standard_done(struct usb_xfer *);
 130 static void saf1761_otg_intr_set(struct usb_xfer *, uint8_t);
 131 static void saf1761_otg_root_intr(struct saf1761_otg_softc *);
 132
 133 /*
 134  * Here is a list of what the SAF1761 chip can support. The main
 135  * limitation is that the sum of the buffer sizes must be less than
 136  * 8192 bytes.
 137  */
 138 static const struct usb_hw_ep_profile saf1761_otg_ep_profile[] = {
 139
 140         [0] = {
 141                 .max_in_frame_size = 64,
 142                 .max_out_frame_size = 64,
 143                 .is_simplex = 0,
 144                 .support_control = 1,
 145         },
 146         [1] = {
 147                 .max_in_frame_size = SOTG_HS_MAX_PACKET_SIZE,
 148                 .max_out_frame_size = SOTG_HS_MAX_PACKET_SIZE,
 149                 .is_simplex = 0,
 150                 .support_interrupt = 1,
 151                 .support_bulk = 1,
 152                 .support_isochronous = 1,
 153                 .support_in = 1,
 154                 .support_out = 1,
 155         },
 156 };
 157
 158 static void
 159 saf1761_otg_get_hw_ep_profile(struct usb_device *udev,
 160     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 161 {
 162         if (ep_addr == 0) {
 163                 *ppf = saf1761_otg_ep_profile + 0;
 164         } else if (ep_addr < 8) {
 165                 *ppf = saf1761_otg_ep_profile + 1;
 166         } else {
 167                 *ppf = NULL;
 168         }
 169 }
 170
 171 static void
 172 saf1761_otg_pull_up(struct saf1761_otg_softc *sc)
 173 {
 174         /* activate pullup on D+, if possible */
 175
 176         if (!sc->sc_flags.d_pulled_up && sc->sc_flags.port_powered) {
 177                 DPRINTF("\n");
 178
 179                 sc->sc_flags.d_pulled_up = 1;
 180         }
 181 }
 182
 183 static void
 184 saf1761_otg_pull_down(struct saf1761_otg_softc *sc)
 185 {
 186         /* release pullup on D+, if possible */
 187
 188         if (sc->sc_flags.d_pulled_up) {
 189                 DPRINTF("\n");
 190
 191                 sc->sc_flags.d_pulled_up = 0;
 192         }
 193 }
 194
 195 static void
 196 saf1761_otg_wakeup_peer(struct saf1761_otg_softc *sc)
 197 {
 198         uint16_t temp;
 199
 200         if (!(sc->sc_flags.status_suspend))
 201                 return;
 202
 203         DPRINTFN(5, "\n");
 204
 205         temp = SAF1761_READ_LE_4(sc, SOTG_MODE);
 206         SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp | SOTG_MODE_SNDRSU);
 207         SAF1761_WRITE_LE_4(sc, SOTG_MODE, temp & ~SOTG_MODE_SNDRSU);
 208
 209         /* Wait 8ms for remote wakeup to complete. */
 210         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 211 }
 212
 213 static uint8_t
 214 saf1761_host_channel_alloc(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 215 {
 216         uint32_t x;
 217
 218         if (td->channel < SOTG_HOST_CHANNEL_MAX)
 219                 return (0);
 220
 221         /* check if device is suspended */
 222         if (SAF1761_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0)
 223                 return (1);             /* busy - cannot transfer data */
 224
 225         switch (td->ep_type) {
 226         case UE_INTERRUPT:
 227                 for (x = 0; x != 32; x++) {
 228                         if (sc->sc_host_intr_map & (1 << x))
 229                                 continue;
 230                         sc->sc_host_intr_map |= (1 << x);
 231                         td->channel = 32 + x;
 232                         return (0);
 233                 }
 234                 break;
 235         case UE_ISOCHRONOUS:
 236                 for (x = 0; x != 32; x++) {
 237                         if (sc->sc_host_isoc_map & (1 << x))
 238                                 continue;
 239                         sc->sc_host_isoc_map |= (1 << x);
 240                         td->channel = x;
 241                         return (0);
 242                 }
 243                 break;
 244         default:
 245                 for (x = 0; x != 32; x++) {
 246                         if (sc->sc_host_async_map & (1 << x))
 247                                 continue;
 248                         sc->sc_host_async_map |= (1 << x);
 249                         td->channel = 64 + x;
 250                         return (0);
 251                 }
 252                 break;
 253         }
 254         return (1);
 255 }
 256
 257 static void
 258 saf1761_host_channel_free(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 259 {
 260         uint32_t x;
 261
 262         if (td->channel >= SOTG_HOST_CHANNEL_MAX)
 263                 return;
 264
 265         switch (td->ep_type) {
 266         case UE_INTERRUPT:
 267                 x = td->channel - 32;
 268                 td->channel = SOTG_HOST_CHANNEL_MAX;
 269                 sc->sc_host_intr_map &= ~(1 << x);
 270                 sc->sc_host_intr_suspend_map &= ~(1 << x);
 271                 SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 272                     (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 273                 break;
 274         case UE_ISOCHRONOUS:
 275                 x = td->channel;
 276                 td->channel = SOTG_HOST_CHANNEL_MAX;
 277                 sc->sc_host_isoc_map &= ~(1 << x);
 278                 sc->sc_host_isoc_suspend_map &= ~(1 << x);
 279                 SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
 280                     (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
 281                 break;
 282         default:
 283                 x = td->channel - 64;
 284                 td->channel = SOTG_HOST_CHANNEL_MAX;
 285                 sc->sc_host_async_map &= ~(1 << x);
 286                 sc->sc_host_async_suspend_map &= ~(1 << x);
 287                 SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 288                     (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 289                 break;
 290         }
 291 }
 292
 293 static uint32_t
 294 saf1761_peek_host_memory_le_4(struct saf1761_otg_softc *sc, uint32_t offset)
 295 {
 296         SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
 297         SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
 298         return (SAF1761_READ_LE_4(sc, offset));
 299 }
 300
 301 static void
 302 saf1761_read_host_memory(struct saf1761_otg_softc *sc,
 303     struct saf1761_otg_td *td, uint32_t len)
 304 {
 305         struct usb_page_search buf_res;
 306         uint32_t offset;
 307         uint32_t count;
 308
 309         if (len == 0)
 310                 return;
 311
 312         offset = SOTG_DATA_ADDR(td->channel);
 313         SAF1761_WRITE_LE_4(sc, SOTG_MEMORY_REG, offset);
 314         SAF1761_90NS_DELAY(sc); /* read prefetch time is 90ns */
 315
 316         /* optimised read first */
 317         while (len > 0) {
 318                 usbd_get_page(td->pc, td->offset, &buf_res);
 319
 320                 /* get correct length */
 321                 if (buf_res.length > len)
 322                         buf_res.length = len;
 323
 324                 /* check buffer alignment */
 325                 if (((uintptr_t)buf_res.buffer) & 3)
 326                         break;
 327
 328                 count = buf_res.length & ~3;
 329                 if (count == 0)
 330                         break;
 331
 332                 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 333                     offset, buf_res.buffer, count / 4);
 334
 335                 len -= count;
 336                 offset += count;
 337
 338                 /* update remainder and offset */
 339                 td->remainder -= count;
 340                 td->offset += count;
 341         }
 342
 343         if (len > 0) {
 344                 /* use bounce buffer */
 345                 bus_space_read_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 346                     offset, sc->sc_bounce_buffer, (len + 3) / 4);
 347                 usbd_copy_in(td->pc, td->offset,
 348                     sc->sc_bounce_buffer, len);
 349
 350                 /* update remainder and offset */
 351                 td->remainder -= len;
 352                 td->offset += len;
 353         }
 354 }
 355
 356 static void
 357 saf1761_write_host_memory(struct saf1761_otg_softc *sc,
 358     struct saf1761_otg_td *td, uint32_t len)
 359 {
 360         struct usb_page_search buf_res;
 361         uint32_t offset;
 362         uint32_t count;
 363
 364         if (len == 0)
 365                 return;
 366
 367         offset = SOTG_DATA_ADDR(td->channel);
 368
 369         /* optimised write first */
 370         while (len > 0) {
 371                 usbd_get_page(td->pc, td->offset, &buf_res);
 372
 373                 /* get correct length */
 374                 if (buf_res.length > len)
 375                         buf_res.length = len;
 376
 377                 /* check buffer alignment */
 378                 if (((uintptr_t)buf_res.buffer) & 3)
 379                         break;
 380
 381                 count = buf_res.length & ~3;
 382                 if (count == 0)
 383                         break;
 384
 385                 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 386                     offset, buf_res.buffer, count / 4);
 387
 388                 len -= count;
 389                 offset += count;
 390
 391                 /* update remainder and offset */
 392                 td->remainder -= count;
 393                 td->offset += count;
 394         }
 395         if (len > 0) {
 396                 /* use bounce buffer */
 397                 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
 398                 bus_space_write_region_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 399                     offset, sc->sc_bounce_buffer, (len + 3) / 4);
 400
 401                 /* update remainder and offset */
 402                 td->remainder -= len;
 403                 td->offset += len;
 404         }
 405 }
 406
 407 static uint8_t
 408 saf1761_host_setup_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 409 {
 410         uint32_t pdt_addr;
 411         uint32_t status;
 412         uint32_t count;
 413         uint32_t temp;
 414
 415         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 416                 pdt_addr = SOTG_PTD(td->channel);
 417
 418                 status = saf1761_peek_host_memory_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 419                 if (status == 0)
 420                         status = saf1761_peek_host_memory_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 421
 422                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 423
 424                 if (status & SOTG_PTD_DW3_ACTIVE) {
 425                         goto busy;
 426                 } else if (status & SOTG_PTD_DW3_HALTED) {
 427                         td->error_any = 1;
 428                 }
 429                 goto complete;
 430         }
 431         if (saf1761_host_channel_alloc(sc, td))
 432                 goto busy;
 433
 434         count = 8;
 435
 436         if (count != td->remainder) {
 437                 td->error_any = 1;
 438                 goto complete;
 439         }
 440
 441         saf1761_write_host_memory(sc, td, count);
 442
 443         pdt_addr = SOTG_PTD(td->channel);
 444
 445         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 446         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 447         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 448         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 449
 450         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 451         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 452
 453         temp = SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8;
 454         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 455
 456         temp = td->dw1_value | (2 << 10) /* SETUP PID */ | (td->ep_index >> 1);
 457         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 458
 459         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 460             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 461             (count << 3) /* transfer count */ |
 462             SOTG_PTD_DW0_VALID;
 463         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 464
 465         /* activate PTD */
 466         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 467             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 468
 469         td->toggle = 1;
 470 busy:
 471         return (1);     /* busy */
 472 complete:
 473         saf1761_host_channel_free(sc, td);
 474         return (0);     /* complete */
 475 }
 476
 477 static uint8_t
 478 saf1761_host_bulk_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 479 {
 480         uint32_t pdt_addr;
 481         uint32_t temp;
 482
 483         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 484                 uint32_t status;
 485                 uint32_t count;
 486                 uint8_t got_short;
 487
 488                 pdt_addr = SOTG_PTD(td->channel);
 489
 490                 status = saf1761_peek_host_memory_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 491                 if (status == 0)
 492                         status = saf1761_peek_host_memory_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 493
 494                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 495
 496                 if (status & SOTG_PTD_DW3_ACTIVE) {
 497                         goto busy;
 498                 } else if (status & SOTG_PTD_DW3_HALTED) {
 499                         if (!(status & SOTG_PTD_DW3_ERRORS))
 500                                 td->error_stall = 1;
 501                         td->error_any = 1;
 502                         goto complete;
 503                 }
 504                 count = (status & SOTG_PTD_DW3_XFER_COUNT);
 505                 got_short = 0;
 506
 507                 /* verify the packet byte count */
 508                 if (count != td->max_packet_size) {
 509                         if (count < td->max_packet_size) {
 510                                 /* we have a short packet */
 511                                 td->short_pkt = 1;
 512                                 got_short = 1;
 513                         } else {
 514                                 /* invalid USB packet */
 515                                 td->error_any = 1;
 516                                 goto complete;
 517                         }
 518                 }
 519                 td->toggle ^= 1;
 520
 521                 /* verify the packet byte count */
 522                 if (count > td->remainder) {
 523                         /* invalid USB packet */
 524                         td->error_any = 1;
 525                         goto complete;
 526                 }
 527
 528                 saf1761_read_host_memory(sc, td, count);
 529
 530                 /* check if we are complete */
 531                 if ((td->remainder == 0) || got_short) {
 532                         if (td->short_pkt)
 533                                 goto complete;
 534                         /* else need to receive a zero length packet */
 535                 }
 536                 saf1761_host_channel_free(sc, td);
 537         }
 538         if (saf1761_host_channel_alloc(sc, td))
 539                 goto busy;
 540
 541         /* set toggle, if any */
 542         if (td->set_toggle) {
 543                 td->set_toggle = 0;
 544                 td->toggle = 1;
 545         }
 546
 547         /* receive one more packet */
 548
 549         pdt_addr = SOTG_PTD(td->channel);
 550
 551         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 552         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 553         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 554         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 555
 556         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
 557             SOTG_PTD_DW3_CERR_2;
 558         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 559
 560         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
 561         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 562
 563         temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
 564         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 565
 566         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 567             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 568             (td->max_packet_size << 3) /* transfer count */ |
 569             SOTG_PTD_DW0_VALID;
 570         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 571
 572         /* activate PTD */
 573         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 574             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 575 busy:
 576         return (1);     /* busy */
 577 complete:
 578         saf1761_host_channel_free(sc, td);
 579         return (0);     /* complete */
 580 }
 581
 582 static uint8_t
 583 saf1761_host_bulk_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 584 {
 585         uint32_t pdt_addr;
 586         uint32_t temp;
 587         uint32_t count;
 588
 589         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 590                 uint32_t status;
 591
 592                 pdt_addr = SOTG_PTD(td->channel);
 593
 594                 status = saf1761_peek_host_memory_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 595                 if (status == 0)
 596                         status = saf1761_peek_host_memory_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 597
 598                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 599
 600                 if (status & SOTG_PTD_DW3_ACTIVE) {
 601                         goto busy;
 602                 } else if (status & SOTG_PTD_DW3_HALTED) {
 603                         if (!(status & SOTG_PTD_DW3_ERRORS))
 604                                 td->error_stall = 1;
 605                         td->error_any = 1;
 606                         goto complete;
 607                 }
 608                 /* check remainder */
 609                 if (td->remainder == 0) {
 610                         if (td->short_pkt)
 611                                 goto complete;
 612                         /* else we need to transmit a short packet */
 613                 }
 614                 saf1761_host_channel_free(sc, td);
 615         }
 616         if (saf1761_host_channel_alloc(sc, td))
 617                 goto busy;
 618
 619         count = td->max_packet_size;
 620         if (td->remainder < count) {
 621                 /* we have a short packet */
 622                 td->short_pkt = 1;
 623                 count = td->remainder;
 624         }
 625
 626         saf1761_write_host_memory(sc, td, count);
 627
 628         /* set toggle, if any */
 629         if (td->set_toggle) {
 630                 td->set_toggle = 0;
 631                 td->toggle = 1;
 632         }
 633
 634         /* send one more packet */
 635
 636         pdt_addr = SOTG_PTD(td->channel);
 637
 638         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 639         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 640         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, 0);
 641         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, 0);
 642
 643         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) |
 644             SOTG_PTD_DW3_CERR_2;
 645         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 646
 647         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8);
 648         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 649
 650         temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
 651         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 652
 653         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 654             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 655             (count << 3) /* transfer count */ |
 656             SOTG_PTD_DW0_VALID;
 657         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 658
 659         /* activate PTD */
 660         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
 661             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
 662
 663         td->toggle ^= 1;
 664 busy:
 665         return (1);     /* busy */
 666 complete:
 667         saf1761_host_channel_free(sc, td);
 668         return (0);     /* complete */
 669 }
 670
 671 static uint8_t
 672 saf1761_host_intr_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 673 {
 674         uint32_t pdt_addr;
 675         uint32_t temp;
 676
 677         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 678                 uint32_t status;
 679                 uint32_t count;
 680                 uint8_t got_short;
 681
 682                 pdt_addr = SOTG_PTD(td->channel);
 683
 684                 status = saf1761_peek_host_memory_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 685                 if (status == 0)
 686                         status = saf1761_peek_host_memory_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 687
 688                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 689
 690                 if (status & SOTG_PTD_DW3_ACTIVE) {
 691                         goto busy;
 692                 } else if (status & SOTG_PTD_DW3_HALTED) {
 693                         if (!(status & SOTG_PTD_DW3_ERRORS))
 694                                 td->error_stall = 1;
 695                         td->error_any = 1;
 696                         goto complete;
 697                 }
 698                 count = (status & SOTG_PTD_DW3_XFER_COUNT);
 699                 got_short = 0;
 700
 701                 /* verify the packet byte count */
 702                 if (count != td->max_packet_size) {
 703                         if (count < td->max_packet_size) {
 704                                 /* we have a short packet */
 705                                 td->short_pkt = 1;
 706                                 got_short = 1;
 707                         } else {
 708                                 /* invalid USB packet */
 709                                 td->error_any = 1;
 710                                 goto complete;
 711                         }
 712                 }
 713                 td->toggle ^= 1;
 714
 715                 /* verify the packet byte count */
 716                 if (count > td->remainder) {
 717                         /* invalid USB packet */
 718                         td->error_any = 1;
 719                         goto complete;
 720                 }
 721
 722                 saf1761_read_host_memory(sc, td, count);
 723
 724                 /* check if we are complete */
 725                 if ((td->remainder == 0) || got_short) {
 726                         if (td->short_pkt)
 727                                 goto complete;
 728                         /* else need to receive a zero length packet */
 729                 }
 730                 saf1761_host_channel_free(sc, td);
 731         }
 732         if (saf1761_host_channel_alloc(sc, td))
 733                 goto busy;
 734
 735         /* set toggle, if any */
 736         if (td->set_toggle) {
 737                 td->set_toggle = 0;
 738                 td->toggle = 1;
 739         }
 740
 741         /* receive one more packet */
 742
 743         pdt_addr = SOTG_PTD(td->channel);
 744
 745         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 746         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 747
 748         temp = (0xFC << td->uframe) & 0xFF;     /* complete split */
 749         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
 750
 751         temp = (1U << td->uframe);              /* start split */
 752         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
 753
 754         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 755         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 756
 757         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) | (td->interval & 0xF8);
 758         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 759
 760         temp = td->dw1_value | (1 << 10) /* IN-PID */ | (td->ep_index >> 1);
 761         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 762
 763         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 764             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 765             (td->max_packet_size << 3) /* transfer count */ |
 766             SOTG_PTD_DW0_VALID;
 767         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 768
 769         /* activate PTD */
 770         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 771             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 772 busy:
 773         return (1);     /* busy */
 774 complete:
 775         saf1761_host_channel_free(sc, td);
 776         return (0);     /* complete */
 777 }
 778
 779 static uint8_t
 780 saf1761_host_intr_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 781 {
 782         uint32_t pdt_addr;
 783         uint32_t temp;
 784         uint32_t count;
 785
 786         if (td->channel < SOTG_HOST_CHANNEL_MAX) {
 787                 uint32_t status;
 788
 789                 pdt_addr = SOTG_PTD(td->channel);
 790
 791                 status = saf1761_peek_host_memory_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 792                 if (status == 0)
 793                         status = saf1761_peek_host_memory_le_4(sc, pdt_addr + SOTG_PTD_DW3);
 794
 795                 DPRINTFN(5, "STATUS=0x%08x\n", status);
 796
 797                 if (status & SOTG_PTD_DW3_ACTIVE) {
 798                         goto busy;
 799                 } else if (status & SOTG_PTD_DW3_HALTED) {
 800                         if (!(status & SOTG_PTD_DW3_ERRORS))
 801                                 td->error_stall = 1;
 802                         td->error_any = 1;
 803                         goto complete;
 804                 }
 805
 806                 /* check remainder */
 807                 if (td->remainder == 0) {
 808                         if (td->short_pkt)
 809                                 goto complete;
 810                         /* else we need to transmit a short packet */
 811                 }
 812                 saf1761_host_channel_free(sc, td);
 813         }
 814         if (saf1761_host_channel_alloc(sc, td))
 815                 goto busy;
 816
 817         count = td->max_packet_size;
 818         if (td->remainder < count) {
 819                 /* we have a short packet */
 820                 td->short_pkt = 1;
 821                 count = td->remainder;
 822         }
 823
 824         saf1761_write_host_memory(sc, td, count);
 825
 826         /* set toggle, if any */
 827         if (td->set_toggle) {
 828                 td->set_toggle = 0;
 829                 td->toggle = 1;
 830         }
 831
 832         /* send one more packet */
 833
 834         pdt_addr = SOTG_PTD(td->channel);
 835
 836         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW7, 0);
 837         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW6, 0);
 838
 839         temp = (0xFC << td->uframe) & 0xFF;     /* complete split */
 840         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW5, temp);
 841
 842         temp = (1U << td->uframe);              /* start split */
 843         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW4, temp);
 844
 845         temp = SOTG_PTD_DW3_ACTIVE | (td->toggle << 25) | SOTG_PTD_DW3_CERR_3;
 846         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW3, temp);
 847
 848         temp = (SOTG_HC_MEMORY_ADDR(SOTG_DATA_ADDR(td->channel)) << 8) | (td->interval & 0xF8);
 849         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW2, temp);
 850
 851         temp = td->dw1_value | (0 << 10) /* OUT-PID */ | (td->ep_index >> 1);
 852         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW1, temp);
 853
 854         temp = (td->ep_index << 31) | (1 << 29) /* pkt-multiplier */ |
 855             (td->max_packet_size << 18) /* wMaxPacketSize */ |
 856             (count << 3) /* transfer count */ |
 857             SOTG_PTD_DW0_VALID;
 858         SAF1761_WRITE_LE_4(sc, pdt_addr + SOTG_PTD_DW0, temp);
 859
 860         /* activate PTD */
 861         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
 862             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
 863
 864         td->toggle ^= 1;
 865 busy:
 866         return (1);     /* busy */
 867 complete:
 868         saf1761_host_channel_free(sc, td);
 869         return (0);     /* complete */
 870 }
 871
 872 static uint8_t
 873 saf1761_host_isoc_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 874 {
 875         /* activate PTD */
 876         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
 877             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
 878
 879         return (1);     /* busy */
 880 }
 881
 882 static uint8_t
 883 saf1761_host_isoc_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 884 {
 885         /* activate PTD */
 886         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
 887             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
 888
 889         return (1);     /* busy */
 890 }
 891
 892 static void
 893 saf1761_otg_set_address(struct saf1761_otg_softc *sc, uint8_t addr)
 894 {
 895         DPRINTFN(5, "addr=%d\n", addr);
 896
 897         SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, addr | SOTG_ADDRESS_ENABLE);
 898 }
 899
 900
 901 static void
 902 saf1761_read_device_fifo(struct saf1761_otg_softc *sc,
 903     struct saf1761_otg_td *td, uint32_t len)
 904 {
 905         struct usb_page_search buf_res;
 906         uint32_t count;
 907
 908         /* optimised read first */
 909         while (len > 0) {
 910                 usbd_get_page(td->pc, td->offset, &buf_res);
 911
 912                 /* get correct length */
 913                 if (buf_res.length > len)
 914                         buf_res.length = len;
 915
 916                 /* check buffer alignment */
 917                 if (((uintptr_t)buf_res.buffer) & 3)
 918                         break;
 919
 920                 count = buf_res.length & ~3;
 921                 if (count == 0)
 922                         break;
 923
 924                 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 925                     SOTG_DATA_PORT, buf_res.buffer, count / 4);
 926
 927                 len -= count;
 928
 929                 /* update remainder and offset */
 930                 td->remainder -= count;
 931                 td->offset += count;
 932         }
 933
 934         if (len > 0) {
 935                 /* use bounce buffer */
 936                 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 937                     SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
 938                 usbd_copy_in(td->pc, td->offset,
 939                     sc->sc_bounce_buffer, len);
 940
 941                 /* update remainder and offset */
 942                 td->remainder -= len;
 943                 td->offset += len;
 944         }
 945 }
 946
 947 static void
 948 saf1761_write_device_fifo(struct saf1761_otg_softc *sc,
 949     struct saf1761_otg_td *td, uint32_t len)
 950 {
 951         struct usb_page_search buf_res;
 952         uint32_t count;
 953
 954         /* optimised write first */
 955         while (len > 0) {
 956                 usbd_get_page(td->pc, td->offset, &buf_res);
 957
 958                 /* get correct length */
 959                 if (buf_res.length > len)
 960                         buf_res.length = len;
 961
 962                 /* check buffer alignment */
 963                 if (((uintptr_t)buf_res.buffer) & 3)
 964                         break;
 965
 966                 count = buf_res.length & ~3;
 967                 if (count == 0)
 968                         break;
 969
 970                 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 971                     SOTG_DATA_PORT, buf_res.buffer, count / 4);
 972
 973                 len -= count;
 974
 975                 /* update remainder and offset */
 976                 td->remainder -= count;
 977                 td->offset += count;
 978         }
 979         if (len > 0) {
 980                 /* use bounce buffer */
 981                 usbd_copy_out(td->pc, td->offset, sc->sc_bounce_buffer, len);
 982                 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl,
 983                     SOTG_DATA_PORT, sc->sc_bounce_buffer, (len + 3) / 4);
 984
 985                 /* update remainder and offset */
 986                 td->remainder -= len;
 987                 td->offset += len;
 988         }
 989 }
 990
 991 static uint8_t
 992 saf1761_device_setup_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
 993 {
 994         struct usb_device_request req;
 995         uint32_t count;
 996
 997         /* select the correct endpoint */
 998         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
 999
1000         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1001
1002         /* check buffer status */
1003         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1004                 goto busy;
1005
1006         /* get buffer length */
1007         count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1008
1009         DPRINTFN(5, "count=%u rem=%u\n", count, td->remainder);
1010
1011         /* clear did stall */
1012         td->did_stall = 0;
1013
1014         /* clear stall */
1015         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
1016
1017         /* verify data length */
1018         if (count != td->remainder) {
1019                 DPRINTFN(0, "Invalid SETUP packet "
1020                     "length, %d bytes\n", count);
1021                 goto busy;
1022         }
1023         if (count != sizeof(req)) {
1024                 DPRINTFN(0, "Unsupported SETUP packet "
1025                     "length, %d bytes\n", count);
1026                 goto busy;
1027         }
1028         /* receive data */
1029         saf1761_read_device_fifo(sc, td, sizeof(req));
1030
1031         /* extract SETUP packet again */
1032         usbd_copy_out(td->pc, 0, &req, sizeof(req));
1033
1034         /* sneak peek the set address request */
1035         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
1036             (req.bRequest == UR_SET_ADDRESS)) {
1037                 sc->sc_dv_addr = req.wValue[0] & 0x7F;
1038                 DPRINTF("Set address %d\n", sc->sc_dv_addr);
1039         } else {
1040                 sc->sc_dv_addr = 0xFF;
1041         }
1042         return (0);                     /* complete */
1043
1044 busy:
1045         /* abort any ongoing transfer */
1046         if (!td->did_stall) {
1047                 DPRINTFN(5, "stalling\n");
1048
1049                 /* set stall */
1050                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
1051
1052                 td->did_stall = 1;
1053         }
1054         return (1);                     /* not complete */
1055 }
1056
1057 static uint8_t
1058 saf1761_device_data_rx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1059 {
1060         uint32_t count;
1061         uint8_t got_short = 0;
1062
1063         if (td->ep_index == 0) {
1064                 /* select the correct endpoint */
1065                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1066
1067                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1068
1069                 /* check buffer status */
1070                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1071
1072                         if (td->remainder == 0) {
1073                                 /*
1074                                  * We are actually complete and have
1075                                  * received the next SETUP:
1076                                  */
1077                                 DPRINTFN(5, "faking complete\n");
1078                                 return (0);     /* complete */
1079                         }
1080                         DPRINTFN(5, "SETUP packet while receiving data\n");
1081                         /*
1082                          * USB Host Aborted the transfer.
1083                          */
1084                         td->error_any = 1;
1085                         return (0);     /* complete */
1086                 }
1087         }
1088         /* select the correct endpoint */
1089         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1090             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1091             SOTG_EP_INDEX_DIR_OUT);
1092
1093         /* enable data stage */
1094         if (td->set_toggle) {
1095                 td->set_toggle = 0;
1096                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1097         }
1098
1099         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1100
1101         /* check buffer status */
1102         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) == 0)
1103                 return (1);             /* not complete */
1104
1105         /* get buffer length */
1106         count &= SOTG_BUF_LENGTH_BUFLEN_MASK;
1107
1108         DPRINTFN(5, "rem=%u count=0x%04x\n", td->remainder, count);
1109
1110         /* verify the packet byte count */
1111         if (count != td->max_packet_size) {
1112                 if (count < td->max_packet_size) {
1113                         /* we have a short packet */
1114                         td->short_pkt = 1;
1115                         got_short = 1;
1116                 } else {
1117                         /* invalid USB packet */
1118                         td->error_any = 1;
1119                         return (0);     /* we are complete */
1120                 }
1121         }
1122         /* verify the packet byte count */
1123         if (count > td->remainder) {
1124                 /* invalid USB packet */
1125                 td->error_any = 1;
1126                 return (0);             /* we are complete */
1127         }
1128         /* receive data */
1129         saf1761_read_device_fifo(sc, td, count);
1130
1131         /* check if we are complete */
1132         if ((td->remainder == 0) || got_short) {
1133                 if (td->short_pkt) {
1134                         /* we are complete */
1135                         return (0);
1136                 }
1137                 /* else need to receive a zero length packet */
1138         }
1139         return (1);                     /* not complete */
1140 }
1141
1142 static uint8_t
1143 saf1761_device_data_tx(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1144 {
1145         uint32_t count;
1146
1147         if (td->ep_index == 0) {
1148                 /* select the correct endpoint */
1149                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1150
1151                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1152
1153                 /* check buffer status */
1154                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1155                         DPRINTFN(5, "SETUP abort\n");
1156                         /*
1157                          * USB Host Aborted the transfer.
1158                          */
1159                         td->error_any = 1;
1160                         return (0);     /* complete */
1161                 }
1162         }
1163         /* select the correct endpoint */
1164         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1165             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1166             SOTG_EP_INDEX_DIR_IN);
1167
1168         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1169
1170         /* check buffer status */
1171         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1172                 return (1);             /* not complete */
1173
1174         /* enable data stage */
1175         if (td->set_toggle) {
1176                 td->set_toggle = 0;
1177                 SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_DSEN);
1178         }
1179
1180         DPRINTFN(5, "rem=%u\n", td->remainder);
1181
1182         count = td->max_packet_size;
1183         if (td->remainder < count) {
1184                 /* we have a short packet */
1185                 td->short_pkt = 1;
1186                 count = td->remainder;
1187         }
1188         /* transmit data */
1189         saf1761_write_device_fifo(sc, td, count);
1190
1191         if (td->ep_index == 0) {
1192                 if (count < SOTG_FS_MAX_PACKET_SIZE) {
1193                         /* set end of packet */
1194                         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1195                 }
1196         } else {
1197                 if (count < SOTG_HS_MAX_PACKET_SIZE) {
1198                         /* set end of packet */
1199                         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_VENDP);
1200                 }
1201         }
1202
1203         /* check remainder */
1204         if (td->remainder == 0) {
1205                 if (td->short_pkt) {
1206                         return (0);     /* complete */
1207                 }
1208                 /* else we need to transmit a short packet */
1209         }
1210         return (1);                     /* not complete */
1211 }
1212
1213 static uint8_t
1214 saf1761_device_data_tx_sync(struct saf1761_otg_softc *sc, struct saf1761_otg_td *td)
1215 {
1216         uint32_t count;
1217
1218         if (td->ep_index == 0) {
1219                 /* select the correct endpoint */
1220                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX, SOTG_EP_INDEX_EP0SETUP);
1221
1222                 count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1223
1224                 /* check buffer status */
1225                 if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0) {
1226                         DPRINTFN(5, "Faking complete\n");
1227                         return (0);     /* complete */
1228                 }
1229         }
1230         /* select the correct endpoint */
1231         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
1232             (td->ep_index << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
1233             SOTG_EP_INDEX_DIR_IN);
1234
1235         count = SAF1761_READ_LE_4(sc, SOTG_BUF_LENGTH);
1236
1237         /* check buffer status */
1238         if ((count & SOTG_BUF_LENGTH_FILLED_MASK) != 0)
1239                 return (1);             /* busy */
1240
1241         if (sc->sc_dv_addr != 0xFF) {
1242                 /* write function address */
1243                 saf1761_otg_set_address(sc, sc->sc_dv_addr);
1244         }
1245         return (0);                     /* complete */
1246 }
1247
1248 static void
1249 saf1761_otg_xfer_do_fifo(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1250 {
1251         struct saf1761_otg_td *td;
1252         uint8_t toggle;
1253
1254         DPRINTFN(9, "\n");
1255
1256         td = xfer->td_transfer_cache;
1257         if (td == NULL)
1258                 return;
1259
1260         while (1) {
1261                 if ((td->func) (sc, td)) {
1262                         /* operation in progress */
1263                         break;
1264                 }
1265                 if (((void *)td) == xfer->td_transfer_last) {
1266                         goto done;
1267                 }
1268                 if (td->error_any) {
1269                         goto done;
1270                 } else if (td->remainder > 0) {
1271                         /*
1272                          * We had a short transfer. If there is no alternate
1273                          * next, stop processing !
1274                          */
1275                         if (!td->alt_next) {
1276                                 goto done;
1277                         }
1278                 }
1279                 /*
1280                  * Fetch the next transfer descriptor.
1281                  */
1282                 toggle = td->toggle;
1283                 td = td->obj_next;
1284                 td->toggle = toggle;
1285                 xfer->td_transfer_cache = td;
1286         }
1287         return;
1288
1289 done:
1290         /* compute all actual lengths */
1291         xfer->td_transfer_cache = NULL;
1292         sc->sc_xfer_complete = 1;
1293 }
1294
1295 static uint8_t
1296 saf1761_otg_xfer_do_complete(struct saf1761_otg_softc *sc, struct usb_xfer *xfer)
1297 {
1298         struct saf1761_otg_td *td;
1299
1300         DPRINTFN(9, "\n");
1301
1302         td = xfer->td_transfer_cache;
1303         if (td == NULL) {
1304                 /* compute all actual lengths */
1305                 saf1761_otg_standard_done(xfer);
1306                 return (1);
1307         }
1308         return (0);
1309 }
1310
1311 static void
1312 saf1761_otg_interrupt_poll_locked(struct saf1761_otg_softc *sc)
1313 {
1314         struct usb_xfer *xfer;
1315
1316         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
1317                 saf1761_otg_xfer_do_fifo(sc, xfer);
1318 }
1319
1320 static void
1321 saf1761_otg_wait_suspend(struct saf1761_otg_softc *sc, uint8_t on)
1322 {
1323         if (on) {
1324                 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IESUSP;
1325                 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IERESM;
1326         } else {
1327                 sc->sc_intr_enable &= ~SOTG_DCINTERRUPT_IESUSP;
1328                 sc->sc_intr_enable |= SOTG_DCINTERRUPT_IERESM;
1329         }
1330         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1331 }
1332
1333 static void
1334 saf1761_otg_update_vbus(struct saf1761_otg_softc *sc)
1335 {
1336         uint16_t status;
1337
1338         /* read fresh status */
1339         status = SAF1761_READ_LE_4(sc, SOTG_STATUS);
1340
1341         DPRINTFN(4, "STATUS=0x%04x\n", status);
1342
1343         if ((status & SOTG_STATUS_VBUS_VLD) &&
1344             (status & SOTG_STATUS_ID)) {
1345                 /* VBUS present and device mode */
1346                 if (!sc->sc_flags.status_vbus) {
1347                         sc->sc_flags.status_vbus = 1;
1348
1349                         /* complete root HUB interrupt endpoint */
1350                         saf1761_otg_root_intr(sc);
1351                 }
1352         } else {
1353                 /* VBUS not-present or host mode */
1354                 if (sc->sc_flags.status_vbus) {
1355                         sc->sc_flags.status_vbus = 0;
1356                         sc->sc_flags.status_bus_reset = 0;
1357                         sc->sc_flags.status_suspend = 0;
1358                         sc->sc_flags.change_suspend = 0;
1359                         sc->sc_flags.change_connect = 1;
1360
1361                         /* complete root HUB interrupt endpoint */
1362                         saf1761_otg_root_intr(sc);
1363                 }
1364         }
1365 }
1366
1367 static void
1368 saf1761_otg_interrupt_complete_locked(struct saf1761_otg_softc *sc)
1369 {
1370         struct usb_xfer *xfer;
1371 repeat:
1372         /* scan for completion events */
1373         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1374                 if (saf1761_otg_xfer_do_complete(sc, xfer))
1375                         goto repeat;
1376         }
1377 }
1378
1379 int
1380 saf1761_otg_filter_interrupt(void *arg)
1381 {
1382         struct saf1761_otg_softc *sc = arg;
1383         int retval = FILTER_HANDLED;
1384         uint32_t hcstat;
1385         uint32_t status;
1386
1387         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1388
1389         hcstat = SAF1761_READ_LE_4(sc, SOTG_HCINTERRUPT);
1390         /* acknowledge all host controller interrupts */
1391         SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT, hcstat);
1392
1393         status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT);
1394         /* acknowledge all device controller interrupts */
1395         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT,
1396             status & ~SAF1761_DCINTERRUPT_THREAD_IRQ);
1397
1398         (void) SAF1761_READ_LE_4(sc, SOTG_ATL_PTD_DONE_PTD);
1399         (void) SAF1761_READ_LE_4(sc, SOTG_INT_PTD_DONE_PTD);
1400         (void) SAF1761_READ_LE_4(sc, SOTG_ISO_PTD_DONE_PTD);
1401
1402         if (status & SAF1761_DCINTERRUPT_THREAD_IRQ)
1403                 retval = FILTER_SCHEDULE_THREAD;
1404
1405         /* poll FIFOs, if any */
1406         saf1761_otg_interrupt_poll_locked(sc);
1407
1408         if (sc->sc_xfer_complete != 0)
1409                 retval = FILTER_SCHEDULE_THREAD;
1410
1411         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1412
1413         return (retval);
1414 }
1415
1416 void
1417 saf1761_otg_interrupt(void *arg)
1418 {
1419         struct saf1761_otg_softc *sc = arg;
1420         uint32_t status;
1421
1422         USB_BUS_LOCK(&sc->sc_bus);
1423         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1424
1425         status = SAF1761_READ_LE_4(sc, SOTG_DCINTERRUPT) &
1426             SAF1761_DCINTERRUPT_THREAD_IRQ;
1427
1428         /* acknowledge all device controller interrupts */
1429         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT, status);
1430
1431         DPRINTF("DCINTERRUPT=0x%08x SOF=0x%08x "
1432             "FRINDEX=0x%08x\n", status,
1433             SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM),
1434             SAF1761_READ_LE_4(sc, SOTG_FRINDEX));
1435
1436         /* update VBUS and ID bits, if any */
1437         if (status & SOTG_DCINTERRUPT_IEVBUS)
1438                 saf1761_otg_update_vbus(sc);
1439
1440         if (status & SOTG_DCINTERRUPT_IEBRST) {
1441                 /* unlock device */
1442                 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1443                     SOTG_UNLOCK_DEVICE_CODE);
1444
1445                 /* Enable device address */
1446                 SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS,
1447                     SOTG_ADDRESS_ENABLE);
1448
1449                 sc->sc_flags.status_bus_reset = 1;
1450                 sc->sc_flags.status_suspend = 0;
1451                 sc->sc_flags.change_suspend = 0;
1452                 sc->sc_flags.change_connect = 1;
1453
1454                 /* disable resume interrupt */
1455                 saf1761_otg_wait_suspend(sc, 1);
1456                 /* complete root HUB interrupt endpoint */
1457                 saf1761_otg_root_intr(sc);
1458         }
1459         /*
1460          * If "RESUME" and "SUSPEND" is set at the same time we
1461          * interpret that like "RESUME". Resume is set when there is
1462          * at least 3 milliseconds of inactivity on the USB BUS:
1463          */
1464         if (status & SOTG_DCINTERRUPT_IERESM) {
1465                 /* unlock device */
1466                 SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE,
1467                     SOTG_UNLOCK_DEVICE_CODE);
1468
1469                 if (sc->sc_flags.status_suspend) {
1470                         sc->sc_flags.status_suspend = 0;
1471                         sc->sc_flags.change_suspend = 1;
1472                         /* disable resume interrupt */
1473                         saf1761_otg_wait_suspend(sc, 1);
1474                         /* complete root HUB interrupt endpoint */
1475                         saf1761_otg_root_intr(sc);
1476                 }
1477         } else if (status & SOTG_DCINTERRUPT_IESUSP) {
1478                 if (!sc->sc_flags.status_suspend) {
1479                         sc->sc_flags.status_suspend = 1;
1480                         sc->sc_flags.change_suspend = 1;
1481                         /* enable resume interrupt */
1482                         saf1761_otg_wait_suspend(sc, 0);
1483                         /* complete root HUB interrupt endpoint */
1484                         saf1761_otg_root_intr(sc);
1485                 }
1486         }
1487
1488         if (sc->sc_xfer_complete != 0) {
1489                 sc->sc_xfer_complete = 0;
1490
1491                 /* complete FIFOs, if any */
1492                 saf1761_otg_interrupt_complete_locked(sc);
1493         }
1494         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1495         USB_BUS_UNLOCK(&sc->sc_bus);
1496 }
1497
1498 static void
1499 saf1761_otg_setup_standard_chain_sub(struct saf1761_otg_std_temp *temp)
1500 {
1501         struct saf1761_otg_td *td;
1502
1503         /* get current Transfer Descriptor */
1504         td = temp->td_next;
1505         temp->td = td;
1506
1507         /* prepare for next TD */
1508         temp->td_next = td->obj_next;
1509
1510         /* fill out the Transfer Descriptor */
1511         td->func = temp->func;
1512         td->pc = temp->pc;
1513         td->offset = temp->offset;
1514         td->remainder = temp->len;
1515         td->error_any = 0;
1516         td->error_stall = 0;
1517         td->set_toggle = 0;
1518         td->did_stall = temp->did_stall;
1519         td->short_pkt = temp->short_pkt;
1520         td->alt_next = temp->setup_alt_next;
1521         td->channel = SOTG_HOST_CHANNEL_MAX;
1522 }
1523
1524 static void
1525 saf1761_otg_setup_standard_chain(struct usb_xfer *xfer)
1526 {
1527         struct saf1761_otg_std_temp temp;
1528         struct saf1761_otg_softc *sc;
1529         struct saf1761_otg_td *td;
1530         uint32_t x;
1531         uint8_t ep_no;
1532         uint8_t ep_type;
1533         uint8_t need_sync;
1534         uint8_t is_host;
1535
1536         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1537             xfer->address, UE_GET_ADDR(xfer->endpointno),
1538             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1539
1540         temp.max_frame_size = xfer->max_frame_size;
1541
1542         td = xfer->td_start[0];
1543         xfer->td_transfer_first = td;
1544         xfer->td_transfer_cache = td;
1545
1546         /* setup temp */
1547
1548         temp.pc = NULL;
1549         temp.td = NULL;
1550         temp.td_next = xfer->td_start[0];
1551         temp.offset = 0;
1552         temp.setup_alt_next = xfer->flags_int.short_frames_ok ||
1553             xfer->flags_int.isochronous_xfr;
1554         temp.did_stall = !xfer->flags_int.control_stall;
1555
1556         is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST);
1557
1558         sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1559         ep_no = (xfer->endpointno & UE_ADDR);
1560         ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
1561
1562         /* check if we should prepend a setup message */
1563
1564         if (xfer->flags_int.control_xfr) {
1565                 if (xfer->flags_int.control_hdr) {
1566
1567                         if (is_host)
1568                                 temp.func = &saf1761_host_setup_tx;
1569                         else
1570                                 temp.func = &saf1761_device_setup_rx;
1571
1572                         temp.len = xfer->frlengths[0];
1573                         temp.pc = xfer->frbuffers + 0;
1574                         temp.short_pkt = temp.len ? 1 : 0;
1575                         /* check for last frame */
1576                         if (xfer->nframes == 1) {
1577                                 /* no STATUS stage yet, SETUP is last */
1578                                 if (xfer->flags_int.control_act)
1579                                         temp.setup_alt_next = 0;
1580                         }
1581                         saf1761_otg_setup_standard_chain_sub(&temp);
1582                 }
1583                 x = 1;
1584         } else {
1585                 x = 0;
1586         }
1587
1588         if (x != xfer->nframes) {
1589                 if (xfer->endpointno & UE_DIR_IN) {
1590                         if (is_host) {
1591                                 if (ep_type == UE_INTERRUPT)
1592                                         temp.func = &saf1761_host_intr_data_rx;
1593                                 else if (ep_type == UE_ISOCHRONOUS)
1594                                         temp.func = &saf1761_host_isoc_data_rx;
1595                                 else
1596                                         temp.func = &saf1761_host_bulk_data_rx;
1597                                 need_sync = 0;
1598                         } else {
1599                                 temp.func = &saf1761_device_data_tx;
1600                                 need_sync = 1;
1601                         }
1602                 } else {
1603                         if (is_host) {
1604                                 if (ep_type == UE_INTERRUPT)
1605                                         temp.func = &saf1761_host_intr_data_tx;
1606                                 else if (ep_type == UE_ISOCHRONOUS)
1607                                         temp.func = &saf1761_host_isoc_data_tx;
1608                                 else
1609                                         temp.func = &saf1761_host_bulk_data_tx;
1610                                 need_sync = 0;
1611                         } else {
1612                                 temp.func = &saf1761_device_data_rx;
1613                                 need_sync = 0;
1614                         }
1615                 }
1616
1617                 /* setup "pc" pointer */
1618                 temp.pc = xfer->frbuffers + x;
1619         } else {
1620                 need_sync = 0;
1621         }
1622
1623         while (x != xfer->nframes) {
1624
1625                 /* DATA0 / DATA1 message */
1626
1627                 temp.len = xfer->frlengths[x];
1628
1629                 x++;
1630
1631                 if (x == xfer->nframes) {
1632                         if (xfer->flags_int.control_xfr) {
1633                                 if (xfer->flags_int.control_act) {
1634                                         temp.setup_alt_next = 0;
1635                                 }
1636                         } else {
1637                                 temp.setup_alt_next = 0;
1638                         }
1639                 }
1640                 if (temp.len == 0) {
1641
1642                         /* make sure that we send an USB packet */
1643
1644                         temp.short_pkt = 0;
1645
1646                 } else {
1647
1648                         /* regular data transfer */
1649
1650                         temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1651                 }
1652
1653                 saf1761_otg_setup_standard_chain_sub(&temp);
1654
1655                 if (xfer->flags_int.isochronous_xfr) {
1656                         temp.offset += temp.len;
1657                 } else {
1658                         /* get next Page Cache pointer */
1659                         temp.pc = xfer->frbuffers + x;
1660                 }
1661         }
1662
1663         /* check for control transfer */
1664         if (xfer->flags_int.control_xfr) {
1665                 /* always setup a valid "pc" pointer for status and sync */
1666                 temp.pc = xfer->frbuffers + 0;
1667                 temp.len = 0;
1668                 temp.short_pkt = 0;
1669                 temp.setup_alt_next = 0;
1670
1671                 /* check if we should append a status stage */
1672                 if (!xfer->flags_int.control_act) {
1673
1674                         /*
1675                          * Send a DATA1 message and invert the current
1676                          * endpoint direction.
1677                          */
1678                         if (xfer->endpointno & UE_DIR_IN) {
1679                                 if (is_host) {
1680                                         temp.func = &saf1761_host_bulk_data_tx;
1681                                         need_sync = 0;
1682                                 } else {
1683                                         temp.func = &saf1761_device_data_rx;
1684                                         need_sync = 0;
1685                                 }
1686                         } else {
1687                                 if (is_host) {
1688                                         temp.func = &saf1761_host_bulk_data_rx;
1689                                         need_sync = 0;
1690                                 } else {
1691                                         temp.func = &saf1761_device_data_tx;
1692                                         need_sync = 1;
1693                                 }
1694                         }
1695                         temp.len = 0;
1696                         temp.short_pkt = 0;
1697
1698                         saf1761_otg_setup_standard_chain_sub(&temp);
1699
1700                         /* data toggle should be DATA1 */
1701                         td = temp.td;
1702                         td->set_toggle = 1;
1703
1704                         if (need_sync) {
1705                                 /* we need a SYNC point after TX */
1706                                 temp.func = &saf1761_device_data_tx_sync;
1707                                 saf1761_otg_setup_standard_chain_sub(&temp);
1708                         }
1709                 }
1710         } else {
1711                 if (need_sync) {
1712                         temp.pc = xfer->frbuffers + 0;
1713                         temp.len = 0;
1714                         temp.short_pkt = 0;
1715                         temp.setup_alt_next = 0;
1716
1717                         /* we need a SYNC point after TX */
1718                         temp.func = &saf1761_device_data_tx_sync;
1719                         saf1761_otg_setup_standard_chain_sub(&temp);
1720                 }
1721         }
1722
1723         /* must have at least one frame! */
1724         td = temp.td;
1725         xfer->td_transfer_last = td;
1726
1727         if (is_host) {
1728                 /* get first again */
1729                 td = xfer->td_transfer_first;
1730                 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0);
1731         }
1732 }
1733
1734 static void
1735 saf1761_otg_timeout(void *arg)
1736 {
1737         struct usb_xfer *xfer = arg;
1738
1739         DPRINTF("xfer=%p\n", xfer);
1740
1741         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1742
1743         /* transfer is transferred */
1744         saf1761_otg_device_done(xfer, USB_ERR_TIMEOUT);
1745 }
1746
1747 static void
1748 saf1761_otg_intr_set(struct usb_xfer *xfer, uint8_t set)
1749 {
1750         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1751         uint8_t ep_no = (xfer->endpointno & UE_ADDR);
1752         uint32_t mask;
1753
1754         DPRINTFN(15, "endpoint=%d set=%d\n", xfer->endpointno, set);
1755
1756         if (ep_no == 0) {
1757                 mask = SOTG_DCINTERRUPT_IEPRX(0) |
1758                     SOTG_DCINTERRUPT_IEPTX(0) |
1759                     SOTG_DCINTERRUPT_IEP0SETUP;
1760         } else if (xfer->endpointno & UE_DIR_IN) {
1761                 mask = SOTG_DCINTERRUPT_IEPTX(ep_no);
1762         } else {
1763                 mask = SOTG_DCINTERRUPT_IEPRX(ep_no);
1764         }
1765
1766         if (set)
1767                 sc->sc_intr_enable |= mask;
1768         else
1769                 sc->sc_intr_enable &= ~mask;
1770
1771         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
1772 }
1773
1774 static void
1775 saf1761_otg_start_standard_chain(struct usb_xfer *xfer)
1776 {
1777         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1778
1779         DPRINTFN(9, "\n");
1780
1781         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1782
1783         /* poll one time */
1784         saf1761_otg_xfer_do_fifo(sc, xfer);
1785
1786         if (xfer->td_transfer_cache != NULL) {
1787                 /*
1788                  * Only enable the endpoint interrupt when we are
1789                  * actually waiting for data, hence we are dealing
1790                  * with level triggered interrupts !
1791                  */
1792                 saf1761_otg_intr_set(xfer, 1);
1793
1794                 /* put transfer on interrupt queue */
1795                 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1796
1797                 /* start timeout, if any */
1798                 if (xfer->timeout != 0) {
1799                         usbd_transfer_timeout_ms(xfer,
1800                             &saf1761_otg_timeout, xfer->timeout);
1801                 }
1802         } else {
1803                 /* catch completion, if any */
1804                 saf1761_otg_interrupt_complete_locked(sc);
1805         }
1806         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1807 }
1808
1809 static void
1810 saf1761_otg_root_intr(struct saf1761_otg_softc *sc)
1811 {
1812         DPRINTFN(9, "\n");
1813
1814         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1815
1816         /* set port bit - we only have one port */
1817         sc->sc_hub_idata[0] = 0x02;
1818
1819         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1820             sizeof(sc->sc_hub_idata));
1821 }
1822
1823 static usb_error_t
1824 saf1761_otg_standard_done_sub(struct usb_xfer *xfer)
1825 {
1826         struct saf1761_otg_td *td;
1827         uint32_t len;
1828         usb_error_t error;
1829
1830         DPRINTFN(9, "\n");
1831
1832         td = xfer->td_transfer_cache;
1833
1834         do {
1835                 len = td->remainder;
1836
1837                 /* store last data toggle */
1838                 xfer->endpoint->toggle_next = td->toggle;
1839
1840                 if (xfer->aframes != xfer->nframes) {
1841                         /*
1842                          * Verify the length and subtract
1843                          * the remainder from "frlengths[]":
1844                          */
1845                         if (len > xfer->frlengths[xfer->aframes]) {
1846                                 td->error_any = 1;
1847                         } else {
1848                                 xfer->frlengths[xfer->aframes] -= len;
1849                         }
1850                 }
1851                 /* Check for transfer error */
1852                 if (td->error_any) {
1853                         /* the transfer is finished */
1854                         error = (td->error_stall ?
1855                             USB_ERR_STALLED : USB_ERR_IOERROR);
1856                         td = NULL;
1857                         break;
1858                 }
1859                 /* Check for short transfer */
1860                 if (len > 0) {
1861                         if (xfer->flags_int.short_frames_ok ||
1862                             xfer->flags_int.isochronous_xfr) {
1863                                 /* follow alt next */
1864                                 if (td->alt_next) {
1865                                         td = td->obj_next;
1866                                 } else {
1867                                         td = NULL;
1868                                 }
1869                         } else {
1870                                 /* the transfer is finished */
1871                                 td = NULL;
1872                         }
1873                         error = 0;
1874                         break;
1875                 }
1876                 td = td->obj_next;
1877
1878                 /* this USB frame is complete */
1879                 error = 0;
1880                 break;
1881
1882         } while (0);
1883
1884         /* update transfer cache */
1885
1886         xfer->td_transfer_cache = td;
1887
1888         return (error);
1889 }
1890
1891 static void
1892 saf1761_otg_standard_done(struct usb_xfer *xfer)
1893 {
1894         usb_error_t err = 0;
1895
1896         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1897             xfer, xfer->endpoint);
1898
1899         /* reset scanner */
1900
1901         xfer->td_transfer_cache = xfer->td_transfer_first;
1902
1903         if (xfer->flags_int.control_xfr) {
1904
1905                 if (xfer->flags_int.control_hdr) {
1906
1907                         err = saf1761_otg_standard_done_sub(xfer);
1908                 }
1909                 xfer->aframes = 1;
1910
1911                 if (xfer->td_transfer_cache == NULL) {
1912                         goto done;
1913                 }
1914         }
1915         while (xfer->aframes != xfer->nframes) {
1916
1917                 err = saf1761_otg_standard_done_sub(xfer);
1918                 xfer->aframes++;
1919
1920                 if (xfer->td_transfer_cache == NULL) {
1921                         goto done;
1922                 }
1923         }
1924
1925         if (xfer->flags_int.control_xfr &&
1926             !xfer->flags_int.control_act) {
1927
1928                 err = saf1761_otg_standard_done_sub(xfer);
1929         }
1930 done:
1931         saf1761_otg_device_done(xfer, err);
1932 }
1933
1934 /*------------------------------------------------------------------------*
1935  *      saf1761_otg_device_done
1936  *
1937  * NOTE: this function can be called more than one time on the
1938  * same USB transfer!
1939  *------------------------------------------------------------------------*/
1940 static void
1941 saf1761_otg_device_done(struct usb_xfer *xfer, usb_error_t error)
1942 {
1943         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
1944
1945         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1946
1947         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1948             xfer, xfer->endpoint, error);
1949
1950         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1951
1952         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1953                 saf1761_otg_intr_set(xfer, 0);
1954         } else {
1955                 struct saf1761_otg_td *td;
1956
1957                 td = xfer->td_transfer_first;
1958
1959                 if (td != NULL)
1960                         saf1761_host_channel_free(sc, td);
1961         }
1962
1963         /* dequeue transfer and start next transfer */
1964         usbd_transfer_done(xfer, error);
1965
1966         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1967 }
1968
1969 static void
1970 saf1761_otg_xfer_stall(struct usb_xfer *xfer)
1971 {
1972         saf1761_otg_device_done(xfer, USB_ERR_STALLED);
1973 }
1974
1975 static void
1976 saf1761_otg_set_stall(struct usb_device *udev,
1977     struct usb_endpoint *ep, uint8_t *did_stall)
1978 {
1979         struct saf1761_otg_softc *sc;
1980         uint8_t ep_no;
1981         uint8_t ep_type;
1982         uint8_t ep_dir;
1983
1984         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1985
1986         /* check mode */
1987         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1988                 /* not supported */
1989                 return;
1990         }
1991
1992         DPRINTFN(5, "endpoint=%p\n", ep);
1993
1994         /* set STALL bit */
1995         sc = SAF1761_OTG_BUS2SC(udev->bus);
1996
1997         ep_no = (ep->edesc->bEndpointAddress & UE_ADDR);
1998         ep_dir = (ep->edesc->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT));
1999         ep_type = (ep->edesc->bmAttributes & UE_XFERTYPE);
2000
2001         if (ep_type == UE_CONTROL) {
2002                 /* should not happen */
2003                 return;
2004         }
2005         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2006
2007         /* select the correct endpoint */
2008         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2009             (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2010             ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2011             SOTG_EP_INDEX_DIR_OUT));
2012
2013         /* set stall */
2014         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_STALL);
2015
2016         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2017 }
2018
2019 static void
2020 saf1761_otg_clear_stall_sub_locked(struct saf1761_otg_softc *sc,
2021     uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir)
2022 {
2023         if (ep_type == UE_CONTROL) {
2024                 /* clearing stall is not needed */
2025                 return;
2026         }
2027         /* select the correct endpoint */
2028         SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2029             (ep_no << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2030             ((ep_dir == UE_DIR_IN) ? SOTG_EP_INDEX_DIR_IN :
2031             SOTG_EP_INDEX_DIR_OUT));
2032
2033         /* disable endpoint */
2034         SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, 0);
2035         /* enable endpoint again - will clear data toggle */
2036         SAF1761_WRITE_LE_4(sc, SOTG_EP_TYPE, ep_type | SOTG_EP_TYPE_ENABLE);
2037
2038         /* clear buffer */
2039         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, SOTG_CTRL_FUNC_CLBUF);
2040         /* clear stall */
2041         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_FUNC, 0);
2042 }
2043
2044 static void
2045 saf1761_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
2046 {
2047         struct saf1761_otg_softc *sc;
2048         struct usb_endpoint_descriptor *ed;
2049
2050         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
2051
2052         DPRINTFN(5, "endpoint=%p\n", ep);
2053
2054         /* check mode */
2055         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
2056                 /* not supported */
2057                 return;
2058         }
2059         /* get softc */
2060         sc = SAF1761_OTG_BUS2SC(udev->bus);
2061
2062         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2063
2064         /* get endpoint descriptor */
2065         ed = ep->edesc;
2066
2067         /* reset endpoint */
2068         saf1761_otg_clear_stall_sub_locked(sc,
2069             (ed->bEndpointAddress & UE_ADDR),
2070             (ed->bmAttributes & UE_XFERTYPE),
2071             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
2072
2073         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2074 }
2075
2076 usb_error_t
2077 saf1761_otg_init(struct saf1761_otg_softc *sc)
2078 {
2079         const struct usb_hw_ep_profile *pf;
2080         uint32_t x;
2081
2082         DPRINTF("\n");
2083
2084         /* set up the bus structure */
2085         sc->sc_bus.usbrev = USB_REV_2_0;
2086         sc->sc_bus.methods = &saf1761_otg_bus_methods;
2087
2088         USB_BUS_LOCK(&sc->sc_bus);
2089
2090         /* Reset Host controller, including HW mode */
2091         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_ALL);
2092
2093         DELAY(1000);
2094
2095         /* Reset Host controller, including HW mode */
2096         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, SOTG_SW_RESET_HC);
2097
2098         /* wait a bit */
2099         DELAY(1000);
2100
2101         SAF1761_WRITE_LE_4(sc, SOTG_SW_RESET, 0);
2102
2103         /* wait a bit */
2104         DELAY(1000);
2105
2106         /* Enable interrupts */
2107         sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN |
2108             SOTG_HW_MODE_CTRL_COMN_INT;
2109
2110         /* unlock device */
2111         SAF1761_WRITE_LE_4(sc, SOTG_UNLOCK_DEVICE, SOTG_UNLOCK_DEVICE_CODE);
2112
2113         /*
2114          * Set correct hardware mode, must be written twice if bus
2115          * width is changed:
2116          */
2117         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2118         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2119
2120         SAF1761_WRITE_LE_4(sc, SOTG_DCSCRATCH, 0xdeadbeef);
2121         SAF1761_WRITE_LE_4(sc, SOTG_HCSCRATCH, 0xdeadbeef);
2122
2123         DPRINTF("DCID=0x%08x VEND_PROD=0x%08x HWMODE=0x%08x SCRATCH=0x%08x,0x%08x\n",
2124             SAF1761_READ_LE_4(sc, SOTG_DCCHIP_ID),
2125             SAF1761_READ_LE_4(sc, SOTG_VEND_PROD_ID),
2126             SAF1761_READ_LE_4(sc, SOTG_HW_MODE_CTRL),
2127             SAF1761_READ_LE_4(sc, SOTG_DCSCRATCH),
2128             SAF1761_READ_LE_4(sc, SOTG_HCSCRATCH));
2129
2130         /* reset device controller */
2131         SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_SFRESET);
2132         SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2133
2134         /* wait a bit */
2135         DELAY(1000);
2136
2137         /* reset host controller */
2138         SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_HCRESET);
2139
2140         /* wait for reset to clear */
2141         for (x = 0; x != 10; x++) {
2142                 if ((SAF1761_READ_LE_4(sc, SOTG_USBCMD) & SOTG_USBCMD_HCRESET) == 0)
2143                         break;
2144                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10);
2145         }
2146
2147         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode |
2148             SOTG_HW_MODE_CTRL_ALL_ATX_RESET);
2149
2150         /* wait a bit */
2151         DELAY(1000);
2152
2153         SAF1761_WRITE_LE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
2154
2155         /* wait a bit */
2156         DELAY(1000);
2157
2158         /* do a pulldown */
2159         saf1761_otg_pull_down(sc);
2160
2161         /* wait 10ms for pulldown to stabilise */
2162         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2163
2164         for (x = 1;; x++) {
2165
2166                 saf1761_otg_get_hw_ep_profile(NULL, &pf, x);
2167                 if (pf == NULL)
2168                         break;
2169
2170                 /* select the correct endpoint */
2171                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2172                     (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2173                     SOTG_EP_INDEX_DIR_IN);
2174
2175                 /* select the maximum packet size */
2176                 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_in_frame_size);
2177
2178                 /* select the correct endpoint */
2179                 SAF1761_WRITE_LE_4(sc, SOTG_EP_INDEX,
2180                     (x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
2181                     SOTG_EP_INDEX_DIR_OUT);
2182
2183                 /* select the maximum packet size */
2184                 SAF1761_WRITE_LE_4(sc, SOTG_EP_MAXPACKET, pf->max_out_frame_size);
2185         }
2186
2187         /* enable interrupts */
2188         SAF1761_WRITE_LE_4(sc, SOTG_MODE, SOTG_MODE_GLINTENA |
2189             SOTG_MODE_CLKAON | SOTG_MODE_WKUPCS);
2190
2191         sc->sc_interrupt_cfg |=
2192             SOTG_INTERRUPT_CFG_CDBGMOD |
2193             SOTG_INTERRUPT_CFG_DDBGMODIN |
2194             SOTG_INTERRUPT_CFG_DDBGMODOUT;
2195
2196         /* set default values */
2197         SAF1761_WRITE_LE_4(sc, SOTG_INTERRUPT_CFG, sc->sc_interrupt_cfg);
2198
2199         /* enable VBUS and ID interrupt */
2200         SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2201             SOTG_IRQ_ENABLE_CLR(0xFFFF));
2202         SAF1761_WRITE_LE_4(sc, SOTG_IRQ_ENABLE_SET_CLR,
2203             SOTG_IRQ_ENABLE_SET(SOTG_IRQ_ID | SOTG_IRQ_VBUS_VLD));
2204
2205         /* enable interrupts */
2206         sc->sc_intr_enable = SOTG_DCINTERRUPT_IEVBUS |
2207             SOTG_DCINTERRUPT_IEBRST | SOTG_DCINTERRUPT_IESUSP;
2208         SAF1761_WRITE_LE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
2209
2210         /*
2211          * Connect ATX port 1 to device controller, select external
2212          * charge pump and driver VBUS to +5V:
2213          */
2214         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2215             SOTG_CTRL_CLR(0xFFFF));
2216         SAF1761_WRITE_LE_4(sc, SOTG_CTRL_SET_CLR,
2217             SOTG_CTRL_SET(SOTG_CTRL_SW_SEL_HC_DC |
2218             SOTG_CTRL_BDIS_ACON_EN | SOTG_CTRL_SEL_CP_EXT |
2219             SOTG_CTRL_VBUS_DRV));
2220
2221         /* disable device address */
2222         SAF1761_WRITE_LE_4(sc, SOTG_ADDRESS, 0);
2223
2224         /* enable host controller clock and preserve reserved bits */
2225         x = SAF1761_READ_LE_4(sc, SOTG_POWER_DOWN);
2226         SAF1761_WRITE_LE_4(sc, SOTG_POWER_DOWN, x | SOTG_POWER_DOWN_HC_CLK_EN);
2227
2228         /* wait 10ms for clock */
2229         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
2230
2231         /* enable configuration flag */
2232         SAF1761_WRITE_LE_4(sc, SOTG_CONFIGFLAG, SOTG_CONFIGFLAG_ENABLE);
2233
2234         /* clear RAM block */
2235         for (x = 0x400; x != 0x10000; x += 4)
2236                 SAF1761_WRITE_LE_4(sc, x, 0);
2237
2238         /* start the HC */
2239         SAF1761_WRITE_LE_4(sc, SOTG_USBCMD, SOTG_USBCMD_RS);
2240
2241         DPRINTF("USBCMD=0x%08x\n", SAF1761_READ_LE_4(sc, SOTG_USBCMD));
2242
2243         /* make HC scan all PTDs */
2244         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_LAST_PTD, (1 << 31));
2245         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_LAST_PTD, (1 << 31));
2246         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_LAST_PTD, (1 << 31));
2247
2248         /* skip all PTDs by default */
2249         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD, -1U);
2250         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD, -1U);
2251         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD, -1U);
2252
2253         /* activate all PTD types */
2254         SAF1761_WRITE_LE_4(sc, SOTG_HCBUFFERSTATUS,
2255             SOTG_HCBUFFERSTATUS_ISO_BUF_FILL |
2256             SOTG_HCBUFFERSTATUS_INT_BUF_FILL |
2257             SOTG_HCBUFFERSTATUS_ATL_BUF_FILL);
2258
2259         /* we don't use the AND mask */
2260         SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_AND, 0);
2261         SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_AND, 0);
2262         SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_AND, 0);
2263
2264         /* enable all PTD OR interrupts by default */
2265         SAF1761_WRITE_LE_4(sc, SOTG_ISO_IRQ_MASK_OR, -1U);
2266         SAF1761_WRITE_LE_4(sc, SOTG_INT_IRQ_MASK_OR, -1U);
2267         SAF1761_WRITE_LE_4(sc, SOTG_ATL_IRQ_MASK_OR, -1U);
2268
2269         /* enable HC interrupts */
2270         SAF1761_WRITE_LE_4(sc, SOTG_HCINTERRUPT_ENABLE,
2271             SOTG_HCINTERRUPT_OTG_IRQ |
2272             SOTG_HCINTERRUPT_ISO_IRQ |
2273             SOTG_HCINTERRUPT_ALT_IRQ |
2274             SOTG_HCINTERRUPT_INT_IRQ);
2275
2276         /* poll initial VBUS status */
2277         saf1761_otg_update_vbus(sc);
2278
2279         USB_BUS_UNLOCK(&sc->sc_bus);
2280
2281         /* catch any lost interrupts */
2282
2283         saf1761_otg_do_poll(&sc->sc_bus);
2284
2285         return (0);                     /* success */
2286 }
2287
2288 void
2289 saf1761_otg_uninit(struct saf1761_otg_softc *sc)
2290 {
2291         USB_BUS_LOCK(&sc->sc_bus);
2292
2293         /* disable all interrupts */
2294         SAF1761_WRITE_LE_4(sc, SOTG_MODE, 0);
2295
2296         sc->sc_flags.port_powered = 0;
2297         sc->sc_flags.status_vbus = 0;
2298         sc->sc_flags.status_bus_reset = 0;
2299         sc->sc_flags.status_suspend = 0;
2300         sc->sc_flags.change_suspend = 0;
2301         sc->sc_flags.change_connect = 1;
2302
2303         saf1761_otg_pull_down(sc);
2304         USB_BUS_UNLOCK(&sc->sc_bus);
2305 }
2306
2307 static void
2308 saf1761_otg_suspend(struct saf1761_otg_softc *sc)
2309 {
2310         /* TODO */
2311 }
2312
2313 static void
2314 saf1761_otg_resume(struct saf1761_otg_softc *sc)
2315 {
2316         /* TODO */
2317 }
2318
2319 static void
2320 saf1761_otg_do_poll(struct usb_bus *bus)
2321 {
2322         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
2323
2324         USB_BUS_LOCK(&sc->sc_bus);
2325         USB_BUS_SPIN_LOCK(&sc->sc_bus);
2326         saf1761_otg_interrupt_poll_locked(sc);
2327         saf1761_otg_interrupt_complete_locked(sc);
2328         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
2329         USB_BUS_UNLOCK(&sc->sc_bus);
2330 }
2331
2332 /*------------------------------------------------------------------------*
2333  * saf1761_otg control support
2334  * saf1761_otg interrupt support
2335  * saf1761_otg bulk support
2336  *------------------------------------------------------------------------*/
2337 static void
2338 saf1761_otg_device_non_isoc_open(struct usb_xfer *xfer)
2339 {
2340         return;
2341 }
2342
2343 static void
2344 saf1761_otg_device_non_isoc_close(struct usb_xfer *xfer)
2345 {
2346         saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2347 }
2348
2349 static void
2350 saf1761_otg_device_non_isoc_enter(struct usb_xfer *xfer)
2351 {
2352         return;
2353 }
2354
2355 static void
2356 saf1761_otg_device_non_isoc_start(struct usb_xfer *xfer)
2357 {
2358         /* setup TDs */
2359         saf1761_otg_setup_standard_chain(xfer);
2360         saf1761_otg_start_standard_chain(xfer);
2361 }
2362
2363 static const struct usb_pipe_methods saf1761_otg_non_isoc_methods =
2364 {
2365         .open = saf1761_otg_device_non_isoc_open,
2366         .close = saf1761_otg_device_non_isoc_close,
2367         .enter = saf1761_otg_device_non_isoc_enter,
2368         .start = saf1761_otg_device_non_isoc_start,
2369 };
2370
2371 /*------------------------------------------------------------------------*
2372  * saf1761_otg isochronous support
2373  *------------------------------------------------------------------------*/
2374 static void
2375 saf1761_otg_device_isoc_open(struct usb_xfer *xfer)
2376 {
2377         return;
2378 }
2379
2380 static void
2381 saf1761_otg_device_isoc_close(struct usb_xfer *xfer)
2382 {
2383         saf1761_otg_device_done(xfer, USB_ERR_CANCELLED);
2384 }
2385
2386 static void
2387 saf1761_otg_device_isoc_enter(struct usb_xfer *xfer)
2388 {
2389         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(xfer->xroot->bus);
2390         uint32_t temp;
2391         uint32_t nframes;
2392
2393         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2394             xfer, xfer->endpoint->isoc_next, xfer->nframes);
2395
2396         /* get the current frame index - we don't need the high bits */
2397
2398         nframes = SAF1761_READ_LE_4(sc, SOTG_FRAME_NUM);
2399
2400         /*
2401          * check if the frame index is within the window where the
2402          * frames will be inserted
2403          */
2404         temp = (nframes - xfer->endpoint->isoc_next) & SOTG_FRAME_NUM_SOFR_MASK;
2405
2406         if ((xfer->endpoint->is_synced == 0) ||
2407             (temp < xfer->nframes)) {
2408                 /*
2409                  * If there is data underflow or the pipe queue is
2410                  * empty we schedule the transfer a few frames ahead
2411                  * of the current frame position. Else two isochronous
2412                  * transfers might overlap.
2413                  */
2414                 xfer->endpoint->isoc_next = (nframes + 3) & SOTG_FRAME_NUM_SOFR_MASK;
2415                 xfer->endpoint->is_synced = 1;
2416                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2417         }
2418         /*
2419          * compute how many milliseconds the insertion is ahead of the
2420          * current frame position:
2421          */
2422         temp = (xfer->endpoint->isoc_next - nframes) & SOTG_FRAME_NUM_SOFR_MASK;
2423
2424         /*
2425          * pre-compute when the isochronous transfer will be finished:
2426          */
2427         xfer->isoc_time_complete =
2428             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2429             xfer->nframes;
2430
2431         /* compute frame number for next insertion */
2432         xfer->endpoint->isoc_next += xfer->nframes;
2433
2434         /* setup TDs */
2435         saf1761_otg_setup_standard_chain(xfer);
2436 }
2437
2438 static void
2439 saf1761_otg_device_isoc_start(struct usb_xfer *xfer)
2440 {
2441         /* start TD chain */
2442         saf1761_otg_start_standard_chain(xfer);
2443 }
2444
2445 static const struct usb_pipe_methods saf1761_otg_device_isoc_methods =
2446 {
2447         .open = saf1761_otg_device_isoc_open,
2448         .close = saf1761_otg_device_isoc_close,
2449         .enter = saf1761_otg_device_isoc_enter,
2450         .start = saf1761_otg_device_isoc_start,
2451 };
2452
2453 /*------------------------------------------------------------------------*
2454  * saf1761_otg root control support
2455  *------------------------------------------------------------------------*
2456  * Simulate a hardware HUB by handling all the necessary requests.
2457  *------------------------------------------------------------------------*/
2458
2459 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
2460
2461 static const struct usb_device_descriptor saf1761_otg_devd = {
2462         .bLength = sizeof(struct usb_device_descriptor),
2463         .bDescriptorType = UDESC_DEVICE,
2464         HSETW(.idVendor, 0x04cc),
2465         HSETW(.idProduct, 0x1761),
2466         .bcdUSB = {0x00, 0x02},
2467         .bDeviceClass = UDCLASS_HUB,
2468         .bDeviceSubClass = UDSUBCLASS_HUB,
2469         .bDeviceProtocol = UDPROTO_FSHUB,
2470         .bMaxPacketSize = 64,
2471         .bcdDevice = {0x00, 0x01},
2472         .iManufacturer = 1,
2473         .iProduct = 2,
2474         .bNumConfigurations = 1,
2475 };
2476
2477 static const struct usb_device_qualifier saf1761_otg_odevd = {
2478         .bLength = sizeof(struct usb_device_qualifier),
2479         .bDescriptorType = UDESC_DEVICE_QUALIFIER,
2480         .bcdUSB = {0x00, 0x02},
2481         .bDeviceClass = UDCLASS_HUB,
2482         .bDeviceSubClass = UDSUBCLASS_HUB,
2483         .bDeviceProtocol = UDPROTO_FSHUB,
2484         .bMaxPacketSize0 = 0,
2485         .bNumConfigurations = 0,
2486 };
2487
2488 static const struct saf1761_otg_config_desc saf1761_otg_confd = {
2489         .confd = {
2490                 .bLength = sizeof(struct usb_config_descriptor),
2491                 .bDescriptorType = UDESC_CONFIG,
2492                 .wTotalLength[0] = sizeof(saf1761_otg_confd),
2493                 .bNumInterface = 1,
2494                 .bConfigurationValue = 1,
2495                 .iConfiguration = 0,
2496                 .bmAttributes = UC_SELF_POWERED,
2497                 .bMaxPower = 0,
2498         },
2499         .ifcd = {
2500                 .bLength = sizeof(struct usb_interface_descriptor),
2501                 .bDescriptorType = UDESC_INTERFACE,
2502                 .bNumEndpoints = 1,
2503                 .bInterfaceClass = UICLASS_HUB,
2504                 .bInterfaceSubClass = UISUBCLASS_HUB,
2505                 .bInterfaceProtocol = 0,
2506         },
2507
2508         .endpd = {
2509                 .bLength = sizeof(struct usb_endpoint_descriptor),
2510                 .bDescriptorType = UDESC_ENDPOINT,
2511                 .bEndpointAddress = (UE_DIR_IN | SAF1761_OTG_INTR_ENDPT),
2512                 .bmAttributes = UE_INTERRUPT,
2513                 .wMaxPacketSize[0] = 8,
2514                 .bInterval = 255,
2515         },
2516 };
2517
2518 static const struct usb_hub_descriptor_min saf1761_otg_hubd = {
2519         .bDescLength = sizeof(saf1761_otg_hubd),
2520         .bDescriptorType = UDESC_HUB,
2521         .bNbrPorts = SOTG_NUM_PORTS,
2522         HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
2523         .bPwrOn2PwrGood = 50,
2524         .bHubContrCurrent = 0,
2525         .DeviceRemovable = {0},         /* port is removable */
2526 };
2527
2528 #define STRING_VENDOR \
2529   "N\0X\0P"
2530
2531 #define STRING_PRODUCT \
2532   "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
2533
2534 USB_MAKE_STRING_DESC(STRING_VENDOR, saf1761_otg_vendor);
2535 USB_MAKE_STRING_DESC(STRING_PRODUCT, saf1761_otg_product);
2536
2537 static usb_error_t
2538 saf1761_otg_roothub_exec(struct usb_device *udev,
2539     struct usb_device_request *req, const void **pptr, uint16_t *plength)
2540 {
2541         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(udev->bus);
2542         const void *ptr;
2543         uint16_t len;
2544         uint16_t value;
2545         uint16_t index;
2546         uint32_t temp;
2547         uint32_t i;
2548         usb_error_t err;
2549
2550         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2551
2552         /* buffer reset */
2553         ptr = (const void *)&sc->sc_hub_temp;
2554         len = 0;
2555         err = 0;
2556
2557         value = UGETW(req->wValue);
2558         index = UGETW(req->wIndex);
2559
2560         /* demultiplex the control request */
2561
2562         switch (req->bmRequestType) {
2563         case UT_READ_DEVICE:
2564                 switch (req->bRequest) {
2565                 case UR_GET_DESCRIPTOR:
2566                         goto tr_handle_get_descriptor;
2567                 case UR_GET_CONFIG:
2568                         goto tr_handle_get_config;
2569                 case UR_GET_STATUS:
2570                         goto tr_handle_get_status;
2571                 default:
2572                         goto tr_stalled;
2573                 }
2574                 break;
2575
2576         case UT_WRITE_DEVICE:
2577                 switch (req->bRequest) {
2578                 case UR_SET_ADDRESS:
2579                         goto tr_handle_set_address;
2580                 case UR_SET_CONFIG:
2581                         goto tr_handle_set_config;
2582                 case UR_CLEAR_FEATURE:
2583                         goto tr_valid;  /* nop */
2584                 case UR_SET_DESCRIPTOR:
2585                         goto tr_valid;  /* nop */
2586                 case UR_SET_FEATURE:
2587                 default:
2588                         goto tr_stalled;
2589                 }
2590                 break;
2591
2592         case UT_WRITE_ENDPOINT:
2593                 switch (req->bRequest) {
2594                 case UR_CLEAR_FEATURE:
2595                         switch (UGETW(req->wValue)) {
2596                         case UF_ENDPOINT_HALT:
2597                                 goto tr_handle_clear_halt;
2598                         case UF_DEVICE_REMOTE_WAKEUP:
2599                                 goto tr_handle_clear_wakeup;
2600                         default:
2601                                 goto tr_stalled;
2602                         }
2603                         break;
2604                 case UR_SET_FEATURE:
2605                         switch (UGETW(req->wValue)) {
2606                         case UF_ENDPOINT_HALT:
2607                                 goto tr_handle_set_halt;
2608                         case UF_DEVICE_REMOTE_WAKEUP:
2609                                 goto tr_handle_set_wakeup;
2610                         default:
2611                                 goto tr_stalled;
2612                         }
2613                         break;
2614                 case UR_SYNCH_FRAME:
2615                         goto tr_valid;  /* nop */
2616                 default:
2617                         goto tr_stalled;
2618                 }
2619                 break;
2620
2621         case UT_READ_ENDPOINT:
2622                 switch (req->bRequest) {
2623                 case UR_GET_STATUS:
2624                         goto tr_handle_get_ep_status;
2625                 default:
2626                         goto tr_stalled;
2627                 }
2628                 break;
2629
2630         case UT_WRITE_INTERFACE:
2631                 switch (req->bRequest) {
2632                 case UR_SET_INTERFACE:
2633                         goto tr_handle_set_interface;
2634                 case UR_CLEAR_FEATURE:
2635                         goto tr_valid;  /* nop */
2636                 case UR_SET_FEATURE:
2637                 default:
2638                         goto tr_stalled;
2639                 }
2640                 break;
2641
2642         case UT_READ_INTERFACE:
2643                 switch (req->bRequest) {
2644                 case UR_GET_INTERFACE:
2645                         goto tr_handle_get_interface;
2646                 case UR_GET_STATUS:
2647                         goto tr_handle_get_iface_status;
2648                 default:
2649                         goto tr_stalled;
2650                 }
2651                 break;
2652
2653         case UT_WRITE_CLASS_INTERFACE:
2654         case UT_WRITE_VENDOR_INTERFACE:
2655                 /* XXX forward */
2656                 break;
2657
2658         case UT_READ_CLASS_INTERFACE:
2659         case UT_READ_VENDOR_INTERFACE:
2660                 /* XXX forward */
2661                 break;
2662
2663         case UT_WRITE_CLASS_DEVICE:
2664                 switch (req->bRequest) {
2665                 case UR_CLEAR_FEATURE:
2666                         goto tr_valid;
2667                 case UR_SET_DESCRIPTOR:
2668                 case UR_SET_FEATURE:
2669                         break;
2670                 default:
2671                         goto tr_stalled;
2672                 }
2673                 break;
2674
2675         case UT_WRITE_CLASS_OTHER:
2676                 switch (req->bRequest) {
2677                 case UR_CLEAR_FEATURE:
2678                         if (index == SOTG_HOST_PORT_NUM)
2679                                 goto tr_handle_clear_port_feature_host;
2680                         else if (index == SOTG_DEVICE_PORT_NUM)
2681                                 goto tr_handle_clear_port_feature_device;
2682                         else
2683                                 goto tr_stalled;
2684                 case UR_SET_FEATURE:
2685                         if (index == SOTG_HOST_PORT_NUM)
2686                                 goto tr_handle_set_port_feature_host;
2687                         else if (index == SOTG_DEVICE_PORT_NUM)
2688                                 goto tr_handle_set_port_feature_device;
2689                         else
2690                                 goto tr_stalled;
2691                 case UR_CLEAR_TT_BUFFER:
2692                 case UR_RESET_TT:
2693                 case UR_STOP_TT:
2694                         goto tr_valid;
2695
2696                 default:
2697                         goto tr_stalled;
2698                 }
2699                 break;
2700
2701         case UT_READ_CLASS_OTHER:
2702                 switch (req->bRequest) {
2703                 case UR_GET_TT_STATE:
2704                         goto tr_handle_get_tt_state;
2705                 case UR_GET_STATUS:
2706                         if (index == SOTG_HOST_PORT_NUM)
2707                                 goto tr_handle_get_port_status_host;
2708                         else if (index == SOTG_DEVICE_PORT_NUM)
2709                                 goto tr_handle_get_port_status_device;
2710                         else
2711                                 goto tr_stalled;
2712                 default:
2713                         goto tr_stalled;
2714                 }
2715                 break;
2716
2717         case UT_READ_CLASS_DEVICE:
2718                 switch (req->bRequest) {
2719                 case UR_GET_DESCRIPTOR:
2720                         goto tr_handle_get_class_descriptor;
2721                 case UR_GET_STATUS:
2722                         goto tr_handle_get_class_status;
2723
2724                 default:
2725                         goto tr_stalled;
2726                 }
2727                 break;
2728         default:
2729                 goto tr_stalled;
2730         }
2731         goto tr_valid;
2732
2733 tr_handle_get_descriptor:
2734         switch (value >> 8) {
2735         case UDESC_DEVICE:
2736                 if (value & 0xff)
2737                         goto tr_stalled;
2738                 len = sizeof(saf1761_otg_devd);
2739                 ptr = (const void *)&saf1761_otg_devd;
2740                 goto tr_valid;
2741         case UDESC_DEVICE_QUALIFIER:
2742                 if (value & 0xff)
2743                         goto tr_stalled;
2744                 len = sizeof(saf1761_otg_odevd);
2745                 ptr = (const void *)&saf1761_otg_odevd;
2746                 goto tr_valid;
2747         case UDESC_CONFIG:
2748                 if (value & 0xff)
2749                         goto tr_stalled;
2750                 len = sizeof(saf1761_otg_confd);
2751                 ptr = (const void *)&saf1761_otg_confd;
2752                 goto tr_valid;
2753         case UDESC_STRING:
2754                 switch (value & 0xff) {
2755                 case 0:         /* Language table */
2756                         len = sizeof(usb_string_lang_en);
2757                         ptr = (const void *)&usb_string_lang_en;
2758                         goto tr_valid;
2759
2760                 case 1:         /* Vendor */
2761                         len = sizeof(saf1761_otg_vendor);
2762                         ptr = (const void *)&saf1761_otg_vendor;
2763                         goto tr_valid;
2764
2765                 case 2:         /* Product */
2766                         len = sizeof(saf1761_otg_product);
2767                         ptr = (const void *)&saf1761_otg_product;
2768                         goto tr_valid;
2769                 default:
2770                         break;
2771                 }
2772                 break;
2773         default:
2774                 goto tr_stalled;
2775         }
2776         goto tr_stalled;
2777
2778 tr_handle_get_config:
2779         len = 1;
2780         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
2781         goto tr_valid;
2782
2783 tr_handle_get_status:
2784         len = 2;
2785         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
2786         goto tr_valid;
2787
2788 tr_handle_set_address:
2789         if (value & 0xFF00)
2790                 goto tr_stalled;
2791
2792         sc->sc_rt_addr = value;
2793         goto tr_valid;
2794
2795 tr_handle_set_config:
2796         if (value >= 2)
2797                 goto tr_stalled;
2798         sc->sc_conf = value;
2799         goto tr_valid;
2800
2801 tr_handle_get_interface:
2802         len = 1;
2803         sc->sc_hub_temp.wValue[0] = 0;
2804         goto tr_valid;
2805
2806 tr_handle_get_tt_state:
2807 tr_handle_get_class_status:
2808 tr_handle_get_iface_status:
2809 tr_handle_get_ep_status:
2810         len = 2;
2811         USETW(sc->sc_hub_temp.wValue, 0);
2812         goto tr_valid;
2813
2814 tr_handle_set_halt:
2815 tr_handle_set_interface:
2816 tr_handle_set_wakeup:
2817 tr_handle_clear_wakeup:
2818 tr_handle_clear_halt:
2819         goto tr_valid;
2820
2821 tr_handle_clear_port_feature_device:
2822         DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
2823
2824         switch (value) {
2825         case UHF_PORT_SUSPEND:
2826                 saf1761_otg_wakeup_peer(sc);
2827                 break;
2828
2829         case UHF_PORT_ENABLE:
2830                 sc->sc_flags.port_enabled = 0;
2831                 break;
2832
2833         case UHF_PORT_TEST:
2834         case UHF_PORT_INDICATOR:
2835         case UHF_C_PORT_ENABLE:
2836         case UHF_C_PORT_OVER_CURRENT:
2837         case UHF_C_PORT_RESET:
2838                 /* nops */
2839                 break;
2840         case UHF_PORT_POWER:
2841                 sc->sc_flags.port_powered = 0;
2842                 saf1761_otg_pull_down(sc);
2843                 break;
2844         case UHF_C_PORT_CONNECTION:
2845                 sc->sc_flags.change_connect = 0;
2846                 break;
2847         case UHF_C_PORT_SUSPEND:
2848                 sc->sc_flags.change_suspend = 0;
2849                 break;
2850         default:
2851                 err = USB_ERR_IOERROR;
2852                 goto tr_valid;
2853         }
2854         goto tr_valid;
2855
2856 tr_handle_clear_port_feature_host:
2857         DPRINTFN(9, "UR_CLEAR_FEATURE on port %d\n", index);
2858
2859         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
2860
2861         switch (value) {
2862         case UHF_PORT_ENABLE:
2863                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PED);
2864                 break;
2865         case UHF_PORT_SUSPEND:
2866                 if ((temp & SOTG_PORTSC1_SUSP) && (!(temp & SOTG_PORTSC1_FPR)))
2867                         SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_FPR);
2868
2869                 /* wait 20ms for resume sequence to complete */
2870                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
2871
2872                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~(SOTG_PORTSC1_SUSP |
2873                     SOTG_PORTSC1_FPR | SOTG_PORTSC1_LS /* High Speed */ ));
2874
2875                 /* 4ms settle time */
2876                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
2877                 break;
2878         case UHF_PORT_INDICATOR:
2879                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PIC);
2880                 break;
2881         case UHF_PORT_TEST:
2882         case UHF_C_PORT_ENABLE:
2883         case UHF_C_PORT_OVER_CURRENT:
2884         case UHF_C_PORT_RESET:
2885         case UHF_C_PORT_SUSPEND:
2886                 /* NOPs */
2887                 break;
2888         case UHF_PORT_POWER:
2889                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_PP);
2890                 break;
2891         case UHF_C_PORT_CONNECTION:
2892                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp & ~SOTG_PORTSC1_ECSC);
2893                 break;
2894         default:
2895                 err = USB_ERR_IOERROR;
2896                 goto tr_valid;
2897         }
2898         goto tr_valid;
2899
2900 tr_handle_set_port_feature_device:
2901         DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
2902
2903         switch (value) {
2904         case UHF_PORT_ENABLE:
2905                 sc->sc_flags.port_enabled = 1;
2906                 break;
2907         case UHF_PORT_SUSPEND:
2908         case UHF_PORT_RESET:
2909         case UHF_PORT_TEST:
2910         case UHF_PORT_INDICATOR:
2911                 /* nops */
2912                 break;
2913         case UHF_PORT_POWER:
2914                 sc->sc_flags.port_powered = 1;
2915                 break;
2916         default:
2917                 err = USB_ERR_IOERROR;
2918                 goto tr_valid;
2919         }
2920         goto tr_valid;
2921
2922 tr_handle_set_port_feature_host:
2923         DPRINTFN(9, "UR_SET_FEATURE on port %d\n", index);
2924
2925         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
2926
2927         switch (value) {
2928         case UHF_PORT_ENABLE:
2929                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PED);
2930                 break;
2931         case UHF_PORT_SUSPEND:
2932                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_SUSP);
2933                 break;
2934         case UHF_PORT_RESET:
2935                 DPRINTFN(6, "reset port %d\n", index);
2936
2937                 /* Start reset sequence. */
2938                 temp &= ~(SOTG_PORTSC1_PED | SOTG_PORTSC1_PR);
2939
2940                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PR);
2941
2942                 /* Wait for reset to complete. */
2943                 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2944                     USB_MS_TO_TICKS(usb_port_root_reset_delay));
2945
2946                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp);
2947
2948                 /* Wait for HC to complete reset. */
2949                 usb_pause_mtx(&sc->sc_bus.bus_mtx, USB_MS_TO_TICKS(2));
2950
2951                 temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
2952
2953                 DPRINTF("After reset, status=0x%08x\n", temp);
2954                 if (temp & SOTG_PORTSC1_PR) {
2955                         device_printf(sc->sc_bus.bdev, "port reset timeout\n");
2956                         err = USB_ERR_TIMEOUT;
2957                         goto tr_valid;
2958                 }
2959                 if (!(temp & SOTG_PORTSC1_PED)) {
2960                         /* Not a high speed device, give up ownership.*/
2961                         SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PO);
2962                         break;
2963                 }
2964                 sc->sc_isreset = 1;
2965                 DPRINTF("port %d reset, status = 0x%08x\n", index, temp);
2966                 break;
2967         case UHF_PORT_POWER:
2968                 DPRINTFN(3, "set port power %d\n", index);
2969                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PP);
2970                 break;
2971
2972         case UHF_PORT_TEST:
2973                 DPRINTFN(3, "set port test %d\n", index);
2974                 break;
2975
2976         case UHF_PORT_INDICATOR:
2977                 DPRINTFN(3, "set port ind %d\n", index);
2978                 SAF1761_WRITE_LE_4(sc, SOTG_PORTSC1, temp | SOTG_PORTSC1_PIC);
2979                 break;
2980         default:
2981                 err = USB_ERR_IOERROR;
2982                 goto tr_valid;
2983         }
2984         goto tr_valid;
2985
2986 tr_handle_get_port_status_device:
2987
2988         DPRINTFN(9, "UR_GET_PORT_STATUS on port %d\n", index);
2989
2990         if (sc->sc_flags.status_vbus) {
2991                 saf1761_otg_pull_up(sc);
2992         } else {
2993                 saf1761_otg_pull_down(sc);
2994         }
2995
2996         /* Select FULL-speed and Device Side Mode */
2997
2998         value = UPS_PORT_MODE_DEVICE;
2999
3000         if (sc->sc_flags.port_powered)
3001                 value |= UPS_PORT_POWER;
3002
3003         if (sc->sc_flags.port_enabled)
3004                 value |= UPS_PORT_ENABLED;
3005
3006         if (sc->sc_flags.status_vbus &&
3007             sc->sc_flags.status_bus_reset)
3008                 value |= UPS_CURRENT_CONNECT_STATUS;
3009
3010         if (sc->sc_flags.status_suspend)
3011                 value |= UPS_SUSPEND;
3012
3013         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
3014
3015         value = 0;
3016
3017         if (sc->sc_flags.change_connect)
3018                 value |= UPS_C_CONNECT_STATUS;
3019
3020         if (sc->sc_flags.change_suspend)
3021                 value |= UPS_C_SUSPEND;
3022
3023         USETW(sc->sc_hub_temp.ps.wPortChange, value);
3024         len = sizeof(sc->sc_hub_temp.ps);
3025         goto tr_valid;
3026
3027 tr_handle_get_port_status_host:
3028
3029         temp = SAF1761_READ_LE_4(sc, SOTG_PORTSC1);
3030
3031         DPRINTFN(9, "UR_GET_PORT_STATUS on port %d = 0x%08x\n", index, temp);
3032
3033         i = UPS_HIGH_SPEED;
3034
3035         if (temp & SOTG_PORTSC1_ECCS)
3036                 i |= UPS_CURRENT_CONNECT_STATUS;
3037         if (temp & SOTG_PORTSC1_PED)
3038                 i |= UPS_PORT_ENABLED;
3039         if ((temp & SOTG_PORTSC1_SUSP) && !(temp & SOTG_PORTSC1_FPR))
3040                 i |= UPS_SUSPEND;
3041         if (temp & SOTG_PORTSC1_PR)
3042                 i |= UPS_RESET;
3043         if (temp & SOTG_PORTSC1_PP)
3044                 i |= UPS_PORT_POWER;
3045
3046         USETW(sc->sc_hub_temp.ps.wPortStatus, i);
3047         i = 0;
3048
3049         if (temp & SOTG_PORTSC1_ECSC)
3050                 i |= UPS_C_CONNECT_STATUS;
3051         if (temp & SOTG_PORTSC1_FPR)
3052                 i |= UPS_C_SUSPEND;
3053         if (sc->sc_isreset)
3054                 i |= UPS_C_PORT_RESET;
3055         USETW(sc->sc_hub_temp.ps.wPortChange, i);
3056         len = sizeof(sc->sc_hub_temp.ps);
3057         goto tr_valid;
3058
3059 tr_handle_get_class_descriptor:
3060         if (value & 0xFF)
3061                 goto tr_stalled;
3062         ptr = (const void *)&saf1761_otg_hubd;
3063         len = sizeof(saf1761_otg_hubd);
3064         goto tr_valid;
3065
3066 tr_stalled:
3067         err = USB_ERR_STALLED;
3068 tr_valid:
3069         *plength = len;
3070         *pptr = ptr;
3071         return (err);
3072 }
3073
3074 static void
3075 saf1761_otg_xfer_setup(struct usb_setup_params *parm)
3076 {
3077         struct saf1761_otg_softc *sc;
3078         struct usb_xfer *xfer;
3079         void *last_obj;
3080         uint32_t dw1;
3081         uint32_t ntd;
3082         uint32_t n;
3083         uint8_t ep_no;
3084         uint8_t ep_type;
3085
3086         sc = SAF1761_OTG_BUS2SC(parm->udev->bus);
3087         xfer = parm->curr_xfer;
3088
3089         /*
3090          * NOTE: This driver does not use any of the parameters that
3091          * are computed from the following values. Just set some
3092          * reasonable dummies:
3093          */
3094         parm->hc_max_packet_size = 0x500;
3095         parm->hc_max_packet_count = 1;
3096         parm->hc_max_frame_size = 0x500;
3097
3098         usbd_transfer_setup_sub(parm);
3099
3100         /*
3101          * Compute maximum number of TDs:
3102          */
3103         ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE);
3104
3105         if (ep_type == UE_CONTROL) {
3106
3107                 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC */ ;
3108
3109         } else {
3110                 ntd = xfer->nframes + 1 /* SYNC */ ;
3111         }
3112
3113         /*
3114          * check if "usbd_transfer_setup_sub" set an error
3115          */
3116         if (parm->err)
3117                 return;
3118
3119         /*
3120          * allocate transfer descriptors
3121          */
3122         last_obj = NULL;
3123
3124         ep_no = xfer->endpointno & UE_ADDR;
3125
3126         /*
3127          * Check profile stuff
3128          */
3129         if (parm->udev->flags.usb_mode == USB_MODE_DEVICE) {
3130                 const struct usb_hw_ep_profile *pf;
3131
3132                 saf1761_otg_get_hw_ep_profile(parm->udev, &pf, ep_no);
3133
3134                 if (pf == NULL) {
3135                         /* should not happen */
3136                         parm->err = USB_ERR_INVAL;
3137                         return;
3138                 }
3139         }
3140
3141         dw1 = (xfer->address << 3) | (ep_type << 12);
3142
3143         switch (parm->udev->speed) {
3144         case USB_SPEED_FULL:
3145         case USB_SPEED_LOW:
3146                 /* check if root HUB port is running High Speed */
3147                 if (parm->udev->parent_hs_hub != NULL) {
3148                         dw1 |= SOTG_PTD_DW1_ENABLE_SPLIT;
3149                         dw1 |= (parm->udev->hs_port_no << 18);
3150                         dw1 |= (parm->udev->hs_hub_addr << 25);
3151                         if (parm->udev->speed == USB_SPEED_LOW)
3152                                 dw1 |= (1 << 17);
3153                 }
3154                 break;
3155         default:
3156                 break;
3157         }
3158
3159         /* align data */
3160         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
3161
3162         for (n = 0; n != ntd; n++) {
3163
3164                 struct saf1761_otg_td *td;
3165
3166                 if (parm->buf) {
3167
3168                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
3169
3170                         /* init TD */
3171                         td->max_packet_size = xfer->max_packet_size;
3172                         td->ep_index = ep_no;
3173                         td->ep_type = ep_type;
3174                         td->dw1_value = dw1;
3175                         td->uframe = 0;
3176                         if (ep_type == UE_INTERRUPT) {
3177                                 if (xfer->interval > 32)
3178                                         td->interval = (32 / 2) << 3;
3179                                 else
3180                                         td->interval = (xfer->interval / 2) << 3;
3181                         } else {
3182                                 td->interval = 0;
3183                         }
3184                         td->obj_next = last_obj;
3185
3186                         last_obj = td;
3187                 }
3188                 parm->size[0] += sizeof(*td);
3189         }
3190
3191         xfer->td_start[0] = last_obj;
3192 }
3193
3194 static void
3195 saf1761_otg_xfer_unsetup(struct usb_xfer *xfer)
3196 {
3197 }
3198
3199 static void
3200 saf1761_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3201     struct usb_endpoint *ep)
3202 {
3203         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3204             ep, udev->address,
3205             edesc->bEndpointAddress, udev->flags.usb_mode);
3206
3207         if (udev->parent_hub == NULL) {
3208                 /* root HUB has special endpoint handling */
3209                 return;
3210         }
3211
3212         if (udev->flags.usb_mode == USB_MODE_DEVICE) {
3213                 if (udev->speed != USB_SPEED_FULL &&
3214                     udev->speed != USB_SPEED_HIGH) {
3215                         /* not supported */
3216                         return;
3217                 }
3218                 switch (edesc->bmAttributes & UE_XFERTYPE) {
3219                 case UE_ISOCHRONOUS:
3220                         ep->methods = &saf1761_otg_device_isoc_methods;
3221                         break;
3222                 default:
3223                         ep->methods = &saf1761_otg_non_isoc_methods;
3224                         break;
3225                 }
3226         } else {
3227                 switch (edesc->bmAttributes & UE_XFERTYPE) {
3228                 case UE_CONTROL:
3229                 case UE_BULK:
3230                 case UE_INTERRUPT:
3231                         ep->methods = &saf1761_otg_non_isoc_methods;
3232                         break;
3233                 default:
3234                         /* TODO */
3235                         break;
3236                 }
3237         }
3238 }
3239
3240 static void
3241 saf1761_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3242 {
3243         struct saf1761_otg_softc *sc = SAF1761_OTG_BUS2SC(bus);
3244
3245         switch (state) {
3246         case USB_HW_POWER_SUSPEND:
3247                 saf1761_otg_suspend(sc);
3248                 break;
3249         case USB_HW_POWER_SHUTDOWN:
3250                 saf1761_otg_uninit(sc);
3251                 break;
3252         case USB_HW_POWER_RESUME:
3253                 saf1761_otg_resume(sc);
3254                 break;
3255         default:
3256                 break;
3257         }
3258 }
3259
3260 static void
3261 saf1761_otg_device_resume(struct usb_device *udev)
3262 {
3263         struct saf1761_otg_softc *sc;
3264         struct saf1761_otg_td *td;
3265         struct usb_xfer *xfer;
3266         uint8_t x;
3267
3268         DPRINTF("\n");
3269
3270         if (udev->flags.usb_mode != USB_MODE_HOST)
3271                 return;
3272
3273         sc = SAF1761_OTG_BUS2SC(udev->bus);
3274
3275         USB_BUS_LOCK(&sc->sc_bus);
3276         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3277
3278         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3279
3280                 if (xfer->xroot->udev != udev)
3281                         continue;
3282
3283                 td = xfer->td_transfer_cache;
3284                 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3285                         continue;
3286
3287                 switch (td->ep_type) {
3288                 case UE_INTERRUPT:
3289                         x = td->channel - 32;
3290                         sc->sc_host_intr_suspend_map &= ~(1 << x);
3291                         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3292                             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3293                         break;
3294                 case UE_ISOCHRONOUS:
3295                         x = td->channel;
3296                         sc->sc_host_isoc_suspend_map &= ~(1 << x);
3297                         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3298                             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3299                         break;
3300                 default:
3301                         x = td->channel - 64;
3302                         sc->sc_host_async_suspend_map &= ~(1 << x);
3303                         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3304                             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3305                         break;
3306                 }
3307         }
3308
3309         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3310         USB_BUS_UNLOCK(&sc->sc_bus);
3311
3312         /* poll all transfers again to restart resumed ones */
3313         saf1761_otg_do_poll(&sc->sc_bus);
3314 }
3315
3316 static void
3317 saf1761_otg_device_suspend(struct usb_device *udev)
3318 {
3319         struct saf1761_otg_softc *sc;
3320         struct saf1761_otg_td *td;
3321         struct usb_xfer *xfer;
3322         uint8_t x;
3323
3324         DPRINTF("\n");
3325
3326         if (udev->flags.usb_mode != USB_MODE_HOST)
3327                 return;
3328
3329         sc = SAF1761_OTG_BUS2SC(udev->bus);
3330
3331         USB_BUS_LOCK(&sc->sc_bus);
3332         USB_BUS_SPIN_LOCK(&sc->sc_bus);
3333
3334         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3335
3336                 if (xfer->xroot->udev != udev)
3337                         continue;
3338
3339                 td = xfer->td_transfer_cache;
3340                 if (td == NULL || td->channel >= SOTG_HOST_CHANNEL_MAX)
3341                         continue;
3342
3343                 switch (td->ep_type) {
3344                 case UE_INTERRUPT:
3345                         x = td->channel - 32;
3346                         sc->sc_host_intr_suspend_map |= (1 << x);
3347                         SAF1761_WRITE_LE_4(sc, SOTG_INT_PTD_SKIP_PTD,
3348                             (~sc->sc_host_intr_map) | sc->sc_host_intr_suspend_map);
3349                         break;
3350                 case UE_ISOCHRONOUS:
3351                         x = td->channel;
3352                         sc->sc_host_isoc_suspend_map |= (1 << x);
3353                         SAF1761_WRITE_LE_4(sc, SOTG_ISO_PTD_SKIP_PTD,
3354                             (~sc->sc_host_isoc_map) | sc->sc_host_isoc_suspend_map);
3355                         break;
3356                 default:
3357                         x = td->channel - 64;
3358                         sc->sc_host_async_suspend_map |= (1 << x);
3359                         SAF1761_WRITE_LE_4(sc, SOTG_ATL_PTD_SKIP_PTD,
3360                             (~sc->sc_host_async_map) | sc->sc_host_async_suspend_map);
3361                         break;
3362                 }
3363         }
3364
3365         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
3366         USB_BUS_UNLOCK(&sc->sc_bus);
3367 }
3368
3369 static const struct usb_bus_methods saf1761_otg_bus_methods =
3370 {
3371         .endpoint_init = &saf1761_otg_ep_init,
3372         .xfer_setup = &saf1761_otg_xfer_setup,
3373         .xfer_unsetup = &saf1761_otg_xfer_unsetup,
3374         .get_hw_ep_profile = &saf1761_otg_get_hw_ep_profile,
3375         .xfer_stall = &saf1761_otg_xfer_stall,
3376         .set_stall = &saf1761_otg_set_stall,
3377         .clear_stall = &saf1761_otg_clear_stall,
3378         .roothub_exec = &saf1761_otg_roothub_exec,
3379         .xfer_poll = &saf1761_otg_do_poll,
3380         .set_hw_power_sleep = saf1761_otg_set_hw_power_sleep,
3381         .device_resume = &saf1761_otg_device_resume,
3382         .device_suspend = &saf1761_otg_device_suspend,
3383 };