3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
6 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
7 * Copyright (c) 1998 Lennart Augustsson. All rights reserved.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * USB Universal Host Controller driver.
33 * Handles e.g. PIIX3 and PIIX4.
35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm
36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip
37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
41 #ifdef USB_GLOBAL_INCLUDE_FILE
42 #include USB_GLOBAL_INCLUDE_FILE
44 #include <sys/stdint.h>
45 #include <sys/stddef.h>
46 #include <sys/param.h>
47 #include <sys/queue.h>
48 #include <sys/types.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/condvar.h>
56 #include <sys/sysctl.h>
58 #include <sys/unistd.h>
59 #include <sys/callout.h>
60 #include <sys/malloc.h>
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #define USB_DEBUG_VAR uhcidebug
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #endif /* USB_GLOBAL_INCLUDE_FILE */
81 #include <dev/usb/controller/uhci.h>
82 #include <dev/usb/controller/uhcireg.h>
85 #define UHCI_BUS2SC(bus) \
86 ((uhci_softc_t *)(((uint8_t *)(bus)) - \
87 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus))))
90 static int uhcidebug = 0;
91 static int uhcinoloop = 0;
93 static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
95 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RWTUN,
96 &uhcidebug, 0, "uhci debug level");
97 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RWTUN,
98 &uhcinoloop, 0, "uhci noloop");
100 static void uhci_dumpregs(uhci_softc_t *sc);
101 static void uhci_dump_tds(uhci_td_t *td);
105 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \
106 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
107 #define UWRITE1(sc, r, x) \
108 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
109 } while (/*CONSTCOND*/0)
110 #define UWRITE2(sc, r, x) \
111 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
112 } while (/*CONSTCOND*/0)
113 #define UWRITE4(sc, r, x) \
114 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
115 } while (/*CONSTCOND*/0)
116 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
117 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
118 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
120 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
121 #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
123 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
125 #define UHCI_INTR_ENDPT 1
127 struct uhci_mem_layout {
128 struct usb_page_search buf_res;
129 struct usb_page_search fix_res;
131 struct usb_page_cache *buf_pc;
132 struct usb_page_cache *fix_pc;
136 uint16_t max_frame_size;
139 struct uhci_std_temp {
140 struct uhci_mem_layout ml;
147 uint16_t max_frame_size;
149 uint8_t setup_alt_next;
153 static const struct usb_bus_methods uhci_bus_methods;
154 static const struct usb_pipe_methods uhci_device_bulk_methods;
155 static const struct usb_pipe_methods uhci_device_ctrl_methods;
156 static const struct usb_pipe_methods uhci_device_intr_methods;
157 static const struct usb_pipe_methods uhci_device_isoc_methods;
159 static uint8_t uhci_restart(uhci_softc_t *sc);
160 static void uhci_do_poll(struct usb_bus *);
161 static void uhci_device_done(struct usb_xfer *, usb_error_t);
162 static void uhci_transfer_intr_enqueue(struct usb_xfer *);
163 static void uhci_timeout(void *);
164 static uint8_t uhci_check_transfer(struct usb_xfer *);
165 static void uhci_root_intr(uhci_softc_t *sc);
168 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
170 struct uhci_softc *sc = UHCI_BUS2SC(bus);
173 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
174 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN);
176 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg,
177 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
179 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg,
180 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
182 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg,
183 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
185 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg,
186 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
188 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg,
189 sizeof(uhci_td_t), UHCI_TD_ALIGN);
191 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) {
192 cb(bus, sc->sc_hw.isoc_start_pc + i,
193 sc->sc_hw.isoc_start_pg + i,
194 sizeof(uhci_td_t), UHCI_TD_ALIGN);
197 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) {
198 cb(bus, sc->sc_hw.intr_start_pc + i,
199 sc->sc_hw.intr_start_pg + i,
200 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
205 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer)
207 ml->buf_pc = xfer->frbuffers + 0;
208 ml->fix_pc = xfer->buf_fixup;
212 ml->max_frame_size = xfer->max_frame_size;
216 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td)
218 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res);
220 if (ml->buf_res.length < td->len) {
221 /* need to do a fixup */
223 usbd_get_page(ml->fix_pc, 0, &ml->fix_res);
225 td->td_buffer = htole32(ml->fix_res.physaddr);
228 * The UHCI driver cannot handle
229 * page crossings, so a fixup is
242 if ((td->td_token & htole32(UHCI_TD_PID)) ==
243 htole32(UHCI_TD_PID_IN)) {
244 td->fix_pc = ml->fix_pc;
245 usb_pc_cpu_invalidate(ml->fix_pc);
250 /* copy data to fixup location */
252 usbd_copy_out(ml->buf_pc, ml->buf_offset,
253 ml->fix_res.buffer, td->len);
255 usb_pc_cpu_flush(ml->fix_pc);
258 /* prepare next fixup */
263 td->td_buffer = htole32(ml->buf_res.physaddr);
267 /* prepare next data location */
269 ml->buf_offset += td->len;
278 uhci_restart(uhci_softc_t *sc)
280 struct usb_page_search buf_res;
282 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
284 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) {
285 DPRINTFN(2, "Already started\n");
289 DPRINTFN(2, "Restarting\n");
291 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
293 /* Reload fresh base address */
294 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr);
297 * Assume 64 byte packets at frame end and start HC controller:
299 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS));
301 /* wait 10 milliseconds */
303 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
305 /* check that controller has started */
307 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
308 DPRINTFN(2, "Failed\n");
315 uhci_reset(uhci_softc_t *sc)
319 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
321 DPRINTF("resetting the HC\n");
323 /* disable interrupts */
325 UWRITE2(sc, UHCI_INTR, 0);
329 UHCICMD(sc, UHCI_CMD_GRESET);
333 usb_pause_mtx(&sc->sc_bus.bus_mtx,
334 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY));
336 /* terminate all transfers */
338 UHCICMD(sc, UHCI_CMD_HCRESET);
340 /* the reset bit goes low when the controller is done */
342 n = UHCI_RESET_TIMEOUT;
344 /* wait one millisecond */
346 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
348 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) {
353 device_printf(sc->sc_bus.bdev,
354 "controller did not reset\n");
360 /* wait one millisecond */
362 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
364 /* check if HC is stopped */
365 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
370 device_printf(sc->sc_bus.bdev,
371 "controller did not stop\n");
375 /* reset frame number */
376 UWRITE2(sc, UHCI_FRNUM, 0);
377 /* set default SOF value */
378 UWRITE1(sc, UHCI_SOF, 0x40);
380 USB_BUS_UNLOCK(&sc->sc_bus);
382 /* stop root interrupt */
383 usb_callout_drain(&sc->sc_root_intr);
385 USB_BUS_LOCK(&sc->sc_bus);
389 uhci_start(uhci_softc_t *sc)
391 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
393 DPRINTFN(2, "enabling\n");
395 /* enable interrupts */
397 UWRITE2(sc, UHCI_INTR,
403 if (uhci_restart(sc)) {
404 device_printf(sc->sc_bus.bdev,
405 "cannot start HC controller\n");
408 /* start root interrupt */
412 static struct uhci_qh *
413 uhci_init_qh(struct usb_page_cache *pc)
415 struct usb_page_search buf_res;
418 usbd_get_page(pc, 0, &buf_res);
423 htole32(buf_res.physaddr) |
424 htole32(UHCI_PTR_QH);
431 static struct uhci_td *
432 uhci_init_td(struct usb_page_cache *pc)
434 struct usb_page_search buf_res;
437 usbd_get_page(pc, 0, &buf_res);
442 htole32(buf_res.physaddr) |
443 htole32(UHCI_PTR_TD);
451 uhci_init(uhci_softc_t *sc)
459 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0);
469 sc->sc_ls_ctl_p_last =
470 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc);
472 sc->sc_fs_ctl_p_last =
473 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc);
476 uhci_init_qh(&sc->sc_hw.bulk_start_pc);
478 sc->sc_reclaim_qh_p =
479 sc->sc_fs_ctl_p_last;
481 /* setup reclaim looping point */
482 sc->sc_reclaim_qh_p =
487 uhci_init_qh(&sc->sc_hw.last_qh_pc);
490 uhci_init_td(&sc->sc_hw.last_td_pc);
492 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) {
493 sc->sc_isoc_p_last[x] =
494 uhci_init_td(sc->sc_hw.isoc_start_pc + x);
497 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) {
498 sc->sc_intr_p_last[x] =
499 uhci_init_qh(sc->sc_hw.intr_start_pc + x);
503 * the QHs are arranged to give poll intervals that are
504 * powers of 2 times 1ms
506 bit = UHCI_IFRAMELIST_COUNT / 2;
513 y = (x ^ bit) | (bit / 2);
516 * the next QH has half the poll interval
518 qh_x = sc->sc_intr_p_last[x];
519 qh_y = sc->sc_intr_p_last[y];
522 qh_x->qh_h_next = qh_y->qh_self;
524 qh_x->qh_e_next = htole32(UHCI_PTR_T);
534 qh_ls = sc->sc_ls_ctl_p_last;
535 qh_intr = sc->sc_intr_p_last[0];
537 /* start QH for interrupt traffic */
538 qh_intr->h_next = qh_ls;
539 qh_intr->qh_h_next = qh_ls->qh_self;
541 qh_intr->qh_e_next = htole32(UHCI_PTR_T);
543 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) {
547 td_x = sc->sc_isoc_p_last[x];
548 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)];
550 /* start TD for isochronous traffic */
552 td_x->td_next = qh_intr->qh_self;
553 td_x->td_status = htole32(UHCI_TD_IOS);
554 td_x->td_token = htole32(0);
555 td_x->td_buffer = htole32(0);
562 qh_ls = sc->sc_ls_ctl_p_last;
563 qh_fs = sc->sc_fs_ctl_p_last;
565 /* start QH where low speed control traffic will be queued */
566 qh_ls->h_next = qh_fs;
567 qh_ls->qh_h_next = qh_fs->qh_self;
569 qh_ls->qh_e_next = htole32(UHCI_PTR_T);
577 qh_ctl = sc->sc_fs_ctl_p_last;
578 qh_blk = sc->sc_bulk_p_last;
580 /* start QH where full speed control traffic will be queued */
581 qh_ctl->h_next = qh_blk;
582 qh_ctl->qh_h_next = qh_blk->qh_self;
584 qh_ctl->qh_e_next = htole32(UHCI_PTR_T);
586 qh_lst = sc->sc_last_qh_p;
588 /* start QH where bulk traffic will be queued */
589 qh_blk->h_next = qh_lst;
590 qh_blk->qh_h_next = qh_lst->qh_self;
592 qh_blk->qh_e_next = htole32(UHCI_PTR_T);
594 td_lst = sc->sc_last_td_p;
596 /* end QH which is used for looping the QHs */
598 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */
599 qh_lst->e_next = td_lst;
600 qh_lst->qh_e_next = td_lst->td_self;
603 * end TD which hangs from the last QH, to avoid a bug in the PIIX
604 * that makes it run berserk otherwise
607 td_lst->td_next = htole32(UHCI_PTR_T);
608 td_lst->td_status = htole32(0); /* inactive */
609 td_lst->td_token = htole32(0);
610 td_lst->td_buffer = htole32(0);
613 struct usb_page_search buf_res;
616 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
618 pframes = buf_res.buffer;
621 * Setup UHCI framelist
625 * pframes -> full speed isochronous -> interrupt QH's -> low
626 * speed control -> full speed control -> bulk transfers
630 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) {
632 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self;
635 /* flush all cache into memory */
637 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc);
639 /* set up the bus struct */
640 sc->sc_bus.methods = &uhci_bus_methods;
642 USB_BUS_LOCK(&sc->sc_bus);
643 /* reset the controller */
646 /* start the controller */
648 USB_BUS_UNLOCK(&sc->sc_bus);
650 /* catch lost interrupts */
651 uhci_do_poll(&sc->sc_bus);
657 uhci_suspend(uhci_softc_t *sc)
665 USB_BUS_LOCK(&sc->sc_bus);
667 /* stop the controller */
671 /* enter global suspend */
673 UHCICMD(sc, UHCI_CMD_EGSM);
675 USB_BUS_UNLOCK(&sc->sc_bus);
679 uhci_resume(uhci_softc_t *sc)
681 USB_BUS_LOCK(&sc->sc_bus);
683 /* reset the controller */
687 /* force global resume */
689 UHCICMD(sc, UHCI_CMD_FGR);
691 /* and start traffic again */
695 USB_BUS_UNLOCK(&sc->sc_bus);
702 /* catch lost interrupts */
703 uhci_do_poll(&sc->sc_bus);
708 uhci_dumpregs(uhci_softc_t *sc)
710 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, "
711 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n",
712 device_get_nameunit(sc->sc_bus.bdev),
713 UREAD2(sc, UHCI_CMD),
714 UREAD2(sc, UHCI_STS),
715 UREAD2(sc, UHCI_INTR),
716 UREAD2(sc, UHCI_FRNUM),
717 UREAD4(sc, UHCI_FLBASEADDR),
718 UREAD1(sc, UHCI_SOF),
719 UREAD2(sc, UHCI_PORTSC1),
720 UREAD2(sc, UHCI_PORTSC2));
724 uhci_dump_td(uhci_td_t *p)
731 usb_pc_cpu_invalidate(p->page_cache);
733 td_next = le32toh(p->td_next);
734 td_status = le32toh(p->td_status);
735 td_token = le32toh(p->td_token);
738 * Check whether the link pointer in this TD marks the link pointer
741 temp = ((td_next & UHCI_PTR_T) || (td_next == 0));
743 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x "
744 "token=0x%08x buffer=0x%08x\n",
750 le32toh(p->td_buffer));
752 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x,"
753 "addr=%d,endpt=%d,D=%d,maxlen=%d\n",
755 (td_next & 1) ? "-T" : "",
756 (td_next & 2) ? "-Q" : "",
757 (td_next & 4) ? "-VF" : "",
758 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "",
759 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "",
760 (td_status & UHCI_TD_NAK) ? "-NAK" : "",
761 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "",
762 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "",
763 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "",
764 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "",
765 (td_status & UHCI_TD_IOC) ? "-IOC" : "",
766 (td_status & UHCI_TD_IOS) ? "-IOS" : "",
767 (td_status & UHCI_TD_LS) ? "-LS" : "",
768 (td_status & UHCI_TD_SPD) ? "-SPD" : "",
769 UHCI_TD_GET_ERRCNT(td_status),
770 UHCI_TD_GET_ACTLEN(td_status),
771 UHCI_TD_GET_PID(td_token),
772 UHCI_TD_GET_DEVADDR(td_token),
773 UHCI_TD_GET_ENDPT(td_token),
774 UHCI_TD_GET_DT(td_token),
775 UHCI_TD_GET_MAXLEN(td_token));
781 uhci_dump_qh(uhci_qh_t *sqh)
787 usb_pc_cpu_invalidate(sqh->page_cache);
789 qh_h_next = le32toh(sqh->qh_h_next);
790 qh_e_next = le32toh(sqh->qh_e_next);
792 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh,
793 le32toh(sqh->qh_self), qh_h_next, qh_e_next);
795 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) |
796 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0));
802 uhci_dump_all(uhci_softc_t *sc)
805 uhci_dump_qh(sc->sc_ls_ctl_p_last);
806 uhci_dump_qh(sc->sc_fs_ctl_p_last);
807 uhci_dump_qh(sc->sc_bulk_p_last);
808 uhci_dump_qh(sc->sc_last_qh_p);
812 uhci_dump_tds(uhci_td_t *td)
817 if (uhci_dump_td(td)) {
826 * Let the last QH loop back to the full speed control transfer QH.
827 * This is what intel calls "bandwidth reclamation" and improves
828 * USB performance a lot for some devices.
829 * If we are already looping, just count it.
832 uhci_add_loop(uhci_softc_t *sc)
834 struct uhci_qh *qh_lst;
835 struct uhci_qh *qh_rec;
842 if (++(sc->sc_loops) == 1) {
843 DPRINTFN(6, "add\n");
845 qh_lst = sc->sc_last_qh_p;
846 qh_rec = sc->sc_reclaim_qh_p;
848 /* NOTE: we don't loop back the soft pointer */
850 qh_lst->qh_h_next = qh_rec->qh_self;
851 usb_pc_cpu_flush(qh_lst->page_cache);
856 uhci_rem_loop(uhci_softc_t *sc)
858 struct uhci_qh *qh_lst;
865 if (--(sc->sc_loops) == 0) {
866 DPRINTFN(6, "remove\n");
868 qh_lst = sc->sc_last_qh_p;
869 qh_lst->qh_h_next = htole32(UHCI_PTR_T);
870 usb_pc_cpu_flush(qh_lst->page_cache);
875 uhci_transfer_intr_enqueue(struct usb_xfer *xfer)
877 /* check for early completion */
878 if (uhci_check_transfer(xfer)) {
881 /* put transfer on interrupt queue */
882 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
884 /* start timeout, if any */
885 if (xfer->timeout != 0) {
886 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout);
890 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last)
892 _uhci_append_td(uhci_td_t *std, uhci_td_t *last)
894 DPRINTFN(11, "%p to %p\n", std, last);
896 /* (sc->sc_bus.mtx) must be locked */
898 std->next = last->next;
899 std->td_next = last->td_next;
903 usb_pc_cpu_flush(std->page_cache);
906 * the last->next->prev is never followed: std->next->prev = std;
909 last->td_next = std->td_self;
911 usb_pc_cpu_flush(last->page_cache);
916 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last)
918 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last)
920 DPRINTFN(11, "%p to %p\n", sqh, last);
922 if (sqh->h_prev != NULL) {
923 /* should not happen */
924 DPRINTFN(0, "QH already linked!\n");
927 /* (sc->sc_bus.mtx) must be locked */
929 sqh->h_next = last->h_next;
930 sqh->qh_h_next = last->qh_h_next;
934 usb_pc_cpu_flush(sqh->page_cache);
937 * The "last->h_next->h_prev" is never followed:
939 * "sqh->h_next->h_prev" = sqh;
943 last->qh_h_next = sqh->qh_self;
945 usb_pc_cpu_flush(last->page_cache);
952 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last)
954 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last)
956 DPRINTFN(11, "%p from %p\n", std, last);
958 /* (sc->sc_bus.mtx) must be locked */
960 std->prev->next = std->next;
961 std->prev->td_next = std->td_next;
963 usb_pc_cpu_flush(std->prev->page_cache);
966 std->next->prev = std->prev;
967 usb_pc_cpu_flush(std->next->page_cache);
969 return ((last == std) ? std->prev : last);
972 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last)
974 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last)
976 DPRINTFN(11, "%p from %p\n", sqh, last);
978 /* (sc->sc_bus.mtx) must be locked */
980 /* only remove if not removed from a queue */
982 sqh->h_prev->h_next = sqh->h_next;
983 sqh->h_prev->qh_h_next = sqh->qh_h_next;
985 usb_pc_cpu_flush(sqh->h_prev->page_cache);
988 sqh->h_next->h_prev = sqh->h_prev;
989 usb_pc_cpu_flush(sqh->h_next->page_cache);
991 last = ((last == sqh) ? sqh->h_prev : last);
995 usb_pc_cpu_flush(sqh->page_cache);
1001 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer)
1003 struct usb_page_search res;
1004 uint32_t nframes = xfer->nframes;
1006 uint32_t offset = 0;
1007 uint32_t *plen = xfer->frlengths;
1009 uhci_td_t *td = xfer->td_transfer_first;
1010 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos];
1012 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1013 xfer, xfer->endpoint);
1015 /* sync any DMA memory before doing fixups */
1017 usb_bdma_post_sync(xfer);
1021 panic("%s:%d: out of TD's\n",
1022 __FUNCTION__, __LINE__);
1024 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) {
1025 pp_last = &sc->sc_isoc_p_last[0];
1028 if (uhcidebug > 5) {
1029 DPRINTF("isoc TD\n");
1033 usb_pc_cpu_invalidate(td->page_cache);
1034 status = le32toh(td->td_status);
1036 len = UHCI_TD_GET_ACTLEN(status);
1042 usbd_get_page(td->fix_pc, 0, &res);
1044 /* copy data from fixup location to real location */
1046 usb_pc_cpu_invalidate(td->fix_pc);
1048 usbd_copy_in(xfer->frbuffers, offset,
1055 /* remove TD from schedule */
1056 UHCI_REMOVE_TD(td, *pp_last);
1063 xfer->aframes = xfer->nframes;
1067 uhci_non_isoc_done_sub(struct usb_xfer *xfer)
1069 struct usb_page_search res;
1071 uhci_td_t *td_alt_next;
1076 td = xfer->td_transfer_cache;
1077 td_alt_next = td->alt_next;
1079 if (xfer->aframes != xfer->nframes) {
1080 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1083 usb_pc_cpu_invalidate(td->page_cache);
1084 status = le32toh(td->td_status);
1085 token = le32toh(td->td_token);
1088 * Verify the status and add
1089 * up the actual length:
1092 len = UHCI_TD_GET_ACTLEN(status);
1093 if (len > td->len) {
1094 /* should not happen */
1095 DPRINTF("Invalid status length, "
1096 "0x%04x/0x%04x bytes\n", len, td->len);
1097 status |= UHCI_TD_STALLED;
1099 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) {
1101 usbd_get_page(td->fix_pc, 0, &res);
1104 * copy data from fixup location to real
1108 usb_pc_cpu_invalidate(td->fix_pc);
1110 usbd_copy_in(xfer->frbuffers + xfer->aframes,
1111 xfer->frlengths[xfer->aframes], res.buffer, len);
1113 /* update actual length */
1115 xfer->frlengths[xfer->aframes] += len;
1117 /* Check for last transfer */
1118 if (((void *)td) == xfer->td_transfer_last) {
1122 if (status & UHCI_TD_STALLED) {
1123 /* the transfer is finished */
1127 /* Check for short transfer */
1128 if (len != td->len) {
1129 if (xfer->flags_int.short_frames_ok) {
1130 /* follow alt next */
1133 /* the transfer is finished */
1140 if (td->alt_next != td_alt_next) {
1141 /* this USB frame is complete */
1146 /* update transfer cache */
1148 xfer->td_transfer_cache = td;
1150 /* update data toggle */
1152 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1;
1155 if (status & UHCI_TD_ERROR) {
1156 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x "
1157 "status=%s%s%s%s%s%s%s%s%s%s%s\n",
1158 xfer->address, xfer->endpointno, xfer->aframes,
1159 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "",
1160 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "",
1161 (status & UHCI_TD_NAK) ? "[NAK]" : "",
1162 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "",
1163 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "",
1164 (status & UHCI_TD_STALLED) ? "[STALLED]" : "",
1165 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1166 (status & UHCI_TD_IOC) ? "[IOC]" : "",
1167 (status & UHCI_TD_IOS) ? "[IOS]" : "",
1168 (status & UHCI_TD_LS) ? "[LS]" : "",
1169 (status & UHCI_TD_SPD) ? "[SPD]" : "");
1172 if (status & UHCI_TD_STALLED) {
1173 /* try to separate I/O errors from STALL */
1174 if (UHCI_TD_GET_ERRCNT(status) == 0)
1175 return (USB_ERR_IOERROR);
1176 return (USB_ERR_STALLED);
1178 return (USB_ERR_NORMAL_COMPLETION);
1182 uhci_non_isoc_done(struct usb_xfer *xfer)
1184 usb_error_t err = 0;
1186 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1187 xfer, xfer->endpoint);
1190 if (uhcidebug > 10) {
1191 uhci_dump_tds(xfer->td_transfer_first);
1195 /* sync any DMA memory before doing fixups */
1197 usb_bdma_post_sync(xfer);
1201 xfer->td_transfer_cache = xfer->td_transfer_first;
1203 if (xfer->flags_int.control_xfr) {
1204 if (xfer->flags_int.control_hdr) {
1205 err = uhci_non_isoc_done_sub(xfer);
1209 if (xfer->td_transfer_cache == NULL) {
1213 while (xfer->aframes != xfer->nframes) {
1214 err = uhci_non_isoc_done_sub(xfer);
1217 if (xfer->td_transfer_cache == NULL) {
1222 if (xfer->flags_int.control_xfr &&
1223 !xfer->flags_int.control_act) {
1224 err = uhci_non_isoc_done_sub(xfer);
1227 uhci_device_done(xfer, err);
1230 /*------------------------------------------------------------------------*
1231 * uhci_check_transfer_sub
1233 * The main purpose of this function is to update the data-toggle
1234 * in case it is wrong.
1235 *------------------------------------------------------------------------*/
1237 uhci_check_transfer_sub(struct usb_xfer *xfer)
1241 uhci_td_t *td_alt_next;
1246 td = xfer->td_transfer_cache;
1247 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1249 td_token = td->obj_next->td_token;
1251 xfer->td_transfer_cache = td;
1252 td_self = td->td_self;
1253 td_alt_next = td->alt_next;
1255 if (xfer->flags_int.control_xfr)
1256 goto skip; /* don't touch the DT value! */
1258 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1))))
1259 goto skip; /* data toggle has correct value */
1262 * The data toggle is wrong and we need to toggle it !
1265 td->td_token ^= htole32(UHCI_TD_SET_DT(1));
1266 usb_pc_cpu_flush(td->page_cache);
1268 if (td == xfer->td_transfer_last) {
1274 if (td->alt_next != td_alt_next) {
1282 qh->qh_e_next = td_self;
1283 usb_pc_cpu_flush(qh->page_cache);
1285 DPRINTFN(13, "xfer=%p following alt next\n", xfer);
1288 /*------------------------------------------------------------------------*
1289 * uhci_check_transfer
1292 * 0: USB transfer is not finished
1293 * Else: USB transfer is finished
1294 *------------------------------------------------------------------------*/
1296 uhci_check_transfer(struct usb_xfer *xfer)
1302 DPRINTFN(16, "xfer=%p checking transfer\n", xfer);
1304 if (xfer->endpoint->methods == &uhci_device_isoc_methods) {
1305 /* isochronous transfer */
1307 td = xfer->td_transfer_last;
1309 usb_pc_cpu_invalidate(td->page_cache);
1310 status = le32toh(td->td_status);
1312 /* check also if the first is complete */
1314 td = xfer->td_transfer_first;
1316 usb_pc_cpu_invalidate(td->page_cache);
1317 status |= le32toh(td->td_status);
1319 if (!(status & UHCI_TD_ACTIVE)) {
1320 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1324 /* non-isochronous transfer */
1327 * check whether there is an error somewhere
1328 * in the middle, or whether there was a short
1329 * packet (SPD and not ACTIVE)
1331 td = xfer->td_transfer_cache;
1334 usb_pc_cpu_invalidate(td->page_cache);
1335 status = le32toh(td->td_status);
1336 token = le32toh(td->td_token);
1339 * if there is an active TD the transfer isn't done
1341 if (status & UHCI_TD_ACTIVE) {
1343 xfer->td_transfer_cache = td;
1347 * last transfer descriptor makes the transfer done
1349 if (((void *)td) == xfer->td_transfer_last) {
1353 * any kind of error makes the transfer done
1355 if (status & UHCI_TD_STALLED) {
1359 * check if we reached the last packet
1360 * or if there is a short packet:
1362 if ((td->td_next == htole32(UHCI_PTR_T)) ||
1363 (UHCI_TD_GET_ACTLEN(status) < td->len)) {
1364 if (xfer->flags_int.short_frames_ok) {
1365 /* follow alt next */
1368 xfer->td_transfer_cache = td;
1369 uhci_check_transfer_sub(xfer);
1373 /* transfer is done */
1378 uhci_non_isoc_done(xfer);
1383 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1391 uhci_interrupt_poll(uhci_softc_t *sc)
1393 struct usb_xfer *xfer;
1396 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1398 * check if transfer is transferred
1400 if (uhci_check_transfer(xfer)) {
1401 /* queue has been modified */
1407 /*------------------------------------------------------------------------*
1408 * uhci_interrupt - UHCI interrupt handler
1410 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1411 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1413 *------------------------------------------------------------------------*/
1415 uhci_interrupt(uhci_softc_t *sc)
1419 USB_BUS_LOCK(&sc->sc_bus);
1421 DPRINTFN(16, "real interrupt\n");
1424 if (uhcidebug > 15) {
1428 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1430 /* the interrupt was not for us */
1433 if (status & (UHCI_STS_RD | UHCI_STS_HSE |
1434 UHCI_STS_HCPE | UHCI_STS_HCH)) {
1435 if (status & UHCI_STS_RD) {
1437 printf("%s: resume detect\n",
1441 if (status & UHCI_STS_HSE) {
1442 printf("%s: host system error\n",
1445 if (status & UHCI_STS_HCPE) {
1446 printf("%s: host controller process error\n",
1449 if (status & UHCI_STS_HCH) {
1450 /* no acknowledge needed */
1451 DPRINTF("%s: host controller halted\n",
1454 if (uhcidebug > 0) {
1460 /* get acknowledge bits */
1461 status &= (UHCI_STS_USBINT |
1469 /* nothing to acknowledge */
1472 /* acknowledge interrupts */
1473 UWRITE2(sc, UHCI_STS, status);
1475 /* poll all the USB transfers */
1476 uhci_interrupt_poll(sc);
1479 USB_BUS_UNLOCK(&sc->sc_bus);
1483 * called when a request does not complete
1486 uhci_timeout(void *arg)
1488 struct usb_xfer *xfer = arg;
1490 DPRINTF("xfer=%p\n", xfer);
1492 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1494 /* transfer is transferred */
1495 uhci_device_done(xfer, USB_ERR_TIMEOUT);
1499 uhci_do_poll(struct usb_bus *bus)
1501 struct uhci_softc *sc = UHCI_BUS2SC(bus);
1503 USB_BUS_LOCK(&sc->sc_bus);
1504 uhci_interrupt_poll(sc);
1505 USB_BUS_UNLOCK(&sc->sc_bus);
1509 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp)
1513 uhci_td_t *td_alt_next;
1516 uint8_t shortpkt_old;
1520 shortpkt_old = temp->shortpkt;
1521 len_old = temp->len;
1524 /* software is used to detect short incoming transfers */
1526 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) {
1527 temp->td_status |= htole32(UHCI_TD_SPD);
1529 temp->td_status &= ~htole32(UHCI_TD_SPD);
1532 temp->ml.buf_offset = 0;
1536 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0));
1537 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average));
1540 td_next = temp->td_next;
1543 if (temp->len == 0) {
1544 if (temp->shortpkt) {
1547 /* send a Zero Length Packet, ZLP, last */
1550 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0));
1554 average = temp->average;
1556 if (temp->len < average) {
1558 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0));
1559 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len));
1560 average = temp->len;
1564 if (td_next == NULL) {
1565 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__);
1570 td_next = td->obj_next;
1572 /* check if we are pre-computing */
1575 /* update remaining length */
1577 temp->len -= average;
1581 /* fill out current TD */
1583 td->td_status = temp->td_status;
1584 td->td_token = temp->td_token;
1586 /* update data toggle */
1588 temp->td_token ^= htole32(UHCI_TD_SET_DT(1));
1596 /* update remaining length */
1598 temp->len -= average;
1602 /* fill out buffer pointer and do fixup, if any */
1604 uhci_mem_layout_fixup(&temp->ml, td);
1607 td->alt_next = td_alt_next;
1609 if ((td_next == td_alt_next) && temp->setup_alt_next) {
1610 /* we need to receive these frames one by one ! */
1611 td->td_status |= htole32(UHCI_TD_IOC);
1612 td->td_next = htole32(UHCI_PTR_T);
1615 /* link the current TD with the next one */
1616 td->td_next = td_next->td_self;
1620 usb_pc_cpu_flush(td->page_cache);
1626 /* setup alt next pointer, if any */
1627 if (temp->last_frame) {
1630 /* we use this field internally */
1631 td_alt_next = td_next;
1635 temp->shortpkt = shortpkt_old;
1636 temp->len = len_old;
1640 temp->td_next = td_next;
1644 uhci_setup_standard_chain(struct usb_xfer *xfer)
1646 struct uhci_std_temp temp;
1650 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1651 xfer->address, UE_GET_ADDR(xfer->endpointno),
1652 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1654 temp.average = xfer->max_frame_size;
1655 temp.max_frame_size = xfer->max_frame_size;
1657 /* toggle the DMA set we are using */
1658 xfer->flags_int.curr_dma_set ^= 1;
1660 /* get next DMA set */
1661 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1662 xfer->td_transfer_first = td;
1663 xfer->td_transfer_cache = td;
1667 temp.last_frame = 0;
1668 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1670 uhci_mem_layout_init(&temp.ml, xfer);
1673 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) |
1676 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1677 temp.td_status |= htole32(UHCI_TD_LS);
1680 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) |
1681 UHCI_TD_SET_DEVADDR(xfer->address));
1683 if (xfer->endpoint->toggle_next) {
1685 temp.td_token |= htole32(UHCI_TD_SET_DT(1));
1687 /* check if we should prepend a setup message */
1689 if (xfer->flags_int.control_xfr) {
1690 if (xfer->flags_int.control_hdr) {
1691 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1692 UHCI_TD_SET_ENDPT(0xF));
1693 temp.td_token |= htole32(UHCI_TD_PID_SETUP |
1696 temp.len = xfer->frlengths[0];
1697 temp.ml.buf_pc = xfer->frbuffers + 0;
1698 temp.shortpkt = temp.len ? 1 : 0;
1699 /* check for last frame */
1700 if (xfer->nframes == 1) {
1701 /* no STATUS stage yet, SETUP is last */
1702 if (xfer->flags_int.control_act) {
1703 temp.last_frame = 1;
1704 temp.setup_alt_next = 0;
1707 uhci_setup_standard_chain_sub(&temp);
1714 while (x != xfer->nframes) {
1715 /* DATA0 / DATA1 message */
1717 temp.len = xfer->frlengths[x];
1718 temp.ml.buf_pc = xfer->frbuffers + x;
1722 if (x == xfer->nframes) {
1723 if (xfer->flags_int.control_xfr) {
1724 /* no STATUS stage yet, DATA is last */
1725 if (xfer->flags_int.control_act) {
1726 temp.last_frame = 1;
1727 temp.setup_alt_next = 0;
1730 temp.last_frame = 1;
1731 temp.setup_alt_next = 0;
1735 * Keep previous data toggle,
1736 * device address and endpoint number:
1739 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1740 UHCI_TD_SET_ENDPT(0xF) |
1743 if (temp.len == 0) {
1744 /* make sure that we send an USB packet */
1749 /* regular data transfer */
1751 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1754 /* set endpoint direction */
1757 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1758 htole32(UHCI_TD_PID_IN) :
1759 htole32(UHCI_TD_PID_OUT);
1761 uhci_setup_standard_chain_sub(&temp);
1764 /* check if we should append a status stage */
1766 if (xfer->flags_int.control_xfr &&
1767 !xfer->flags_int.control_act) {
1769 * send a DATA1 message and reverse the current endpoint
1773 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1774 UHCI_TD_SET_ENDPT(0xF) |
1777 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1778 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) :
1779 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1));
1782 temp.ml.buf_pc = NULL;
1784 temp.last_frame = 1;
1785 temp.setup_alt_next = 0;
1787 uhci_setup_standard_chain_sub(&temp);
1791 /* Ensure that last TD is terminating: */
1792 td->td_next = htole32(UHCI_PTR_T);
1794 /* set interrupt bit */
1796 td->td_status |= htole32(UHCI_TD_IOC);
1798 usb_pc_cpu_flush(td->page_cache);
1800 /* must have at least one frame! */
1802 xfer->td_transfer_last = td;
1805 if (uhcidebug > 8) {
1806 DPRINTF("nexttog=%d; data before transfer:\n",
1807 xfer->endpoint->toggle_next);
1808 uhci_dump_tds(xfer->td_transfer_first);
1811 return (xfer->td_transfer_first);
1814 /* NOTE: "done" can be run two times in a row,
1815 * from close and from interrupt
1819 uhci_device_done(struct usb_xfer *xfer, usb_error_t error)
1821 const struct usb_pipe_methods *methods = xfer->endpoint->methods;
1822 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1825 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1827 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1828 xfer, xfer->endpoint, error);
1830 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1832 usb_pc_cpu_invalidate(qh->page_cache);
1834 if (xfer->flags_int.bandwidth_reclaimed) {
1835 xfer->flags_int.bandwidth_reclaimed = 0;
1838 if (methods == &uhci_device_bulk_methods) {
1839 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last);
1841 if (methods == &uhci_device_ctrl_methods) {
1842 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1843 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last);
1845 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last);
1848 if (methods == &uhci_device_intr_methods) {
1849 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
1852 * Only finish isochronous transfers once
1853 * which will update "xfer->frlengths".
1855 if (xfer->td_transfer_first &&
1856 xfer->td_transfer_last) {
1857 if (methods == &uhci_device_isoc_methods) {
1858 uhci_isoc_done(sc, xfer);
1860 xfer->td_transfer_first = NULL;
1861 xfer->td_transfer_last = NULL;
1863 /* dequeue transfer and start next transfer */
1864 usbd_transfer_done(xfer, error);
1867 /*------------------------------------------------------------------------*
1869 *------------------------------------------------------------------------*/
1871 uhci_device_bulk_open(struct usb_xfer *xfer)
1877 uhci_device_bulk_close(struct usb_xfer *xfer)
1879 uhci_device_done(xfer, USB_ERR_CANCELLED);
1883 uhci_device_bulk_enter(struct usb_xfer *xfer)
1889 uhci_device_bulk_start(struct usb_xfer *xfer)
1891 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1896 td = uhci_setup_standard_chain(xfer);
1899 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1902 qh->qh_e_next = td->td_self;
1904 if (xfer->xroot->udev->flags.self_suspended == 0) {
1905 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last);
1907 xfer->flags_int.bandwidth_reclaimed = 1;
1909 usb_pc_cpu_flush(qh->page_cache);
1912 /* put transfer on interrupt queue */
1913 uhci_transfer_intr_enqueue(xfer);
1916 static const struct usb_pipe_methods uhci_device_bulk_methods =
1918 .open = uhci_device_bulk_open,
1919 .close = uhci_device_bulk_close,
1920 .enter = uhci_device_bulk_enter,
1921 .start = uhci_device_bulk_start,
1924 /*------------------------------------------------------------------------*
1925 * uhci control support
1926 *------------------------------------------------------------------------*/
1928 uhci_device_ctrl_open(struct usb_xfer *xfer)
1934 uhci_device_ctrl_close(struct usb_xfer *xfer)
1936 uhci_device_done(xfer, USB_ERR_CANCELLED);
1940 uhci_device_ctrl_enter(struct usb_xfer *xfer)
1946 uhci_device_ctrl_start(struct usb_xfer *xfer)
1948 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1953 td = uhci_setup_standard_chain(xfer);
1956 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1959 qh->qh_e_next = td->td_self;
1962 * NOTE: some devices choke on bandwidth- reclamation for control
1965 if (xfer->xroot->udev->flags.self_suspended == 0) {
1966 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1967 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last);
1969 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last);
1972 usb_pc_cpu_flush(qh->page_cache);
1974 /* put transfer on interrupt queue */
1975 uhci_transfer_intr_enqueue(xfer);
1978 static const struct usb_pipe_methods uhci_device_ctrl_methods =
1980 .open = uhci_device_ctrl_open,
1981 .close = uhci_device_ctrl_close,
1982 .enter = uhci_device_ctrl_enter,
1983 .start = uhci_device_ctrl_start,
1986 /*------------------------------------------------------------------------*
1987 * uhci interrupt support
1988 *------------------------------------------------------------------------*/
1990 uhci_device_intr_open(struct usb_xfer *xfer)
1992 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1998 bit = UHCI_IFRAMELIST_COUNT / 2;
2000 if (xfer->interval >= bit) {
2004 if (sc->sc_intr_stat[x] <
2005 sc->sc_intr_stat[best]) {
2015 sc->sc_intr_stat[best]++;
2016 xfer->qh_pos = best;
2018 DPRINTFN(3, "best=%d interval=%d\n",
2019 best, xfer->interval);
2023 uhci_device_intr_close(struct usb_xfer *xfer)
2025 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2027 sc->sc_intr_stat[xfer->qh_pos]--;
2029 uhci_device_done(xfer, USB_ERR_CANCELLED);
2033 uhci_device_intr_enter(struct usb_xfer *xfer)
2039 uhci_device_intr_start(struct usb_xfer *xfer)
2041 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2046 td = uhci_setup_standard_chain(xfer);
2049 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
2052 qh->qh_e_next = td->td_self;
2054 if (xfer->xroot->udev->flags.self_suspended == 0) {
2055 /* enter QHs into the controller data structures */
2056 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
2058 usb_pc_cpu_flush(qh->page_cache);
2061 /* put transfer on interrupt queue */
2062 uhci_transfer_intr_enqueue(xfer);
2065 static const struct usb_pipe_methods uhci_device_intr_methods =
2067 .open = uhci_device_intr_open,
2068 .close = uhci_device_intr_close,
2069 .enter = uhci_device_intr_enter,
2070 .start = uhci_device_intr_start,
2073 /*------------------------------------------------------------------------*
2074 * uhci isochronous support
2075 *------------------------------------------------------------------------*/
2077 uhci_device_isoc_open(struct usb_xfer *xfer)
2084 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
2085 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) :
2086 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0);
2088 td_token = htole32(td_token);
2090 /* initialize all TD's */
2092 for (ds = 0; ds != 2; ds++) {
2093 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2094 /* mark TD as inactive */
2095 td->td_status = htole32(UHCI_TD_IOS);
2096 td->td_token = td_token;
2098 usb_pc_cpu_flush(td->page_cache);
2104 uhci_device_isoc_close(struct usb_xfer *xfer)
2106 uhci_device_done(xfer, USB_ERR_CANCELLED);
2110 uhci_device_isoc_enter(struct usb_xfer *xfer)
2112 struct uhci_mem_layout ml;
2113 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2123 uhci_td_t *td_last = NULL;
2124 uhci_td_t **pp_last;
2126 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2127 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2129 nframes = UREAD2(sc, UHCI_FRNUM);
2131 temp = (nframes - xfer->endpoint->isoc_next) &
2132 (UHCI_VFRAMELIST_COUNT - 1);
2134 if ((xfer->endpoint->is_synced == 0) ||
2135 (temp < xfer->nframes)) {
2137 * If there is data underflow or the pipe queue is empty we
2138 * schedule the transfer a few frames ahead of the current
2139 * frame position. Else two isochronous transfers might
2142 xfer->endpoint->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1);
2143 xfer->endpoint->is_synced = 1;
2144 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2147 * compute how many milliseconds the insertion is ahead of the
2148 * current frame position:
2150 temp = (xfer->endpoint->isoc_next - nframes) &
2151 (UHCI_VFRAMELIST_COUNT - 1);
2154 * pre-compute when the isochronous transfer will be finished:
2156 xfer->isoc_time_complete =
2157 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2160 /* get the real number of frames */
2162 nframes = xfer->nframes;
2164 uhci_mem_layout_init(&ml, xfer);
2166 plen = xfer->frlengths;
2168 /* toggle the DMA set we are using */
2169 xfer->flags_int.curr_dma_set ^= 1;
2171 /* get next DMA set */
2172 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2173 xfer->td_transfer_first = td;
2175 pp_last = &sc->sc_isoc_p_last[xfer->endpoint->isoc_next];
2177 /* store starting position */
2179 xfer->qh_pos = xfer->endpoint->isoc_next;
2183 panic("%s:%d: out of TD's\n",
2184 __FUNCTION__, __LINE__);
2186 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) {
2187 pp_last = &sc->sc_isoc_p_last[0];
2189 if (*plen > xfer->max_frame_size) {
2193 printf("%s: frame length(%d) exceeds %d "
2194 "bytes (frame truncated)\n",
2195 __FUNCTION__, *plen,
2196 xfer->max_frame_size);
2199 *plen = xfer->max_frame_size;
2201 /* reuse td_token from last transfer */
2203 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
2204 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen));
2210 * Do not call "uhci_mem_layout_fixup()" when the
2217 /* fill out buffer pointer and do fixup, if any */
2219 uhci_mem_layout_fixup(&ml, td);
2224 td->td_status = htole32
2225 (UHCI_TD_ZERO_ACTLEN
2226 (UHCI_TD_SET_ERRCNT(0) |
2231 td->td_status = htole32
2232 (UHCI_TD_ZERO_ACTLEN
2233 (UHCI_TD_SET_ERRCNT(0) |
2238 usb_pc_cpu_flush(td->page_cache);
2241 if (uhcidebug > 5) {
2242 DPRINTF("TD %d\n", nframes);
2246 /* insert TD into schedule */
2247 UHCI_APPEND_TD(td, *pp_last);
2255 xfer->td_transfer_last = td_last;
2257 /* update isoc_next */
2258 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) &
2259 (UHCI_VFRAMELIST_COUNT - 1);
2263 uhci_device_isoc_start(struct usb_xfer *xfer)
2265 /* put transfer on interrupt queue */
2266 uhci_transfer_intr_enqueue(xfer);
2269 static const struct usb_pipe_methods uhci_device_isoc_methods =
2271 .open = uhci_device_isoc_open,
2272 .close = uhci_device_isoc_close,
2273 .enter = uhci_device_isoc_enter,
2274 .start = uhci_device_isoc_start,
2277 /*------------------------------------------------------------------------*
2278 * uhci root control support
2279 *------------------------------------------------------------------------*
2280 * Simulate a hardware hub by handling all the necessary requests.
2281 *------------------------------------------------------------------------*/
2284 struct usb_device_descriptor uhci_devd =
2286 sizeof(struct usb_device_descriptor),
2287 UDESC_DEVICE, /* type */
2288 {0x00, 0x01}, /* USB version */
2289 UDCLASS_HUB, /* class */
2290 UDSUBCLASS_HUB, /* subclass */
2291 UDPROTO_FSHUB, /* protocol */
2292 64, /* max packet */
2293 {0}, {0}, {0x00, 0x01}, /* device id */
2294 1, 2, 0, /* string indexes */
2295 1 /* # of configurations */
2298 static const struct uhci_config_desc uhci_confd = {
2300 .bLength = sizeof(struct usb_config_descriptor),
2301 .bDescriptorType = UDESC_CONFIG,
2302 .wTotalLength[0] = sizeof(uhci_confd),
2304 .bConfigurationValue = 1,
2305 .iConfiguration = 0,
2306 .bmAttributes = UC_SELF_POWERED,
2307 .bMaxPower = 0 /* max power */
2310 .bLength = sizeof(struct usb_interface_descriptor),
2311 .bDescriptorType = UDESC_INTERFACE,
2313 .bInterfaceClass = UICLASS_HUB,
2314 .bInterfaceSubClass = UISUBCLASS_HUB,
2315 .bInterfaceProtocol = UIPROTO_FSHUB,
2318 .bLength = sizeof(struct usb_endpoint_descriptor),
2319 .bDescriptorType = UDESC_ENDPOINT,
2320 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT,
2321 .bmAttributes = UE_INTERRUPT,
2322 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
2328 struct usb_hub_descriptor_min uhci_hubd_piix =
2330 .bDescLength = sizeof(uhci_hubd_piix),
2331 .bDescriptorType = UDESC_HUB,
2333 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0},
2334 .bPwrOn2PwrGood = 50,
2338 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
2339 * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
2340 * should not be used by the USB subsystem. As we cannot issue a
2341 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
2342 * will be enabled as part of the reset.
2344 * On the VT83C572, the port cannot be successfully enabled until the
2345 * outstanding "port enable change" and "connection status change"
2346 * events have been reset.
2349 uhci_portreset(uhci_softc_t *sc, uint16_t index)
2356 port = UHCI_PORTSC1;
2357 else if (index == 2)
2358 port = UHCI_PORTSC2;
2360 return (USB_ERR_IOERROR);
2363 * Before we do anything, turn on SOF messages on the USB
2364 * BUS. Some USB devices do not cope without them!
2368 x = URWMASK(UREAD2(sc, port));
2369 UWRITE2(sc, port, x | UHCI_PORTSC_PR);
2371 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2372 USB_MS_TO_TICKS(usb_port_root_reset_delay));
2374 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n",
2375 index, UREAD2(sc, port));
2377 x = URWMASK(UREAD2(sc, port));
2378 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2380 mtx_unlock(&sc->sc_bus.bus_mtx);
2383 * This delay needs to be exactly 100us, else some USB devices
2388 mtx_lock(&sc->sc_bus.bus_mtx);
2390 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n",
2391 index, UREAD2(sc, port));
2393 x = URWMASK(UREAD2(sc, port));
2394 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2396 for (lim = 0; lim < 12; lim++) {
2397 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2398 USB_MS_TO_TICKS(usb_port_reset_delay));
2400 x = UREAD2(sc, port);
2402 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n",
2405 if (!(x & UHCI_PORTSC_CCS)) {
2407 * No device is connected (or was disconnected
2408 * during reset). Consider the port reset.
2409 * The delay must be long enough to ensure on
2410 * the initial iteration that the device
2411 * connection will have been registered. 50ms
2412 * appears to be sufficient, but 20ms is not.
2414 DPRINTFN(4, "uhci port %d loop %u, device detached\n",
2418 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
2420 * Port enabled changed and/or connection
2421 * status changed were set. Reset either or
2422 * both raised flags (by writing a 1 to that
2423 * bit), and wait again for state to settle.
2425 UWRITE2(sc, port, URWMASK(x) |
2426 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
2429 if (x & UHCI_PORTSC_PE) {
2430 /* port is enabled */
2433 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
2436 DPRINTFN(2, "uhci port %d reset timed out\n", index);
2437 return (USB_ERR_TIMEOUT);
2440 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n",
2441 index, UREAD2(sc, port));
2444 return (USB_ERR_NORMAL_COMPLETION);
2448 uhci_roothub_exec(struct usb_device *udev,
2449 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2451 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus);
2453 const char *str_ptr;
2463 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2466 ptr = (const void *)&sc->sc_hub_desc.temp;
2470 value = UGETW(req->wValue);
2471 index = UGETW(req->wIndex);
2473 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
2474 "wValue=0x%04x wIndex=0x%04x\n",
2475 req->bmRequestType, req->bRequest,
2476 UGETW(req->wLength), value, index);
2478 #define C(x,y) ((x) | ((y) << 8))
2479 switch (C(req->bRequest, req->bmRequestType)) {
2480 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2481 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2482 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
2484 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2485 * for the integrated root hub.
2488 case C(UR_GET_CONFIG, UT_READ_DEVICE):
2490 sc->sc_hub_desc.temp[0] = sc->sc_conf;
2492 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2493 switch (value >> 8) {
2495 if ((value & 0xff) != 0) {
2496 err = USB_ERR_IOERROR;
2499 len = sizeof(uhci_devd);
2500 ptr = (const void *)&uhci_devd;
2504 if ((value & 0xff) != 0) {
2505 err = USB_ERR_IOERROR;
2508 len = sizeof(uhci_confd);
2509 ptr = (const void *)&uhci_confd;
2513 switch (value & 0xff) {
2514 case 0: /* Language table */
2518 case 1: /* Vendor */
2519 str_ptr = sc->sc_vendor;
2522 case 2: /* Product */
2523 str_ptr = "UHCI root HUB";
2531 len = usb_make_str_desc
2532 (sc->sc_hub_desc.temp,
2533 sizeof(sc->sc_hub_desc.temp),
2538 err = USB_ERR_IOERROR;
2542 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
2544 sc->sc_hub_desc.temp[0] = 0;
2546 case C(UR_GET_STATUS, UT_READ_DEVICE):
2548 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
2550 case C(UR_GET_STATUS, UT_READ_INTERFACE):
2551 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
2553 USETW(sc->sc_hub_desc.stat.wStatus, 0);
2555 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
2556 if (value >= UHCI_MAX_DEVICES) {
2557 err = USB_ERR_IOERROR;
2560 sc->sc_addr = value;
2562 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
2563 if ((value != 0) && (value != 1)) {
2564 err = USB_ERR_IOERROR;
2567 sc->sc_conf = value;
2569 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
2571 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
2572 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
2573 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
2574 err = USB_ERR_IOERROR;
2576 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
2578 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
2581 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2583 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2584 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE "
2585 "port=%d feature=%d\n",
2588 port = UHCI_PORTSC1;
2589 else if (index == 2)
2590 port = UHCI_PORTSC2;
2592 err = USB_ERR_IOERROR;
2596 case UHF_PORT_ENABLE:
2597 x = URWMASK(UREAD2(sc, port));
2598 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
2600 case UHF_PORT_SUSPEND:
2601 x = URWMASK(UREAD2(sc, port));
2602 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP));
2604 case UHF_PORT_RESET:
2605 x = URWMASK(UREAD2(sc, port));
2606 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2608 case UHF_C_PORT_CONNECTION:
2609 x = URWMASK(UREAD2(sc, port));
2610 UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
2612 case UHF_C_PORT_ENABLE:
2613 x = URWMASK(UREAD2(sc, port));
2614 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
2616 case UHF_C_PORT_OVER_CURRENT:
2617 x = URWMASK(UREAD2(sc, port));
2618 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
2620 case UHF_C_PORT_RESET:
2622 err = USB_ERR_NORMAL_COMPLETION;
2624 case UHF_C_PORT_SUSPEND:
2625 sc->sc_isresumed &= ~(1 << index);
2627 case UHF_PORT_CONNECTION:
2628 case UHF_PORT_OVER_CURRENT:
2629 case UHF_PORT_POWER:
2630 case UHF_PORT_LOW_SPEED:
2632 err = USB_ERR_IOERROR;
2636 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
2638 port = UHCI_PORTSC1;
2639 else if (index == 2)
2640 port = UHCI_PORTSC2;
2642 err = USB_ERR_IOERROR;
2646 sc->sc_hub_desc.temp[0] =
2647 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >>
2648 UHCI_PORTSC_LS_SHIFT);
2650 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2651 if ((value & 0xff) != 0) {
2652 err = USB_ERR_IOERROR;
2655 len = sizeof(uhci_hubd_piix);
2656 ptr = (const void *)&uhci_hubd_piix;
2658 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2660 memset(sc->sc_hub_desc.temp, 0, 16);
2662 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2664 port = UHCI_PORTSC1;
2665 else if (index == 2)
2666 port = UHCI_PORTSC2;
2668 err = USB_ERR_IOERROR;
2671 x = UREAD2(sc, port);
2672 status = change = 0;
2673 if (x & UHCI_PORTSC_CCS)
2674 status |= UPS_CURRENT_CONNECT_STATUS;
2675 if (x & UHCI_PORTSC_CSC)
2676 change |= UPS_C_CONNECT_STATUS;
2677 if (x & UHCI_PORTSC_PE)
2678 status |= UPS_PORT_ENABLED;
2679 if (x & UHCI_PORTSC_POEDC)
2680 change |= UPS_C_PORT_ENABLED;
2681 if (x & UHCI_PORTSC_OCI)
2682 status |= UPS_OVERCURRENT_INDICATOR;
2683 if (x & UHCI_PORTSC_OCIC)
2684 change |= UPS_C_OVERCURRENT_INDICATOR;
2685 if (x & UHCI_PORTSC_LSDA)
2686 status |= UPS_LOW_SPEED;
2687 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) {
2688 /* need to do a write back */
2689 UWRITE2(sc, port, URWMASK(x));
2691 /* wait 20ms for resume sequence to complete */
2692 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
2694 /* clear suspend and resume detect */
2695 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD |
2698 /* wait a little bit */
2699 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500);
2701 sc->sc_isresumed |= (1 << index);
2703 } else if (x & UHCI_PORTSC_SUSP) {
2704 status |= UPS_SUSPEND;
2706 status |= UPS_PORT_POWER;
2707 if (sc->sc_isresumed & (1 << index))
2708 change |= UPS_C_SUSPEND;
2710 change |= UPS_C_PORT_RESET;
2711 USETW(sc->sc_hub_desc.ps.wPortStatus, status);
2712 USETW(sc->sc_hub_desc.ps.wPortChange, change);
2713 len = sizeof(sc->sc_hub_desc.ps);
2715 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2716 err = USB_ERR_IOERROR;
2718 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2720 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2722 port = UHCI_PORTSC1;
2723 else if (index == 2)
2724 port = UHCI_PORTSC2;
2726 err = USB_ERR_IOERROR;
2730 case UHF_PORT_ENABLE:
2731 x = URWMASK(UREAD2(sc, port));
2732 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2734 case UHF_PORT_SUSPEND:
2735 x = URWMASK(UREAD2(sc, port));
2736 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
2738 case UHF_PORT_RESET:
2739 err = uhci_portreset(sc, index);
2741 case UHF_PORT_POWER:
2742 /* pretend we turned on power */
2743 err = USB_ERR_NORMAL_COMPLETION;
2745 case UHF_C_PORT_CONNECTION:
2746 case UHF_C_PORT_ENABLE:
2747 case UHF_C_PORT_OVER_CURRENT:
2748 case UHF_PORT_CONNECTION:
2749 case UHF_PORT_OVER_CURRENT:
2750 case UHF_PORT_LOW_SPEED:
2751 case UHF_C_PORT_SUSPEND:
2752 case UHF_C_PORT_RESET:
2754 err = USB_ERR_IOERROR;
2759 err = USB_ERR_IOERROR;
2769 * This routine is executed periodically and simulates interrupts from
2770 * the root controller interrupt pipe for port status change:
2773 uhci_root_intr(uhci_softc_t *sc)
2777 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2779 sc->sc_hub_idata[0] = 0;
2781 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC |
2782 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) {
2783 sc->sc_hub_idata[0] |= 1 << 1;
2785 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC |
2786 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) {
2787 sc->sc_hub_idata[0] |= 1 << 2;
2791 usb_callout_reset(&sc->sc_root_intr, hz,
2792 (void *)&uhci_root_intr, sc);
2794 if (sc->sc_hub_idata[0] != 0) {
2795 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2796 sizeof(sc->sc_hub_idata));
2801 uhci_xfer_setup(struct usb_setup_params *parm)
2803 struct usb_page_search page_info;
2804 struct usb_page_cache *pc;
2806 struct usb_xfer *xfer;
2814 sc = UHCI_BUS2SC(parm->udev->bus);
2815 xfer = parm->curr_xfer;
2817 parm->hc_max_packet_size = 0x500;
2818 parm->hc_max_packet_count = 1;
2819 parm->hc_max_frame_size = 0x500;
2822 * compute ntd and nqh
2824 if (parm->methods == &uhci_device_ctrl_methods) {
2825 xfer->flags_int.bdma_enable = 1;
2826 xfer->flags_int.bdma_no_post_sync = 1;
2828 usbd_transfer_setup_sub(parm);
2830 /* see EHCI HC driver for proof of "ntd" formula */
2833 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
2834 + (xfer->max_data_length / xfer->max_frame_size));
2836 } else if (parm->methods == &uhci_device_bulk_methods) {
2837 xfer->flags_int.bdma_enable = 1;
2838 xfer->flags_int.bdma_no_post_sync = 1;
2840 usbd_transfer_setup_sub(parm);
2843 ntd = ((2 * xfer->nframes)
2844 + (xfer->max_data_length / xfer->max_frame_size));
2846 } else if (parm->methods == &uhci_device_intr_methods) {
2847 xfer->flags_int.bdma_enable = 1;
2848 xfer->flags_int.bdma_no_post_sync = 1;
2850 usbd_transfer_setup_sub(parm);
2853 ntd = ((2 * xfer->nframes)
2854 + (xfer->max_data_length / xfer->max_frame_size));
2856 } else if (parm->methods == &uhci_device_isoc_methods) {
2857 xfer->flags_int.bdma_enable = 1;
2858 xfer->flags_int.bdma_no_post_sync = 1;
2860 usbd_transfer_setup_sub(parm);
2863 ntd = xfer->nframes;
2866 usbd_transfer_setup_sub(parm);
2876 * NOTE: the UHCI controller requires that
2877 * every packet must be contiguous on
2878 * the same USB memory page !
2880 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1;
2883 * Compute a suitable power of two alignment
2884 * for our "max_frame_size" fixup buffer(s):
2886 align = xfer->max_frame_size;
2893 /* check for power of two */
2894 if (!(xfer->max_frame_size &
2895 (xfer->max_frame_size - 1))) {
2899 * We don't allow alignments of
2900 * less than 8 bytes:
2902 * NOTE: Allocating using an aligment
2903 * of 1 byte has special meaning!
2910 if (usbd_transfer_setup_sub_malloc(
2911 parm, &pc, xfer->max_frame_size,
2913 parm->err = USB_ERR_NOMEM;
2916 xfer->buf_fixup = pc;
2925 if (usbd_transfer_setup_sub_malloc(
2926 parm, &pc, sizeof(uhci_td_t),
2927 UHCI_TD_ALIGN, ntd)) {
2928 parm->err = USB_ERR_NOMEM;
2932 for (n = 0; n != ntd; n++) {
2935 usbd_get_page(pc + n, 0, &page_info);
2937 td = page_info.buffer;
2940 if ((parm->methods == &uhci_device_bulk_methods) ||
2941 (parm->methods == &uhci_device_ctrl_methods) ||
2942 (parm->methods == &uhci_device_intr_methods)) {
2943 /* set depth first bit */
2944 td->td_self = htole32(page_info.physaddr |
2945 UHCI_PTR_TD | UHCI_PTR_VF);
2947 td->td_self = htole32(page_info.physaddr |
2951 td->obj_next = last_obj;
2952 td->page_cache = pc + n;
2956 usb_pc_cpu_flush(pc + n);
2959 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
2963 if (usbd_transfer_setup_sub_malloc(
2964 parm, &pc, sizeof(uhci_qh_t),
2965 UHCI_QH_ALIGN, nqh)) {
2966 parm->err = USB_ERR_NOMEM;
2970 for (n = 0; n != nqh; n++) {
2973 usbd_get_page(pc + n, 0, &page_info);
2975 qh = page_info.buffer;
2978 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH);
2979 qh->obj_next = last_obj;
2980 qh->page_cache = pc + n;
2984 usb_pc_cpu_flush(pc + n);
2987 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
2989 if (!xfer->flags_int.curr_dma_set) {
2990 xfer->flags_int.curr_dma_set = 1;
2996 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2997 struct usb_endpoint *ep)
2999 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus);
3001 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3003 edesc->bEndpointAddress, udev->flags.usb_mode,
3006 if (udev->device_index != sc->sc_addr) {
3007 switch (edesc->bmAttributes & UE_XFERTYPE) {
3009 ep->methods = &uhci_device_ctrl_methods;
3012 ep->methods = &uhci_device_intr_methods;
3014 case UE_ISOCHRONOUS:
3015 if (udev->speed == USB_SPEED_FULL) {
3016 ep->methods = &uhci_device_isoc_methods;
3020 ep->methods = &uhci_device_bulk_methods;
3030 uhci_xfer_unsetup(struct usb_xfer *xfer)
3036 uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3039 * Wait until hardware has finished any possible use of the
3040 * transfer descriptor(s) and QH
3042 *pus = (1125); /* microseconds */
3046 uhci_device_resume(struct usb_device *udev)
3048 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus);
3049 struct usb_xfer *xfer;
3050 const struct usb_pipe_methods *methods;
3055 USB_BUS_LOCK(udev->bus);
3057 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3058 if (xfer->xroot->udev == udev) {
3059 methods = xfer->endpoint->methods;
3060 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
3062 if (methods == &uhci_device_bulk_methods) {
3063 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last);
3065 xfer->flags_int.bandwidth_reclaimed = 1;
3067 if (methods == &uhci_device_ctrl_methods) {
3068 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
3069 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last);
3071 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last);
3074 if (methods == &uhci_device_intr_methods) {
3075 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
3080 USB_BUS_UNLOCK(udev->bus);
3086 uhci_device_suspend(struct usb_device *udev)
3088 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus);
3089 struct usb_xfer *xfer;
3090 const struct usb_pipe_methods *methods;
3095 USB_BUS_LOCK(udev->bus);
3097 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3098 if (xfer->xroot->udev == udev) {
3099 methods = xfer->endpoint->methods;
3100 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
3102 if (xfer->flags_int.bandwidth_reclaimed) {
3103 xfer->flags_int.bandwidth_reclaimed = 0;
3106 if (methods == &uhci_device_bulk_methods) {
3107 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last);
3109 if (methods == &uhci_device_ctrl_methods) {
3110 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
3111 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last);
3113 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last);
3116 if (methods == &uhci_device_intr_methods) {
3117 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
3122 USB_BUS_UNLOCK(udev->bus);
3128 uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3130 struct uhci_softc *sc = UHCI_BUS2SC(bus);
3133 case USB_HW_POWER_SUSPEND:
3134 case USB_HW_POWER_SHUTDOWN:
3137 case USB_HW_POWER_RESUME:
3146 uhci_set_hw_power(struct usb_bus *bus)
3148 struct uhci_softc *sc = UHCI_BUS2SC(bus);
3155 flags = bus->hw_power_state;
3158 * WARNING: Some FULL speed USB devices require periodic SOF
3159 * messages! If any USB devices are connected through the
3160 * UHCI, power save will be disabled!
3162 if (flags & (USB_HW_POWER_CONTROL |
3163 USB_HW_POWER_NON_ROOT_HUB |
3165 USB_HW_POWER_INTERRUPT |
3166 USB_HW_POWER_ISOC)) {
3167 DPRINTF("Some USB transfer is "
3168 "active on unit %u.\n",
3169 device_get_unit(sc->sc_bus.bdev));
3172 DPRINTF("Power save on unit %u.\n",
3173 device_get_unit(sc->sc_bus.bdev));
3174 UHCICMD(sc, UHCI_CMD_MAXP);
3177 USB_BUS_UNLOCK(bus);
3182 static const struct usb_bus_methods uhci_bus_methods =
3184 .endpoint_init = uhci_ep_init,
3185 .xfer_setup = uhci_xfer_setup,
3186 .xfer_unsetup = uhci_xfer_unsetup,
3187 .get_dma_delay = uhci_get_dma_delay,
3188 .device_resume = uhci_device_resume,
3189 .device_suspend = uhci_device_suspend,
3190 .set_hw_power = uhci_set_hw_power,
3191 .set_hw_power_sleep = uhci_set_hw_power_sleep,
3192 .roothub_exec = uhci_roothub_exec,
3193 .xfer_poll = uhci_do_poll,