3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
6 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
7 * Copyright (c) 1998 Lennart Augustsson. All rights reserved.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * USB Universal Host Controller driver.
33 * Handles e.g. PIIX3 and PIIX4.
35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm
36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip
37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
41 #ifdef USB_GLOBAL_INCLUDE_FILE
42 #include USB_GLOBAL_INCLUDE_FILE
44 #include <sys/stdint.h>
45 #include <sys/stddef.h>
46 #include <sys/param.h>
47 #include <sys/queue.h>
48 #include <sys/types.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
52 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/condvar.h>
56 #include <sys/sysctl.h>
58 #include <sys/unistd.h>
59 #include <sys/callout.h>
60 #include <sys/malloc.h>
63 #include <dev/usb/usb.h>
64 #include <dev/usb/usbdi.h>
66 #define USB_DEBUG_VAR uhcidebug
68 #include <dev/usb/usb_core.h>
69 #include <dev/usb/usb_debug.h>
70 #include <dev/usb/usb_busdma.h>
71 #include <dev/usb/usb_process.h>
72 #include <dev/usb/usb_transfer.h>
73 #include <dev/usb/usb_device.h>
74 #include <dev/usb/usb_hub.h>
75 #include <dev/usb/usb_util.h>
77 #include <dev/usb/usb_controller.h>
78 #include <dev/usb/usb_bus.h>
79 #endif /* USB_GLOBAL_INCLUDE_FILE */
81 #include <dev/usb/controller/uhci.h>
82 #include <dev/usb/controller/uhcireg.h>
85 #define UHCI_BUS2SC(bus) \
86 ((uhci_softc_t *)(((uint8_t *)(bus)) - \
87 ((uint8_t *)&(((uhci_softc_t *)0)->sc_bus))))
90 static int uhcidebug = 0;
91 static int uhcinoloop = 0;
93 static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
95 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RWTUN,
96 &uhcidebug, 0, "uhci debug level");
97 SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RWTUN,
98 &uhcinoloop, 0, "uhci noloop");
100 static void uhci_dumpregs(uhci_softc_t *sc);
101 static void uhci_dump_tds(uhci_td_t *td);
105 #define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \
106 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
107 #define UWRITE1(sc, r, x) \
108 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
109 } while (/*CONSTCOND*/0)
110 #define UWRITE2(sc, r, x) \
111 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
112 } while (/*CONSTCOND*/0)
113 #define UWRITE4(sc, r, x) \
114 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
115 } while (/*CONSTCOND*/0)
116 #define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
117 #define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
118 #define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
120 #define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
121 #define UHCISTS(sc) UREAD2(sc, UHCI_STS)
123 #define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
125 #define UHCI_INTR_ENDPT 1
127 struct uhci_mem_layout {
129 struct usb_page_search buf_res;
130 struct usb_page_search fix_res;
132 struct usb_page_cache *buf_pc;
133 struct usb_page_cache *fix_pc;
137 uint16_t max_frame_size;
140 struct uhci_std_temp {
142 struct uhci_mem_layout ml;
149 uint16_t max_frame_size;
151 uint8_t setup_alt_next;
155 static const struct usb_bus_methods uhci_bus_methods;
156 static const struct usb_pipe_methods uhci_device_bulk_methods;
157 static const struct usb_pipe_methods uhci_device_ctrl_methods;
158 static const struct usb_pipe_methods uhci_device_intr_methods;
159 static const struct usb_pipe_methods uhci_device_isoc_methods;
161 static uint8_t uhci_restart(uhci_softc_t *sc);
162 static void uhci_do_poll(struct usb_bus *);
163 static void uhci_device_done(struct usb_xfer *, usb_error_t);
164 static void uhci_transfer_intr_enqueue(struct usb_xfer *);
165 static void uhci_timeout(void *);
166 static uint8_t uhci_check_transfer(struct usb_xfer *);
167 static void uhci_root_intr(uhci_softc_t *sc);
170 uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
172 struct uhci_softc *sc = UHCI_BUS2SC(bus);
175 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
176 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN);
178 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg,
179 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
181 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg,
182 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
184 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg,
185 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
187 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg,
188 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
190 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg,
191 sizeof(uhci_td_t), UHCI_TD_ALIGN);
193 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) {
194 cb(bus, sc->sc_hw.isoc_start_pc + i,
195 sc->sc_hw.isoc_start_pg + i,
196 sizeof(uhci_td_t), UHCI_TD_ALIGN);
199 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) {
200 cb(bus, sc->sc_hw.intr_start_pc + i,
201 sc->sc_hw.intr_start_pg + i,
202 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
207 uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer)
209 ml->buf_pc = xfer->frbuffers + 0;
210 ml->fix_pc = xfer->buf_fixup;
214 ml->max_frame_size = xfer->max_frame_size;
218 uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td)
220 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res);
222 if (ml->buf_res.length < td->len) {
224 /* need to do a fixup */
226 usbd_get_page(ml->fix_pc, 0, &ml->fix_res);
228 td->td_buffer = htole32(ml->fix_res.physaddr);
231 * The UHCI driver cannot handle
232 * page crossings, so a fixup is
245 if ((td->td_token & htole32(UHCI_TD_PID)) ==
246 htole32(UHCI_TD_PID_IN)) {
247 td->fix_pc = ml->fix_pc;
248 usb_pc_cpu_invalidate(ml->fix_pc);
253 /* copy data to fixup location */
255 usbd_copy_out(ml->buf_pc, ml->buf_offset,
256 ml->fix_res.buffer, td->len);
258 usb_pc_cpu_flush(ml->fix_pc);
261 /* prepare next fixup */
267 td->td_buffer = htole32(ml->buf_res.physaddr);
271 /* prepare next data location */
273 ml->buf_offset += td->len;
282 uhci_restart(uhci_softc_t *sc)
284 struct usb_page_search buf_res;
286 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
288 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) {
289 DPRINTFN(2, "Already started\n");
293 DPRINTFN(2, "Restarting\n");
295 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
297 /* Reload fresh base address */
298 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr);
301 * Assume 64 byte packets at frame end and start HC controller:
303 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS));
305 /* wait 10 milliseconds */
307 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
309 /* check that controller has started */
311 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
312 DPRINTFN(2, "Failed\n");
319 uhci_reset(uhci_softc_t *sc)
323 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
325 DPRINTF("resetting the HC\n");
327 /* disable interrupts */
329 UWRITE2(sc, UHCI_INTR, 0);
333 UHCICMD(sc, UHCI_CMD_GRESET);
337 usb_pause_mtx(&sc->sc_bus.bus_mtx,
338 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY));
340 /* terminate all transfers */
342 UHCICMD(sc, UHCI_CMD_HCRESET);
344 /* the reset bit goes low when the controller is done */
346 n = UHCI_RESET_TIMEOUT;
348 /* wait one millisecond */
350 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
352 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) {
357 device_printf(sc->sc_bus.bdev,
358 "controller did not reset\n");
364 /* wait one millisecond */
366 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
368 /* check if HC is stopped */
369 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
374 device_printf(sc->sc_bus.bdev,
375 "controller did not stop\n");
379 /* reset frame number */
380 UWRITE2(sc, UHCI_FRNUM, 0);
381 /* set default SOF value */
382 UWRITE1(sc, UHCI_SOF, 0x40);
384 USB_BUS_UNLOCK(&sc->sc_bus);
386 /* stop root interrupt */
387 usb_callout_drain(&sc->sc_root_intr);
389 USB_BUS_LOCK(&sc->sc_bus);
393 uhci_start(uhci_softc_t *sc)
395 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
397 DPRINTFN(2, "enabling\n");
399 /* enable interrupts */
401 UWRITE2(sc, UHCI_INTR,
407 if (uhci_restart(sc)) {
408 device_printf(sc->sc_bus.bdev,
409 "cannot start HC controller\n");
412 /* start root interrupt */
416 static struct uhci_qh *
417 uhci_init_qh(struct usb_page_cache *pc)
419 struct usb_page_search buf_res;
422 usbd_get_page(pc, 0, &buf_res);
427 htole32(buf_res.physaddr) |
428 htole32(UHCI_PTR_QH);
435 static struct uhci_td *
436 uhci_init_td(struct usb_page_cache *pc)
438 struct usb_page_search buf_res;
441 usbd_get_page(pc, 0, &buf_res);
446 htole32(buf_res.physaddr) |
447 htole32(UHCI_PTR_TD);
455 uhci_init(uhci_softc_t *sc)
463 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0);
473 sc->sc_ls_ctl_p_last =
474 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc);
476 sc->sc_fs_ctl_p_last =
477 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc);
480 uhci_init_qh(&sc->sc_hw.bulk_start_pc);
482 sc->sc_reclaim_qh_p =
483 sc->sc_fs_ctl_p_last;
485 /* setup reclaim looping point */
486 sc->sc_reclaim_qh_p =
491 uhci_init_qh(&sc->sc_hw.last_qh_pc);
494 uhci_init_td(&sc->sc_hw.last_td_pc);
496 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) {
497 sc->sc_isoc_p_last[x] =
498 uhci_init_td(sc->sc_hw.isoc_start_pc + x);
501 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) {
502 sc->sc_intr_p_last[x] =
503 uhci_init_qh(sc->sc_hw.intr_start_pc + x);
507 * the QHs are arranged to give poll intervals that are
508 * powers of 2 times 1ms
510 bit = UHCI_IFRAMELIST_COUNT / 2;
517 y = (x ^ bit) | (bit / 2);
520 * the next QH has half the poll interval
522 qh_x = sc->sc_intr_p_last[x];
523 qh_y = sc->sc_intr_p_last[y];
526 qh_x->qh_h_next = qh_y->qh_self;
528 qh_x->qh_e_next = htole32(UHCI_PTR_T);
538 qh_ls = sc->sc_ls_ctl_p_last;
539 qh_intr = sc->sc_intr_p_last[0];
541 /* start QH for interrupt traffic */
542 qh_intr->h_next = qh_ls;
543 qh_intr->qh_h_next = qh_ls->qh_self;
545 qh_intr->qh_e_next = htole32(UHCI_PTR_T);
547 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) {
552 td_x = sc->sc_isoc_p_last[x];
553 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)];
555 /* start TD for isochronous traffic */
557 td_x->td_next = qh_intr->qh_self;
558 td_x->td_status = htole32(UHCI_TD_IOS);
559 td_x->td_token = htole32(0);
560 td_x->td_buffer = htole32(0);
567 qh_ls = sc->sc_ls_ctl_p_last;
568 qh_fs = sc->sc_fs_ctl_p_last;
570 /* start QH where low speed control traffic will be queued */
571 qh_ls->h_next = qh_fs;
572 qh_ls->qh_h_next = qh_fs->qh_self;
574 qh_ls->qh_e_next = htole32(UHCI_PTR_T);
582 qh_ctl = sc->sc_fs_ctl_p_last;
583 qh_blk = sc->sc_bulk_p_last;
585 /* start QH where full speed control traffic will be queued */
586 qh_ctl->h_next = qh_blk;
587 qh_ctl->qh_h_next = qh_blk->qh_self;
589 qh_ctl->qh_e_next = htole32(UHCI_PTR_T);
591 qh_lst = sc->sc_last_qh_p;
593 /* start QH where bulk traffic will be queued */
594 qh_blk->h_next = qh_lst;
595 qh_blk->qh_h_next = qh_lst->qh_self;
597 qh_blk->qh_e_next = htole32(UHCI_PTR_T);
599 td_lst = sc->sc_last_td_p;
601 /* end QH which is used for looping the QHs */
603 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */
604 qh_lst->e_next = td_lst;
605 qh_lst->qh_e_next = td_lst->td_self;
608 * end TD which hangs from the last QH, to avoid a bug in the PIIX
609 * that makes it run berserk otherwise
612 td_lst->td_next = htole32(UHCI_PTR_T);
613 td_lst->td_status = htole32(0); /* inactive */
614 td_lst->td_token = htole32(0);
615 td_lst->td_buffer = htole32(0);
618 struct usb_page_search buf_res;
621 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
623 pframes = buf_res.buffer;
627 * Setup UHCI framelist
631 * pframes -> full speed isochronous -> interrupt QH's -> low
632 * speed control -> full speed control -> bulk transfers
636 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) {
638 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self;
641 /* flush all cache into memory */
643 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc);
645 /* set up the bus struct */
646 sc->sc_bus.methods = &uhci_bus_methods;
648 USB_BUS_LOCK(&sc->sc_bus);
649 /* reset the controller */
652 /* start the controller */
654 USB_BUS_UNLOCK(&sc->sc_bus);
656 /* catch lost interrupts */
657 uhci_do_poll(&sc->sc_bus);
663 uhci_suspend(uhci_softc_t *sc)
671 USB_BUS_LOCK(&sc->sc_bus);
673 /* stop the controller */
677 /* enter global suspend */
679 UHCICMD(sc, UHCI_CMD_EGSM);
681 USB_BUS_UNLOCK(&sc->sc_bus);
685 uhci_resume(uhci_softc_t *sc)
687 USB_BUS_LOCK(&sc->sc_bus);
689 /* reset the controller */
693 /* force global resume */
695 UHCICMD(sc, UHCI_CMD_FGR);
697 /* and start traffic again */
701 USB_BUS_UNLOCK(&sc->sc_bus);
708 /* catch lost interrupts */
709 uhci_do_poll(&sc->sc_bus);
714 uhci_dumpregs(uhci_softc_t *sc)
716 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, "
717 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n",
718 device_get_nameunit(sc->sc_bus.bdev),
719 UREAD2(sc, UHCI_CMD),
720 UREAD2(sc, UHCI_STS),
721 UREAD2(sc, UHCI_INTR),
722 UREAD2(sc, UHCI_FRNUM),
723 UREAD4(sc, UHCI_FLBASEADDR),
724 UREAD1(sc, UHCI_SOF),
725 UREAD2(sc, UHCI_PORTSC1),
726 UREAD2(sc, UHCI_PORTSC2));
730 uhci_dump_td(uhci_td_t *p)
737 usb_pc_cpu_invalidate(p->page_cache);
739 td_next = le32toh(p->td_next);
740 td_status = le32toh(p->td_status);
741 td_token = le32toh(p->td_token);
744 * Check whether the link pointer in this TD marks the link pointer
747 temp = ((td_next & UHCI_PTR_T) || (td_next == 0));
749 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x "
750 "token=0x%08x buffer=0x%08x\n",
756 le32toh(p->td_buffer));
758 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x,"
759 "addr=%d,endpt=%d,D=%d,maxlen=%d\n",
761 (td_next & 1) ? "-T" : "",
762 (td_next & 2) ? "-Q" : "",
763 (td_next & 4) ? "-VF" : "",
764 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "",
765 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "",
766 (td_status & UHCI_TD_NAK) ? "-NAK" : "",
767 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "",
768 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "",
769 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "",
770 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "",
771 (td_status & UHCI_TD_IOC) ? "-IOC" : "",
772 (td_status & UHCI_TD_IOS) ? "-IOS" : "",
773 (td_status & UHCI_TD_LS) ? "-LS" : "",
774 (td_status & UHCI_TD_SPD) ? "-SPD" : "",
775 UHCI_TD_GET_ERRCNT(td_status),
776 UHCI_TD_GET_ACTLEN(td_status),
777 UHCI_TD_GET_PID(td_token),
778 UHCI_TD_GET_DEVADDR(td_token),
779 UHCI_TD_GET_ENDPT(td_token),
780 UHCI_TD_GET_DT(td_token),
781 UHCI_TD_GET_MAXLEN(td_token));
787 uhci_dump_qh(uhci_qh_t *sqh)
793 usb_pc_cpu_invalidate(sqh->page_cache);
795 qh_h_next = le32toh(sqh->qh_h_next);
796 qh_e_next = le32toh(sqh->qh_e_next);
798 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh,
799 le32toh(sqh->qh_self), qh_h_next, qh_e_next);
801 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) |
802 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0));
808 uhci_dump_all(uhci_softc_t *sc)
811 uhci_dump_qh(sc->sc_ls_ctl_p_last);
812 uhci_dump_qh(sc->sc_fs_ctl_p_last);
813 uhci_dump_qh(sc->sc_bulk_p_last);
814 uhci_dump_qh(sc->sc_last_qh_p);
818 uhci_dump_tds(uhci_td_t *td)
823 if (uhci_dump_td(td)) {
832 * Let the last QH loop back to the full speed control transfer QH.
833 * This is what intel calls "bandwidth reclamation" and improves
834 * USB performance a lot for some devices.
835 * If we are already looping, just count it.
838 uhci_add_loop(uhci_softc_t *sc)
840 struct uhci_qh *qh_lst;
841 struct uhci_qh *qh_rec;
848 if (++(sc->sc_loops) == 1) {
849 DPRINTFN(6, "add\n");
851 qh_lst = sc->sc_last_qh_p;
852 qh_rec = sc->sc_reclaim_qh_p;
854 /* NOTE: we don't loop back the soft pointer */
856 qh_lst->qh_h_next = qh_rec->qh_self;
857 usb_pc_cpu_flush(qh_lst->page_cache);
862 uhci_rem_loop(uhci_softc_t *sc)
864 struct uhci_qh *qh_lst;
871 if (--(sc->sc_loops) == 0) {
872 DPRINTFN(6, "remove\n");
874 qh_lst = sc->sc_last_qh_p;
875 qh_lst->qh_h_next = htole32(UHCI_PTR_T);
876 usb_pc_cpu_flush(qh_lst->page_cache);
881 uhci_transfer_intr_enqueue(struct usb_xfer *xfer)
883 /* check for early completion */
884 if (uhci_check_transfer(xfer)) {
887 /* put transfer on interrupt queue */
888 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
890 /* start timeout, if any */
891 if (xfer->timeout != 0) {
892 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout);
896 #define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last)
898 _uhci_append_td(uhci_td_t *std, uhci_td_t *last)
900 DPRINTFN(11, "%p to %p\n", std, last);
902 /* (sc->sc_bus.mtx) must be locked */
904 std->next = last->next;
905 std->td_next = last->td_next;
909 usb_pc_cpu_flush(std->page_cache);
912 * the last->next->prev is never followed: std->next->prev = std;
915 last->td_next = std->td_self;
917 usb_pc_cpu_flush(last->page_cache);
922 #define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last)
924 _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last)
926 DPRINTFN(11, "%p to %p\n", sqh, last);
928 if (sqh->h_prev != NULL) {
929 /* should not happen */
930 DPRINTFN(0, "QH already linked!\n");
933 /* (sc->sc_bus.mtx) must be locked */
935 sqh->h_next = last->h_next;
936 sqh->qh_h_next = last->qh_h_next;
940 usb_pc_cpu_flush(sqh->page_cache);
943 * The "last->h_next->h_prev" is never followed:
945 * "sqh->h_next->h_prev" = sqh;
949 last->qh_h_next = sqh->qh_self;
951 usb_pc_cpu_flush(last->page_cache);
958 #define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last)
960 _uhci_remove_td(uhci_td_t *std, uhci_td_t *last)
962 DPRINTFN(11, "%p from %p\n", std, last);
964 /* (sc->sc_bus.mtx) must be locked */
966 std->prev->next = std->next;
967 std->prev->td_next = std->td_next;
969 usb_pc_cpu_flush(std->prev->page_cache);
972 std->next->prev = std->prev;
973 usb_pc_cpu_flush(std->next->page_cache);
975 return ((last == std) ? std->prev : last);
978 #define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last)
980 _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last)
982 DPRINTFN(11, "%p from %p\n", sqh, last);
984 /* (sc->sc_bus.mtx) must be locked */
986 /* only remove if not removed from a queue */
989 sqh->h_prev->h_next = sqh->h_next;
990 sqh->h_prev->qh_h_next = sqh->qh_h_next;
992 usb_pc_cpu_flush(sqh->h_prev->page_cache);
995 sqh->h_next->h_prev = sqh->h_prev;
996 usb_pc_cpu_flush(sqh->h_next->page_cache);
998 last = ((last == sqh) ? sqh->h_prev : last);
1002 usb_pc_cpu_flush(sqh->page_cache);
1008 uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer)
1010 struct usb_page_search res;
1011 uint32_t nframes = xfer->nframes;
1013 uint32_t offset = 0;
1014 uint32_t *plen = xfer->frlengths;
1016 uhci_td_t *td = xfer->td_transfer_first;
1017 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos];
1019 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1020 xfer, xfer->endpoint);
1022 /* sync any DMA memory before doing fixups */
1024 usb_bdma_post_sync(xfer);
1028 panic("%s:%d: out of TD's\n",
1029 __FUNCTION__, __LINE__);
1031 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) {
1032 pp_last = &sc->sc_isoc_p_last[0];
1035 if (uhcidebug > 5) {
1036 DPRINTF("isoc TD\n");
1040 usb_pc_cpu_invalidate(td->page_cache);
1041 status = le32toh(td->td_status);
1043 len = UHCI_TD_GET_ACTLEN(status);
1050 usbd_get_page(td->fix_pc, 0, &res);
1052 /* copy data from fixup location to real location */
1054 usb_pc_cpu_invalidate(td->fix_pc);
1056 usbd_copy_in(xfer->frbuffers, offset,
1063 /* remove TD from schedule */
1064 UHCI_REMOVE_TD(td, *pp_last);
1071 xfer->aframes = xfer->nframes;
1075 uhci_non_isoc_done_sub(struct usb_xfer *xfer)
1077 struct usb_page_search res;
1079 uhci_td_t *td_alt_next;
1084 td = xfer->td_transfer_cache;
1085 td_alt_next = td->alt_next;
1087 if (xfer->aframes != xfer->nframes) {
1088 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1092 usb_pc_cpu_invalidate(td->page_cache);
1093 status = le32toh(td->td_status);
1094 token = le32toh(td->td_token);
1097 * Verify the status and add
1098 * up the actual length:
1101 len = UHCI_TD_GET_ACTLEN(status);
1102 if (len > td->len) {
1103 /* should not happen */
1104 DPRINTF("Invalid status length, "
1105 "0x%04x/0x%04x bytes\n", len, td->len);
1106 status |= UHCI_TD_STALLED;
1108 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) {
1112 usbd_get_page(td->fix_pc, 0, &res);
1115 * copy data from fixup location to real
1119 usb_pc_cpu_invalidate(td->fix_pc);
1121 usbd_copy_in(xfer->frbuffers + xfer->aframes,
1122 xfer->frlengths[xfer->aframes], res.buffer, len);
1124 /* update actual length */
1126 xfer->frlengths[xfer->aframes] += len;
1128 /* Check for last transfer */
1129 if (((void *)td) == xfer->td_transfer_last) {
1133 if (status & UHCI_TD_STALLED) {
1134 /* the transfer is finished */
1138 /* Check for short transfer */
1139 if (len != td->len) {
1140 if (xfer->flags_int.short_frames_ok) {
1141 /* follow alt next */
1144 /* the transfer is finished */
1151 if (td->alt_next != td_alt_next) {
1152 /* this USB frame is complete */
1157 /* update transfer cache */
1159 xfer->td_transfer_cache = td;
1161 /* update data toggle */
1163 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1;
1166 if (status & UHCI_TD_ERROR) {
1167 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x "
1168 "status=%s%s%s%s%s%s%s%s%s%s%s\n",
1169 xfer->address, xfer->endpointno, xfer->aframes,
1170 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "",
1171 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "",
1172 (status & UHCI_TD_NAK) ? "[NAK]" : "",
1173 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "",
1174 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "",
1175 (status & UHCI_TD_STALLED) ? "[STALLED]" : "",
1176 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1177 (status & UHCI_TD_IOC) ? "[IOC]" : "",
1178 (status & UHCI_TD_IOS) ? "[IOS]" : "",
1179 (status & UHCI_TD_LS) ? "[LS]" : "",
1180 (status & UHCI_TD_SPD) ? "[SPD]" : "");
1183 if (status & UHCI_TD_STALLED) {
1184 /* try to separate I/O errors from STALL */
1185 if (UHCI_TD_GET_ERRCNT(status) == 0)
1186 return (USB_ERR_IOERROR);
1187 return (USB_ERR_STALLED);
1189 return (USB_ERR_NORMAL_COMPLETION);
1193 uhci_non_isoc_done(struct usb_xfer *xfer)
1195 usb_error_t err = 0;
1197 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1198 xfer, xfer->endpoint);
1201 if (uhcidebug > 10) {
1202 uhci_dump_tds(xfer->td_transfer_first);
1206 /* sync any DMA memory before doing fixups */
1208 usb_bdma_post_sync(xfer);
1212 xfer->td_transfer_cache = xfer->td_transfer_first;
1214 if (xfer->flags_int.control_xfr) {
1215 if (xfer->flags_int.control_hdr) {
1217 err = uhci_non_isoc_done_sub(xfer);
1221 if (xfer->td_transfer_cache == NULL) {
1225 while (xfer->aframes != xfer->nframes) {
1227 err = uhci_non_isoc_done_sub(xfer);
1230 if (xfer->td_transfer_cache == NULL) {
1235 if (xfer->flags_int.control_xfr &&
1236 !xfer->flags_int.control_act) {
1238 err = uhci_non_isoc_done_sub(xfer);
1241 uhci_device_done(xfer, err);
1244 /*------------------------------------------------------------------------*
1245 * uhci_check_transfer_sub
1247 * The main purpose of this function is to update the data-toggle
1248 * in case it is wrong.
1249 *------------------------------------------------------------------------*/
1251 uhci_check_transfer_sub(struct usb_xfer *xfer)
1255 uhci_td_t *td_alt_next;
1260 td = xfer->td_transfer_cache;
1261 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1263 td_token = td->obj_next->td_token;
1265 xfer->td_transfer_cache = td;
1266 td_self = td->td_self;
1267 td_alt_next = td->alt_next;
1269 if (xfer->flags_int.control_xfr)
1270 goto skip; /* don't touch the DT value! */
1272 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1))))
1273 goto skip; /* data toggle has correct value */
1276 * The data toggle is wrong and we need to toggle it !
1280 td->td_token ^= htole32(UHCI_TD_SET_DT(1));
1281 usb_pc_cpu_flush(td->page_cache);
1283 if (td == xfer->td_transfer_last) {
1289 if (td->alt_next != td_alt_next) {
1297 qh->qh_e_next = td_self;
1298 usb_pc_cpu_flush(qh->page_cache);
1300 DPRINTFN(13, "xfer=%p following alt next\n", xfer);
1303 /*------------------------------------------------------------------------*
1304 * uhci_check_transfer
1307 * 0: USB transfer is not finished
1308 * Else: USB transfer is finished
1309 *------------------------------------------------------------------------*/
1311 uhci_check_transfer(struct usb_xfer *xfer)
1317 DPRINTFN(16, "xfer=%p checking transfer\n", xfer);
1319 if (xfer->endpoint->methods == &uhci_device_isoc_methods) {
1320 /* isochronous transfer */
1322 td = xfer->td_transfer_last;
1324 usb_pc_cpu_invalidate(td->page_cache);
1325 status = le32toh(td->td_status);
1327 /* check also if the first is complete */
1329 td = xfer->td_transfer_first;
1331 usb_pc_cpu_invalidate(td->page_cache);
1332 status |= le32toh(td->td_status);
1334 if (!(status & UHCI_TD_ACTIVE)) {
1335 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1339 /* non-isochronous transfer */
1342 * check whether there is an error somewhere
1343 * in the middle, or whether there was a short
1344 * packet (SPD and not ACTIVE)
1346 td = xfer->td_transfer_cache;
1349 usb_pc_cpu_invalidate(td->page_cache);
1350 status = le32toh(td->td_status);
1351 token = le32toh(td->td_token);
1354 * if there is an active TD the transfer isn't done
1356 if (status & UHCI_TD_ACTIVE) {
1358 xfer->td_transfer_cache = td;
1362 * last transfer descriptor makes the transfer done
1364 if (((void *)td) == xfer->td_transfer_last) {
1368 * any kind of error makes the transfer done
1370 if (status & UHCI_TD_STALLED) {
1374 * check if we reached the last packet
1375 * or if there is a short packet:
1377 if ((td->td_next == htole32(UHCI_PTR_T)) ||
1378 (UHCI_TD_GET_ACTLEN(status) < td->len)) {
1380 if (xfer->flags_int.short_frames_ok) {
1381 /* follow alt next */
1384 xfer->td_transfer_cache = td;
1385 uhci_check_transfer_sub(xfer);
1389 /* transfer is done */
1394 uhci_non_isoc_done(xfer);
1399 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1407 uhci_interrupt_poll(uhci_softc_t *sc)
1409 struct usb_xfer *xfer;
1412 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1414 * check if transfer is transferred
1416 if (uhci_check_transfer(xfer)) {
1417 /* queue has been modified */
1423 /*------------------------------------------------------------------------*
1424 * uhci_interrupt - UHCI interrupt handler
1426 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1427 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1429 *------------------------------------------------------------------------*/
1431 uhci_interrupt(uhci_softc_t *sc)
1435 USB_BUS_LOCK(&sc->sc_bus);
1437 DPRINTFN(16, "real interrupt\n");
1440 if (uhcidebug > 15) {
1444 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1446 /* the interrupt was not for us */
1449 if (status & (UHCI_STS_RD | UHCI_STS_HSE |
1450 UHCI_STS_HCPE | UHCI_STS_HCH)) {
1452 if (status & UHCI_STS_RD) {
1454 printf("%s: resume detect\n",
1458 if (status & UHCI_STS_HSE) {
1459 printf("%s: host system error\n",
1462 if (status & UHCI_STS_HCPE) {
1463 printf("%s: host controller process error\n",
1466 if (status & UHCI_STS_HCH) {
1467 /* no acknowledge needed */
1468 DPRINTF("%s: host controller halted\n",
1471 if (uhcidebug > 0) {
1477 /* get acknowledge bits */
1478 status &= (UHCI_STS_USBINT |
1486 /* nothing to acknowledge */
1489 /* acknowledge interrupts */
1490 UWRITE2(sc, UHCI_STS, status);
1492 /* poll all the USB transfers */
1493 uhci_interrupt_poll(sc);
1496 USB_BUS_UNLOCK(&sc->sc_bus);
1500 * called when a request does not complete
1503 uhci_timeout(void *arg)
1505 struct usb_xfer *xfer = arg;
1507 DPRINTF("xfer=%p\n", xfer);
1509 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1511 /* transfer is transferred */
1512 uhci_device_done(xfer, USB_ERR_TIMEOUT);
1516 uhci_do_poll(struct usb_bus *bus)
1518 struct uhci_softc *sc = UHCI_BUS2SC(bus);
1520 USB_BUS_LOCK(&sc->sc_bus);
1521 uhci_interrupt_poll(sc);
1522 USB_BUS_UNLOCK(&sc->sc_bus);
1526 uhci_setup_standard_chain_sub(struct uhci_std_temp *temp)
1530 uhci_td_t *td_alt_next;
1533 uint8_t shortpkt_old;
1537 shortpkt_old = temp->shortpkt;
1538 len_old = temp->len;
1541 /* software is used to detect short incoming transfers */
1543 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) {
1544 temp->td_status |= htole32(UHCI_TD_SPD);
1546 temp->td_status &= ~htole32(UHCI_TD_SPD);
1549 temp->ml.buf_offset = 0;
1553 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0));
1554 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average));
1557 td_next = temp->td_next;
1561 if (temp->len == 0) {
1563 if (temp->shortpkt) {
1566 /* send a Zero Length Packet, ZLP, last */
1569 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0));
1574 average = temp->average;
1576 if (temp->len < average) {
1578 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0));
1579 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len));
1580 average = temp->len;
1584 if (td_next == NULL) {
1585 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__);
1590 td_next = td->obj_next;
1592 /* check if we are pre-computing */
1596 /* update remaining length */
1598 temp->len -= average;
1602 /* fill out current TD */
1604 td->td_status = temp->td_status;
1605 td->td_token = temp->td_token;
1607 /* update data toggle */
1609 temp->td_token ^= htole32(UHCI_TD_SET_DT(1));
1619 /* update remaining length */
1621 temp->len -= average;
1625 /* fill out buffer pointer and do fixup, if any */
1627 uhci_mem_layout_fixup(&temp->ml, td);
1630 td->alt_next = td_alt_next;
1632 if ((td_next == td_alt_next) && temp->setup_alt_next) {
1633 /* we need to receive these frames one by one ! */
1634 td->td_status |= htole32(UHCI_TD_IOC);
1635 td->td_next = htole32(UHCI_PTR_T);
1638 /* link the current TD with the next one */
1639 td->td_next = td_next->td_self;
1643 usb_pc_cpu_flush(td->page_cache);
1649 /* setup alt next pointer, if any */
1650 if (temp->last_frame) {
1653 /* we use this field internally */
1654 td_alt_next = td_next;
1658 temp->shortpkt = shortpkt_old;
1659 temp->len = len_old;
1663 temp->td_next = td_next;
1667 uhci_setup_standard_chain(struct usb_xfer *xfer)
1669 struct uhci_std_temp temp;
1673 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1674 xfer->address, UE_GET_ADDR(xfer->endpointno),
1675 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1677 temp.average = xfer->max_frame_size;
1678 temp.max_frame_size = xfer->max_frame_size;
1680 /* toggle the DMA set we are using */
1681 xfer->flags_int.curr_dma_set ^= 1;
1683 /* get next DMA set */
1684 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1685 xfer->td_transfer_first = td;
1686 xfer->td_transfer_cache = td;
1690 temp.last_frame = 0;
1691 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1693 uhci_mem_layout_init(&temp.ml, xfer);
1696 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) |
1699 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1700 temp.td_status |= htole32(UHCI_TD_LS);
1703 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) |
1704 UHCI_TD_SET_DEVADDR(xfer->address));
1706 if (xfer->endpoint->toggle_next) {
1708 temp.td_token |= htole32(UHCI_TD_SET_DT(1));
1710 /* check if we should prepend a setup message */
1712 if (xfer->flags_int.control_xfr) {
1714 if (xfer->flags_int.control_hdr) {
1716 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1717 UHCI_TD_SET_ENDPT(0xF));
1718 temp.td_token |= htole32(UHCI_TD_PID_SETUP |
1721 temp.len = xfer->frlengths[0];
1722 temp.ml.buf_pc = xfer->frbuffers + 0;
1723 temp.shortpkt = temp.len ? 1 : 0;
1724 /* check for last frame */
1725 if (xfer->nframes == 1) {
1726 /* no STATUS stage yet, SETUP is last */
1727 if (xfer->flags_int.control_act) {
1728 temp.last_frame = 1;
1729 temp.setup_alt_next = 0;
1732 uhci_setup_standard_chain_sub(&temp);
1739 while (x != xfer->nframes) {
1741 /* DATA0 / DATA1 message */
1743 temp.len = xfer->frlengths[x];
1744 temp.ml.buf_pc = xfer->frbuffers + x;
1748 if (x == xfer->nframes) {
1749 if (xfer->flags_int.control_xfr) {
1750 /* no STATUS stage yet, DATA is last */
1751 if (xfer->flags_int.control_act) {
1752 temp.last_frame = 1;
1753 temp.setup_alt_next = 0;
1756 temp.last_frame = 1;
1757 temp.setup_alt_next = 0;
1761 * Keep previous data toggle,
1762 * device address and endpoint number:
1765 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1766 UHCI_TD_SET_ENDPT(0xF) |
1769 if (temp.len == 0) {
1771 /* make sure that we send an USB packet */
1777 /* regular data transfer */
1779 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1782 /* set endpoint direction */
1785 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1786 htole32(UHCI_TD_PID_IN) :
1787 htole32(UHCI_TD_PID_OUT);
1789 uhci_setup_standard_chain_sub(&temp);
1792 /* check if we should append a status stage */
1794 if (xfer->flags_int.control_xfr &&
1795 !xfer->flags_int.control_act) {
1798 * send a DATA1 message and reverse the current endpoint
1802 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1803 UHCI_TD_SET_ENDPT(0xF) |
1806 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1807 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) :
1808 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1));
1811 temp.ml.buf_pc = NULL;
1813 temp.last_frame = 1;
1814 temp.setup_alt_next = 0;
1816 uhci_setup_standard_chain_sub(&temp);
1820 /* Ensure that last TD is terminating: */
1821 td->td_next = htole32(UHCI_PTR_T);
1823 /* set interrupt bit */
1825 td->td_status |= htole32(UHCI_TD_IOC);
1827 usb_pc_cpu_flush(td->page_cache);
1829 /* must have at least one frame! */
1831 xfer->td_transfer_last = td;
1834 if (uhcidebug > 8) {
1835 DPRINTF("nexttog=%d; data before transfer:\n",
1836 xfer->endpoint->toggle_next);
1837 uhci_dump_tds(xfer->td_transfer_first);
1840 return (xfer->td_transfer_first);
1843 /* NOTE: "done" can be run two times in a row,
1844 * from close and from interrupt
1848 uhci_device_done(struct usb_xfer *xfer, usb_error_t error)
1850 const struct usb_pipe_methods *methods = xfer->endpoint->methods;
1851 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1854 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1856 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1857 xfer, xfer->endpoint, error);
1859 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1861 usb_pc_cpu_invalidate(qh->page_cache);
1863 if (xfer->flags_int.bandwidth_reclaimed) {
1864 xfer->flags_int.bandwidth_reclaimed = 0;
1867 if (methods == &uhci_device_bulk_methods) {
1868 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last);
1870 if (methods == &uhci_device_ctrl_methods) {
1871 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1872 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last);
1874 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last);
1877 if (methods == &uhci_device_intr_methods) {
1878 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
1881 * Only finish isochronous transfers once
1882 * which will update "xfer->frlengths".
1884 if (xfer->td_transfer_first &&
1885 xfer->td_transfer_last) {
1886 if (methods == &uhci_device_isoc_methods) {
1887 uhci_isoc_done(sc, xfer);
1889 xfer->td_transfer_first = NULL;
1890 xfer->td_transfer_last = NULL;
1892 /* dequeue transfer and start next transfer */
1893 usbd_transfer_done(xfer, error);
1896 /*------------------------------------------------------------------------*
1898 *------------------------------------------------------------------------*/
1900 uhci_device_bulk_open(struct usb_xfer *xfer)
1906 uhci_device_bulk_close(struct usb_xfer *xfer)
1908 uhci_device_done(xfer, USB_ERR_CANCELLED);
1912 uhci_device_bulk_enter(struct usb_xfer *xfer)
1918 uhci_device_bulk_start(struct usb_xfer *xfer)
1920 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1925 td = uhci_setup_standard_chain(xfer);
1928 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1931 qh->qh_e_next = td->td_self;
1933 if (xfer->xroot->udev->flags.self_suspended == 0) {
1934 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last);
1936 xfer->flags_int.bandwidth_reclaimed = 1;
1938 usb_pc_cpu_flush(qh->page_cache);
1941 /* put transfer on interrupt queue */
1942 uhci_transfer_intr_enqueue(xfer);
1945 static const struct usb_pipe_methods uhci_device_bulk_methods =
1947 .open = uhci_device_bulk_open,
1948 .close = uhci_device_bulk_close,
1949 .enter = uhci_device_bulk_enter,
1950 .start = uhci_device_bulk_start,
1953 /*------------------------------------------------------------------------*
1954 * uhci control support
1955 *------------------------------------------------------------------------*/
1957 uhci_device_ctrl_open(struct usb_xfer *xfer)
1963 uhci_device_ctrl_close(struct usb_xfer *xfer)
1965 uhci_device_done(xfer, USB_ERR_CANCELLED);
1969 uhci_device_ctrl_enter(struct usb_xfer *xfer)
1975 uhci_device_ctrl_start(struct usb_xfer *xfer)
1977 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1982 td = uhci_setup_standard_chain(xfer);
1985 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1988 qh->qh_e_next = td->td_self;
1991 * NOTE: some devices choke on bandwidth- reclamation for control
1994 if (xfer->xroot->udev->flags.self_suspended == 0) {
1995 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1996 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last);
1998 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last);
2001 usb_pc_cpu_flush(qh->page_cache);
2003 /* put transfer on interrupt queue */
2004 uhci_transfer_intr_enqueue(xfer);
2007 static const struct usb_pipe_methods uhci_device_ctrl_methods =
2009 .open = uhci_device_ctrl_open,
2010 .close = uhci_device_ctrl_close,
2011 .enter = uhci_device_ctrl_enter,
2012 .start = uhci_device_ctrl_start,
2015 /*------------------------------------------------------------------------*
2016 * uhci interrupt support
2017 *------------------------------------------------------------------------*/
2019 uhci_device_intr_open(struct usb_xfer *xfer)
2021 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2027 bit = UHCI_IFRAMELIST_COUNT / 2;
2029 if (xfer->interval >= bit) {
2033 if (sc->sc_intr_stat[x] <
2034 sc->sc_intr_stat[best]) {
2044 sc->sc_intr_stat[best]++;
2045 xfer->qh_pos = best;
2047 DPRINTFN(3, "best=%d interval=%d\n",
2048 best, xfer->interval);
2052 uhci_device_intr_close(struct usb_xfer *xfer)
2054 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2056 sc->sc_intr_stat[xfer->qh_pos]--;
2058 uhci_device_done(xfer, USB_ERR_CANCELLED);
2062 uhci_device_intr_enter(struct usb_xfer *xfer)
2068 uhci_device_intr_start(struct usb_xfer *xfer)
2070 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2075 td = uhci_setup_standard_chain(xfer);
2078 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
2081 qh->qh_e_next = td->td_self;
2083 if (xfer->xroot->udev->flags.self_suspended == 0) {
2084 /* enter QHs into the controller data structures */
2085 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
2087 usb_pc_cpu_flush(qh->page_cache);
2090 /* put transfer on interrupt queue */
2091 uhci_transfer_intr_enqueue(xfer);
2094 static const struct usb_pipe_methods uhci_device_intr_methods =
2096 .open = uhci_device_intr_open,
2097 .close = uhci_device_intr_close,
2098 .enter = uhci_device_intr_enter,
2099 .start = uhci_device_intr_start,
2102 /*------------------------------------------------------------------------*
2103 * uhci isochronous support
2104 *------------------------------------------------------------------------*/
2106 uhci_device_isoc_open(struct usb_xfer *xfer)
2113 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
2114 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) :
2115 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0);
2117 td_token = htole32(td_token);
2119 /* initialize all TD's */
2121 for (ds = 0; ds != 2; ds++) {
2123 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2125 /* mark TD as inactive */
2126 td->td_status = htole32(UHCI_TD_IOS);
2127 td->td_token = td_token;
2129 usb_pc_cpu_flush(td->page_cache);
2135 uhci_device_isoc_close(struct usb_xfer *xfer)
2137 uhci_device_done(xfer, USB_ERR_CANCELLED);
2141 uhci_device_isoc_enter(struct usb_xfer *xfer)
2143 struct uhci_mem_layout ml;
2144 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2154 uhci_td_t *td_last = NULL;
2155 uhci_td_t **pp_last;
2157 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2158 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2160 nframes = UREAD2(sc, UHCI_FRNUM);
2162 temp = (nframes - xfer->endpoint->isoc_next) &
2163 (UHCI_VFRAMELIST_COUNT - 1);
2165 if ((xfer->endpoint->is_synced == 0) ||
2166 (temp < xfer->nframes)) {
2168 * If there is data underflow or the pipe queue is empty we
2169 * schedule the transfer a few frames ahead of the current
2170 * frame position. Else two isochronous transfers might
2173 xfer->endpoint->isoc_next = (nframes + 3) & (UHCI_VFRAMELIST_COUNT - 1);
2174 xfer->endpoint->is_synced = 1;
2175 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2178 * compute how many milliseconds the insertion is ahead of the
2179 * current frame position:
2181 temp = (xfer->endpoint->isoc_next - nframes) &
2182 (UHCI_VFRAMELIST_COUNT - 1);
2185 * pre-compute when the isochronous transfer will be finished:
2187 xfer->isoc_time_complete =
2188 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
2191 /* get the real number of frames */
2193 nframes = xfer->nframes;
2195 uhci_mem_layout_init(&ml, xfer);
2197 plen = xfer->frlengths;
2199 /* toggle the DMA set we are using */
2200 xfer->flags_int.curr_dma_set ^= 1;
2202 /* get next DMA set */
2203 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2204 xfer->td_transfer_first = td;
2206 pp_last = &sc->sc_isoc_p_last[xfer->endpoint->isoc_next];
2208 /* store starting position */
2210 xfer->qh_pos = xfer->endpoint->isoc_next;
2214 panic("%s:%d: out of TD's\n",
2215 __FUNCTION__, __LINE__);
2217 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) {
2218 pp_last = &sc->sc_isoc_p_last[0];
2220 if (*plen > xfer->max_frame_size) {
2224 printf("%s: frame length(%d) exceeds %d "
2225 "bytes (frame truncated)\n",
2226 __FUNCTION__, *plen,
2227 xfer->max_frame_size);
2230 *plen = xfer->max_frame_size;
2232 /* reuse td_token from last transfer */
2234 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
2235 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen));
2241 * Do not call "uhci_mem_layout_fixup()" when the
2249 /* fill out buffer pointer and do fixup, if any */
2251 uhci_mem_layout_fixup(&ml, td);
2257 td->td_status = htole32
2258 (UHCI_TD_ZERO_ACTLEN
2259 (UHCI_TD_SET_ERRCNT(0) |
2264 td->td_status = htole32
2265 (UHCI_TD_ZERO_ACTLEN
2266 (UHCI_TD_SET_ERRCNT(0) |
2271 usb_pc_cpu_flush(td->page_cache);
2274 if (uhcidebug > 5) {
2275 DPRINTF("TD %d\n", nframes);
2279 /* insert TD into schedule */
2280 UHCI_APPEND_TD(td, *pp_last);
2288 xfer->td_transfer_last = td_last;
2290 /* update isoc_next */
2291 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_p_last[0]) &
2292 (UHCI_VFRAMELIST_COUNT - 1);
2296 uhci_device_isoc_start(struct usb_xfer *xfer)
2298 /* put transfer on interrupt queue */
2299 uhci_transfer_intr_enqueue(xfer);
2302 static const struct usb_pipe_methods uhci_device_isoc_methods =
2304 .open = uhci_device_isoc_open,
2305 .close = uhci_device_isoc_close,
2306 .enter = uhci_device_isoc_enter,
2307 .start = uhci_device_isoc_start,
2310 /*------------------------------------------------------------------------*
2311 * uhci root control support
2312 *------------------------------------------------------------------------*
2313 * Simulate a hardware hub by handling all the necessary requests.
2314 *------------------------------------------------------------------------*/
2317 struct usb_device_descriptor uhci_devd =
2319 sizeof(struct usb_device_descriptor),
2320 UDESC_DEVICE, /* type */
2321 {0x00, 0x01}, /* USB version */
2322 UDCLASS_HUB, /* class */
2323 UDSUBCLASS_HUB, /* subclass */
2324 UDPROTO_FSHUB, /* protocol */
2325 64, /* max packet */
2326 {0}, {0}, {0x00, 0x01}, /* device id */
2327 1, 2, 0, /* string indexes */
2328 1 /* # of configurations */
2331 static const struct uhci_config_desc uhci_confd = {
2333 .bLength = sizeof(struct usb_config_descriptor),
2334 .bDescriptorType = UDESC_CONFIG,
2335 .wTotalLength[0] = sizeof(uhci_confd),
2337 .bConfigurationValue = 1,
2338 .iConfiguration = 0,
2339 .bmAttributes = UC_SELF_POWERED,
2340 .bMaxPower = 0 /* max power */
2343 .bLength = sizeof(struct usb_interface_descriptor),
2344 .bDescriptorType = UDESC_INTERFACE,
2346 .bInterfaceClass = UICLASS_HUB,
2347 .bInterfaceSubClass = UISUBCLASS_HUB,
2348 .bInterfaceProtocol = UIPROTO_FSHUB,
2351 .bLength = sizeof(struct usb_endpoint_descriptor),
2352 .bDescriptorType = UDESC_ENDPOINT,
2353 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT,
2354 .bmAttributes = UE_INTERRUPT,
2355 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
2361 struct usb_hub_descriptor_min uhci_hubd_piix =
2363 .bDescLength = sizeof(uhci_hubd_piix),
2364 .bDescriptorType = UDESC_HUB,
2366 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0},
2367 .bPwrOn2PwrGood = 50,
2371 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
2372 * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
2373 * should not be used by the USB subsystem. As we cannot issue a
2374 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
2375 * will be enabled as part of the reset.
2377 * On the VT83C572, the port cannot be successfully enabled until the
2378 * outstanding "port enable change" and "connection status change"
2379 * events have been reset.
2382 uhci_portreset(uhci_softc_t *sc, uint16_t index)
2389 port = UHCI_PORTSC1;
2390 else if (index == 2)
2391 port = UHCI_PORTSC2;
2393 return (USB_ERR_IOERROR);
2396 * Before we do anything, turn on SOF messages on the USB
2397 * BUS. Some USB devices do not cope without them!
2401 x = URWMASK(UREAD2(sc, port));
2402 UWRITE2(sc, port, x | UHCI_PORTSC_PR);
2404 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2405 USB_MS_TO_TICKS(usb_port_root_reset_delay));
2407 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n",
2408 index, UREAD2(sc, port));
2410 x = URWMASK(UREAD2(sc, port));
2411 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2414 mtx_unlock(&sc->sc_bus.bus_mtx);
2417 * This delay needs to be exactly 100us, else some USB devices
2422 mtx_lock(&sc->sc_bus.bus_mtx);
2424 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n",
2425 index, UREAD2(sc, port));
2427 x = URWMASK(UREAD2(sc, port));
2428 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2430 for (lim = 0; lim < 12; lim++) {
2432 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2433 USB_MS_TO_TICKS(usb_port_reset_delay));
2435 x = UREAD2(sc, port);
2437 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n",
2440 if (!(x & UHCI_PORTSC_CCS)) {
2442 * No device is connected (or was disconnected
2443 * during reset). Consider the port reset.
2444 * The delay must be long enough to ensure on
2445 * the initial iteration that the device
2446 * connection will have been registered. 50ms
2447 * appears to be sufficient, but 20ms is not.
2449 DPRINTFN(4, "uhci port %d loop %u, device detached\n",
2453 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
2455 * Port enabled changed and/or connection
2456 * status changed were set. Reset either or
2457 * both raised flags (by writing a 1 to that
2458 * bit), and wait again for state to settle.
2460 UWRITE2(sc, port, URWMASK(x) |
2461 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
2464 if (x & UHCI_PORTSC_PE) {
2465 /* port is enabled */
2468 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
2471 DPRINTFN(2, "uhci port %d reset timed out\n", index);
2472 return (USB_ERR_TIMEOUT);
2475 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n",
2476 index, UREAD2(sc, port));
2479 return (USB_ERR_NORMAL_COMPLETION);
2483 uhci_roothub_exec(struct usb_device *udev,
2484 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2486 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus);
2488 const char *str_ptr;
2498 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2501 ptr = (const void *)&sc->sc_hub_desc.temp;
2505 value = UGETW(req->wValue);
2506 index = UGETW(req->wIndex);
2508 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
2509 "wValue=0x%04x wIndex=0x%04x\n",
2510 req->bmRequestType, req->bRequest,
2511 UGETW(req->wLength), value, index);
2513 #define C(x,y) ((x) | ((y) << 8))
2514 switch (C(req->bRequest, req->bmRequestType)) {
2515 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2516 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2517 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
2519 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2520 * for the integrated root hub.
2523 case C(UR_GET_CONFIG, UT_READ_DEVICE):
2525 sc->sc_hub_desc.temp[0] = sc->sc_conf;
2527 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2528 switch (value >> 8) {
2530 if ((value & 0xff) != 0) {
2531 err = USB_ERR_IOERROR;
2534 len = sizeof(uhci_devd);
2535 ptr = (const void *)&uhci_devd;
2539 if ((value & 0xff) != 0) {
2540 err = USB_ERR_IOERROR;
2543 len = sizeof(uhci_confd);
2544 ptr = (const void *)&uhci_confd;
2548 switch (value & 0xff) {
2549 case 0: /* Language table */
2553 case 1: /* Vendor */
2554 str_ptr = sc->sc_vendor;
2557 case 2: /* Product */
2558 str_ptr = "UHCI root HUB";
2566 len = usb_make_str_desc
2567 (sc->sc_hub_desc.temp,
2568 sizeof(sc->sc_hub_desc.temp),
2573 err = USB_ERR_IOERROR;
2577 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
2579 sc->sc_hub_desc.temp[0] = 0;
2581 case C(UR_GET_STATUS, UT_READ_DEVICE):
2583 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
2585 case C(UR_GET_STATUS, UT_READ_INTERFACE):
2586 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
2588 USETW(sc->sc_hub_desc.stat.wStatus, 0);
2590 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
2591 if (value >= UHCI_MAX_DEVICES) {
2592 err = USB_ERR_IOERROR;
2595 sc->sc_addr = value;
2597 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
2598 if ((value != 0) && (value != 1)) {
2599 err = USB_ERR_IOERROR;
2602 sc->sc_conf = value;
2604 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
2606 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
2607 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
2608 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
2609 err = USB_ERR_IOERROR;
2611 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
2613 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
2616 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2618 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2619 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE "
2620 "port=%d feature=%d\n",
2623 port = UHCI_PORTSC1;
2624 else if (index == 2)
2625 port = UHCI_PORTSC2;
2627 err = USB_ERR_IOERROR;
2631 case UHF_PORT_ENABLE:
2632 x = URWMASK(UREAD2(sc, port));
2633 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
2635 case UHF_PORT_SUSPEND:
2636 x = URWMASK(UREAD2(sc, port));
2637 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP));
2639 case UHF_PORT_RESET:
2640 x = URWMASK(UREAD2(sc, port));
2641 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2643 case UHF_C_PORT_CONNECTION:
2644 x = URWMASK(UREAD2(sc, port));
2645 UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
2647 case UHF_C_PORT_ENABLE:
2648 x = URWMASK(UREAD2(sc, port));
2649 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
2651 case UHF_C_PORT_OVER_CURRENT:
2652 x = URWMASK(UREAD2(sc, port));
2653 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
2655 case UHF_C_PORT_RESET:
2657 err = USB_ERR_NORMAL_COMPLETION;
2659 case UHF_C_PORT_SUSPEND:
2660 sc->sc_isresumed &= ~(1 << index);
2662 case UHF_PORT_CONNECTION:
2663 case UHF_PORT_OVER_CURRENT:
2664 case UHF_PORT_POWER:
2665 case UHF_PORT_LOW_SPEED:
2667 err = USB_ERR_IOERROR;
2671 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
2673 port = UHCI_PORTSC1;
2674 else if (index == 2)
2675 port = UHCI_PORTSC2;
2677 err = USB_ERR_IOERROR;
2681 sc->sc_hub_desc.temp[0] =
2682 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >>
2683 UHCI_PORTSC_LS_SHIFT);
2685 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2686 if ((value & 0xff) != 0) {
2687 err = USB_ERR_IOERROR;
2690 len = sizeof(uhci_hubd_piix);
2691 ptr = (const void *)&uhci_hubd_piix;
2693 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2695 memset(sc->sc_hub_desc.temp, 0, 16);
2697 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2699 port = UHCI_PORTSC1;
2700 else if (index == 2)
2701 port = UHCI_PORTSC2;
2703 err = USB_ERR_IOERROR;
2706 x = UREAD2(sc, port);
2707 status = change = 0;
2708 if (x & UHCI_PORTSC_CCS)
2709 status |= UPS_CURRENT_CONNECT_STATUS;
2710 if (x & UHCI_PORTSC_CSC)
2711 change |= UPS_C_CONNECT_STATUS;
2712 if (x & UHCI_PORTSC_PE)
2713 status |= UPS_PORT_ENABLED;
2714 if (x & UHCI_PORTSC_POEDC)
2715 change |= UPS_C_PORT_ENABLED;
2716 if (x & UHCI_PORTSC_OCI)
2717 status |= UPS_OVERCURRENT_INDICATOR;
2718 if (x & UHCI_PORTSC_OCIC)
2719 change |= UPS_C_OVERCURRENT_INDICATOR;
2720 if (x & UHCI_PORTSC_LSDA)
2721 status |= UPS_LOW_SPEED;
2722 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) {
2723 /* need to do a write back */
2724 UWRITE2(sc, port, URWMASK(x));
2726 /* wait 20ms for resume sequence to complete */
2727 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
2729 /* clear suspend and resume detect */
2730 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD |
2733 /* wait a little bit */
2734 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500);
2736 sc->sc_isresumed |= (1 << index);
2738 } else if (x & UHCI_PORTSC_SUSP) {
2739 status |= UPS_SUSPEND;
2741 status |= UPS_PORT_POWER;
2742 if (sc->sc_isresumed & (1 << index))
2743 change |= UPS_C_SUSPEND;
2745 change |= UPS_C_PORT_RESET;
2746 USETW(sc->sc_hub_desc.ps.wPortStatus, status);
2747 USETW(sc->sc_hub_desc.ps.wPortChange, change);
2748 len = sizeof(sc->sc_hub_desc.ps);
2750 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2751 err = USB_ERR_IOERROR;
2753 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2755 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2757 port = UHCI_PORTSC1;
2758 else if (index == 2)
2759 port = UHCI_PORTSC2;
2761 err = USB_ERR_IOERROR;
2765 case UHF_PORT_ENABLE:
2766 x = URWMASK(UREAD2(sc, port));
2767 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2769 case UHF_PORT_SUSPEND:
2770 x = URWMASK(UREAD2(sc, port));
2771 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
2773 case UHF_PORT_RESET:
2774 err = uhci_portreset(sc, index);
2776 case UHF_PORT_POWER:
2777 /* pretend we turned on power */
2778 err = USB_ERR_NORMAL_COMPLETION;
2780 case UHF_C_PORT_CONNECTION:
2781 case UHF_C_PORT_ENABLE:
2782 case UHF_C_PORT_OVER_CURRENT:
2783 case UHF_PORT_CONNECTION:
2784 case UHF_PORT_OVER_CURRENT:
2785 case UHF_PORT_LOW_SPEED:
2786 case UHF_C_PORT_SUSPEND:
2787 case UHF_C_PORT_RESET:
2789 err = USB_ERR_IOERROR;
2794 err = USB_ERR_IOERROR;
2804 * This routine is executed periodically and simulates interrupts from
2805 * the root controller interrupt pipe for port status change:
2808 uhci_root_intr(uhci_softc_t *sc)
2812 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2814 sc->sc_hub_idata[0] = 0;
2816 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC |
2817 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) {
2818 sc->sc_hub_idata[0] |= 1 << 1;
2820 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC |
2821 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) {
2822 sc->sc_hub_idata[0] |= 1 << 2;
2826 usb_callout_reset(&sc->sc_root_intr, hz,
2827 (void *)&uhci_root_intr, sc);
2829 if (sc->sc_hub_idata[0] != 0) {
2830 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2831 sizeof(sc->sc_hub_idata));
2836 uhci_xfer_setup(struct usb_setup_params *parm)
2838 struct usb_page_search page_info;
2839 struct usb_page_cache *pc;
2841 struct usb_xfer *xfer;
2849 sc = UHCI_BUS2SC(parm->udev->bus);
2850 xfer = parm->curr_xfer;
2852 parm->hc_max_packet_size = 0x500;
2853 parm->hc_max_packet_count = 1;
2854 parm->hc_max_frame_size = 0x500;
2857 * compute ntd and nqh
2859 if (parm->methods == &uhci_device_ctrl_methods) {
2860 xfer->flags_int.bdma_enable = 1;
2861 xfer->flags_int.bdma_no_post_sync = 1;
2863 usbd_transfer_setup_sub(parm);
2865 /* see EHCI HC driver for proof of "ntd" formula */
2868 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
2869 + (xfer->max_data_length / xfer->max_frame_size));
2871 } else if (parm->methods == &uhci_device_bulk_methods) {
2872 xfer->flags_int.bdma_enable = 1;
2873 xfer->flags_int.bdma_no_post_sync = 1;
2875 usbd_transfer_setup_sub(parm);
2878 ntd = ((2 * xfer->nframes)
2879 + (xfer->max_data_length / xfer->max_frame_size));
2881 } else if (parm->methods == &uhci_device_intr_methods) {
2882 xfer->flags_int.bdma_enable = 1;
2883 xfer->flags_int.bdma_no_post_sync = 1;
2885 usbd_transfer_setup_sub(parm);
2888 ntd = ((2 * xfer->nframes)
2889 + (xfer->max_data_length / xfer->max_frame_size));
2891 } else if (parm->methods == &uhci_device_isoc_methods) {
2892 xfer->flags_int.bdma_enable = 1;
2893 xfer->flags_int.bdma_no_post_sync = 1;
2895 usbd_transfer_setup_sub(parm);
2898 ntd = xfer->nframes;
2902 usbd_transfer_setup_sub(parm);
2912 * NOTE: the UHCI controller requires that
2913 * every packet must be contiguous on
2914 * the same USB memory page !
2916 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1;
2919 * Compute a suitable power of two alignment
2920 * for our "max_frame_size" fixup buffer(s):
2922 align = xfer->max_frame_size;
2929 /* check for power of two */
2930 if (!(xfer->max_frame_size &
2931 (xfer->max_frame_size - 1))) {
2935 * We don't allow alignments of
2936 * less than 8 bytes:
2938 * NOTE: Allocating using an aligment
2939 * of 1 byte has special meaning!
2946 if (usbd_transfer_setup_sub_malloc(
2947 parm, &pc, xfer->max_frame_size,
2949 parm->err = USB_ERR_NOMEM;
2952 xfer->buf_fixup = pc;
2961 if (usbd_transfer_setup_sub_malloc(
2962 parm, &pc, sizeof(uhci_td_t),
2963 UHCI_TD_ALIGN, ntd)) {
2964 parm->err = USB_ERR_NOMEM;
2968 for (n = 0; n != ntd; n++) {
2971 usbd_get_page(pc + n, 0, &page_info);
2973 td = page_info.buffer;
2976 if ((parm->methods == &uhci_device_bulk_methods) ||
2977 (parm->methods == &uhci_device_ctrl_methods) ||
2978 (parm->methods == &uhci_device_intr_methods)) {
2979 /* set depth first bit */
2980 td->td_self = htole32(page_info.physaddr |
2981 UHCI_PTR_TD | UHCI_PTR_VF);
2983 td->td_self = htole32(page_info.physaddr |
2987 td->obj_next = last_obj;
2988 td->page_cache = pc + n;
2992 usb_pc_cpu_flush(pc + n);
2995 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
2999 if (usbd_transfer_setup_sub_malloc(
3000 parm, &pc, sizeof(uhci_qh_t),
3001 UHCI_QH_ALIGN, nqh)) {
3002 parm->err = USB_ERR_NOMEM;
3006 for (n = 0; n != nqh; n++) {
3009 usbd_get_page(pc + n, 0, &page_info);
3011 qh = page_info.buffer;
3014 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH);
3015 qh->obj_next = last_obj;
3016 qh->page_cache = pc + n;
3020 usb_pc_cpu_flush(pc + n);
3023 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3025 if (!xfer->flags_int.curr_dma_set) {
3026 xfer->flags_int.curr_dma_set = 1;
3032 uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3033 struct usb_endpoint *ep)
3035 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus);
3037 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3039 edesc->bEndpointAddress, udev->flags.usb_mode,
3042 if (udev->device_index != sc->sc_addr) {
3043 switch (edesc->bmAttributes & UE_XFERTYPE) {
3045 ep->methods = &uhci_device_ctrl_methods;
3048 ep->methods = &uhci_device_intr_methods;
3050 case UE_ISOCHRONOUS:
3051 if (udev->speed == USB_SPEED_FULL) {
3052 ep->methods = &uhci_device_isoc_methods;
3056 ep->methods = &uhci_device_bulk_methods;
3066 uhci_xfer_unsetup(struct usb_xfer *xfer)
3072 uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3075 * Wait until hardware has finished any possible use of the
3076 * transfer descriptor(s) and QH
3078 *pus = (1125); /* microseconds */
3082 uhci_device_resume(struct usb_device *udev)
3084 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus);
3085 struct usb_xfer *xfer;
3086 const struct usb_pipe_methods *methods;
3091 USB_BUS_LOCK(udev->bus);
3093 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3095 if (xfer->xroot->udev == udev) {
3097 methods = xfer->endpoint->methods;
3098 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
3100 if (methods == &uhci_device_bulk_methods) {
3101 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last);
3103 xfer->flags_int.bandwidth_reclaimed = 1;
3105 if (methods == &uhci_device_ctrl_methods) {
3106 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
3107 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last);
3109 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last);
3112 if (methods == &uhci_device_intr_methods) {
3113 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
3118 USB_BUS_UNLOCK(udev->bus);
3124 uhci_device_suspend(struct usb_device *udev)
3126 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus);
3127 struct usb_xfer *xfer;
3128 const struct usb_pipe_methods *methods;
3133 USB_BUS_LOCK(udev->bus);
3135 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3137 if (xfer->xroot->udev == udev) {
3139 methods = xfer->endpoint->methods;
3140 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
3142 if (xfer->flags_int.bandwidth_reclaimed) {
3143 xfer->flags_int.bandwidth_reclaimed = 0;
3146 if (methods == &uhci_device_bulk_methods) {
3147 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last);
3149 if (methods == &uhci_device_ctrl_methods) {
3150 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
3151 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last);
3153 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last);
3156 if (methods == &uhci_device_intr_methods) {
3157 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
3162 USB_BUS_UNLOCK(udev->bus);
3168 uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3170 struct uhci_softc *sc = UHCI_BUS2SC(bus);
3173 case USB_HW_POWER_SUSPEND:
3174 case USB_HW_POWER_SHUTDOWN:
3177 case USB_HW_POWER_RESUME:
3186 uhci_set_hw_power(struct usb_bus *bus)
3188 struct uhci_softc *sc = UHCI_BUS2SC(bus);
3195 flags = bus->hw_power_state;
3198 * WARNING: Some FULL speed USB devices require periodic SOF
3199 * messages! If any USB devices are connected through the
3200 * UHCI, power save will be disabled!
3202 if (flags & (USB_HW_POWER_CONTROL |
3203 USB_HW_POWER_NON_ROOT_HUB |
3205 USB_HW_POWER_INTERRUPT |
3206 USB_HW_POWER_ISOC)) {
3207 DPRINTF("Some USB transfer is "
3208 "active on unit %u.\n",
3209 device_get_unit(sc->sc_bus.bdev));
3212 DPRINTF("Power save on unit %u.\n",
3213 device_get_unit(sc->sc_bus.bdev));
3214 UHCICMD(sc, UHCI_CMD_MAXP);
3217 USB_BUS_UNLOCK(bus);
3223 static const struct usb_bus_methods uhci_bus_methods =
3225 .endpoint_init = uhci_ep_init,
3226 .xfer_setup = uhci_xfer_setup,
3227 .xfer_unsetup = uhci_xfer_unsetup,
3228 .get_dma_delay = uhci_get_dma_delay,
3229 .device_resume = uhci_device_resume,
3230 .device_suspend = uhci_device_suspend,
3231 .set_hw_power = uhci_set_hw_power,
3232 .set_hw_power_sleep = uhci_set_hw_power_sleep,
3233 .roothub_exec = uhci_roothub_exec,
3234 .xfer_poll = uhci_do_poll,