sys/dev/usb/controller/xhci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   4  *
   5  * Copyright (c) 2010-2022 Hans Petter Selasky
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  31  *
  32  * The XHCI 1.0 spec can be found at
  33  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  34  * and the USB 3.0 spec at
  35  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  36  */
  37
  38 /*
  39  * A few words about the design implementation: This driver emulates
  40  * the concept about TDs which is found in EHCI specification. This
  41  * way we achieve that the USB controller drivers look similar to
  42  * eachother which makes it easier to understand the code.
  43  */
  44
  45 #ifdef USB_GLOBAL_INCLUDE_FILE
  46 #include USB_GLOBAL_INCLUDE_FILE
  47 #else
  48 #include <sys/stdint.h>
  49 #include <sys/stddef.h>
  50 #include <sys/param.h>
  51 #include <sys/queue.h>
  52 #include <sys/types.h>
  53 #include <sys/systm.h>
  54 #include <sys/kernel.h>
  55 #include <sys/bus.h>
  56 #include <sys/module.h>
  57 #include <sys/lock.h>
  58 #include <sys/mutex.h>
  59 #include <sys/condvar.h>
  60 #include <sys/sysctl.h>
  61 #include <sys/sx.h>
  62 #include <sys/unistd.h>
  63 #include <sys/callout.h>
  64 #include <sys/malloc.h>
  65 #include <sys/priv.h>
  66
  67 #include <dev/usb/usb.h>
  68 #include <dev/usb/usbdi.h>
  69
  70 #define USB_DEBUG_VAR xhcidebug
  71
  72 #include <dev/usb/usb_core.h>
  73 #include <dev/usb/usb_debug.h>
  74 #include <dev/usb/usb_busdma.h>
  75 #include <dev/usb/usb_process.h>
  76 #include <dev/usb/usb_transfer.h>
  77 #include <dev/usb/usb_device.h>
  78 #include <dev/usb/usb_hub.h>
  79 #include <dev/usb/usb_util.h>
  80
  81 #include <dev/usb/usb_controller.h>
  82 #include <dev/usb/usb_bus.h>
  83 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  84
  85 #include <dev/usb/controller/xhci.h>
  86 #include <dev/usb/controller/xhcireg.h>
  87
  88 #define XHCI_BUS2SC(bus) \
  89         __containerof(bus, struct xhci_softc, sc_bus)
  90
  91 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
  92     "USB XHCI");
  93
  94 static int xhcistreams;
  95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN,
  96     &xhcistreams, 0, "Set to enable streams mode support");
  97
  98 static int xhcictlquirk = 1;
  99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN,
 100     &xhcictlquirk, 0, "Set to enable control endpoint quirk");
 101
 102 static int xhcidcepquirk;
 103 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dcepquirk, CTLFLAG_RWTUN,
 104     &xhcidcepquirk, 0, "Set to disable endpoint deconfigure command");
 105
 106 #ifdef USB_DEBUG
 107 static int xhcidebug;
 108 static int xhciroute;
 109 static int xhcipolling;
 110 static int xhcidma32;
 111 static int xhcictlstep;
 112
 113 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN,
 114     &xhcidebug, 0, "Debug level");
 115 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN,
 116     &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
 117 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN,
 118     &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
 119 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
 120     &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
 121 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
 122     &xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
 123 #else
 124 #define xhciroute 0
 125 #define xhcidma32 0
 126 #define xhcictlstep 0
 127 #endif
 128
 129 #define XHCI_INTR_ENDPT 1
 130
 131 struct xhci_std_temp {
 132         struct xhci_softc       *sc;
 133         struct usb_page_cache   *pc;
 134         struct xhci_td          *td;
 135         struct xhci_td          *td_next;
 136         uint32_t                len;
 137         uint32_t                offset;
 138         uint32_t                max_packet_size;
 139         uint32_t                average;
 140         uint32_t                isoc_frame;
 141         uint16_t                isoc_delta;
 142         uint8_t                 shortpkt;
 143         uint8_t                 multishort;
 144         uint8_t                 last_frame;
 145         uint8_t                 trb_type;
 146         uint8_t                 direction;
 147         uint8_t                 tbc;
 148         uint8_t                 tlbpc;
 149         uint8_t                 step_td;
 150         uint8_t                 do_isoc_sync;
 151 };
 152
 153 static void     xhci_do_poll(struct usb_bus *);
 154 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 155 static void     xhci_root_intr(struct xhci_softc *);
 156 static void     xhci_free_device_ext(struct usb_device *);
 157 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 158                     struct usb_endpoint_descriptor *);
 159 static usb_proc_callback_t xhci_configure_msg;
 160 static usb_error_t xhci_configure_device(struct usb_device *);
 161 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 162                    struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 163                    uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
 164                    uint8_t);
 165 static usb_error_t xhci_configure_mask(struct usb_device *,
 166                     uint32_t, uint8_t);
 167 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 168                     uint64_t, uint8_t);
 169 static void xhci_endpoint_doorbell(struct usb_xfer *);
 170 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 171 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 172 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 173 #ifdef USB_DEBUG
 174 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 175 #endif
 176
 177 static const struct usb_bus_methods xhci_bus_methods;
 178
 179 #ifdef USB_DEBUG
 180 static void
 181 xhci_dump_trb(struct xhci_trb *trb)
 182 {
 183         DPRINTFN(5, "trb = %p\n", trb);
 184         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 185         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 186         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 187 }
 188
 189 static void
 190 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 191 {
 192         DPRINTFN(5, "pep = %p\n", pep);
 193         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 194         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 195         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 196         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 197         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 198         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 199         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 200 }
 201
 202 static void
 203 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 204 {
 205         DPRINTFN(5, "psl = %p\n", psl);
 206         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 207         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 208         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 209         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 210 }
 211 #endif
 212
 213 uint8_t
 214 xhci_use_polling(void)
 215 {
 216 #ifdef USB_DEBUG
 217         return (xhcipolling != 0);
 218 #else
 219         return (0);
 220 #endif
 221 }
 222
 223 static void
 224 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 225 {
 226         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 227         uint16_t i;
 228
 229         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 230            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 231
 232         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 233            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 234
 235         for (i = 0; i != sc->sc_noscratch; i++) {
 236                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 237                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 238         }
 239 }
 240
 241 static void
 242 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 243 {
 244         if (sc->sc_ctx_is_64_byte) {
 245                 uint32_t offset;
 246                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 247                 /* all contexts are initially 32-bytes */
 248                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 249                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 250         }
 251         *ptr = htole32(val);
 252 }
 253
 254 static uint32_t
 255 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 256 {
 257         if (sc->sc_ctx_is_64_byte) {
 258                 uint32_t offset;
 259                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 260                 /* all contexts are initially 32-bytes */
 261                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 262                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 263         }
 264         return (le32toh(*ptr));
 265 }
 266
 267 static void
 268 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 269 {
 270         if (sc->sc_ctx_is_64_byte) {
 271                 uint32_t offset;
 272                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 273                 /* all contexts are initially 32-bytes */
 274                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 275                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 276         }
 277         *ptr = htole64(val);
 278 }
 279
 280 #ifdef USB_DEBUG
 281 static uint64_t
 282 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 283 {
 284         if (sc->sc_ctx_is_64_byte) {
 285                 uint32_t offset;
 286                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 287                 /* all contexts are initially 32-bytes */
 288                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 289                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 290         }
 291         return (le64toh(*ptr));
 292 }
 293 #endif
 294
 295 static int
 296 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 297 {
 298         struct usb_page_search buf_res;
 299         struct xhci_hw_root *phwr;
 300         uint64_t addr;
 301         uint32_t temp;
 302
 303         DPRINTF("\n");
 304
 305         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 306         if (temp & XHCI_CRCR_LO_CRR) {
 307                 DPRINTF("Command ring running\n");
 308                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 309
 310                 /*
 311                  * Try to abort the last command as per section
 312                  * 4.6.1.2 "Aborting a Command" of the XHCI
 313                  * specification:
 314                  */
 315
 316                 /* stop and cancel */
 317                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 318                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 319
 320                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 321                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 322
 323                 /* wait 250ms */
 324                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 325
 326                 /* check if command ring is still running */
 327                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 328                 if (temp & XHCI_CRCR_LO_CRR) {
 329                         DPRINTF("Comand ring still running\n");
 330                         return (USB_ERR_IOERROR);
 331                 }
 332         }
 333
 334         /* reset command ring */
 335         sc->sc_command_ccs = 1;
 336         sc->sc_command_idx = 0;
 337
 338         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 339
 340         /* set up command ring control base address */
 341         addr = buf_res.physaddr;
 342         phwr = buf_res.buffer;
 343         addr += __offsetof(struct xhci_hw_root, hwr_commands[0]);
 344
 345         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 346
 347         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 348         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 349
 350         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 351
 352         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 353         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 354
 355         return (0);
 356 }
 357
 358 usb_error_t
 359 xhci_start_controller(struct xhci_softc *sc)
 360 {
 361         struct usb_page_search buf_res;
 362         struct xhci_hw_root *phwr;
 363         struct xhci_dev_ctx_addr *pdctxa;
 364         usb_error_t err;
 365         uint64_t addr;
 366         uint32_t temp;
 367         uint16_t i;
 368
 369         DPRINTF("\n");
 370
 371         sc->sc_event_ccs = 1;
 372         sc->sc_event_idx = 0;
 373         sc->sc_command_ccs = 1;
 374         sc->sc_command_idx = 0;
 375
 376         err = xhci_reset_controller(sc);
 377         if (err)
 378                 return (err);
 379
 380         /* set up number of device slots */
 381         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 382             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 383
 384         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 385
 386         temp = XREAD4(sc, oper, XHCI_USBSTS);
 387
 388         /* clear interrupts */
 389         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 390         /* disable all device notifications */
 391         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 392
 393         /* set up device context base address */
 394         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 395         pdctxa = buf_res.buffer;
 396         memset(pdctxa, 0, sizeof(*pdctxa));
 397
 398         addr = buf_res.physaddr;
 399         addr += __offsetof(struct xhci_dev_ctx_addr, qwSpBufPtr[0]);
 400
 401         /* slot 0 points to the table of scratchpad pointers */
 402         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 403
 404         for (i = 0; i != sc->sc_noscratch; i++) {
 405                 struct usb_page_search buf_scp;
 406                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 407                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 408         }
 409
 410         addr = buf_res.physaddr;
 411
 412         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 413         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 414         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 415         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 416
 417         /* set up event table size */
 418         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 419             XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
 420
 421         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
 422
 423         /* set up interrupt rate */
 424         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 425
 426         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 427
 428         phwr = buf_res.buffer;
 429         addr = buf_res.physaddr;
 430         addr += __offsetof(struct xhci_hw_root, hwr_events[0]);
 431
 432         /* reset hardware root structure */
 433         memset(phwr, 0, sizeof(*phwr));
 434
 435         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 436         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 437
 438         /*
 439          * PR 237666:
 440          *
 441          * According to the XHCI specification, the XWRITE4's to
 442          * XHCI_ERSTBA_LO and _HI lead to the XHCI to copy the
 443          * qwEvrsTablePtr and dwEvrsTableSize values above at that
 444          * time, as the XHCI initializes its event ring support. This
 445          * is before the event ring starts to pay attention to the
 446          * RUN/STOP bit. Thus, make sure the values are observable to
 447          * the XHCI before that point.
 448          */
 449         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 450
 451         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 452
 453         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 454         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 455
 456         addr = buf_res.physaddr;
 457
 458         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 459
 460         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 461         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 462
 463         /* set up interrupter registers */
 464         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 465         temp |= XHCI_IMAN_INTR_ENA;
 466         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 467
 468         /* set up command ring control base address */
 469         addr = buf_res.physaddr;
 470         addr += __offsetof(struct xhci_hw_root, hwr_commands[0]);
 471
 472         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 473
 474         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 475         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 476
 477         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 478
 479         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 480
 481         /* Go! */
 482         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 483             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 484
 485         for (i = 0; i != 100; i++) {
 486                 usb_pause_mtx(NULL, hz / 100);
 487                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 488                 if (!temp)
 489                         break;
 490         }
 491         if (temp) {
 492                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 493                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 494                 return (USB_ERR_IOERROR);
 495         }
 496
 497         /* catch any lost interrupts */
 498         xhci_do_poll(&sc->sc_bus);
 499
 500         if (sc->sc_port_route != NULL) {
 501                 /* Route all ports to the XHCI by default */
 502                 sc->sc_port_route(sc->sc_bus.parent,
 503                     ~xhciroute, xhciroute);
 504         }
 505         return (0);
 506 }
 507
 508 usb_error_t
 509 xhci_halt_controller(struct xhci_softc *sc)
 510 {
 511         uint32_t temp;
 512         uint16_t i;
 513
 514         DPRINTF("\n");
 515
 516         sc->sc_capa_off = 0;
 517         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 518         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 519         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 520
 521         /* Halt controller */
 522         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 523
 524         for (i = 0; i != 100; i++) {
 525                 usb_pause_mtx(NULL, hz / 100);
 526                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 527                 if (temp)
 528                         break;
 529         }
 530
 531         if (!temp) {
 532                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 533                 return (USB_ERR_IOERROR);
 534         }
 535         return (0);
 536 }
 537
 538 usb_error_t
 539 xhci_reset_controller(struct xhci_softc *sc)
 540 {
 541         uint32_t temp = 0;
 542         uint16_t i;
 543
 544         DPRINTF("\n");
 545
 546         /* Reset controller */
 547         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 548
 549         for (i = 0; i != 100; i++) {
 550                 usb_pause_mtx(NULL, hz / 100);
 551                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 552                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 553                 if (!temp)
 554                         break;
 555         }
 556
 557         if (temp) {
 558                 device_printf(sc->sc_bus.parent, "Controller "
 559                     "reset timeout.\n");
 560                 return (USB_ERR_IOERROR);
 561         }
 562         return (0);
 563 }
 564
 565 usb_error_t
 566 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
 567 {
 568         uint32_t temp;
 569
 570         DPRINTF("\n");
 571
 572         /* initialize some bus fields */
 573         sc->sc_bus.parent = self;
 574
 575         /* set the bus revision */
 576         sc->sc_bus.usbrev = USB_REV_3_0;
 577
 578         /* set up the bus struct */
 579         sc->sc_bus.methods = &xhci_bus_methods;
 580
 581         /* set up devices array */
 582         sc->sc_bus.devices = sc->sc_devices;
 583         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 584
 585         /* set default cycle state in case of early interrupts */
 586         sc->sc_event_ccs = 1;
 587         sc->sc_command_ccs = 1;
 588
 589         /* set up bus space offsets */
 590         sc->sc_capa_off = 0;
 591         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 592         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 593         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 594
 595         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 596         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 597         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 598
 599         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 600
 601         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 602                 device_printf(sc->sc_bus.parent, "Controller does "
 603                     "not support 4K page size.\n");
 604                 return (ENXIO);
 605         }
 606
 607         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 608
 609         DPRINTF("HCS0 = 0x%08x\n", temp);
 610
 611         /* set up context size */
 612         if (XHCI_HCS0_CSZ(temp)) {
 613                 sc->sc_ctx_is_64_byte = 1;
 614         } else {
 615                 sc->sc_ctx_is_64_byte = 0;
 616         }
 617
 618         /* get DMA bits */
 619         sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
 620             xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
 621
 622         device_printf(self, "%d bytes context size, %d-bit DMA\n",
 623             sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
 624
 625         /* enable 64Kbyte control endpoint quirk */
 626         sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0);
 627
 628         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 629
 630         /* get number of device slots */
 631         sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
 632
 633         if (sc->sc_noport == 0) {
 634                 device_printf(sc->sc_bus.parent, "Invalid number "
 635                     "of ports: %u\n", sc->sc_noport);
 636                 return (ENXIO);
 637         }
 638
 639         sc->sc_noport = sc->sc_noport;
 640         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 641
 642         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 643
 644         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 645                 sc->sc_noslot = XHCI_MAX_DEVICES;
 646
 647         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 648
 649         DPRINTF("HCS2=0x%08x\n", temp);
 650
 651         /* get isochronous scheduling threshold */
 652         sc->sc_ist = XHCI_HCS2_IST(temp);
 653
 654         /* get number of scratchpads */
 655         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 656
 657         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 658                 device_printf(sc->sc_bus.parent, "XHCI request "
 659                     "too many scratchpads\n");
 660                 return (ENOMEM);
 661         }
 662
 663         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 664
 665         /* get event table size */
 666         sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
 667         if (sc->sc_erst_max > XHCI_MAX_RSEG)
 668                 sc->sc_erst_max = XHCI_MAX_RSEG;
 669
 670         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 671
 672         /* get maximum exit latency */
 673         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 674             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 675
 676         /* Check if we should use the default IMOD value. */
 677         if (sc->sc_imod_default == 0)
 678                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 679
 680         /* get all DMA memory */
 681         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 682             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 683                 return (ENOMEM);
 684         }
 685
 686         /* set up command queue mutex and condition varible */
 687         cv_init(&sc->sc_cmd_cv, "CMDQ");
 688         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 689
 690         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 691         sc->sc_config_msg[0].bus = &sc->sc_bus;
 692         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 693         sc->sc_config_msg[1].bus = &sc->sc_bus;
 694
 695         return (0);
 696 }
 697
 698 void
 699 xhci_uninit(struct xhci_softc *sc)
 700 {
 701         /*
 702          * NOTE: At this point the control transfer process is gone
 703          * and "xhci_configure_msg" is no longer called. Consequently
 704          * waiting for the configuration messages to complete is not
 705          * needed.
 706          */
 707         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 708
 709         cv_destroy(&sc->sc_cmd_cv);
 710         sx_destroy(&sc->sc_cmd_sx);
 711 }
 712
 713 static void
 714 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 715 {
 716         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 717
 718         switch (state) {
 719         case USB_HW_POWER_SUSPEND:
 720                 DPRINTF("Stopping the XHCI\n");
 721                 xhci_halt_controller(sc);
 722                 xhci_reset_controller(sc);
 723                 break;
 724         case USB_HW_POWER_SHUTDOWN:
 725                 DPRINTF("Stopping the XHCI\n");
 726                 xhci_halt_controller(sc);
 727                 xhci_reset_controller(sc);
 728                 break;
 729         case USB_HW_POWER_RESUME:
 730                 DPRINTF("Starting the XHCI\n");
 731                 xhci_start_controller(sc);
 732                 break;
 733         default:
 734                 break;
 735         }
 736 }
 737
 738 static usb_error_t
 739 xhci_generic_done_sub(struct usb_xfer *xfer)
 740 {
 741         struct xhci_td *td;
 742         struct xhci_td *td_alt_next;
 743         uint32_t len;
 744         uint8_t status;
 745
 746         td = xfer->td_transfer_cache;
 747         td_alt_next = td->alt_next;
 748
 749         if (xfer->aframes != xfer->nframes)
 750                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 751
 752         while (1) {
 753                 usb_pc_cpu_invalidate(td->page_cache);
 754
 755                 status = td->status;
 756                 len = td->remainder;
 757
 758                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 759                     xfer, (unsigned int)xfer->aframes,
 760                     (unsigned int)xfer->nframes,
 761                     (unsigned int)len, (unsigned int)td->len,
 762                     (unsigned int)status);
 763
 764                 /*
 765                  * Verify the status length and
 766                  * add the length to "frlengths[]":
 767                  */
 768                 if (len > td->len) {
 769                         /* should not happen */
 770                         DPRINTF("Invalid status length, "
 771                             "0x%04x/0x%04x bytes\n", len, td->len);
 772                         status = XHCI_TRB_ERROR_LENGTH;
 773                 } else if (xfer->aframes != xfer->nframes) {
 774                         xfer->frlengths[xfer->aframes] += td->len - len;
 775                 }
 776                 /* Check for last transfer */
 777                 if (((void *)td) == xfer->td_transfer_last) {
 778                         td = NULL;
 779                         break;
 780                 }
 781                 /* Check for transfer error */
 782                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 783                     status != XHCI_TRB_ERROR_SUCCESS) {
 784                         /* the transfer is finished */
 785                         td = NULL;
 786                         break;
 787                 }
 788                 /* Check for short transfer */
 789                 if (len > 0) {
 790                         if (xfer->flags_int.short_frames_ok ||
 791                             xfer->flags_int.isochronous_xfr ||
 792                             xfer->flags_int.control_xfr) {
 793                                 /* follow alt next */
 794                                 td = td->alt_next;
 795                         } else {
 796                                 /* the transfer is finished */
 797                                 td = NULL;
 798                         }
 799                         break;
 800                 }
 801                 td = td->obj_next;
 802
 803                 if (td->alt_next != td_alt_next) {
 804                         /* this USB frame is complete */
 805                         break;
 806                 }
 807         }
 808
 809         /* update transfer cache */
 810
 811         xfer->td_transfer_cache = td;
 812
 813         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 814             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 815             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 816             USB_ERR_NORMAL_COMPLETION);
 817 }
 818
 819 static void
 820 xhci_generic_done(struct usb_xfer *xfer)
 821 {
 822         usb_error_t err = 0;
 823
 824         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 825             xfer, xfer->endpoint);
 826
 827         /* reset scanner */
 828
 829         xfer->td_transfer_cache = xfer->td_transfer_first;
 830
 831         if (xfer->flags_int.control_xfr) {
 832                 if (xfer->flags_int.control_hdr)
 833                         err = xhci_generic_done_sub(xfer);
 834
 835                 xfer->aframes = 1;
 836
 837                 if (xfer->td_transfer_cache == NULL)
 838                         goto done;
 839         }
 840
 841         while (xfer->aframes != xfer->nframes) {
 842                 err = xhci_generic_done_sub(xfer);
 843                 xfer->aframes++;
 844
 845                 if (xfer->td_transfer_cache == NULL)
 846                         goto done;
 847         }
 848
 849         if (xfer->flags_int.control_xfr &&
 850             !xfer->flags_int.control_act)
 851                 err = xhci_generic_done_sub(xfer);
 852 done:
 853         /* transfer is complete */
 854         xhci_device_done(xfer, err);
 855 }
 856
 857 static void
 858 xhci_activate_transfer(struct usb_xfer *xfer)
 859 {
 860         struct xhci_td *td;
 861
 862         td = xfer->td_transfer_cache;
 863
 864         usb_pc_cpu_invalidate(td->page_cache);
 865
 866         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 867                 /* activate the transfer */
 868
 869                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 870                 usb_pc_cpu_flush(td->page_cache);
 871
 872                 xhci_endpoint_doorbell(xfer);
 873         }
 874 }
 875
 876 static void
 877 xhci_skip_transfer(struct usb_xfer *xfer)
 878 {
 879         struct xhci_td *td;
 880         struct xhci_td *td_last;
 881
 882         td = xfer->td_transfer_cache;
 883         td_last = xfer->td_transfer_last;
 884
 885         td = td->alt_next;
 886
 887         usb_pc_cpu_invalidate(td->page_cache);
 888
 889         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 890                 usb_pc_cpu_invalidate(td_last->page_cache);
 891
 892                 /* copy LINK TRB to current waiting location */
 893
 894                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 895                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 896                 usb_pc_cpu_flush(td->page_cache);
 897
 898                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 899                 usb_pc_cpu_flush(td->page_cache);
 900
 901                 xhci_endpoint_doorbell(xfer);
 902         }
 903 }
 904
 905 /*------------------------------------------------------------------------*
 906  *      xhci_check_transfer
 907  *------------------------------------------------------------------------*/
 908 static void
 909 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 910 {
 911         struct xhci_endpoint_ext *pepext;
 912         int64_t offset;
 913         uint64_t td_event;
 914         uint32_t temp;
 915         uint32_t remainder;
 916         uint16_t stream_id = 0;
 917         uint16_t i;
 918         uint8_t status;
 919         uint8_t halted;
 920         uint8_t epno;
 921         uint8_t index;
 922
 923         /* decode TRB */
 924         td_event = le64toh(trb->qwTrb0);
 925         temp = le32toh(trb->dwTrb2);
 926
 927         remainder = XHCI_TRB_2_REM_GET(temp);
 928         status = XHCI_TRB_2_ERROR_GET(temp);
 929
 930         temp = le32toh(trb->dwTrb3);
 931         epno = XHCI_TRB_3_EP_GET(temp);
 932         index = XHCI_TRB_3_SLOT_GET(temp);
 933
 934         /* check if error means halted */
 935         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 936             status != XHCI_TRB_ERROR_SUCCESS);
 937
 938         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 939             index, epno, remainder, status);
 940
 941         if (index > sc->sc_noslot) {
 942                 DPRINTF("Invalid slot.\n");
 943                 return;
 944         }
 945
 946         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 947                 DPRINTF("Invalid endpoint.\n");
 948                 return;
 949         }
 950
 951         pepext = &sc->sc_hw.devs[index].endp[epno];
 952
 953         /* try to find the USB transfer that generated the event */
 954         for (i = 0;; i++) {
 955                 struct usb_xfer *xfer;
 956                 struct xhci_td *td;
 957
 958                 if (i == (XHCI_MAX_TRANSFERS - 1)) {
 959                         if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS ||
 960                             stream_id == (XHCI_MAX_STREAMS - 1))
 961                                 break;
 962                         stream_id++;
 963                         i = 0;
 964                         DPRINTFN(5, "stream_id=%u\n", stream_id);
 965                 }
 966
 967                 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
 968                 if (xfer == NULL)
 969                         continue;
 970
 971                 td = xfer->td_transfer_cache;
 972
 973                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 974                         (long long)td_event,
 975                         (long long)td->td_self,
 976                         (long long)td->td_self + sizeof(td->td_trb));
 977
 978                 /*
 979                  * NOTE: Some XHCI implementations might not trigger
 980                  * an event on the last LINK TRB so we need to
 981                  * consider both the last and second last event
 982                  * address as conditions for a successful transfer.
 983                  *
 984                  * NOTE: We assume that the XHCI will only trigger one
 985                  * event per chain of TRBs.
 986                  */
 987
 988                 offset = td_event - td->td_self;
 989
 990                 if (offset >= 0 &&
 991                     offset < (int64_t)sizeof(td->td_trb)) {
 992                         usb_pc_cpu_invalidate(td->page_cache);
 993
 994                         /* compute rest of remainder, if any */
 995                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 996                                 temp = le32toh(td->td_trb[i].dwTrb2);
 997                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 998                         }
 999
1000                         DPRINTFN(5, "New remainder: %u\n", remainder);
1001
1002                         /* clear isochronous transfer errors */
1003                         if (xfer->flags_int.isochronous_xfr) {
1004                                 if (halted) {
1005                                         halted = 0;
1006                                         status = XHCI_TRB_ERROR_SUCCESS;
1007                                         remainder = td->len;
1008                                 }
1009                         }
1010
1011                         /* "td->remainder" is verified later */
1012                         td->remainder = remainder;
1013                         td->status = status;
1014
1015                         usb_pc_cpu_flush(td->page_cache);
1016
1017                         /*
1018                          * 1) Last transfer descriptor makes the
1019                          * transfer done
1020                          */
1021                         if (((void *)td) == xfer->td_transfer_last) {
1022                                 DPRINTF("TD is last\n");
1023                                 xhci_generic_done(xfer);
1024                                 break;
1025                         }
1026
1027                         /*
1028                          * 2) Any kind of error makes the transfer
1029                          * done
1030                          */
1031                         if (halted) {
1032                                 DPRINTF("TD has I/O error\n");
1033                                 xhci_generic_done(xfer);
1034                                 break;
1035                         }
1036
1037                         /*
1038                          * 3) If there is no alternate next transfer,
1039                          * a short packet also makes the transfer done
1040                          */
1041                         if (td->remainder > 0) {
1042                                 if (td->alt_next == NULL) {
1043                                         DPRINTF(
1044                                             "short TD has no alternate next\n");
1045                                         xhci_generic_done(xfer);
1046                                         break;
1047                                 }
1048                                 DPRINTF("TD has short pkt\n");
1049                                 if (xfer->flags_int.short_frames_ok ||
1050                                     xfer->flags_int.isochronous_xfr ||
1051                                     xfer->flags_int.control_xfr) {
1052                                         /* follow the alt next */
1053                                         xfer->td_transfer_cache = td->alt_next;
1054                                         xhci_activate_transfer(xfer);
1055                                         break;
1056                                 }
1057                                 xhci_skip_transfer(xfer);
1058                                 xhci_generic_done(xfer);
1059                                 break;
1060                         }
1061
1062                         /*
1063                          * 4) Transfer complete - go to next TD
1064                          */
1065                         DPRINTF("Following next TD\n");
1066                         xfer->td_transfer_cache = td->obj_next;
1067                         xhci_activate_transfer(xfer);
1068                         break;          /* there should only be one match */
1069                 }
1070         }
1071 }
1072
1073 static int
1074 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1075 {
1076         if (sc->sc_cmd_addr == trb->qwTrb0) {
1077                 DPRINTF("Received command event\n");
1078                 sc->sc_cmd_result[0] = trb->dwTrb2;
1079                 sc->sc_cmd_result[1] = trb->dwTrb3;
1080                 cv_signal(&sc->sc_cmd_cv);
1081                 return (1);     /* command match */
1082         }
1083         return (0);
1084 }
1085
1086 static int
1087 xhci_interrupt_poll(struct xhci_softc *sc)
1088 {
1089         struct usb_page_search buf_res;
1090         struct xhci_hw_root *phwr;
1091         uint64_t addr;
1092         uint32_t temp;
1093         int retval = 0;
1094         uint16_t i;
1095         uint8_t event;
1096         uint8_t j;
1097         uint8_t k;
1098         uint8_t t;
1099
1100         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1101
1102         phwr = buf_res.buffer;
1103
1104         /* Receive any events */
1105
1106         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1107
1108         i = sc->sc_event_idx;
1109         j = sc->sc_event_ccs;
1110         t = 2;
1111
1112         while (1) {
1113                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1114
1115                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1116
1117                 if (j != k)
1118                         break;
1119
1120                 event = XHCI_TRB_3_TYPE_GET(temp);
1121
1122                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1123                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1124                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1125                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1126
1127                 switch (event) {
1128                 case XHCI_TRB_EVENT_TRANSFER:
1129                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1130                         break;
1131                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1132                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1133                         break;
1134                 default:
1135                         DPRINTF("Unhandled event = %u\n", event);
1136                         break;
1137                 }
1138
1139                 i++;
1140
1141                 if (i == XHCI_MAX_EVENTS) {
1142                         i = 0;
1143                         j ^= 1;
1144
1145                         /* check for timeout */
1146                         if (!--t)
1147                                 break;
1148                 }
1149         }
1150
1151         sc->sc_event_idx = i;
1152         sc->sc_event_ccs = j;
1153
1154         /*
1155          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1156          * latched. That means to activate the register we need to
1157          * write both the low and high double word of the 64-bit
1158          * register.
1159          */
1160
1161         addr = buf_res.physaddr;
1162         addr += __offsetof(struct xhci_hw_root, hwr_events[i]);
1163
1164         /* try to clear busy bit */
1165         addr |= XHCI_ERDP_LO_BUSY;
1166
1167         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1168         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1169
1170         return (retval);
1171 }
1172
1173 static usb_error_t
1174 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1175     uint16_t timeout_ms)
1176 {
1177         struct usb_page_search buf_res;
1178         struct xhci_hw_root *phwr;
1179         uint64_t addr;
1180         uint32_t temp;
1181         uint8_t i;
1182         uint8_t j;
1183         uint8_t timeout = 0;
1184         int err;
1185
1186         XHCI_CMD_ASSERT_LOCKED(sc);
1187
1188         /* get hardware root structure */
1189
1190         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1191
1192         phwr = buf_res.buffer;
1193
1194         /* Queue command */
1195
1196         USB_BUS_LOCK(&sc->sc_bus);
1197 retry:
1198         i = sc->sc_command_idx;
1199         j = sc->sc_command_ccs;
1200
1201         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1202             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1203             (long long)le64toh(trb->qwTrb0),
1204             (long)le32toh(trb->dwTrb2),
1205             (long)le32toh(trb->dwTrb3));
1206
1207         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1208         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1209
1210         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1211
1212         temp = trb->dwTrb3;
1213
1214         if (j)
1215                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1216         else
1217                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1218
1219         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1220
1221         phwr->hwr_commands[i].dwTrb3 = temp;
1222
1223         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1224
1225         addr = buf_res.physaddr;
1226         addr += __offsetof(struct xhci_hw_root, hwr_commands[i]);
1227
1228         sc->sc_cmd_addr = htole64(addr);
1229
1230         i++;
1231
1232         if (i == (XHCI_MAX_COMMANDS - 1)) {
1233                 if (j) {
1234                         temp = htole32(XHCI_TRB_3_TC_BIT |
1235                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1236                             XHCI_TRB_3_CYCLE_BIT);
1237                 } else {
1238                         temp = htole32(XHCI_TRB_3_TC_BIT |
1239                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1240                 }
1241
1242                 phwr->hwr_commands[i].dwTrb3 = temp;
1243
1244                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1245
1246                 i = 0;
1247                 j ^= 1;
1248         }
1249
1250         sc->sc_command_idx = i;
1251         sc->sc_command_ccs = j;
1252
1253         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1254
1255         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1256             USB_MS_TO_TICKS(timeout_ms));
1257
1258         /*
1259          * In some error cases event interrupts are not generated.
1260          * Poll one time to see if the command has completed.
1261          */
1262         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1263                 DPRINTF("Command was completed when polling\n");
1264                 err = 0;
1265         }
1266         if (err != 0) {
1267                 DPRINTF("Command timeout!\n");
1268                 /*
1269                  * After some weeks of continuous operation, it has
1270                  * been observed that the ASMedia Technology, ASM1042
1271                  * SuperSpeed USB Host Controller can suddenly stop
1272                  * accepting commands via the command queue. Try to
1273                  * first reset the command queue. If that fails do a
1274                  * host controller reset.
1275                  */
1276                 if (timeout == 0 &&
1277                     xhci_reset_command_queue_locked(sc) == 0) {
1278                         temp = le32toh(trb->dwTrb3);
1279
1280                         /*
1281                          * Avoid infinite XHCI reset loops if the set
1282                          * address command fails to respond due to a
1283                          * non-enumerating device:
1284                          */
1285                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1286                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1287                                 DPRINTF("Set address timeout\n");
1288                         } else {
1289                                 timeout = 1;
1290                                 goto retry;
1291                         }
1292                 } else {
1293                         DPRINTF("Controller reset!\n");
1294                         usb_bus_reset_async_locked(&sc->sc_bus);
1295                 }
1296                 err = USB_ERR_TIMEOUT;
1297                 trb->dwTrb2 = 0;
1298                 trb->dwTrb3 = 0;
1299         } else {
1300                 temp = le32toh(sc->sc_cmd_result[0]);
1301                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1302                         err = USB_ERR_IOERROR;
1303
1304                 trb->dwTrb2 = sc->sc_cmd_result[0];
1305                 trb->dwTrb3 = sc->sc_cmd_result[1];
1306         }
1307
1308         USB_BUS_UNLOCK(&sc->sc_bus);
1309
1310         return (err);
1311 }
1312
1313 #if 0
1314 static usb_error_t
1315 xhci_cmd_nop(struct xhci_softc *sc)
1316 {
1317         struct xhci_trb trb;
1318         uint32_t temp;
1319
1320         DPRINTF("\n");
1321
1322         trb.qwTrb0 = 0;
1323         trb.dwTrb2 = 0;
1324         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1325
1326         trb.dwTrb3 = htole32(temp);
1327
1328         return (xhci_do_command(sc, &trb, 100 /* ms */));
1329 }
1330 #endif
1331
1332 static usb_error_t
1333 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1334 {
1335         struct xhci_trb trb;
1336         uint32_t temp;
1337         usb_error_t err;
1338
1339         DPRINTF("\n");
1340
1341         trb.qwTrb0 = 0;
1342         trb.dwTrb2 = 0;
1343         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1344
1345         err = xhci_do_command(sc, &trb, 100 /* ms */);
1346         if (err)
1347                 goto done;
1348
1349         temp = le32toh(trb.dwTrb3);
1350
1351         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1352
1353 done:
1354         return (err);
1355 }
1356
1357 static usb_error_t
1358 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1359 {
1360         struct xhci_trb trb;
1361         uint32_t temp;
1362
1363         DPRINTF("\n");
1364
1365         trb.qwTrb0 = 0;
1366         trb.dwTrb2 = 0;
1367         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1368             XHCI_TRB_3_SLOT_SET(slot_id);
1369
1370         trb.dwTrb3 = htole32(temp);
1371
1372         return (xhci_do_command(sc, &trb, 100 /* ms */));
1373 }
1374
1375 static usb_error_t
1376 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1377     uint8_t bsr, uint8_t slot_id)
1378 {
1379         struct xhci_trb trb;
1380         uint32_t temp;
1381
1382         DPRINTF("\n");
1383
1384         trb.qwTrb0 = htole64(input_ctx);
1385         trb.dwTrb2 = 0;
1386         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1387             XHCI_TRB_3_SLOT_SET(slot_id);
1388
1389         if (bsr)
1390                 temp |= XHCI_TRB_3_BSR_BIT;
1391
1392         trb.dwTrb3 = htole32(temp);
1393
1394         return (xhci_do_command(sc, &trb, 500 /* ms */));
1395 }
1396
1397 static usb_error_t
1398 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1399 {
1400         struct usb_page_search buf_inp;
1401         struct usb_page_search buf_dev;
1402         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1403         struct xhci_hw_dev *hdev;
1404         struct xhci_dev_ctx *pdev;
1405         struct xhci_endpoint_ext *pepext;
1406         uint32_t temp;
1407         uint16_t mps;
1408         usb_error_t err;
1409         uint8_t index;
1410
1411         /* the root HUB case is not handled here */
1412         if (udev->parent_hub == NULL)
1413                 return (USB_ERR_INVAL);
1414
1415         index = udev->controller_slot_id;
1416
1417         hdev =  &sc->sc_hw.devs[index];
1418
1419         if (mtx != NULL)
1420                 mtx_unlock(mtx);
1421
1422         XHCI_CMD_LOCK(sc);
1423
1424         switch (hdev->state) {
1425         case XHCI_ST_DEFAULT:
1426         case XHCI_ST_ENABLED:
1427
1428                 hdev->state = XHCI_ST_ENABLED;
1429
1430                 /* set configure mask to slot and EP0 */
1431                 xhci_configure_mask(udev, 3, 0);
1432
1433                 /* configure input slot context structure */
1434                 err = xhci_configure_device(udev);
1435
1436                 if (err != 0) {
1437                         DPRINTF("Could not configure device\n");
1438                         break;
1439                 }
1440
1441                 /* configure input endpoint context structure */
1442                 switch (udev->speed) {
1443                 case USB_SPEED_LOW:
1444                 case USB_SPEED_FULL:
1445                         mps = 8;
1446                         break;
1447                 case USB_SPEED_HIGH:
1448                         mps = 64;
1449                         break;
1450                 default:
1451                         mps = 512;
1452                         break;
1453                 }
1454
1455                 pepext = xhci_get_endpoint_ext(udev,
1456                     &udev->ctrl_ep_desc);
1457
1458                 /* ensure the control endpoint is setup again */
1459                 USB_BUS_LOCK(udev->bus);
1460                 pepext->trb_halted = 1;
1461                 pepext->trb_running = 0;
1462                 USB_BUS_UNLOCK(udev->bus);
1463
1464                 err = xhci_configure_endpoint(udev,
1465                     &udev->ctrl_ep_desc, pepext,
1466                     0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1467
1468                 if (err != 0) {
1469                         DPRINTF("Could not configure default endpoint\n");
1470                         break;
1471                 }
1472
1473                 /* execute set address command */
1474                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1475
1476                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1477                     (address == 0), index);
1478
1479                 if (err != 0) {
1480                         temp = le32toh(sc->sc_cmd_result[0]);
1481                         if (address == 0 && sc->sc_port_route != NULL &&
1482                             XHCI_TRB_2_ERROR_GET(temp) ==
1483                             XHCI_TRB_ERROR_PARAMETER) {
1484                                 /* LynxPoint XHCI - ports are not switchable */
1485                                 /* Un-route all ports from the XHCI */
1486                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1487                         }
1488                         DPRINTF("Could not set address "
1489                             "for slot %u.\n", index);
1490                         if (address != 0)
1491                                 break;
1492                 }
1493
1494                 /* update device address to new value */
1495
1496                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1497                 pdev = buf_dev.buffer;
1498                 usb_pc_cpu_invalidate(&hdev->device_pc);
1499
1500                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1501                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1502
1503                 /* update device state to new value */
1504
1505                 if (address != 0)
1506                         hdev->state = XHCI_ST_ADDRESSED;
1507                 else
1508                         hdev->state = XHCI_ST_DEFAULT;
1509                 break;
1510
1511         default:
1512                 DPRINTF("Wrong state for set address.\n");
1513                 err = USB_ERR_IOERROR;
1514                 break;
1515         }
1516         XHCI_CMD_UNLOCK(sc);
1517
1518         if (mtx != NULL)
1519                 mtx_lock(mtx);
1520
1521         return (err);
1522 }
1523
1524 static usb_error_t
1525 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1526     uint8_t deconfigure, uint8_t slot_id)
1527 {
1528         struct xhci_trb trb;
1529         uint32_t temp;
1530
1531         DPRINTF("\n");
1532
1533         trb.qwTrb0 = htole64(input_ctx);
1534         trb.dwTrb2 = 0;
1535         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1536             XHCI_TRB_3_SLOT_SET(slot_id);
1537
1538         if (deconfigure) {
1539                 if (sc->sc_no_deconfigure != 0 || xhcidcepquirk != 0)
1540                         return (0);     /* Success */
1541                 temp |= XHCI_TRB_3_DCEP_BIT;
1542         }
1543
1544         trb.dwTrb3 = htole32(temp);
1545
1546         return (xhci_do_command(sc, &trb, 100 /* ms */));
1547 }
1548
1549 static usb_error_t
1550 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1551     uint8_t slot_id)
1552 {
1553         struct xhci_trb trb;
1554         uint32_t temp;
1555
1556         DPRINTF("\n");
1557
1558         trb.qwTrb0 = htole64(input_ctx);
1559         trb.dwTrb2 = 0;
1560         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1561             XHCI_TRB_3_SLOT_SET(slot_id);
1562         trb.dwTrb3 = htole32(temp);
1563
1564         return (xhci_do_command(sc, &trb, 100 /* ms */));
1565 }
1566
1567 static usb_error_t
1568 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1569     uint8_t ep_id, uint8_t slot_id)
1570 {
1571         struct xhci_trb trb;
1572         uint32_t temp;
1573
1574         DPRINTF("\n");
1575
1576         trb.qwTrb0 = 0;
1577         trb.dwTrb2 = 0;
1578         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1579             XHCI_TRB_3_SLOT_SET(slot_id) |
1580             XHCI_TRB_3_EP_SET(ep_id);
1581
1582         if (preserve)
1583                 temp |= XHCI_TRB_3_PRSV_BIT;
1584
1585         trb.dwTrb3 = htole32(temp);
1586
1587         return (xhci_do_command(sc, &trb, 100 /* ms */));
1588 }
1589
1590 static usb_error_t
1591 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1592     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1593 {
1594         struct xhci_trb trb;
1595         uint32_t temp;
1596
1597         DPRINTF("\n");
1598
1599         trb.qwTrb0 = htole64(dequeue_ptr);
1600
1601         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1602         trb.dwTrb2 = htole32(temp);
1603
1604         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1605             XHCI_TRB_3_SLOT_SET(slot_id) |
1606             XHCI_TRB_3_EP_SET(ep_id);
1607         trb.dwTrb3 = htole32(temp);
1608
1609         return (xhci_do_command(sc, &trb, 100 /* ms */));
1610 }
1611
1612 static usb_error_t
1613 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1614     uint8_t ep_id, uint8_t slot_id)
1615 {
1616         struct xhci_trb trb;
1617         uint32_t temp;
1618
1619         DPRINTF("\n");
1620
1621         trb.qwTrb0 = 0;
1622         trb.dwTrb2 = 0;
1623         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1624             XHCI_TRB_3_SLOT_SET(slot_id) |
1625             XHCI_TRB_3_EP_SET(ep_id);
1626
1627         if (suspend)
1628                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1629
1630         trb.dwTrb3 = htole32(temp);
1631
1632         return (xhci_do_command(sc, &trb, 100 /* ms */));
1633 }
1634
1635 static usb_error_t
1636 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1637 {
1638         struct xhci_trb trb;
1639         uint32_t temp;
1640
1641         DPRINTF("\n");
1642
1643         trb.qwTrb0 = 0;
1644         trb.dwTrb2 = 0;
1645         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1646             XHCI_TRB_3_SLOT_SET(slot_id);
1647
1648         trb.dwTrb3 = htole32(temp);
1649
1650         return (xhci_do_command(sc, &trb, 100 /* ms */));
1651 }
1652
1653 /*------------------------------------------------------------------------*
1654  *      xhci_interrupt - XHCI interrupt handler
1655  *------------------------------------------------------------------------*/
1656 void
1657 xhci_interrupt(struct xhci_softc *sc)
1658 {
1659         uint32_t status;
1660         uint32_t temp;
1661
1662         USB_BUS_LOCK(&sc->sc_bus);
1663
1664         status = XREAD4(sc, oper, XHCI_USBSTS);
1665
1666         /* acknowledge interrupts, if any */
1667         if (status != 0) {
1668                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1669                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1670         }
1671
1672         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1673
1674         /* force clearing of pending interrupts */
1675         if (temp & XHCI_IMAN_INTR_PEND)
1676                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1677
1678         /* check for event(s) */
1679         xhci_interrupt_poll(sc);
1680
1681         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1682             XHCI_STS_HSE | XHCI_STS_HCE)) {
1683                 if (status & XHCI_STS_PCD) {
1684                         xhci_root_intr(sc);
1685                 }
1686
1687                 if (status & XHCI_STS_HCH) {
1688                         printf("%s: host controller halted\n",
1689                             __FUNCTION__);
1690                 }
1691
1692                 if (status & XHCI_STS_HSE) {
1693                         printf("%s: host system error\n",
1694                             __FUNCTION__);
1695                 }
1696
1697                 if (status & XHCI_STS_HCE) {
1698                         printf("%s: host controller error\n",
1699                            __FUNCTION__);
1700                 }
1701         }
1702         USB_BUS_UNLOCK(&sc->sc_bus);
1703 }
1704
1705 /*------------------------------------------------------------------------*
1706  *      xhci_timeout - XHCI timeout handler
1707  *------------------------------------------------------------------------*/
1708 static void
1709 xhci_timeout(void *arg)
1710 {
1711         struct usb_xfer *xfer = arg;
1712
1713         DPRINTF("xfer=%p\n", xfer);
1714
1715         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1716
1717         /* transfer is transferred */
1718         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1719 }
1720
1721 static void
1722 xhci_do_poll(struct usb_bus *bus)
1723 {
1724         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1725
1726         USB_BUS_LOCK(&sc->sc_bus);
1727         xhci_interrupt_poll(sc);
1728         USB_BUS_UNLOCK(&sc->sc_bus);
1729 }
1730
1731 static void
1732 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1733 {
1734         struct usb_page_search buf_res;
1735         struct xhci_td *td;
1736         struct xhci_td *td_next;
1737         struct xhci_td *td_alt_next;
1738         struct xhci_td *td_first;
1739         uint32_t buf_offset;
1740         uint32_t average;
1741         uint32_t len_old;
1742         uint32_t npkt_off;
1743         uint32_t dword;
1744         uint8_t shortpkt_old;
1745         uint8_t precompute;
1746         uint8_t x;
1747
1748         td_alt_next = NULL;
1749         buf_offset = 0;
1750         shortpkt_old = temp->shortpkt;
1751         len_old = temp->len;
1752         npkt_off = 0;
1753         precompute = 1;
1754
1755 restart:
1756
1757         td = temp->td;
1758         td_next = td_first = temp->td_next;
1759
1760         while (1) {
1761                 if (temp->len == 0) {
1762                         if (temp->shortpkt)
1763                                 break;
1764
1765                         /* send a Zero Length Packet, ZLP, last */
1766
1767                         temp->shortpkt = 1;
1768                         average = 0;
1769
1770                 } else {
1771                         average = temp->average;
1772
1773                         if (temp->len < average) {
1774                                 if (temp->len % temp->max_packet_size) {
1775                                         temp->shortpkt = 1;
1776                                 }
1777                                 average = temp->len;
1778                         }
1779                 }
1780
1781                 if (td_next == NULL)
1782                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1783
1784                 /* get next TD */
1785
1786                 td = td_next;
1787                 td_next = td->obj_next;
1788
1789                 /* check if we are pre-computing */
1790
1791                 if (precompute) {
1792                         /* update remaining length */
1793
1794                         temp->len -= average;
1795
1796                         continue;
1797                 }
1798                 /* fill out current TD */
1799
1800                 td->len = average;
1801                 td->remainder = 0;
1802                 td->status = 0;
1803
1804                 /* update remaining length */
1805
1806                 temp->len -= average;
1807
1808                 /* reset TRB index */
1809
1810                 x = 0;
1811
1812                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1813                         /* immediate data */
1814
1815                         if (average > 8)
1816                                 average = 8;
1817
1818                         td->td_trb[0].qwTrb0 = 0;
1819
1820                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1821                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1822                            average);
1823
1824                         dword = XHCI_TRB_2_BYTES_SET(8) |
1825                             XHCI_TRB_2_TDSZ_SET(0) |
1826                             XHCI_TRB_2_IRQ_SET(0);
1827
1828                         td->td_trb[0].dwTrb2 = htole32(dword);
1829
1830                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1831                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1832
1833                         /* check wLength */
1834                         if (td->td_trb[0].qwTrb0 &
1835                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1836                                 if (td->td_trb[0].qwTrb0 &
1837                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1838                                         dword |= XHCI_TRB_3_TRT_IN;
1839                                 else
1840                                         dword |= XHCI_TRB_3_TRT_OUT;
1841                         }
1842
1843                         td->td_trb[0].dwTrb3 = htole32(dword);
1844 #ifdef USB_DEBUG
1845                         xhci_dump_trb(&td->td_trb[x]);
1846 #endif
1847                         x++;
1848
1849                 } else do {
1850                         uint32_t npkt;
1851
1852                         /* fill out buffer pointers */
1853
1854                         if (average == 0) {
1855                                 memset(&buf_res, 0, sizeof(buf_res));
1856                         } else {
1857                                 usbd_get_page(temp->pc, temp->offset +
1858                                     buf_offset, &buf_res);
1859
1860                                 /* get length to end of page */
1861                                 if (buf_res.length > average)
1862                                         buf_res.length = average;
1863
1864                                 /* check for maximum length */
1865                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1866                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1867
1868                                 npkt_off += buf_res.length;
1869                         }
1870
1871                         /* set up npkt */
1872                         npkt = howmany(len_old - npkt_off,
1873                                        temp->max_packet_size);
1874
1875                         if (npkt == 0)
1876                                 npkt = 1;
1877                         else if (npkt > 31)
1878                                 npkt = 31;
1879
1880                         /* fill out TRB's */
1881                         td->td_trb[x].qwTrb0 =
1882                             htole64((uint64_t)buf_res.physaddr);
1883
1884                         dword =
1885                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1886                           XHCI_TRB_2_TDSZ_SET(npkt) |
1887                           XHCI_TRB_2_IRQ_SET(0);
1888
1889                         td->td_trb[x].dwTrb2 = htole32(dword);
1890
1891                         switch (temp->trb_type) {
1892                         case XHCI_TRB_TYPE_ISOCH:
1893                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1894                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1895                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1896                                 if (td != td_first) {
1897                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1898                                 } else if (temp->do_isoc_sync != 0) {
1899                                         temp->do_isoc_sync = 0;
1900                                         /* wait until "isoc_frame" */
1901                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1902                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1903                                 } else {
1904                                         /* start data transfer at next interval */
1905                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1906                                             XHCI_TRB_3_ISO_SIA_BIT;
1907                                 }
1908                                 if (temp->direction == UE_DIR_IN)
1909                                         dword |= XHCI_TRB_3_ISP_BIT;
1910                                 break;
1911                         case XHCI_TRB_TYPE_DATA_STAGE:
1912                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1913                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1914                                 if (temp->direction == UE_DIR_IN)
1915                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1916                                 /*
1917                                  * Section 3.2.9 in the XHCI
1918                                  * specification about control
1919                                  * transfers says that we should use a
1920                                  * normal-TRB if there are more TRBs
1921                                  * extending the data-stage
1922                                  * TRB. Update the "trb_type".
1923                                  */
1924                                 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1925                                 break;
1926                         case XHCI_TRB_TYPE_STATUS_STAGE:
1927                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1928                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1929                                 if (temp->direction == UE_DIR_IN)
1930                                         dword |= XHCI_TRB_3_DIR_IN;
1931                                 break;
1932                         default:        /* XHCI_TRB_TYPE_NORMAL */
1933                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1934                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1935                                 if (temp->direction == UE_DIR_IN)
1936                                         dword |= XHCI_TRB_3_ISP_BIT;
1937                                 break;
1938                         }
1939                         td->td_trb[x].dwTrb3 = htole32(dword);
1940
1941                         average -= buf_res.length;
1942                         buf_offset += buf_res.length;
1943 #ifdef USB_DEBUG
1944                         xhci_dump_trb(&td->td_trb[x]);
1945 #endif
1946                         x++;
1947
1948                 } while (average != 0);
1949
1950                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1951
1952                 /* store number of data TRB's */
1953
1954                 td->ntrb = x;
1955
1956                 DPRINTF("NTRB=%u\n", x);
1957
1958                 /* fill out link TRB */
1959
1960                 if (td_next != NULL) {
1961                         /* link the current TD with the next one */
1962                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1963                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1964                 } else {
1965                         /* this field will get updated later */
1966                         DPRINTF("NOLINK\n");
1967                 }
1968
1969                 dword = XHCI_TRB_2_IRQ_SET(0);
1970
1971                 td->td_trb[x].dwTrb2 = htole32(dword);
1972
1973                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1974                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1975                     /*
1976                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1977                      * frame only receives a single short packet event
1978                      * by setting the CHAIN bit in the LINK field. In
1979                      * addition some XHCI controllers have problems
1980                      * sending a ZLP unless the CHAIN-BIT is set in
1981                      * the LINK TRB.
1982                      */
1983                     XHCI_TRB_3_CHAIN_BIT;
1984
1985                 td->td_trb[x].dwTrb3 = htole32(dword);
1986
1987                 td->alt_next = td_alt_next;
1988 #ifdef USB_DEBUG
1989                 xhci_dump_trb(&td->td_trb[x]);
1990 #endif
1991                 usb_pc_cpu_flush(td->page_cache);
1992         }
1993
1994         if (precompute) {
1995                 precompute = 0;
1996
1997                 /* set up alt next pointer, if any */
1998                 if (temp->last_frame) {
1999                         td_alt_next = NULL;
2000                 } else {
2001                         /* we use this field internally */
2002                         td_alt_next = td_next;
2003                 }
2004
2005                 /* restore */
2006                 temp->shortpkt = shortpkt_old;
2007                 temp->len = len_old;
2008                 goto restart;
2009         }
2010
2011         /*
2012          * Remove cycle bit from the first TRB if we are
2013          * stepping them:
2014          */
2015         if (temp->step_td != 0) {
2016                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
2017                 usb_pc_cpu_flush(td_first->page_cache);
2018         }
2019
2020         /* clear TD SIZE to zero, hence this is the last TRB */
2021         /* remove chain bit because this is the last data TRB in the chain */
2022         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31));
2023         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2024         /* remove CHAIN-BIT from last LINK TRB */
2025         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2026
2027         usb_pc_cpu_flush(td->page_cache);
2028
2029         temp->td = td;
2030         temp->td_next = td_next;
2031 }
2032
2033 static void
2034 xhci_setup_generic_chain(struct usb_xfer *xfer)
2035 {
2036         struct xhci_std_temp temp;
2037         struct xhci_td *td;
2038         uint32_t x;
2039         uint32_t y;
2040         uint8_t mult;
2041
2042         temp.do_isoc_sync = 0;
2043         temp.step_td = 0;
2044         temp.tbc = 0;
2045         temp.tlbpc = 0;
2046         temp.average = xfer->max_hc_frame_size;
2047         temp.max_packet_size = xfer->max_packet_size;
2048         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2049         temp.pc = NULL;
2050         temp.last_frame = 0;
2051         temp.offset = 0;
2052         temp.multishort = xfer->flags_int.isochronous_xfr ||
2053             xfer->flags_int.control_xfr ||
2054             xfer->flags_int.short_frames_ok;
2055
2056         /* toggle the DMA set we are using */
2057         xfer->flags_int.curr_dma_set ^= 1;
2058
2059         /* get next DMA set */
2060         td = xfer->td_start[xfer->flags_int.curr_dma_set];
2061
2062         temp.td = NULL;
2063         temp.td_next = td;
2064
2065         xfer->td_transfer_first = td;
2066         xfer->td_transfer_cache = td;
2067
2068         if (xfer->flags_int.isochronous_xfr) {
2069                 uint8_t shift;
2070
2071                 /* compute multiplier for ISOCHRONOUS transfers */
2072                 mult = xfer->endpoint->ecomp ?
2073                     UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2074                     : 0;
2075                 /* check for USB 2.0 multiplier */
2076                 if (mult == 0) {
2077                         mult = (xfer->endpoint->edesc->
2078                             wMaxPacketSize[1] >> 3) & 3;
2079                 }
2080                 /* range check */
2081                 if (mult > 2)
2082                         mult = 3;
2083                 else
2084                         mult++;
2085
2086                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2087
2088                 DPRINTF("MFINDEX=0x%08x IST=0x%x\n", x, temp.sc->sc_ist);
2089
2090                 switch (usbd_get_speed(xfer->xroot->udev)) {
2091                 case USB_SPEED_FULL:
2092                         shift = 3;
2093                         temp.isoc_delta = 8;    /* 1ms */
2094                         break;
2095                 default:
2096                         shift = usbd_xfer_get_fps_shift(xfer);
2097                         temp.isoc_delta = 1U << shift;
2098                         break;
2099                 }
2100
2101                 /* Compute isochronous scheduling threshold. */
2102                 if (temp.sc->sc_ist & 8)
2103                         y = (temp.sc->sc_ist & 7) << 3;
2104                 else
2105                         y = (temp.sc->sc_ist & 7);
2106
2107                 /* Range check the IST. */
2108                 if (y < 8) {
2109                         y = 0;
2110                 } else if (y > 15) {
2111                         DPRINTFN(3, "IST(%d) is too big!\n", temp.sc->sc_ist);
2112                         /*
2113                          * The USB stack minimum isochronous transfer
2114                          * size is typically 2x2 ms of payload. If the
2115                          * IST makes is above 15 microframes, we have
2116                          * an effective scheduling delay of more than
2117                          * or equal to 2 milliseconds, which is too
2118                          * much.
2119                          */
2120                         y = 7;
2121                 } else {
2122                         /*
2123                          * Subtract one millisecond, because the
2124                          * generic code adds that to the latency.
2125                          */
2126                         y -= 8;
2127                 }
2128
2129                 if (usbd_xfer_get_isochronous_start_frame(
2130                     xfer, x, y, 8, XHCI_MFINDEX_GET(-1), &temp.isoc_frame)) {
2131                         /* Start isochronous transfer at specified time. */
2132                         temp.do_isoc_sync = 1;
2133
2134                         DPRINTFN(3, "start next=%d\n", temp.isoc_frame);
2135                 }
2136
2137                 x = 0;
2138                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2139
2140         } else if (xfer->flags_int.control_xfr) {
2141                 /* check if we should prepend a setup message */
2142
2143                 if (xfer->flags_int.control_hdr) {
2144                         temp.len = xfer->frlengths[0];
2145                         temp.pc = xfer->frbuffers + 0;
2146                         temp.shortpkt = temp.len ? 1 : 0;
2147                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2148                         temp.direction = 0;
2149
2150                         /* check for last frame */
2151                         if (xfer->nframes == 1) {
2152                                 /* no STATUS stage yet, SETUP is last */
2153                                 if (xfer->flags_int.control_act)
2154                                         temp.last_frame = 1;
2155                         }
2156
2157                         xhci_setup_generic_chain_sub(&temp);
2158                 }
2159                 x = 1;
2160                 mult = 1;
2161                 temp.isoc_delta = 0;
2162                 temp.isoc_frame = 0;
2163                 temp.trb_type = xfer->flags_int.control_did_data ?
2164                     XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2165         } else {
2166                 x = 0;
2167                 mult = 1;
2168                 temp.isoc_delta = 0;
2169                 temp.isoc_frame = 0;
2170                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2171         }
2172
2173         if (x != xfer->nframes) {
2174                 /* set up page_cache pointer */
2175                 temp.pc = xfer->frbuffers + x;
2176                 /* set endpoint direction */
2177                 temp.direction = UE_GET_DIR(xfer->endpointno);
2178         }
2179
2180         while (x != xfer->nframes) {
2181                 /* DATA0 / DATA1 message */
2182
2183                 temp.len = xfer->frlengths[x];
2184                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2185                     x != 0 && temp.multishort == 0);
2186
2187                 x++;
2188
2189                 if (x == xfer->nframes) {
2190                         if (xfer->flags_int.control_xfr) {
2191                                 /* no STATUS stage yet, DATA is last */
2192                                 if (xfer->flags_int.control_act)
2193                                         temp.last_frame = 1;
2194                         } else {
2195                                 temp.last_frame = 1;
2196                         }
2197                 }
2198                 if (temp.len == 0) {
2199                         /* make sure that we send an USB packet */
2200
2201                         temp.shortpkt = 0;
2202
2203                         temp.tbc = 0;
2204                         temp.tlbpc = mult - 1;
2205
2206                 } else if (xfer->flags_int.isochronous_xfr) {
2207                         uint8_t tdpc;
2208
2209                         /*
2210                          * Isochronous transfers don't have short
2211                          * packet termination:
2212                          */
2213
2214                         temp.shortpkt = 1;
2215
2216                         /* isochronous transfers have a transfer limit */
2217
2218                         if (temp.len > xfer->max_frame_size)
2219                                 temp.len = xfer->max_frame_size;
2220
2221                         /* compute TD packet count */
2222                         tdpc = howmany(temp.len, xfer->max_packet_size);
2223
2224                         temp.tbc = howmany(tdpc, mult) - 1;
2225                         temp.tlbpc = (tdpc % mult);
2226
2227                         if (temp.tlbpc == 0)
2228                                 temp.tlbpc = mult - 1;
2229                         else
2230                                 temp.tlbpc--;
2231                 } else {
2232                         /* regular data transfer */
2233
2234                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2235                 }
2236
2237                 xhci_setup_generic_chain_sub(&temp);
2238
2239                 if (xfer->flags_int.isochronous_xfr) {
2240                         temp.offset += xfer->frlengths[x - 1];
2241                         temp.isoc_frame += temp.isoc_delta;
2242                 } else {
2243                         /* get next Page Cache pointer */
2244                         temp.pc = xfer->frbuffers + x;
2245                 }
2246         }
2247
2248         /* check if we should append a status stage */
2249
2250         if (xfer->flags_int.control_xfr &&
2251             !xfer->flags_int.control_act) {
2252                 /*
2253                  * Send a DATA1 message and invert the current
2254                  * endpoint direction.
2255                  */
2256                 if (xhcictlstep || temp.sc->sc_ctlstep) {
2257                         /*
2258                          * Some XHCI controllers will not delay the
2259                          * status stage until the next SOF. Force this
2260                          * behaviour to avoid failed control
2261                          * transfers.
2262                          */
2263                         temp.step_td = (xfer->nframes != 0);
2264                 } else {
2265                         temp.step_td = 0;
2266                 }
2267                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2268                 temp.len = 0;
2269                 temp.pc = NULL;
2270                 temp.shortpkt = 0;
2271                 temp.last_frame = 1;
2272                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2273
2274                 xhci_setup_generic_chain_sub(&temp);
2275         }
2276
2277         td = temp.td;
2278
2279         /* must have at least one frame! */
2280
2281         xfer->td_transfer_last = td;
2282
2283         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2284 }
2285
2286 static void
2287 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2288 {
2289         struct usb_page_search buf_res;
2290         struct xhci_dev_ctx_addr *pdctxa;
2291
2292         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2293
2294         pdctxa = buf_res.buffer;
2295
2296         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2297
2298         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2299
2300         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2301 }
2302
2303 static usb_error_t
2304 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2305 {
2306         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2307         struct usb_page_search buf_inp;
2308         struct xhci_input_dev_ctx *pinp;
2309         uint32_t temp;
2310         uint8_t index;
2311         uint8_t x;
2312
2313         index = udev->controller_slot_id;
2314
2315         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2316
2317         pinp = buf_inp.buffer;
2318
2319         if (drop) {
2320                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2321                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2322                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2323         } else {
2324                 /*
2325                  * Some hardware requires that we drop the endpoint
2326                  * context before adding it again:
2327                  */
2328                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2329                     mask & XHCI_INCTX_NON_CTRL_MASK);
2330
2331                 /* Add new endpoint context */
2332                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2333
2334                 /* find most significant set bit */
2335                 for (x = 31; x != 1; x--) {
2336                         if (mask & (1 << x))
2337                                 break;
2338                 }
2339
2340                 /* adjust */
2341                 x--;
2342
2343                 /* figure out the maximum number of contexts */
2344                 if (x > sc->sc_hw.devs[index].context_num)
2345                         sc->sc_hw.devs[index].context_num = x;
2346                 else
2347                         x = sc->sc_hw.devs[index].context_num;
2348
2349                 /* update number of contexts */
2350                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2351                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2352                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2353                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2354         }
2355         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2356         return (0);
2357 }
2358
2359 static usb_error_t
2360 xhci_configure_endpoint(struct usb_device *udev,
2361     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2362     uint16_t interval, uint8_t max_packet_count,
2363     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2364     uint16_t max_frame_size, uint8_t ep_mode)
2365 {
2366         struct usb_page_search buf_inp;
2367         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2368         struct xhci_input_dev_ctx *pinp;
2369         uint64_t ring_addr = pepext->physaddr;
2370         uint32_t temp;
2371         uint8_t index;
2372         uint8_t epno;
2373         uint8_t type;
2374
2375         index = udev->controller_slot_id;
2376
2377         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2378
2379         pinp = buf_inp.buffer;
2380
2381         epno = edesc->bEndpointAddress;
2382         type = edesc->bmAttributes & UE_XFERTYPE;
2383
2384         if (type == UE_CONTROL)
2385                 epno |= UE_DIR_IN;
2386
2387         epno = XHCI_EPNO2EPID(epno);
2388
2389         if (epno == 0)
2390                 return (USB_ERR_NO_PIPE);               /* invalid */
2391
2392         if (max_packet_count == 0)
2393                 return (USB_ERR_BAD_BUFSIZE);
2394
2395         max_packet_count--;
2396
2397         if (mult == 0)
2398                 return (USB_ERR_BAD_BUFSIZE);
2399
2400         /* store endpoint mode */
2401         pepext->trb_ep_mode = ep_mode;
2402         /* store bMaxPacketSize for control endpoints */
2403         pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2404         usb_pc_cpu_flush(pepext->page_cache);
2405
2406         if (ep_mode == USB_EP_MODE_STREAMS) {
2407                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2408                     XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2409                     XHCI_EPCTX_0_LSA_SET(1);
2410
2411                 ring_addr += sizeof(struct xhci_trb) *
2412                     XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2413         } else {
2414                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2415                     XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2416                     XHCI_EPCTX_0_LSA_SET(0);
2417
2418                 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2419         }
2420
2421         switch (udev->speed) {
2422         case USB_SPEED_FULL:
2423         case USB_SPEED_LOW:
2424                 /* 1ms -> 125us */
2425                 fps_shift += 3;
2426                 break;
2427         default:
2428                 break;
2429         }
2430
2431         switch (type) {
2432         case UE_INTERRUPT:
2433                 if (fps_shift > 3)
2434                         fps_shift--;
2435                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2436                 break;
2437         case UE_ISOCHRONOUS:
2438                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2439
2440                 switch (udev->speed) {
2441                 case USB_SPEED_SUPER:
2442                         if (mult > 3)
2443                                 mult = 3;
2444                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2445                         max_packet_count /= mult;
2446                         break;
2447                 default:
2448                         break;
2449                 }
2450                 break;
2451         default:
2452                 break;
2453         }
2454
2455         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2456
2457         temp =
2458             XHCI_EPCTX_1_HID_SET(0) |
2459             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2460             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2461
2462         /*
2463          * Always enable the "three strikes and you are gone" feature
2464          * except for ISOCHRONOUS endpoints. This is suggested by
2465          * section 4.3.3 in the XHCI specification about device slot
2466          * initialisation.
2467          */
2468         if (type != UE_ISOCHRONOUS)
2469                 temp |= XHCI_EPCTX_1_CERR_SET(3);
2470
2471         switch (type) {
2472         case UE_CONTROL:
2473                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2474                 break;
2475         case UE_ISOCHRONOUS:
2476                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2477                 break;
2478         case UE_BULK:
2479                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2480                 break;
2481         default:
2482                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2483                 break;
2484         }
2485
2486         /* check for IN direction */
2487         if (epno & 1)
2488                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2489
2490         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2491         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2492
2493         switch (edesc->bmAttributes & UE_XFERTYPE) {
2494         case UE_INTERRUPT:
2495         case UE_ISOCHRONOUS:
2496                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2497                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2498                     max_frame_size));
2499                 break;
2500         case UE_CONTROL:
2501                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2502                 break;
2503         default:
2504                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2505                 break;
2506         }
2507
2508         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2509
2510 #ifdef USB_DEBUG
2511         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2512 #endif
2513         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2514
2515         return (0);             /* success */
2516 }
2517
2518 static usb_error_t
2519 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2520 {
2521         struct xhci_endpoint_ext *pepext;
2522         struct usb_endpoint_ss_comp_descriptor *ecomp;
2523         usb_stream_t x;
2524
2525         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2526             xfer->endpoint->edesc);
2527
2528         ecomp = xfer->endpoint->ecomp;
2529
2530         for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2531                 uint64_t temp;
2532
2533                 /* halt any transfers */
2534                 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2535
2536                 /* compute start of TRB ring for stream "x" */
2537                 temp = pepext->physaddr +
2538                     (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2539                     XHCI_SCTX_0_SCT_SEC_TR_RING;
2540
2541                 /* make tree structure */
2542                 pepext->trb[(XHCI_MAX_TRANSFERS *
2543                     XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2544
2545                 /* reserved fields */
2546                 pepext->trb[(XHCI_MAX_TRANSFERS *
2547                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2548                 pepext->trb[(XHCI_MAX_TRANSFERS *
2549                     XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2550         }
2551         usb_pc_cpu_flush(pepext->page_cache);
2552
2553         return (xhci_configure_endpoint(xfer->xroot->udev,
2554             xfer->endpoint->edesc, pepext,
2555             xfer->interval, xfer->max_packet_count,
2556             (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2557             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2558             xfer->max_frame_size, xfer->endpoint->ep_mode));
2559 }
2560
2561 static usb_error_t
2562 xhci_configure_device(struct usb_device *udev)
2563 {
2564         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2565         struct usb_page_search buf_inp;
2566         struct usb_page_cache *pcinp;
2567         struct xhci_input_dev_ctx *pinp;
2568         struct usb_device *hubdev;
2569         uint32_t temp;
2570         uint32_t route;
2571         uint32_t rh_port;
2572         uint8_t is_hub;
2573         uint8_t index;
2574         uint8_t depth;
2575
2576         index = udev->controller_slot_id;
2577
2578         DPRINTF("index=%u\n", index);
2579
2580         pcinp = &sc->sc_hw.devs[index].input_pc;
2581
2582         usbd_get_page(pcinp, 0, &buf_inp);
2583
2584         pinp = buf_inp.buffer;
2585
2586         rh_port = 0;
2587         route = 0;
2588
2589         /* figure out route string and root HUB port number */
2590
2591         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2592                 if (hubdev->parent_hub == NULL)
2593                         break;
2594
2595                 depth = hubdev->parent_hub->depth;
2596
2597                 /*
2598                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2599                  * more than 15 ports
2600                  */
2601
2602                 rh_port = hubdev->port_no;
2603
2604                 if (depth == 0)
2605                         break;
2606
2607                 if (rh_port > 15)
2608                         rh_port = 15;
2609
2610                 if (depth < 6)
2611                         route |= rh_port << (4 * (depth - 1));
2612         }
2613
2614         DPRINTF("Route=0x%08x\n", route);
2615
2616         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2617             XHCI_SCTX_0_CTX_NUM_SET(
2618             sc->sc_hw.devs[index].context_num + 1);
2619
2620         switch (udev->speed) {
2621         case USB_SPEED_LOW:
2622                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2623                 if (udev->parent_hs_hub != NULL &&
2624                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2625                     UDPROTO_HSHUBMTT) {
2626                         DPRINTF("Device inherits MTT\n");
2627                         temp |= XHCI_SCTX_0_MTT_SET(1);
2628                 }
2629                 break;
2630         case USB_SPEED_HIGH:
2631                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2632                 if (sc->sc_hw.devs[index].nports != 0 &&
2633                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2634                         DPRINTF("HUB supports MTT\n");
2635                         temp |= XHCI_SCTX_0_MTT_SET(1);
2636                 }
2637                 break;
2638         case USB_SPEED_FULL:
2639                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2640                 if (udev->parent_hs_hub != NULL &&
2641                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2642                     UDPROTO_HSHUBMTT) {
2643                         DPRINTF("Device inherits MTT\n");
2644                         temp |= XHCI_SCTX_0_MTT_SET(1);
2645                 }
2646                 break;
2647         default:
2648                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2649                 break;
2650         }
2651
2652         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2653             (udev->speed == USB_SPEED_SUPER ||
2654             udev->speed == USB_SPEED_HIGH);
2655
2656         if (is_hub)
2657                 temp |= XHCI_SCTX_0_HUB_SET(1);
2658
2659         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2660
2661         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2662
2663         if (is_hub) {
2664                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2665                     sc->sc_hw.devs[index].nports);
2666         }
2667
2668         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2669
2670         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2671
2672         if (is_hub) {
2673                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2674                     sc->sc_hw.devs[index].tt);
2675         }
2676
2677         hubdev = udev->parent_hs_hub;
2678
2679         /* check if we should activate the transaction translator */
2680         switch (udev->speed) {
2681         case USB_SPEED_FULL:
2682         case USB_SPEED_LOW:
2683                 if (hubdev != NULL) {
2684                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2685                             hubdev->controller_slot_id);
2686                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2687                             udev->hs_port_no);
2688                 }
2689                 break;
2690         default:
2691                 break;
2692         }
2693
2694         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2695
2696         /*
2697          * These fields should be initialized to zero, according to
2698          * XHCI section 6.2.2 - slot context:
2699          */
2700         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2701             XHCI_SCTX_3_SLOT_STATE_SET(0);
2702
2703         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2704
2705 #ifdef USB_DEBUG
2706         xhci_dump_device(sc, &pinp->ctx_slot);
2707 #endif
2708         usb_pc_cpu_flush(pcinp);
2709
2710         return (0);             /* success */
2711 }
2712
2713 static usb_error_t
2714 xhci_alloc_device_ext(struct usb_device *udev)
2715 {
2716         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2717         struct usb_page_search buf_dev;
2718         struct usb_page_search buf_ep;
2719         struct xhci_trb *trb;
2720         struct usb_page_cache *pc;
2721         struct usb_page *pg;
2722         uint64_t addr;
2723         uint8_t index;
2724         uint8_t i;
2725
2726         index = udev->controller_slot_id;
2727
2728         pc = &sc->sc_hw.devs[index].device_pc;
2729         pg = &sc->sc_hw.devs[index].device_pg;
2730
2731         /* need to initialize the page cache */
2732         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2733
2734         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2735             (2 * sizeof(struct xhci_dev_ctx)) :
2736             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2737                 goto error;
2738
2739         usbd_get_page(pc, 0, &buf_dev);
2740
2741         pc = &sc->sc_hw.devs[index].input_pc;
2742         pg = &sc->sc_hw.devs[index].input_pg;
2743
2744         /* need to initialize the page cache */
2745         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2746
2747         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2748             (2 * sizeof(struct xhci_input_dev_ctx)) :
2749             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2750                 goto error;
2751         }
2752
2753         /* initialize all endpoint LINK TRBs */
2754
2755         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2756                 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2757                 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2758
2759                 /* need to initialize the page cache */
2760                 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2761
2762                 if (usb_pc_alloc_mem(pc, pg,
2763                     sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2764                         goto error;
2765                 }
2766
2767                 /* lookup endpoint TRB ring */
2768                 usbd_get_page(pc, 0, &buf_ep);
2769
2770                 /* get TRB pointer */
2771                 trb = buf_ep.buffer;
2772                 trb += XHCI_MAX_TRANSFERS - 1;
2773
2774                 /* get TRB start address */
2775                 addr = buf_ep.physaddr;
2776
2777                 /* create LINK TRB */
2778                 trb->qwTrb0 = htole64(addr);
2779                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2780                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2781                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2782
2783                 usb_pc_cpu_flush(pc);
2784         }
2785
2786         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2787
2788         return (0);
2789
2790 error:
2791         xhci_free_device_ext(udev);
2792
2793         return (USB_ERR_NOMEM);
2794 }
2795
2796 static void
2797 xhci_free_device_ext(struct usb_device *udev)
2798 {
2799         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2800         uint8_t index;
2801         uint8_t i;
2802
2803         index = udev->controller_slot_id;
2804         xhci_set_slot_pointer(sc, index, 0);
2805
2806         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2807         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2808         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2809                 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2810 }
2811
2812 static struct xhci_endpoint_ext *
2813 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2814 {
2815         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2816         struct xhci_endpoint_ext *pepext;
2817         struct usb_page_cache *pc;
2818         struct usb_page_search buf_ep;
2819         uint8_t epno;
2820         uint8_t index;
2821
2822         epno = edesc->bEndpointAddress;
2823         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2824                 epno |= UE_DIR_IN;
2825
2826         epno = XHCI_EPNO2EPID(epno);
2827
2828         index = udev->controller_slot_id;
2829
2830         pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2831
2832         usbd_get_page(pc, 0, &buf_ep);
2833
2834         pepext = &sc->sc_hw.devs[index].endp[epno];
2835         pepext->page_cache = pc;
2836         pepext->trb = buf_ep.buffer;
2837         pepext->physaddr = buf_ep.physaddr;
2838
2839         return (pepext);
2840 }
2841
2842 static void
2843 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2844 {
2845         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2846         uint8_t epno;
2847         uint8_t index;
2848
2849         epno = xfer->endpointno;
2850         if (xfer->flags_int.control_xfr)
2851                 epno |= UE_DIR_IN;
2852
2853         epno = XHCI_EPNO2EPID(epno);
2854         index = xfer->xroot->udev->controller_slot_id;
2855
2856         if (xfer->xroot->udev->flags.self_suspended == 0) {
2857                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2858                     epno | XHCI_DB_SID_SET(xfer->stream_id));
2859         }
2860 }
2861
2862 static void
2863 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2864 {
2865         struct xhci_endpoint_ext *pepext;
2866
2867         if (xfer->flags_int.bandwidth_reclaimed) {
2868                 xfer->flags_int.bandwidth_reclaimed = 0;
2869
2870                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2871                     xfer->endpoint->edesc);
2872
2873                 pepext->trb_used[xfer->stream_id]--;
2874
2875                 pepext->xfer[xfer->qh_pos] = NULL;
2876
2877                 if (error && pepext->trb_running != 0) {
2878                         pepext->trb_halted = 1;
2879                         pepext->trb_running = 0;
2880                 }
2881         }
2882 }
2883
2884 static usb_error_t
2885 xhci_transfer_insert(struct usb_xfer *xfer)
2886 {
2887         struct xhci_td *td_first;
2888         struct xhci_td *td_last;
2889         struct xhci_trb *trb_link;
2890         struct xhci_endpoint_ext *pepext;
2891         uint64_t addr;
2892         usb_stream_t id;
2893         uint8_t i;
2894         uint8_t inext;
2895         uint8_t trb_limit;
2896
2897         DPRINTFN(8, "\n");
2898
2899         id = xfer->stream_id;
2900
2901         /* check if already inserted */
2902         if (xfer->flags_int.bandwidth_reclaimed) {
2903                 DPRINTFN(8, "Already in schedule\n");
2904                 return (0);
2905         }
2906
2907         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2908             xfer->endpoint->edesc);
2909
2910         td_first = xfer->td_transfer_first;
2911         td_last = xfer->td_transfer_last;
2912         addr = pepext->physaddr;
2913
2914         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2915         case UE_CONTROL:
2916         case UE_INTERRUPT:
2917                 /* single buffered */
2918                 trb_limit = 1;
2919                 break;
2920         default:
2921                 /* multi buffered */
2922                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2923                 break;
2924         }
2925
2926         if (pepext->trb_used[id] >= trb_limit) {
2927                 DPRINTFN(8, "Too many TDs queued.\n");
2928                 return (USB_ERR_NOMEM);
2929         }
2930
2931         /* check if bMaxPacketSize changed */
2932         if (xfer->flags_int.control_xfr != 0 &&
2933             pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2934                 DPRINTFN(8, "Reconfigure control endpoint\n");
2935
2936                 /* force driver to reconfigure endpoint */
2937                 pepext->trb_halted = 1;
2938                 pepext->trb_running = 0;
2939         }
2940
2941         /* check for stopped condition, after putting transfer on interrupt queue */
2942         if (pepext->trb_running == 0) {
2943                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2944
2945                 DPRINTFN(8, "Not running\n");
2946
2947                 /* start configuration */
2948                 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2949                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2950                 return (0);
2951         }
2952
2953         pepext->trb_used[id]++;
2954
2955         /* get current TRB index */
2956         i = pepext->trb_index[id];
2957
2958         /* get next TRB index */
2959         inext = (i + 1);
2960
2961         /* the last entry of the ring is a hardcoded link TRB */
2962         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2963                 inext = 0;
2964
2965         /* store next TRB index, before stream ID offset is added */
2966         pepext->trb_index[id] = inext;
2967
2968         /* offset for stream */
2969         i += id * XHCI_MAX_TRANSFERS;
2970         inext += id * XHCI_MAX_TRANSFERS;
2971
2972         /* compute terminating return address */
2973         addr += (inext * sizeof(struct xhci_trb));
2974
2975         /* compute link TRB pointer */
2976         trb_link = td_last->td_trb + td_last->ntrb;
2977
2978         /* update next pointer of last link TRB */
2979         trb_link->qwTrb0 = htole64(addr);
2980         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2981         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2982             XHCI_TRB_3_CYCLE_BIT |
2983             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2984
2985 #ifdef USB_DEBUG
2986         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2987 #endif
2988         usb_pc_cpu_flush(td_last->page_cache);
2989
2990         /* write ahead chain end marker */
2991
2992         pepext->trb[inext].qwTrb0 = 0;
2993         pepext->trb[inext].dwTrb2 = 0;
2994         pepext->trb[inext].dwTrb3 = 0;
2995
2996         /* update next pointer of link TRB */
2997
2998         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2999         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3000
3001 #ifdef USB_DEBUG
3002         xhci_dump_trb(&pepext->trb[i]);
3003 #endif
3004         usb_pc_cpu_flush(pepext->page_cache);
3005
3006         /* toggle cycle bit which activates the transfer chain */
3007
3008         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
3009             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3010
3011         usb_pc_cpu_flush(pepext->page_cache);
3012
3013         DPRINTF("qh_pos = %u\n", i);
3014
3015         pepext->xfer[i] = xfer;
3016
3017         xfer->qh_pos = i;
3018
3019         xfer->flags_int.bandwidth_reclaimed = 1;
3020
3021         xhci_endpoint_doorbell(xfer);
3022
3023         return (0);
3024 }
3025
3026 static void
3027 xhci_root_intr(struct xhci_softc *sc)
3028 {
3029         uint16_t i;
3030
3031         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3032
3033         /* clear any old interrupt data */
3034         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3035
3036         for (i = 1; i <= sc->sc_noport; i++) {
3037                 /* pick out CHANGE bits from the status register */
3038                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3039                     XHCI_PS_CSC | XHCI_PS_PEC |
3040                     XHCI_PS_OCC | XHCI_PS_WRC |
3041                     XHCI_PS_PRC | XHCI_PS_PLC |
3042                     XHCI_PS_CEC)) {
3043                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3044                         DPRINTF("port %d changed\n", i);
3045                 }
3046         }
3047         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3048             sizeof(sc->sc_hub_idata));
3049 }
3050
3051 /*------------------------------------------------------------------------*
3052  *      xhci_device_done - XHCI done handler
3053  *
3054  * NOTE: This function can be called two times in a row on
3055  * the same USB transfer. From close and from interrupt.
3056  *------------------------------------------------------------------------*/
3057 static void
3058 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3059 {
3060         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3061             xfer, xfer->endpoint, error);
3062
3063         /* remove transfer from HW queue */
3064         xhci_transfer_remove(xfer, error);
3065
3066         /* dequeue transfer and start next transfer */
3067         usbd_transfer_done(xfer, error);
3068 }
3069
3070 /*------------------------------------------------------------------------*
3071  * XHCI data transfer support (generic type)
3072  *------------------------------------------------------------------------*/
3073 static void
3074 xhci_device_generic_open(struct usb_xfer *xfer)
3075 {
3076         DPRINTF("\n");
3077 }
3078
3079 static void
3080 xhci_device_generic_close(struct usb_xfer *xfer)
3081 {
3082         DPRINTF("\n");
3083
3084         xhci_device_done(xfer, USB_ERR_CANCELLED);
3085 }
3086
3087 static void
3088 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3089     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3090 {
3091         struct usb_xfer *xfer;
3092
3093         /* check if there is a current transfer */
3094         xfer = ep->endpoint_q[stream_id].curr;
3095         if (xfer == NULL)
3096                 return;
3097
3098         /*
3099          * Check if the current transfer is started and then pickup
3100          * the next one, if any. Else wait for next start event due to
3101          * block on failure feature.
3102          */
3103         if (!xfer->flags_int.bandwidth_reclaimed)
3104                 return;
3105
3106         xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3107         if (xfer == NULL) {
3108                 /*
3109                  * In case of enter we have to consider that the
3110                  * transfer is queued by the USB core after the enter
3111                  * method is called.
3112                  */
3113                 xfer = enter_xfer;
3114
3115                 if (xfer == NULL)
3116                         return;
3117         }
3118
3119         /* try to multi buffer */
3120         xhci_transfer_insert(xfer);
3121 }
3122
3123 static void
3124 xhci_device_generic_enter(struct usb_xfer *xfer)
3125 {
3126         DPRINTF("\n");
3127
3128         /* set up TD's and QH */
3129         xhci_setup_generic_chain(xfer);
3130
3131         xhci_device_generic_multi_enter(xfer->endpoint,
3132             xfer->stream_id, xfer);
3133 }
3134
3135 static void
3136 xhci_device_generic_start(struct usb_xfer *xfer)
3137 {
3138         DPRINTF("\n");
3139
3140         /* try to insert xfer on HW queue */
3141         xhci_transfer_insert(xfer);
3142
3143         /* try to multi buffer */
3144         xhci_device_generic_multi_enter(xfer->endpoint,
3145             xfer->stream_id, NULL);
3146
3147         /* add transfer last on interrupt queue */
3148         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3149
3150         /* start timeout, if any */
3151         if (xfer->timeout != 0)
3152                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3153 }
3154
3155 static const struct usb_pipe_methods xhci_device_generic_methods =
3156 {
3157         .open = xhci_device_generic_open,
3158         .close = xhci_device_generic_close,
3159         .enter = xhci_device_generic_enter,
3160         .start = xhci_device_generic_start,
3161 };
3162
3163 /*------------------------------------------------------------------------*
3164  * xhci root HUB support
3165  *------------------------------------------------------------------------*
3166  * Simulate a hardware HUB by handling all the necessary requests.
3167  *------------------------------------------------------------------------*/
3168 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3169
3170 static const
3171 struct usb_device_descriptor xhci_devd =
3172 {
3173         .bLength = sizeof(xhci_devd),
3174         .bDescriptorType = UDESC_DEVICE,        /* type */
3175         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3176         .bDeviceClass = UDCLASS_HUB,            /* class */
3177         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3178         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3179         .bMaxPacketSize = 9,                    /* max packet size */
3180         HSETW(.idVendor, 0x0000),               /* vendor */
3181         HSETW(.idProduct, 0x0000),              /* product */
3182         HSETW(.bcdDevice, 0x0100),              /* device version */
3183         .iManufacturer = 1,
3184         .iProduct = 2,
3185         .iSerialNumber = 0,
3186         .bNumConfigurations = 1,                /* # of configurations */
3187 };
3188
3189 static const
3190 struct xhci_bos_desc xhci_bosd = {
3191         .bosd = {
3192                 .bLength = sizeof(xhci_bosd.bosd),
3193                 .bDescriptorType = UDESC_BOS,
3194                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3195                 .bNumDeviceCaps = 3,
3196         },
3197         .usb2extd = {
3198                 .bLength = sizeof(xhci_bosd.usb2extd),
3199                 .bDescriptorType = 1,
3200                 .bDevCapabilityType = 2,
3201                 .bmAttributes[0] = 2,
3202         },
3203         .usbdcd = {
3204                 .bLength = sizeof(xhci_bosd.usbdcd),
3205                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3206                 .bDevCapabilityType = 3,
3207                 .bmAttributes = 0, /* XXX */
3208                 HSETW(.wSpeedsSupported, 0x000C),
3209                 .bFunctionalitySupport = 8,
3210                 .bU1DevExitLat = 255,   /* dummy - not used */
3211                 .wU2DevExitLat = { 0x00, 0x08 },
3212         },
3213         .cidd = {
3214                 .bLength = sizeof(xhci_bosd.cidd),
3215                 .bDescriptorType = 1,
3216                 .bDevCapabilityType = 4,
3217                 .bReserved = 0,
3218                 .bContainerID = 0, /* XXX */
3219         },
3220 };
3221
3222 static const
3223 struct xhci_config_desc xhci_confd = {
3224         .confd = {
3225                 .bLength = sizeof(xhci_confd.confd),
3226                 .bDescriptorType = UDESC_CONFIG,
3227                 .wTotalLength[0] = sizeof(xhci_confd),
3228                 .bNumInterface = 1,
3229                 .bConfigurationValue = 1,
3230                 .iConfiguration = 0,
3231                 .bmAttributes = UC_SELF_POWERED,
3232                 .bMaxPower = 0          /* max power */
3233         },
3234         .ifcd = {
3235                 .bLength = sizeof(xhci_confd.ifcd),
3236                 .bDescriptorType = UDESC_INTERFACE,
3237                 .bNumEndpoints = 1,
3238                 .bInterfaceClass = UICLASS_HUB,
3239                 .bInterfaceSubClass = UISUBCLASS_HUB,
3240                 .bInterfaceProtocol = 0,
3241         },
3242         .endpd = {
3243                 .bLength = sizeof(xhci_confd.endpd),
3244                 .bDescriptorType = UDESC_ENDPOINT,
3245                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3246                 .bmAttributes = UE_INTERRUPT,
3247                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3248                 .bInterval = 255,
3249         },
3250         .endpcd = {
3251                 .bLength = sizeof(xhci_confd.endpcd),
3252                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3253                 .bMaxBurst = 0,
3254                 .bmAttributes = 0,
3255         },
3256 };
3257
3258 static const
3259 struct usb_hub_ss_descriptor xhci_hubd = {
3260         .bLength = sizeof(xhci_hubd),
3261         .bDescriptorType = UDESC_SS_HUB,
3262 };
3263
3264 static usb_error_t
3265 xhci_roothub_exec(struct usb_device *udev,
3266     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3267 {
3268         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3269         const char *str_ptr;
3270         const void *ptr;
3271         uint32_t port;
3272         uint32_t v;
3273         uint16_t len;
3274         uint16_t i;
3275         uint16_t value;
3276         uint16_t index;
3277         uint8_t j;
3278         usb_error_t err;
3279
3280         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3281
3282         /* buffer reset */
3283         ptr = (const void *)&sc->sc_hub_desc;
3284         len = 0;
3285         err = 0;
3286
3287         value = UGETW(req->wValue);
3288         index = UGETW(req->wIndex);
3289
3290         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3291             "wValue=0x%04x wIndex=0x%04x\n",
3292             req->bmRequestType, req->bRequest,
3293             UGETW(req->wLength), value, index);
3294
3295 #define C(x,y) ((x) | ((y) << 8))
3296         switch (C(req->bRequest, req->bmRequestType)) {
3297         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3298         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3299         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3300                 /*
3301                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3302                  * for the integrated root hub.
3303                  */
3304                 break;
3305         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3306                 len = 1;
3307                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3308                 break;
3309         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3310                 switch (value >> 8) {
3311                 case UDESC_DEVICE:
3312                         if ((value & 0xff) != 0) {
3313                                 err = USB_ERR_IOERROR;
3314                                 goto done;
3315                         }
3316                         len = sizeof(xhci_devd);
3317                         ptr = (const void *)&xhci_devd;
3318                         break;
3319
3320                 case UDESC_BOS:
3321                         if ((value & 0xff) != 0) {
3322                                 err = USB_ERR_IOERROR;
3323                                 goto done;
3324                         }
3325                         len = sizeof(xhci_bosd);
3326                         ptr = (const void *)&xhci_bosd;
3327                         break;
3328
3329                 case UDESC_CONFIG:
3330                         if ((value & 0xff) != 0) {
3331                                 err = USB_ERR_IOERROR;
3332                                 goto done;
3333                         }
3334                         len = sizeof(xhci_confd);
3335                         ptr = (const void *)&xhci_confd;
3336                         break;
3337
3338                 case UDESC_STRING:
3339                         switch (value & 0xff) {
3340                         case 0: /* Language table */
3341                                 str_ptr = "\001";
3342                                 break;
3343
3344                         case 1: /* Vendor */
3345                                 str_ptr = sc->sc_vendor;
3346                                 break;
3347
3348                         case 2: /* Product */
3349                                 str_ptr = "XHCI root HUB";
3350                                 break;
3351
3352                         default:
3353                                 str_ptr = "";
3354                                 break;
3355                         }
3356
3357                         len = usb_make_str_desc(
3358                             sc->sc_hub_desc.temp,
3359                             sizeof(sc->sc_hub_desc.temp),
3360                             str_ptr);
3361                         break;
3362
3363                 default:
3364                         err = USB_ERR_IOERROR;
3365                         goto done;
3366                 }
3367                 break;
3368         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3369                 len = 1;
3370                 sc->sc_hub_desc.temp[0] = 0;
3371                 break;
3372         case C(UR_GET_STATUS, UT_READ_DEVICE):
3373                 len = 2;
3374                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3375                 break;
3376         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3377         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3378                 len = 2;
3379                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3380                 break;
3381         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3382                 if (value >= XHCI_MAX_DEVICES) {
3383                         err = USB_ERR_IOERROR;
3384                         goto done;
3385                 }
3386                 break;
3387         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3388                 if (value != 0 && value != 1) {
3389                         err = USB_ERR_IOERROR;
3390                         goto done;
3391                 }
3392                 sc->sc_conf = value;
3393                 break;
3394         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3395                 break;
3396         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3397         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3398         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3399                 err = USB_ERR_IOERROR;
3400                 goto done;
3401         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3402                 break;
3403         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3404                 break;
3405                 /* Hub requests */
3406         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3407                 break;
3408         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3409                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3410
3411                 if ((index < 1) ||
3412                     (index > sc->sc_noport)) {
3413                         err = USB_ERR_IOERROR;
3414                         goto done;
3415                 }
3416                 port = XHCI_PORTSC(index);
3417
3418                 v = XREAD4(sc, oper, port);
3419                 i = XHCI_PS_PLS_GET(v);
3420                 v &= ~XHCI_PS_CLEAR;
3421
3422                 switch (value) {
3423                 case UHF_C_BH_PORT_RESET:
3424                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3425                         break;
3426                 case UHF_C_PORT_CONFIG_ERROR:
3427                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3428                         break;
3429                 case UHF_C_PORT_SUSPEND:
3430                 case UHF_C_PORT_LINK_STATE:
3431                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3432                         break;
3433                 case UHF_C_PORT_CONNECTION:
3434                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3435                         break;
3436                 case UHF_C_PORT_ENABLE:
3437                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3438                         break;
3439                 case UHF_C_PORT_OVER_CURRENT:
3440                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3441                         break;
3442                 case UHF_C_PORT_RESET:
3443                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3444                         break;
3445                 case UHF_PORT_ENABLE:
3446                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3447                         break;
3448                 case UHF_PORT_POWER:
3449                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3450                         break;
3451                 case UHF_PORT_INDICATOR:
3452                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3453                         break;
3454                 case UHF_PORT_SUSPEND:
3455
3456                         /* U3 -> U15 */
3457                         if (i == 3) {
3458                                 XWRITE4(sc, oper, port, v |
3459                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3460                         }
3461
3462                         /* wait 20ms for resume sequence to complete */
3463                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3464
3465                         /* U0 */
3466                         XWRITE4(sc, oper, port, v |
3467                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3468                         break;
3469                 default:
3470                         err = USB_ERR_IOERROR;
3471                         goto done;
3472                 }
3473                 break;
3474
3475         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3476                 if ((value & 0xff) != 0) {
3477                         err = USB_ERR_IOERROR;
3478                         goto done;
3479                 }
3480
3481                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3482
3483                 sc->sc_hub_desc.hubd = xhci_hubd;
3484
3485                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3486
3487                 if (XHCI_HCS0_PPC(v))
3488                         i = UHD_PWR_INDIVIDUAL;
3489                 else
3490                         i = UHD_PWR_GANGED;
3491
3492                 if (XHCI_HCS0_PIND(v))
3493                         i |= UHD_PORT_IND;
3494
3495                 i |= UHD_OC_INDIVIDUAL;
3496
3497                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3498
3499                 /* see XHCI section 5.4.9: */
3500                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3501
3502                 for (j = 1; j <= sc->sc_noport; j++) {
3503                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3504                         if (v & XHCI_PS_DR) {
3505                                 sc->sc_hub_desc.hubd.
3506                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3507                         }
3508                 }
3509                 len = sc->sc_hub_desc.hubd.bLength;
3510                 break;
3511
3512         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3513                 len = 16;
3514                 memset(sc->sc_hub_desc.temp, 0, 16);
3515                 break;
3516
3517         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3518                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3519
3520                 if ((index < 1) ||
3521                     (index > sc->sc_noport)) {
3522                         err = USB_ERR_IOERROR;
3523                         goto done;
3524                 }
3525
3526                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3527
3528                 DPRINTFN(9, "port status=0x%08x\n", v);
3529
3530                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3531
3532                 switch (XHCI_PS_SPEED_GET(v)) {
3533                 case 3:
3534                         i |= UPS_HIGH_SPEED;
3535                         break;
3536                 case 2:
3537                         i |= UPS_LOW_SPEED;
3538                         break;
3539                 case 1:
3540                         /* FULL speed */
3541                         break;
3542                 default:
3543                         i |= UPS_OTHER_SPEED;
3544                         break;
3545                 }
3546
3547                 if (v & XHCI_PS_CCS)
3548                         i |= UPS_CURRENT_CONNECT_STATUS;
3549                 if (v & XHCI_PS_PED)
3550                         i |= UPS_PORT_ENABLED;
3551                 if (v & XHCI_PS_OCA)
3552                         i |= UPS_OVERCURRENT_INDICATOR;
3553                 if (v & XHCI_PS_PR)
3554                         i |= UPS_RESET;
3555 #if 0
3556                 if (v & XHCI_PS_PP)
3557                         /* XXX undefined */
3558 #endif
3559                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3560
3561                 i = 0;
3562                 if (v & XHCI_PS_CSC)
3563                         i |= UPS_C_CONNECT_STATUS;
3564                 if (v & XHCI_PS_PEC)
3565                         i |= UPS_C_PORT_ENABLED;
3566                 if (v & XHCI_PS_OCC)
3567                         i |= UPS_C_OVERCURRENT_INDICATOR;
3568                 if (v & XHCI_PS_WRC)
3569                         i |= UPS_C_BH_PORT_RESET;
3570                 if (v & XHCI_PS_PRC)
3571                         i |= UPS_C_PORT_RESET;
3572                 if (v & XHCI_PS_PLC)
3573                         i |= UPS_C_PORT_LINK_STATE;
3574                 if (v & XHCI_PS_CEC)
3575                         i |= UPS_C_PORT_CONFIG_ERROR;
3576
3577                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3578                 len = sizeof(sc->sc_hub_desc.ps);
3579                 break;
3580
3581         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3582                 err = USB_ERR_IOERROR;
3583                 goto done;
3584
3585         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3586                 break;
3587
3588         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3589
3590                 i = index >> 8;
3591                 index &= 0x00FF;
3592
3593                 if ((index < 1) ||
3594                     (index > sc->sc_noport)) {
3595                         err = USB_ERR_IOERROR;
3596                         goto done;
3597                 }
3598
3599                 port = XHCI_PORTSC(index);
3600                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3601
3602                 switch (value) {
3603                 case UHF_PORT_U1_TIMEOUT:
3604                         if (XHCI_PS_SPEED_GET(v) != 4) {
3605                                 err = USB_ERR_IOERROR;
3606                                 goto done;
3607                         }
3608                         port = XHCI_PORTPMSC(index);
3609                         v = XREAD4(sc, oper, port);
3610                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3611                         v |= XHCI_PM3_U1TO_SET(i);
3612                         XWRITE4(sc, oper, port, v);
3613                         break;
3614                 case UHF_PORT_U2_TIMEOUT:
3615                         if (XHCI_PS_SPEED_GET(v) != 4) {
3616                                 err = USB_ERR_IOERROR;
3617                                 goto done;
3618                         }
3619                         port = XHCI_PORTPMSC(index);
3620                         v = XREAD4(sc, oper, port);
3621                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3622                         v |= XHCI_PM3_U2TO_SET(i);
3623                         XWRITE4(sc, oper, port, v);
3624                         break;
3625                 case UHF_BH_PORT_RESET:
3626                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3627                         break;
3628                 case UHF_PORT_LINK_STATE:
3629                         XWRITE4(sc, oper, port, v |
3630                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3631                         /* 4ms settle time */
3632                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3633                         break;
3634                 case UHF_PORT_ENABLE:
3635                         DPRINTFN(3, "set port enable %d\n", index);
3636                         break;
3637                 case UHF_PORT_SUSPEND:
3638                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3639                         j = XHCI_PS_SPEED_GET(v);
3640                         if ((j < 1) || (j > 3)) {
3641                                 /* non-supported speed */
3642                                 err = USB_ERR_IOERROR;
3643                                 goto done;
3644                         }
3645                         XWRITE4(sc, oper, port, v |
3646                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3647                         break;
3648                 case UHF_PORT_RESET:
3649                         DPRINTFN(6, "reset port %d\n", index);
3650                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3651                         break;
3652                 case UHF_PORT_POWER:
3653                         DPRINTFN(3, "set port power %d\n", index);
3654                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3655                         break;
3656                 case UHF_PORT_TEST:
3657                         DPRINTFN(3, "set port test %d\n", index);
3658                         break;
3659                 case UHF_PORT_INDICATOR:
3660                         DPRINTFN(3, "set port indicator %d\n", index);
3661
3662                         v &= ~XHCI_PS_PIC_SET(3);
3663                         v |= XHCI_PS_PIC_SET(1);
3664
3665                         XWRITE4(sc, oper, port, v);
3666                         break;
3667                 default:
3668                         err = USB_ERR_IOERROR;
3669                         goto done;
3670                 }
3671                 break;
3672
3673         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3674         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3675         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3676         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3677                 break;
3678         default:
3679                 err = USB_ERR_IOERROR;
3680                 goto done;
3681         }
3682 done:
3683         *plength = len;
3684         *pptr = ptr;
3685         return (err);
3686 }
3687
3688 static void
3689 xhci_xfer_setup(struct usb_setup_params *parm)
3690 {
3691         struct usb_page_search page_info;
3692         struct usb_page_cache *pc;
3693         struct usb_xfer *xfer;
3694         void *last_obj;
3695         uint32_t ntd;
3696         uint32_t n;
3697
3698         xfer = parm->curr_xfer;
3699
3700         /*
3701          * The proof for the "ntd" formula is illustrated like this:
3702          *
3703          * +------------------------------------+
3704          * |                                    |
3705          * |         |remainder ->              |
3706          * |   +-----+---+                      |
3707          * |   | xxx | x | frm 0                |
3708          * |   +-----+---++                     |
3709          * |   | xxx | xx | frm 1               |
3710          * |   +-----+----+                     |
3711          * |            ...                     |
3712          * +------------------------------------+
3713          *
3714          * "xxx" means a completely full USB transfer descriptor
3715          *
3716          * "x" and "xx" means a short USB packet
3717          *
3718          * For the remainder of an USB transfer modulo
3719          * "max_data_length" we need two USB transfer descriptors.
3720          * One to transfer the remaining data and one to finalise with
3721          * a zero length packet in case the "force_short_xfer" flag is
3722          * set. We only need two USB transfer descriptors in the case
3723          * where the transfer length of the first one is a factor of
3724          * "max_frame_size". The rest of the needed USB transfer
3725          * descriptors is given by the buffer size divided by the
3726          * maximum data payload.
3727          */
3728         parm->hc_max_packet_size = 0x400;
3729         parm->hc_max_packet_count = 16 * 3;
3730         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3731
3732         xfer->flags_int.bdma_enable = 1;
3733
3734         usbd_transfer_setup_sub(parm);
3735
3736         if (xfer->flags_int.isochronous_xfr) {
3737                 ntd = ((1 * xfer->nframes)
3738                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3739         } else if (xfer->flags_int.control_xfr) {
3740                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3741                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3742         } else {
3743                 ntd = ((2 * xfer->nframes)
3744                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3745         }
3746
3747 alloc_dma_set:
3748
3749         if (parm->err)
3750                 return;
3751
3752         /*
3753          * Allocate queue heads and transfer descriptors
3754          */
3755         last_obj = NULL;
3756
3757         if (usbd_transfer_setup_sub_malloc(
3758             parm, &pc, sizeof(struct xhci_td),
3759             XHCI_TD_ALIGN, ntd)) {
3760                 parm->err = USB_ERR_NOMEM;
3761                 return;
3762         }
3763         if (parm->buf) {
3764                 for (n = 0; n != ntd; n++) {
3765                         struct xhci_td *td;
3766
3767                         usbd_get_page(pc + n, 0, &page_info);
3768
3769                         td = page_info.buffer;
3770
3771                         /* init TD */
3772                         td->td_self = page_info.physaddr;
3773                         td->obj_next = last_obj;
3774                         td->page_cache = pc + n;
3775
3776                         last_obj = td;
3777
3778                         usb_pc_cpu_flush(pc + n);
3779                 }
3780         }
3781         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3782
3783         if (!xfer->flags_int.curr_dma_set) {
3784                 xfer->flags_int.curr_dma_set = 1;
3785                 goto alloc_dma_set;
3786         }
3787 }
3788
3789 static uint8_t
3790 xhci_get_endpoint_state(struct usb_device *udev, uint8_t epno)
3791 {
3792         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3793         struct usb_page_search buf_dev;
3794         struct xhci_hw_dev *hdev;
3795         struct xhci_dev_ctx *pdev;
3796         uint32_t temp;
3797
3798         MPASS(epno != 0);
3799
3800         hdev =  &sc->sc_hw.devs[udev->controller_slot_id];
3801
3802         usbd_get_page(&hdev->device_pc, 0, &buf_dev);
3803         pdev = buf_dev.buffer;
3804         usb_pc_cpu_invalidate(&hdev->device_pc);
3805
3806         temp = xhci_ctx_get_le32(sc, &pdev->ctx_ep[epno - 1].dwEpCtx0);
3807
3808         return (XHCI_EPCTX_0_EPSTATE_GET(temp));
3809 }
3810
3811 static usb_error_t
3812 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3813 {
3814         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3815         struct usb_page_search buf_inp;
3816         struct usb_device *udev;
3817         struct xhci_endpoint_ext *pepext;
3818         struct usb_endpoint_descriptor *edesc;
3819         struct usb_page_cache *pcinp;
3820         usb_error_t err;
3821         usb_stream_t stream_id;
3822         uint32_t mask;
3823         uint8_t index;
3824         uint8_t epno;
3825         uint8_t drop;
3826
3827         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3828             xfer->endpoint->edesc);
3829
3830         udev = xfer->xroot->udev;
3831         index = udev->controller_slot_id;
3832
3833         pcinp = &sc->sc_hw.devs[index].input_pc;
3834
3835         usbd_get_page(pcinp, 0, &buf_inp);
3836
3837         edesc = xfer->endpoint->edesc;
3838
3839         epno = edesc->bEndpointAddress;
3840         stream_id = xfer->stream_id;
3841
3842         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3843                 epno |= UE_DIR_IN;
3844
3845         epno = XHCI_EPNO2EPID(epno);
3846
3847         if (epno == 0)
3848                 return (USB_ERR_NO_PIPE);               /* invalid */
3849
3850         XHCI_CMD_LOCK(sc);
3851
3852         /* configure endpoint */
3853
3854         err = xhci_configure_endpoint_by_xfer(xfer);
3855
3856         if (err != 0) {
3857                 XHCI_CMD_UNLOCK(sc);
3858                 return (err);
3859         }
3860
3861         /*
3862          * Get the endpoint into the stopped state according to the
3863          * endpoint context state diagram in the XHCI specification:
3864          */
3865         switch (xhci_get_endpoint_state(udev, epno)) {
3866         case XHCI_EPCTX_0_EPSTATE_DISABLED:
3867                 drop = 0;
3868                 break;
3869         case XHCI_EPCTX_0_EPSTATE_STOPPED:
3870                 drop = 1;
3871                 break;
3872         case XHCI_EPCTX_0_EPSTATE_HALTED:
3873                 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3874                 drop = (err != 0);
3875                 if (drop)
3876                         DPRINTF("Could not reset endpoint %u\n", epno);
3877                 break;
3878         default:
3879                 drop = 1;
3880                 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3881                 if (err != 0)
3882                         DPRINTF("Could not stop endpoint %u\n", epno);
3883                 break;
3884         }
3885
3886         err = xhci_cmd_set_tr_dequeue_ptr(sc,
3887             (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3888             XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3889             stream_id, epno, index);
3890
3891         if (err != 0)
3892                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3893
3894         /*
3895          * Get the endpoint into the running state according to the
3896          * endpoint context state diagram in the XHCI specification:
3897          */
3898
3899         mask = (1U << epno);
3900
3901         /*
3902          * So-called control and isochronous transfer types have
3903          * predefined data toggles (USB 2.0) or sequence numbers (USB
3904          * 3.0) and does not need to be dropped.
3905          */
3906         if (drop != 0 &&
3907             (edesc->bmAttributes & UE_XFERTYPE) != UE_CONTROL &&
3908             (edesc->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS) {
3909                 /* drop endpoint context to reset data toggle value, if any. */
3910                 xhci_configure_mask(udev, mask, 1);
3911                 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3912                 if (err != 0) {
3913                         DPRINTF("Could not drop "
3914                             "endpoint %u at slot %u.\n", epno, index);
3915                 } else {
3916                         sc->sc_hw.devs[index].ep_configured &= ~mask;
3917                 }
3918         }
3919
3920         /*
3921          * Always need to evaluate the slot context, because the maximum
3922          * number of endpoint contexts is stored there.
3923          */
3924         xhci_configure_mask(udev, mask | 1U, 0);
3925
3926         if (!(sc->sc_hw.devs[index].ep_configured & mask)) {
3927                 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3928                 if (err == 0)
3929                         sc->sc_hw.devs[index].ep_configured |= mask;
3930         } else {
3931                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3932         }
3933
3934         if (err != 0) {
3935                 DPRINTF("Could not configure "
3936                     "endpoint %u at slot %u.\n", epno, index);
3937         }
3938         XHCI_CMD_UNLOCK(sc);
3939
3940         return (0);
3941 }
3942
3943 static void
3944 xhci_xfer_unsetup(struct usb_xfer *xfer)
3945 {
3946         return;
3947 }
3948
3949 static void
3950 xhci_start_dma_delay(struct usb_xfer *xfer)
3951 {
3952         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3953
3954         /* put transfer on interrupt queue (again) */
3955         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3956
3957         (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3958             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3959 }
3960
3961 static void
3962 xhci_configure_msg(struct usb_proc_msg *pm)
3963 {
3964         struct xhci_softc *sc;
3965         struct xhci_endpoint_ext *pepext;
3966         struct usb_xfer *xfer;
3967
3968         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3969
3970 restart:
3971         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3972                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3973                     xfer->endpoint->edesc);
3974
3975                 if ((pepext->trb_halted != 0) ||
3976                     (pepext->trb_running == 0)) {
3977                         uint16_t i;
3978
3979                         /* clear halted and running */
3980                         pepext->trb_halted = 0;
3981                         pepext->trb_running = 0;
3982
3983                         /* nuke remaining buffered transfers */
3984
3985                         for (i = 0; i != (XHCI_MAX_TRANSFERS *
3986                             XHCI_MAX_STREAMS); i++) {
3987                                 /*
3988                                  * NOTE: We need to use the timeout
3989                                  * error code here else existing
3990                                  * isochronous clients can get
3991                                  * confused:
3992                                  */
3993                                 if (pepext->xfer[i] != NULL) {
3994                                         xhci_device_done(pepext->xfer[i],
3995                                             USB_ERR_TIMEOUT);
3996                                 }
3997                         }
3998
3999                         /*
4000                          * NOTE: The USB transfer cannot vanish in
4001                          * this state!
4002                          */
4003
4004                         USB_BUS_UNLOCK(&sc->sc_bus);
4005
4006                         xhci_configure_reset_endpoint(xfer);
4007
4008                         USB_BUS_LOCK(&sc->sc_bus);
4009
4010                         /* check if halted is still cleared */
4011                         if (pepext->trb_halted == 0) {
4012                                 pepext->trb_running = 1;
4013                                 memset(pepext->trb_index, 0,
4014                                     sizeof(pepext->trb_index));
4015                         }
4016                         goto restart;
4017                 }
4018
4019                 if (xfer->flags_int.did_dma_delay) {
4020                         /* remove transfer from interrupt queue (again) */
4021                         usbd_transfer_dequeue(xfer);
4022
4023                         /* we are finally done */
4024                         usb_dma_delay_done_cb(xfer);
4025
4026                         /* queue changed - restart */
4027                         goto restart;
4028                 }
4029         }
4030
4031         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
4032                 /* try to insert xfer on HW queue */
4033                 xhci_transfer_insert(xfer);
4034
4035                 /* try to multi buffer */
4036                 xhci_device_generic_multi_enter(xfer->endpoint,
4037                     xfer->stream_id, NULL);
4038         }
4039 }
4040
4041 static void
4042 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4043     struct usb_endpoint *ep)
4044 {
4045         struct xhci_endpoint_ext *pepext;
4046         struct xhci_softc *sc;
4047         uint8_t index;
4048         uint8_t epno;
4049
4050         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4051             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4052
4053         if (udev->parent_hub == NULL) {
4054                 /* root HUB has special endpoint handling */
4055                 return;
4056         }
4057
4058         ep->methods = &xhci_device_generic_methods;
4059
4060         pepext = xhci_get_endpoint_ext(udev, edesc);
4061
4062         USB_BUS_LOCK(udev->bus);
4063         pepext->trb_halted = 1;
4064         pepext->trb_running = 0;
4065
4066         /*
4067          * When doing an alternate setting, except for control
4068          * endpoints, we need to re-configure the XHCI endpoint
4069          * context:
4070          */
4071         if ((edesc->bEndpointAddress & UE_ADDR) != 0) {
4072                 sc = XHCI_BUS2SC(udev->bus);
4073                 index = udev->controller_slot_id;
4074                 epno = XHCI_EPNO2EPID(edesc->bEndpointAddress);
4075                 sc->sc_hw.devs[index].ep_configured &= ~(1U << epno);
4076         }
4077         USB_BUS_UNLOCK(udev->bus);
4078 }
4079
4080 static void
4081 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4082 {
4083
4084 }
4085
4086 static void
4087 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4088 {
4089         struct xhci_endpoint_ext *pepext;
4090
4091         DPRINTF("\n");
4092
4093         if (udev->flags.usb_mode != USB_MODE_HOST) {
4094                 /* not supported */
4095                 return;
4096         }
4097         if (udev->parent_hub == NULL) {
4098                 /* root HUB has special endpoint handling */
4099                 return;
4100         }
4101
4102         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4103
4104         USB_BUS_LOCK(udev->bus);
4105         pepext->trb_halted = 1;
4106         pepext->trb_running = 0;
4107         USB_BUS_UNLOCK(udev->bus);
4108 }
4109
4110 static usb_error_t
4111 xhci_device_init(struct usb_device *udev)
4112 {
4113         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4114         usb_error_t err;
4115         uint8_t temp;
4116
4117         /* no init for root HUB */
4118         if (udev->parent_hub == NULL)
4119                 return (0);
4120
4121         XHCI_CMD_LOCK(sc);
4122
4123         /* set invalid default */
4124
4125         udev->controller_slot_id = sc->sc_noslot + 1;
4126
4127         /* try to get a new slot ID from the XHCI */
4128
4129         err = xhci_cmd_enable_slot(sc, &temp);
4130
4131         if (err) {
4132                 XHCI_CMD_UNLOCK(sc);
4133                 return (err);
4134         }
4135
4136         if (temp > sc->sc_noslot) {
4137                 XHCI_CMD_UNLOCK(sc);
4138                 return (USB_ERR_BAD_ADDRESS);
4139         }
4140
4141         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4142                 DPRINTF("slot %u already allocated.\n", temp);
4143                 XHCI_CMD_UNLOCK(sc);
4144                 return (USB_ERR_BAD_ADDRESS);
4145         }
4146
4147         /* store slot ID for later reference */
4148
4149         udev->controller_slot_id = temp;
4150
4151         /* reset data structure */
4152
4153         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4154
4155         /* set mark slot allocated */
4156
4157         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4158
4159         err = xhci_alloc_device_ext(udev);
4160
4161         XHCI_CMD_UNLOCK(sc);
4162
4163         /* get device into default state */
4164
4165         if (err == 0)
4166                 err = xhci_set_address(udev, NULL, 0);
4167
4168         return (err);
4169 }
4170
4171 static void
4172 xhci_device_uninit(struct usb_device *udev)
4173 {
4174         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4175         uint8_t index;
4176
4177         /* no init for root HUB */
4178         if (udev->parent_hub == NULL)
4179                 return;
4180
4181         XHCI_CMD_LOCK(sc);
4182
4183         index = udev->controller_slot_id;
4184
4185         if (index <= sc->sc_noslot) {
4186                 xhci_cmd_disable_slot(sc, index);
4187                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4188
4189                 /* free device extension */
4190                 xhci_free_device_ext(udev);
4191         }
4192
4193         XHCI_CMD_UNLOCK(sc);
4194 }
4195
4196 static void
4197 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4198 {
4199         /*
4200          * Wait until the hardware has finished any possible use of
4201          * the transfer descriptor(s)
4202          */
4203         *pus = 2048;                    /* microseconds */
4204 }
4205
4206 static void
4207 xhci_device_resume(struct usb_device *udev)
4208 {
4209         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4210         uint8_t index;
4211         uint8_t n;
4212         uint8_t p;
4213
4214         DPRINTF("\n");
4215
4216         /* check for root HUB */
4217         if (udev->parent_hub == NULL)
4218                 return;
4219
4220         index = udev->controller_slot_id;
4221
4222         XHCI_CMD_LOCK(sc);
4223
4224         /* blindly resume all endpoints */
4225
4226         USB_BUS_LOCK(udev->bus);
4227
4228         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4229                 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4230                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4231                             n | XHCI_DB_SID_SET(p));
4232                 }
4233         }
4234
4235         USB_BUS_UNLOCK(udev->bus);
4236
4237         XHCI_CMD_UNLOCK(sc);
4238 }
4239
4240 static void
4241 xhci_device_suspend(struct usb_device *udev)
4242 {
4243         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4244         uint8_t index;
4245         uint8_t n;
4246         usb_error_t err;
4247
4248         DPRINTF("\n");
4249
4250         /* check for root HUB */
4251         if (udev->parent_hub == NULL)
4252                 return;
4253
4254         index = udev->controller_slot_id;
4255
4256         XHCI_CMD_LOCK(sc);
4257
4258         /* blindly suspend all endpoints */
4259
4260         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4261                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4262                 if (err != 0) {
4263                         DPRINTF("Failed to suspend endpoint "
4264                             "%u on slot %u (ignored).\n", n, index);
4265                 }
4266         }
4267
4268         XHCI_CMD_UNLOCK(sc);
4269 }
4270
4271 static void
4272 xhci_set_hw_power(struct usb_bus *bus)
4273 {
4274         DPRINTF("\n");
4275 }
4276
4277 static void
4278 xhci_device_state_change(struct usb_device *udev)
4279 {
4280         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4281         struct usb_page_search buf_inp;
4282         usb_error_t err;
4283         uint8_t index;
4284
4285         /* check for root HUB */
4286         if (udev->parent_hub == NULL)
4287                 return;
4288
4289         index = udev->controller_slot_id;
4290
4291         DPRINTF("\n");
4292
4293         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4294                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4295                     &sc->sc_hw.devs[index].tt);
4296                 if (err != 0)
4297                         sc->sc_hw.devs[index].nports = 0;
4298         }
4299
4300         XHCI_CMD_LOCK(sc);
4301
4302         switch (usb_get_device_state(udev)) {
4303         case USB_STATE_POWERED:
4304                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4305                         break;
4306
4307                 /* set default state */
4308                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4309                 sc->sc_hw.devs[index].ep_configured = 3U;
4310
4311                 /* reset number of contexts */
4312                 sc->sc_hw.devs[index].context_num = 0;
4313
4314                 err = xhci_cmd_reset_dev(sc, index);
4315
4316                 if (err != 0) {
4317                         DPRINTF("Device reset failed "
4318                             "for slot %u.\n", index);
4319                 }
4320                 break;
4321
4322         case USB_STATE_ADDRESSED:
4323                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4324                         break;
4325
4326                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4327                 sc->sc_hw.devs[index].ep_configured = 3U;
4328
4329                 /* set configure mask to slot only */
4330                 xhci_configure_mask(udev, 1, 0);
4331
4332                 /* deconfigure all endpoints, except EP0 */
4333                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4334
4335                 if (err) {
4336                         DPRINTF("Failed to deconfigure "
4337                             "slot %u.\n", index);
4338                 }
4339                 break;
4340
4341         case USB_STATE_CONFIGURED:
4342                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) {
4343                         /* deconfigure all endpoints, except EP0 */
4344                         err = xhci_cmd_configure_ep(sc, 0, 1, index);
4345
4346                         if (err) {
4347                                 DPRINTF("Failed to deconfigure "
4348                                     "slot %u.\n", index);
4349                         }
4350                 }
4351
4352                 /* set configured state */
4353                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4354                 sc->sc_hw.devs[index].ep_configured = 3U;
4355
4356                 /* reset number of contexts */
4357                 sc->sc_hw.devs[index].context_num = 0;
4358
4359                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4360
4361                 xhci_configure_mask(udev, 3, 0);
4362
4363                 err = xhci_configure_device(udev);
4364                 if (err != 0) {
4365                         DPRINTF("Could not configure device "
4366                             "at slot %u.\n", index);
4367                 }
4368
4369                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4370                 if (err != 0) {
4371                         DPRINTF("Could not evaluate device "
4372                             "context at slot %u.\n", index);
4373                 }
4374                 break;
4375
4376         default:
4377                 break;
4378         }
4379         XHCI_CMD_UNLOCK(sc);
4380 }
4381
4382 static usb_error_t
4383 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4384     uint8_t ep_mode)
4385 {
4386         switch (ep_mode) {
4387         case USB_EP_MODE_DEFAULT:
4388                 return (0);
4389         case USB_EP_MODE_STREAMS:
4390                 if (xhcistreams == 0 ||
4391                     (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4392                     udev->speed != USB_SPEED_SUPER)
4393                         return (USB_ERR_INVAL);
4394                 return (0);
4395         default:
4396                 return (USB_ERR_INVAL);
4397         }
4398 }
4399
4400 static const struct usb_bus_methods xhci_bus_methods = {
4401         .endpoint_init = xhci_ep_init,
4402         .endpoint_uninit = xhci_ep_uninit,
4403         .xfer_setup = xhci_xfer_setup,
4404         .xfer_unsetup = xhci_xfer_unsetup,
4405         .get_dma_delay = xhci_get_dma_delay,
4406         .device_init = xhci_device_init,
4407         .device_uninit = xhci_device_uninit,
4408         .device_resume = xhci_device_resume,
4409         .device_suspend = xhci_device_suspend,
4410         .set_hw_power = xhci_set_hw_power,
4411         .roothub_exec = xhci_roothub_exec,
4412         .xfer_poll = xhci_do_poll,
4413         .start_dma_delay = xhci_start_dma_delay,
4414         .set_address = xhci_set_address,
4415         .clear_stall = xhci_ep_clear_stall,
4416         .device_state_change = xhci_device_state_change,
4417         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4418         .set_endpoint_mode = xhci_set_endpoint_mode,
4419 };