3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
30 * The XHCI 1.0 spec can be found at
31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
32 * and the USB 3.0 spec at
33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
37 * A few words about the design implementation: This driver emulates
38 * the concept about TDs which is found in EHCI specification. This
39 * way we achieve that the USB controller drivers look similar to
40 * eachother which makes it easier to understand the code.
43 #ifdef USB_GLOBAL_INCLUDE_FILE
44 #include USB_GLOBAL_INCLUDE_FILE
46 #include <sys/stdint.h>
47 #include <sys/stddef.h>
48 #include <sys/param.h>
49 #include <sys/queue.h>
50 #include <sys/types.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
54 #include <sys/module.h>
56 #include <sys/mutex.h>
57 #include <sys/condvar.h>
58 #include <sys/sysctl.h>
60 #include <sys/unistd.h>
61 #include <sys/callout.h>
62 #include <sys/malloc.h>
65 #include <dev/usb/usb.h>
66 #include <dev/usb/usbdi.h>
68 #define USB_DEBUG_VAR xhcidebug
70 #include <dev/usb/usb_core.h>
71 #include <dev/usb/usb_debug.h>
72 #include <dev/usb/usb_busdma.h>
73 #include <dev/usb/usb_process.h>
74 #include <dev/usb/usb_transfer.h>
75 #include <dev/usb/usb_device.h>
76 #include <dev/usb/usb_hub.h>
77 #include <dev/usb/usb_util.h>
79 #include <dev/usb/usb_controller.h>
80 #include <dev/usb/usb_bus.h>
81 #endif /* USB_GLOBAL_INCLUDE_FILE */
83 #include <dev/usb/controller/xhci.h>
84 #include <dev/usb/controller/xhcireg.h>
86 #define XHCI_BUS2SC(bus) \
87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
92 static int xhcistreams;
93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN,
94 &xhcistreams, 0, "Set to enable streams mode support");
99 static int xhcipolling;
100 static int xhcidma32;
102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN,
103 &xhcidebug, 0, "Debug level");
104 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN,
105 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
106 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN,
107 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
109 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
115 #define XHCI_INTR_ENDPT 1
117 struct xhci_std_temp {
118 struct xhci_softc *sc;
119 struct usb_page_cache *pc;
121 struct xhci_td *td_next;
124 uint32_t max_packet_size;
136 uint8_t do_isoc_sync;
139 static void xhci_do_poll(struct usb_bus *);
140 static void xhci_device_done(struct usb_xfer *, usb_error_t);
141 static void xhci_root_intr(struct xhci_softc *);
142 static void xhci_free_device_ext(struct usb_device *);
143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
144 struct usb_endpoint_descriptor *);
145 static usb_proc_callback_t xhci_configure_msg;
146 static usb_error_t xhci_configure_device(struct usb_device *);
147 static usb_error_t xhci_configure_endpoint(struct usb_device *,
148 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
149 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
151 static usb_error_t xhci_configure_mask(struct usb_device *,
153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
155 static void xhci_endpoint_doorbell(struct usb_xfer *);
156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
163 static const struct usb_bus_methods xhci_bus_methods;
167 xhci_dump_trb(struct xhci_trb *trb)
169 DPRINTFN(5, "trb = %p\n", trb);
170 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
171 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
172 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
178 DPRINTFN(5, "pep = %p\n", pep);
179 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
180 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
181 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
182 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
183 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
184 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
185 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
191 DPRINTFN(5, "psl = %p\n", psl);
192 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
193 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
194 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
195 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
200 xhci_use_polling(void)
203 return (xhcipolling != 0);
210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
212 struct xhci_softc *sc = XHCI_BUS2SC(bus);
215 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
216 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
218 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
219 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
221 for (i = 0; i != sc->sc_noscratch; i++) {
222 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
223 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
230 if (sc->sc_ctx_is_64_byte) {
232 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
233 /* all contexts are initially 32-bytes */
234 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
235 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
243 if (sc->sc_ctx_is_64_byte) {
245 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
246 /* all contexts are initially 32-bytes */
247 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
248 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
250 return (le32toh(*ptr));
254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
256 if (sc->sc_ctx_is_64_byte) {
258 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
259 /* all contexts are initially 32-bytes */
260 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
261 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
270 if (sc->sc_ctx_is_64_byte) {
272 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
273 /* all contexts are initially 32-bytes */
274 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
275 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
277 return (le64toh(*ptr));
282 xhci_reset_command_queue_locked(struct xhci_softc *sc)
284 struct usb_page_search buf_res;
285 struct xhci_hw_root *phwr;
291 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
292 if (temp & XHCI_CRCR_LO_CRR) {
293 DPRINTF("Command ring running\n");
294 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
297 * Try to abort the last command as per section
298 * 4.6.1.2 "Aborting a Command" of the XHCI
302 /* stop and cancel */
303 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
304 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
306 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
307 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
310 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
312 /* check if command ring is still running */
313 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
314 if (temp & XHCI_CRCR_LO_CRR) {
315 DPRINTF("Comand ring still running\n");
316 return (USB_ERR_IOERROR);
320 /* reset command ring */
321 sc->sc_command_ccs = 1;
322 sc->sc_command_idx = 0;
324 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
326 /* set up command ring control base address */
327 addr = buf_res.physaddr;
328 phwr = buf_res.buffer;
329 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
331 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
333 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
334 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
336 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
338 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
339 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
345 xhci_start_controller(struct xhci_softc *sc)
347 struct usb_page_search buf_res;
348 struct xhci_hw_root *phwr;
349 struct xhci_dev_ctx_addr *pdctxa;
357 sc->sc_event_ccs = 1;
358 sc->sc_event_idx = 0;
359 sc->sc_command_ccs = 1;
360 sc->sc_command_idx = 0;
362 err = xhci_reset_controller(sc);
366 /* set up number of device slots */
367 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
368 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
370 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
372 temp = XREAD4(sc, oper, XHCI_USBSTS);
374 /* clear interrupts */
375 XWRITE4(sc, oper, XHCI_USBSTS, temp);
376 /* disable all device notifications */
377 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
379 /* set up device context base address */
380 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
381 pdctxa = buf_res.buffer;
382 memset(pdctxa, 0, sizeof(*pdctxa));
384 addr = buf_res.physaddr;
385 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
387 /* slot 0 points to the table of scratchpad pointers */
388 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
390 for (i = 0; i != sc->sc_noscratch; i++) {
391 struct usb_page_search buf_scp;
392 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
393 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
396 addr = buf_res.physaddr;
398 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
399 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
400 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
401 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
403 /* set up event table size */
404 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
405 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
407 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
409 /* set up interrupt rate */
410 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
412 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
414 phwr = buf_res.buffer;
415 addr = buf_res.physaddr;
416 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
418 /* reset hardware root structure */
419 memset(phwr, 0, sizeof(*phwr));
421 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
422 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
424 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
426 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
427 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
429 addr = buf_res.physaddr;
431 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
433 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
434 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
436 /* set up interrupter registers */
437 temp = XREAD4(sc, runt, XHCI_IMAN(0));
438 temp |= XHCI_IMAN_INTR_ENA;
439 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
441 /* set up command ring control base address */
442 addr = buf_res.physaddr;
443 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
445 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
447 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
448 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
450 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
452 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
455 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
456 XHCI_CMD_INTE | XHCI_CMD_HSEE);
458 for (i = 0; i != 100; i++) {
459 usb_pause_mtx(NULL, hz / 100);
460 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
465 XWRITE4(sc, oper, XHCI_USBCMD, 0);
466 device_printf(sc->sc_bus.parent, "Run timeout.\n");
467 return (USB_ERR_IOERROR);
470 /* catch any lost interrupts */
471 xhci_do_poll(&sc->sc_bus);
473 if (sc->sc_port_route != NULL) {
474 /* Route all ports to the XHCI by default */
475 sc->sc_port_route(sc->sc_bus.parent,
476 ~xhciroute, xhciroute);
482 xhci_halt_controller(struct xhci_softc *sc)
490 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
491 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
492 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
494 /* Halt controller */
495 XWRITE4(sc, oper, XHCI_USBCMD, 0);
497 for (i = 0; i != 100; i++) {
498 usb_pause_mtx(NULL, hz / 100);
499 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
505 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
506 return (USB_ERR_IOERROR);
512 xhci_reset_controller(struct xhci_softc *sc)
519 /* Reset controller */
520 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
522 for (i = 0; i != 100; i++) {
523 usb_pause_mtx(NULL, hz / 100);
524 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
525 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
531 device_printf(sc->sc_bus.parent, "Controller "
533 return (USB_ERR_IOERROR);
539 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
545 /* initialize some bus fields */
546 sc->sc_bus.parent = self;
548 /* set the bus revision */
549 sc->sc_bus.usbrev = USB_REV_3_0;
551 /* set up the bus struct */
552 sc->sc_bus.methods = &xhci_bus_methods;
554 /* set up devices array */
555 sc->sc_bus.devices = sc->sc_devices;
556 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
558 /* set default cycle state in case of early interrupts */
559 sc->sc_event_ccs = 1;
560 sc->sc_command_ccs = 1;
562 /* set up bus space offsets */
564 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
565 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
566 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
568 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
569 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
570 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
572 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
574 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
575 device_printf(sc->sc_bus.parent, "Controller does "
576 "not support 4K page size.\n");
580 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
582 DPRINTF("HCS0 = 0x%08x\n", temp);
584 /* set up context size */
585 if (XHCI_HCS0_CSZ(temp)) {
586 sc->sc_ctx_is_64_byte = 1;
588 sc->sc_ctx_is_64_byte = 0;
592 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
593 xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
595 device_printf(self, "%d bytes context size, %d-bit DMA\n",
596 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
598 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
600 /* get number of device slots */
601 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
603 if (sc->sc_noport == 0) {
604 device_printf(sc->sc_bus.parent, "Invalid number "
605 "of ports: %u\n", sc->sc_noport);
609 sc->sc_noport = sc->sc_noport;
610 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
612 DPRINTF("Max slots: %u\n", sc->sc_noslot);
614 if (sc->sc_noslot > XHCI_MAX_DEVICES)
615 sc->sc_noslot = XHCI_MAX_DEVICES;
617 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
619 DPRINTF("HCS2=0x%08x\n", temp);
621 /* get number of scratchpads */
622 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
624 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
625 device_printf(sc->sc_bus.parent, "XHCI request "
626 "too many scratchpads\n");
630 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
632 /* get event table size */
633 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
634 if (sc->sc_erst_max > XHCI_MAX_RSEG)
635 sc->sc_erst_max = XHCI_MAX_RSEG;
637 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
639 /* get maximum exit latency */
640 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
641 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
643 /* Check if we should use the default IMOD value. */
644 if (sc->sc_imod_default == 0)
645 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
647 /* get all DMA memory */
648 if (usb_bus_mem_alloc_all(&sc->sc_bus,
649 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
653 /* set up command queue mutex and condition varible */
654 cv_init(&sc->sc_cmd_cv, "CMDQ");
655 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
657 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
658 sc->sc_config_msg[0].bus = &sc->sc_bus;
659 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
660 sc->sc_config_msg[1].bus = &sc->sc_bus;
666 xhci_uninit(struct xhci_softc *sc)
669 * NOTE: At this point the control transfer process is gone
670 * and "xhci_configure_msg" is no longer called. Consequently
671 * waiting for the configuration messages to complete is not
674 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
676 cv_destroy(&sc->sc_cmd_cv);
677 sx_destroy(&sc->sc_cmd_sx);
681 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
683 struct xhci_softc *sc = XHCI_BUS2SC(bus);
686 case USB_HW_POWER_SUSPEND:
687 DPRINTF("Stopping the XHCI\n");
688 xhci_halt_controller(sc);
689 xhci_reset_controller(sc);
691 case USB_HW_POWER_SHUTDOWN:
692 DPRINTF("Stopping the XHCI\n");
693 xhci_halt_controller(sc);
694 xhci_reset_controller(sc);
696 case USB_HW_POWER_RESUME:
697 DPRINTF("Starting the XHCI\n");
698 xhci_start_controller(sc);
706 xhci_generic_done_sub(struct usb_xfer *xfer)
709 struct xhci_td *td_alt_next;
713 td = xfer->td_transfer_cache;
714 td_alt_next = td->alt_next;
716 if (xfer->aframes != xfer->nframes)
717 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
721 usb_pc_cpu_invalidate(td->page_cache);
726 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
727 xfer, (unsigned int)xfer->aframes,
728 (unsigned int)xfer->nframes,
729 (unsigned int)len, (unsigned int)td->len,
730 (unsigned int)status);
733 * Verify the status length and
734 * add the length to "frlengths[]":
737 /* should not happen */
738 DPRINTF("Invalid status length, "
739 "0x%04x/0x%04x bytes\n", len, td->len);
740 status = XHCI_TRB_ERROR_LENGTH;
741 } else if (xfer->aframes != xfer->nframes) {
742 xfer->frlengths[xfer->aframes] += td->len - len;
744 /* Check for last transfer */
745 if (((void *)td) == xfer->td_transfer_last) {
749 /* Check for transfer error */
750 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
751 status != XHCI_TRB_ERROR_SUCCESS) {
752 /* the transfer is finished */
756 /* Check for short transfer */
758 if (xfer->flags_int.short_frames_ok ||
759 xfer->flags_int.isochronous_xfr ||
760 xfer->flags_int.control_xfr) {
761 /* follow alt next */
764 /* the transfer is finished */
771 if (td->alt_next != td_alt_next) {
772 /* this USB frame is complete */
777 /* update transfer cache */
779 xfer->td_transfer_cache = td;
781 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
782 (status != XHCI_TRB_ERROR_SHORT_PKT &&
783 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
784 USB_ERR_NORMAL_COMPLETION);
788 xhci_generic_done(struct usb_xfer *xfer)
792 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
793 xfer, xfer->endpoint);
797 xfer->td_transfer_cache = xfer->td_transfer_first;
799 if (xfer->flags_int.control_xfr) {
801 if (xfer->flags_int.control_hdr)
802 err = xhci_generic_done_sub(xfer);
806 if (xfer->td_transfer_cache == NULL)
810 while (xfer->aframes != xfer->nframes) {
812 err = xhci_generic_done_sub(xfer);
815 if (xfer->td_transfer_cache == NULL)
819 if (xfer->flags_int.control_xfr &&
820 !xfer->flags_int.control_act)
821 err = xhci_generic_done_sub(xfer);
823 /* transfer is complete */
824 xhci_device_done(xfer, err);
828 xhci_activate_transfer(struct usb_xfer *xfer)
832 td = xfer->td_transfer_cache;
834 usb_pc_cpu_invalidate(td->page_cache);
836 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
838 /* activate the transfer */
840 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
841 usb_pc_cpu_flush(td->page_cache);
843 xhci_endpoint_doorbell(xfer);
848 xhci_skip_transfer(struct usb_xfer *xfer)
851 struct xhci_td *td_last;
853 td = xfer->td_transfer_cache;
854 td_last = xfer->td_transfer_last;
858 usb_pc_cpu_invalidate(td->page_cache);
860 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
862 usb_pc_cpu_invalidate(td_last->page_cache);
864 /* copy LINK TRB to current waiting location */
866 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
867 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
868 usb_pc_cpu_flush(td->page_cache);
870 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
871 usb_pc_cpu_flush(td->page_cache);
873 xhci_endpoint_doorbell(xfer);
877 /*------------------------------------------------------------------------*
878 * xhci_check_transfer
879 *------------------------------------------------------------------------*/
881 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
883 struct xhci_endpoint_ext *pepext;
896 td_event = le64toh(trb->qwTrb0);
897 temp = le32toh(trb->dwTrb2);
899 remainder = XHCI_TRB_2_REM_GET(temp);
900 status = XHCI_TRB_2_ERROR_GET(temp);
901 stream_id = XHCI_TRB_2_STREAM_GET(temp);
903 temp = le32toh(trb->dwTrb3);
904 epno = XHCI_TRB_3_EP_GET(temp);
905 index = XHCI_TRB_3_SLOT_GET(temp);
907 /* check if error means halted */
908 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
909 status != XHCI_TRB_ERROR_SUCCESS);
911 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
912 index, epno, stream_id, remainder, status);
914 if (index > sc->sc_noslot) {
915 DPRINTF("Invalid slot.\n");
919 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
920 DPRINTF("Invalid endpoint.\n");
924 pepext = &sc->sc_hw.devs[index].endp[epno];
926 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
928 DPRINTF("stream_id=0\n");
929 } else if (stream_id >= XHCI_MAX_STREAMS) {
930 DPRINTF("Invalid stream ID.\n");
934 /* try to find the USB transfer that generated the event */
935 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
936 struct usb_xfer *xfer;
939 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
943 td = xfer->td_transfer_cache;
945 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
947 (long long)td->td_self,
948 (long long)td->td_self + sizeof(td->td_trb));
951 * NOTE: Some XHCI implementations might not trigger
952 * an event on the last LINK TRB so we need to
953 * consider both the last and second last event
954 * address as conditions for a successful transfer.
956 * NOTE: We assume that the XHCI will only trigger one
957 * event per chain of TRBs.
960 offset = td_event - td->td_self;
963 offset < (int64_t)sizeof(td->td_trb)) {
965 usb_pc_cpu_invalidate(td->page_cache);
967 /* compute rest of remainder, if any */
968 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
969 temp = le32toh(td->td_trb[i].dwTrb2);
970 remainder += XHCI_TRB_2_BYTES_GET(temp);
973 DPRINTFN(5, "New remainder: %u\n", remainder);
975 /* clear isochronous transfer errors */
976 if (xfer->flags_int.isochronous_xfr) {
979 status = XHCI_TRB_ERROR_SUCCESS;
984 /* "td->remainder" is verified later */
985 td->remainder = remainder;
988 usb_pc_cpu_flush(td->page_cache);
991 * 1) Last transfer descriptor makes the
994 if (((void *)td) == xfer->td_transfer_last) {
995 DPRINTF("TD is last\n");
996 xhci_generic_done(xfer);
1001 * 2) Any kind of error makes the transfer
1005 DPRINTF("TD has I/O error\n");
1006 xhci_generic_done(xfer);
1011 * 3) If there is no alternate next transfer,
1012 * a short packet also makes the transfer done
1014 if (td->remainder > 0) {
1015 if (td->alt_next == NULL) {
1017 "short TD has no alternate next\n");
1018 xhci_generic_done(xfer);
1021 DPRINTF("TD has short pkt\n");
1022 if (xfer->flags_int.short_frames_ok ||
1023 xfer->flags_int.isochronous_xfr ||
1024 xfer->flags_int.control_xfr) {
1025 /* follow the alt next */
1026 xfer->td_transfer_cache = td->alt_next;
1027 xhci_activate_transfer(xfer);
1030 xhci_skip_transfer(xfer);
1031 xhci_generic_done(xfer);
1036 * 4) Transfer complete - go to next TD
1038 DPRINTF("Following next TD\n");
1039 xfer->td_transfer_cache = td->obj_next;
1040 xhci_activate_transfer(xfer);
1041 break; /* there should only be one match */
1047 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1049 if (sc->sc_cmd_addr == trb->qwTrb0) {
1050 DPRINTF("Received command event\n");
1051 sc->sc_cmd_result[0] = trb->dwTrb2;
1052 sc->sc_cmd_result[1] = trb->dwTrb3;
1053 cv_signal(&sc->sc_cmd_cv);
1054 return (1); /* command match */
1060 xhci_interrupt_poll(struct xhci_softc *sc)
1062 struct usb_page_search buf_res;
1063 struct xhci_hw_root *phwr;
1073 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1075 phwr = buf_res.buffer;
1077 /* Receive any events */
1079 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1081 i = sc->sc_event_idx;
1082 j = sc->sc_event_ccs;
1087 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1089 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1094 event = XHCI_TRB_3_TYPE_GET(temp);
1096 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1097 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1098 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1099 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1102 case XHCI_TRB_EVENT_TRANSFER:
1103 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1105 case XHCI_TRB_EVENT_CMD_COMPLETE:
1106 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1109 DPRINTF("Unhandled event = %u\n", event);
1115 if (i == XHCI_MAX_EVENTS) {
1119 /* check for timeout */
1125 sc->sc_event_idx = i;
1126 sc->sc_event_ccs = j;
1129 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1130 * latched. That means to activate the register we need to
1131 * write both the low and high double word of the 64-bit
1135 addr = buf_res.physaddr;
1136 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1138 /* try to clear busy bit */
1139 addr |= XHCI_ERDP_LO_BUSY;
1141 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1142 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1148 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1149 uint16_t timeout_ms)
1151 struct usb_page_search buf_res;
1152 struct xhci_hw_root *phwr;
1157 uint8_t timeout = 0;
1160 XHCI_CMD_ASSERT_LOCKED(sc);
1162 /* get hardware root structure */
1164 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1166 phwr = buf_res.buffer;
1170 USB_BUS_LOCK(&sc->sc_bus);
1172 i = sc->sc_command_idx;
1173 j = sc->sc_command_ccs;
1175 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1176 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1177 (long long)le64toh(trb->qwTrb0),
1178 (long)le32toh(trb->dwTrb2),
1179 (long)le32toh(trb->dwTrb3));
1181 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1182 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1184 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1189 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1191 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1193 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1195 phwr->hwr_commands[i].dwTrb3 = temp;
1197 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1199 addr = buf_res.physaddr;
1200 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1202 sc->sc_cmd_addr = htole64(addr);
1206 if (i == (XHCI_MAX_COMMANDS - 1)) {
1209 temp = htole32(XHCI_TRB_3_TC_BIT |
1210 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1211 XHCI_TRB_3_CYCLE_BIT);
1213 temp = htole32(XHCI_TRB_3_TC_BIT |
1214 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1217 phwr->hwr_commands[i].dwTrb3 = temp;
1219 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1225 sc->sc_command_idx = i;
1226 sc->sc_command_ccs = j;
1228 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1230 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1231 USB_MS_TO_TICKS(timeout_ms));
1234 * In some error cases event interrupts are not generated.
1235 * Poll one time to see if the command has completed.
1237 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1238 DPRINTF("Command was completed when polling\n");
1242 DPRINTF("Command timeout!\n");
1244 * After some weeks of continuous operation, it has
1245 * been observed that the ASMedia Technology, ASM1042
1246 * SuperSpeed USB Host Controller can suddenly stop
1247 * accepting commands via the command queue. Try to
1248 * first reset the command queue. If that fails do a
1249 * host controller reset.
1252 xhci_reset_command_queue_locked(sc) == 0) {
1253 temp = le32toh(trb->dwTrb3);
1256 * Avoid infinite XHCI reset loops if the set
1257 * address command fails to respond due to a
1258 * non-enumerating device:
1260 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1261 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1262 DPRINTF("Set address timeout\n");
1268 DPRINTF("Controller reset!\n");
1269 usb_bus_reset_async_locked(&sc->sc_bus);
1271 err = USB_ERR_TIMEOUT;
1275 temp = le32toh(sc->sc_cmd_result[0]);
1276 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1277 err = USB_ERR_IOERROR;
1279 trb->dwTrb2 = sc->sc_cmd_result[0];
1280 trb->dwTrb3 = sc->sc_cmd_result[1];
1283 USB_BUS_UNLOCK(&sc->sc_bus);
1290 xhci_cmd_nop(struct xhci_softc *sc)
1292 struct xhci_trb trb;
1299 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1301 trb.dwTrb3 = htole32(temp);
1303 return (xhci_do_command(sc, &trb, 100 /* ms */));
1308 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1310 struct xhci_trb trb;
1318 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1320 err = xhci_do_command(sc, &trb, 100 /* ms */);
1324 temp = le32toh(trb.dwTrb3);
1326 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1333 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1335 struct xhci_trb trb;
1342 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1343 XHCI_TRB_3_SLOT_SET(slot_id);
1345 trb.dwTrb3 = htole32(temp);
1347 return (xhci_do_command(sc, &trb, 100 /* ms */));
1351 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1352 uint8_t bsr, uint8_t slot_id)
1354 struct xhci_trb trb;
1359 trb.qwTrb0 = htole64(input_ctx);
1361 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1362 XHCI_TRB_3_SLOT_SET(slot_id);
1365 temp |= XHCI_TRB_3_BSR_BIT;
1367 trb.dwTrb3 = htole32(temp);
1369 return (xhci_do_command(sc, &trb, 500 /* ms */));
1373 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1375 struct usb_page_search buf_inp;
1376 struct usb_page_search buf_dev;
1377 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1378 struct xhci_hw_dev *hdev;
1379 struct xhci_dev_ctx *pdev;
1380 struct xhci_endpoint_ext *pepext;
1386 /* the root HUB case is not handled here */
1387 if (udev->parent_hub == NULL)
1388 return (USB_ERR_INVAL);
1390 index = udev->controller_slot_id;
1392 hdev = &sc->sc_hw.devs[index];
1399 switch (hdev->state) {
1400 case XHCI_ST_DEFAULT:
1401 case XHCI_ST_ENABLED:
1403 hdev->state = XHCI_ST_ENABLED;
1405 /* set configure mask to slot and EP0 */
1406 xhci_configure_mask(udev, 3, 0);
1408 /* configure input slot context structure */
1409 err = xhci_configure_device(udev);
1412 DPRINTF("Could not configure device\n");
1416 /* configure input endpoint context structure */
1417 switch (udev->speed) {
1419 case USB_SPEED_FULL:
1422 case USB_SPEED_HIGH:
1430 pepext = xhci_get_endpoint_ext(udev,
1431 &udev->ctrl_ep_desc);
1433 /* ensure the control endpoint is setup again */
1434 USB_BUS_LOCK(udev->bus);
1435 pepext->trb_halted = 1;
1436 pepext->trb_running = 0;
1437 USB_BUS_UNLOCK(udev->bus);
1439 err = xhci_configure_endpoint(udev,
1440 &udev->ctrl_ep_desc, pepext,
1441 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1444 DPRINTF("Could not configure default endpoint\n");
1448 /* execute set address command */
1449 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1451 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1452 (address == 0), index);
1455 temp = le32toh(sc->sc_cmd_result[0]);
1456 if (address == 0 && sc->sc_port_route != NULL &&
1457 XHCI_TRB_2_ERROR_GET(temp) ==
1458 XHCI_TRB_ERROR_PARAMETER) {
1459 /* LynxPoint XHCI - ports are not switchable */
1460 /* Un-route all ports from the XHCI */
1461 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1463 DPRINTF("Could not set address "
1464 "for slot %u.\n", index);
1469 /* update device address to new value */
1471 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1472 pdev = buf_dev.buffer;
1473 usb_pc_cpu_invalidate(&hdev->device_pc);
1475 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1476 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1478 /* update device state to new value */
1481 hdev->state = XHCI_ST_ADDRESSED;
1483 hdev->state = XHCI_ST_DEFAULT;
1487 DPRINTF("Wrong state for set address.\n");
1488 err = USB_ERR_IOERROR;
1491 XHCI_CMD_UNLOCK(sc);
1500 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1501 uint8_t deconfigure, uint8_t slot_id)
1503 struct xhci_trb trb;
1508 trb.qwTrb0 = htole64(input_ctx);
1510 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1511 XHCI_TRB_3_SLOT_SET(slot_id);
1514 temp |= XHCI_TRB_3_DCEP_BIT;
1516 trb.dwTrb3 = htole32(temp);
1518 return (xhci_do_command(sc, &trb, 100 /* ms */));
1522 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1525 struct xhci_trb trb;
1530 trb.qwTrb0 = htole64(input_ctx);
1532 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1533 XHCI_TRB_3_SLOT_SET(slot_id);
1534 trb.dwTrb3 = htole32(temp);
1536 return (xhci_do_command(sc, &trb, 100 /* ms */));
1540 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1541 uint8_t ep_id, uint8_t slot_id)
1543 struct xhci_trb trb;
1550 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1551 XHCI_TRB_3_SLOT_SET(slot_id) |
1552 XHCI_TRB_3_EP_SET(ep_id);
1555 temp |= XHCI_TRB_3_PRSV_BIT;
1557 trb.dwTrb3 = htole32(temp);
1559 return (xhci_do_command(sc, &trb, 100 /* ms */));
1563 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1564 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1566 struct xhci_trb trb;
1571 trb.qwTrb0 = htole64(dequeue_ptr);
1573 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1574 trb.dwTrb2 = htole32(temp);
1576 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1577 XHCI_TRB_3_SLOT_SET(slot_id) |
1578 XHCI_TRB_3_EP_SET(ep_id);
1579 trb.dwTrb3 = htole32(temp);
1581 return (xhci_do_command(sc, &trb, 100 /* ms */));
1585 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1586 uint8_t ep_id, uint8_t slot_id)
1588 struct xhci_trb trb;
1595 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1596 XHCI_TRB_3_SLOT_SET(slot_id) |
1597 XHCI_TRB_3_EP_SET(ep_id);
1600 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1602 trb.dwTrb3 = htole32(temp);
1604 return (xhci_do_command(sc, &trb, 100 /* ms */));
1608 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1610 struct xhci_trb trb;
1617 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1618 XHCI_TRB_3_SLOT_SET(slot_id);
1620 trb.dwTrb3 = htole32(temp);
1622 return (xhci_do_command(sc, &trb, 100 /* ms */));
1625 /*------------------------------------------------------------------------*
1626 * xhci_interrupt - XHCI interrupt handler
1627 *------------------------------------------------------------------------*/
1629 xhci_interrupt(struct xhci_softc *sc)
1634 USB_BUS_LOCK(&sc->sc_bus);
1636 status = XREAD4(sc, oper, XHCI_USBSTS);
1638 /* acknowledge interrupts, if any */
1640 XWRITE4(sc, oper, XHCI_USBSTS, status);
1641 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1644 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1646 /* force clearing of pending interrupts */
1647 if (temp & XHCI_IMAN_INTR_PEND)
1648 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1650 /* check for event(s) */
1651 xhci_interrupt_poll(sc);
1653 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1654 XHCI_STS_HSE | XHCI_STS_HCE)) {
1656 if (status & XHCI_STS_PCD) {
1660 if (status & XHCI_STS_HCH) {
1661 printf("%s: host controller halted\n",
1665 if (status & XHCI_STS_HSE) {
1666 printf("%s: host system error\n",
1670 if (status & XHCI_STS_HCE) {
1671 printf("%s: host controller error\n",
1675 USB_BUS_UNLOCK(&sc->sc_bus);
1678 /*------------------------------------------------------------------------*
1679 * xhci_timeout - XHCI timeout handler
1680 *------------------------------------------------------------------------*/
1682 xhci_timeout(void *arg)
1684 struct usb_xfer *xfer = arg;
1686 DPRINTF("xfer=%p\n", xfer);
1688 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1690 /* transfer is transferred */
1691 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1695 xhci_do_poll(struct usb_bus *bus)
1697 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1699 USB_BUS_LOCK(&sc->sc_bus);
1700 xhci_interrupt_poll(sc);
1701 USB_BUS_UNLOCK(&sc->sc_bus);
1705 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1707 struct usb_page_search buf_res;
1709 struct xhci_td *td_next;
1710 struct xhci_td *td_alt_next;
1711 struct xhci_td *td_first;
1712 uint32_t buf_offset;
1717 uint8_t shortpkt_old;
1723 shortpkt_old = temp->shortpkt;
1724 len_old = temp->len;
1731 td_next = td_first = temp->td_next;
1735 if (temp->len == 0) {
1740 /* send a Zero Length Packet, ZLP, last */
1747 average = temp->average;
1749 if (temp->len < average) {
1750 if (temp->len % temp->max_packet_size) {
1753 average = temp->len;
1757 if (td_next == NULL)
1758 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1763 td_next = td->obj_next;
1765 /* check if we are pre-computing */
1769 /* update remaining length */
1771 temp->len -= average;
1775 /* fill out current TD */
1781 /* update remaining length */
1783 temp->len -= average;
1785 /* reset TRB index */
1789 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1790 /* immediate data */
1795 td->td_trb[0].qwTrb0 = 0;
1797 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1798 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1801 dword = XHCI_TRB_2_BYTES_SET(8) |
1802 XHCI_TRB_2_TDSZ_SET(0) |
1803 XHCI_TRB_2_IRQ_SET(0);
1805 td->td_trb[0].dwTrb2 = htole32(dword);
1807 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1808 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1811 if (td->td_trb[0].qwTrb0 &
1812 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1813 if (td->td_trb[0].qwTrb0 &
1814 htole64(XHCI_TRB_0_DIR_IN_MASK))
1815 dword |= XHCI_TRB_3_TRT_IN;
1817 dword |= XHCI_TRB_3_TRT_OUT;
1820 td->td_trb[0].dwTrb3 = htole32(dword);
1822 xhci_dump_trb(&td->td_trb[x]);
1830 /* fill out buffer pointers */
1833 memset(&buf_res, 0, sizeof(buf_res));
1835 usbd_get_page(temp->pc, temp->offset +
1836 buf_offset, &buf_res);
1838 /* get length to end of page */
1839 if (buf_res.length > average)
1840 buf_res.length = average;
1842 /* check for maximum length */
1843 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1844 buf_res.length = XHCI_TD_PAGE_SIZE;
1846 npkt_off += buf_res.length;
1850 npkt = howmany(len_old - npkt_off,
1851 temp->max_packet_size);
1858 /* fill out TRB's */
1859 td->td_trb[x].qwTrb0 =
1860 htole64((uint64_t)buf_res.physaddr);
1863 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1864 XHCI_TRB_2_TDSZ_SET(npkt) |
1865 XHCI_TRB_2_IRQ_SET(0);
1867 td->td_trb[x].dwTrb2 = htole32(dword);
1869 switch (temp->trb_type) {
1870 case XHCI_TRB_TYPE_ISOCH:
1871 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1872 XHCI_TRB_3_TBC_SET(temp->tbc) |
1873 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1874 if (td != td_first) {
1875 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1876 } else if (temp->do_isoc_sync != 0) {
1877 temp->do_isoc_sync = 0;
1878 /* wait until "isoc_frame" */
1879 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1880 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1882 /* start data transfer at next interval */
1883 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1884 XHCI_TRB_3_ISO_SIA_BIT;
1886 if (temp->direction == UE_DIR_IN)
1887 dword |= XHCI_TRB_3_ISP_BIT;
1889 case XHCI_TRB_TYPE_DATA_STAGE:
1890 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1891 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1892 if (temp->direction == UE_DIR_IN)
1893 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1895 * Section 3.2.9 in the XHCI
1896 * specification about control
1897 * transfers says that we should use a
1898 * normal-TRB if there are more TRBs
1899 * extending the data-stage
1900 * TRB. Update the "trb_type".
1902 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1904 case XHCI_TRB_TYPE_STATUS_STAGE:
1905 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1906 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1907 if (temp->direction == UE_DIR_IN)
1908 dword |= XHCI_TRB_3_DIR_IN;
1910 default: /* XHCI_TRB_TYPE_NORMAL */
1911 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1912 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1913 if (temp->direction == UE_DIR_IN)
1914 dword |= XHCI_TRB_3_ISP_BIT;
1917 td->td_trb[x].dwTrb3 = htole32(dword);
1919 average -= buf_res.length;
1920 buf_offset += buf_res.length;
1922 xhci_dump_trb(&td->td_trb[x]);
1926 } while (average != 0);
1928 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1930 /* store number of data TRB's */
1934 DPRINTF("NTRB=%u\n", x);
1936 /* fill out link TRB */
1938 if (td_next != NULL) {
1939 /* link the current TD with the next one */
1940 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1941 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1943 /* this field will get updated later */
1944 DPRINTF("NOLINK\n");
1947 dword = XHCI_TRB_2_IRQ_SET(0);
1949 td->td_trb[x].dwTrb2 = htole32(dword);
1951 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1952 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1954 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1955 * frame only receives a single short packet event
1956 * by setting the CHAIN bit in the LINK field. In
1957 * addition some XHCI controllers have problems
1958 * sending a ZLP unless the CHAIN-BIT is set in
1961 XHCI_TRB_3_CHAIN_BIT;
1963 td->td_trb[x].dwTrb3 = htole32(dword);
1965 td->alt_next = td_alt_next;
1967 xhci_dump_trb(&td->td_trb[x]);
1969 usb_pc_cpu_flush(td->page_cache);
1975 /* set up alt next pointer, if any */
1976 if (temp->last_frame) {
1979 /* we use this field internally */
1980 td_alt_next = td_next;
1984 temp->shortpkt = shortpkt_old;
1985 temp->len = len_old;
1990 * Remove cycle bit from the first TRB if we are
1993 if (temp->step_td != 0) {
1994 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1995 usb_pc_cpu_flush(td_first->page_cache);
1998 /* clear TD SIZE to zero, hence this is the last TRB */
1999 /* remove chain bit because this is the last data TRB in the chain */
2000 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
2001 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2002 /* remove CHAIN-BIT from last LINK TRB */
2003 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2005 usb_pc_cpu_flush(td->page_cache);
2008 temp->td_next = td_next;
2012 xhci_setup_generic_chain(struct usb_xfer *xfer)
2014 struct xhci_std_temp temp;
2020 temp.do_isoc_sync = 0;
2024 temp.average = xfer->max_hc_frame_size;
2025 temp.max_packet_size = xfer->max_packet_size;
2026 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2028 temp.last_frame = 0;
2030 temp.multishort = xfer->flags_int.isochronous_xfr ||
2031 xfer->flags_int.control_xfr ||
2032 xfer->flags_int.short_frames_ok;
2034 /* toggle the DMA set we are using */
2035 xfer->flags_int.curr_dma_set ^= 1;
2037 /* get next DMA set */
2038 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2043 xfer->td_transfer_first = td;
2044 xfer->td_transfer_cache = td;
2046 if (xfer->flags_int.isochronous_xfr) {
2049 /* compute multiplier for ISOCHRONOUS transfers */
2050 mult = xfer->endpoint->ecomp ?
2051 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2053 /* check for USB 2.0 multiplier */
2055 mult = (xfer->endpoint->edesc->
2056 wMaxPacketSize[1] >> 3) & 3;
2064 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2066 DPRINTF("MFINDEX=0x%08x\n", x);
2068 switch (usbd_get_speed(xfer->xroot->udev)) {
2069 case USB_SPEED_FULL:
2071 temp.isoc_delta = 8; /* 1ms */
2072 x += temp.isoc_delta - 1;
2073 x &= ~(temp.isoc_delta - 1);
2076 shift = usbd_xfer_get_fps_shift(xfer);
2077 temp.isoc_delta = 1U << shift;
2078 x += temp.isoc_delta - 1;
2079 x &= ~(temp.isoc_delta - 1);
2080 /* simple frame load balancing */
2081 x += xfer->endpoint->usb_uframe;
2085 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2087 if ((xfer->endpoint->is_synced == 0) ||
2088 (y < (xfer->nframes << shift)) ||
2089 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2091 * If there is data underflow or the pipe
2092 * queue is empty we schedule the transfer a
2093 * few frames ahead of the current frame
2094 * position. Else two isochronous transfers
2097 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2098 xfer->endpoint->is_synced = 1;
2099 temp.do_isoc_sync = 1;
2101 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2104 /* compute isochronous completion time */
2106 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2108 xfer->isoc_time_complete =
2109 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2110 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2113 temp.isoc_frame = xfer->endpoint->isoc_next;
2114 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2116 xfer->endpoint->isoc_next += xfer->nframes << shift;
2118 } else if (xfer->flags_int.control_xfr) {
2120 /* check if we should prepend a setup message */
2122 if (xfer->flags_int.control_hdr) {
2124 temp.len = xfer->frlengths[0];
2125 temp.pc = xfer->frbuffers + 0;
2126 temp.shortpkt = temp.len ? 1 : 0;
2127 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2130 /* check for last frame */
2131 if (xfer->nframes == 1) {
2132 /* no STATUS stage yet, SETUP is last */
2133 if (xfer->flags_int.control_act)
2134 temp.last_frame = 1;
2137 xhci_setup_generic_chain_sub(&temp);
2141 temp.isoc_delta = 0;
2142 temp.isoc_frame = 0;
2143 temp.trb_type = xfer->flags_int.control_did_data ?
2144 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2148 temp.isoc_delta = 0;
2149 temp.isoc_frame = 0;
2150 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2153 if (x != xfer->nframes) {
2154 /* set up page_cache pointer */
2155 temp.pc = xfer->frbuffers + x;
2156 /* set endpoint direction */
2157 temp.direction = UE_GET_DIR(xfer->endpointno);
2160 while (x != xfer->nframes) {
2162 /* DATA0 / DATA1 message */
2164 temp.len = xfer->frlengths[x];
2165 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2166 x != 0 && temp.multishort == 0);
2170 if (x == xfer->nframes) {
2171 if (xfer->flags_int.control_xfr) {
2172 /* no STATUS stage yet, DATA is last */
2173 if (xfer->flags_int.control_act)
2174 temp.last_frame = 1;
2176 temp.last_frame = 1;
2179 if (temp.len == 0) {
2181 /* make sure that we send an USB packet */
2186 temp.tlbpc = mult - 1;
2188 } else if (xfer->flags_int.isochronous_xfr) {
2193 * Isochronous transfers don't have short
2194 * packet termination:
2199 /* isochronous transfers have a transfer limit */
2201 if (temp.len > xfer->max_frame_size)
2202 temp.len = xfer->max_frame_size;
2204 /* compute TD packet count */
2205 tdpc = howmany(temp.len, xfer->max_packet_size);
2207 temp.tbc = howmany(tdpc, mult) - 1;
2208 temp.tlbpc = (tdpc % mult);
2210 if (temp.tlbpc == 0)
2211 temp.tlbpc = mult - 1;
2216 /* regular data transfer */
2218 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2221 xhci_setup_generic_chain_sub(&temp);
2223 if (xfer->flags_int.isochronous_xfr) {
2224 temp.offset += xfer->frlengths[x - 1];
2225 temp.isoc_frame += temp.isoc_delta;
2227 /* get next Page Cache pointer */
2228 temp.pc = xfer->frbuffers + x;
2232 /* check if we should append a status stage */
2234 if (xfer->flags_int.control_xfr &&
2235 !xfer->flags_int.control_act) {
2238 * Send a DATA1 message and invert the current
2239 * endpoint direction.
2241 #ifdef XHCI_STEP_STATUS_STAGE
2242 temp.step_td = (xfer->nframes != 0);
2246 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2250 temp.last_frame = 1;
2251 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2253 xhci_setup_generic_chain_sub(&temp);
2258 /* must have at least one frame! */
2260 xfer->td_transfer_last = td;
2262 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2266 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2268 struct usb_page_search buf_res;
2269 struct xhci_dev_ctx_addr *pdctxa;
2271 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2273 pdctxa = buf_res.buffer;
2275 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2277 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2279 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2283 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2285 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2286 struct usb_page_search buf_inp;
2287 struct xhci_input_dev_ctx *pinp;
2292 index = udev->controller_slot_id;
2294 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2296 pinp = buf_inp.buffer;
2299 mask &= XHCI_INCTX_NON_CTRL_MASK;
2300 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2301 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2304 * Some hardware requires that we drop the endpoint
2305 * context before adding it again:
2307 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2308 mask & XHCI_INCTX_NON_CTRL_MASK);
2310 /* Add new endpoint context */
2311 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2313 /* find most significant set bit */
2314 for (x = 31; x != 1; x--) {
2315 if (mask & (1 << x))
2322 /* figure out the maximum number of contexts */
2323 if (x > sc->sc_hw.devs[index].context_num)
2324 sc->sc_hw.devs[index].context_num = x;
2326 x = sc->sc_hw.devs[index].context_num;
2328 /* update number of contexts */
2329 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2330 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2331 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2332 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2334 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2339 xhci_configure_endpoint(struct usb_device *udev,
2340 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2341 uint16_t interval, uint8_t max_packet_count,
2342 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2343 uint16_t max_frame_size, uint8_t ep_mode)
2345 struct usb_page_search buf_inp;
2346 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2347 struct xhci_input_dev_ctx *pinp;
2348 uint64_t ring_addr = pepext->physaddr;
2354 index = udev->controller_slot_id;
2356 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2358 pinp = buf_inp.buffer;
2360 epno = edesc->bEndpointAddress;
2361 type = edesc->bmAttributes & UE_XFERTYPE;
2363 if (type == UE_CONTROL)
2366 epno = XHCI_EPNO2EPID(epno);
2369 return (USB_ERR_NO_PIPE); /* invalid */
2371 if (max_packet_count == 0)
2372 return (USB_ERR_BAD_BUFSIZE);
2377 return (USB_ERR_BAD_BUFSIZE);
2379 /* store endpoint mode */
2380 pepext->trb_ep_mode = ep_mode;
2381 /* store bMaxPacketSize for control endpoints */
2382 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2383 usb_pc_cpu_flush(pepext->page_cache);
2385 if (ep_mode == USB_EP_MODE_STREAMS) {
2386 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2387 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2388 XHCI_EPCTX_0_LSA_SET(1);
2390 ring_addr += sizeof(struct xhci_trb) *
2391 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2393 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2394 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2395 XHCI_EPCTX_0_LSA_SET(0);
2397 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2400 switch (udev->speed) {
2401 case USB_SPEED_FULL:
2414 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2416 case UE_ISOCHRONOUS:
2417 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2419 switch (udev->speed) {
2420 case USB_SPEED_SUPER:
2423 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2424 max_packet_count /= mult;
2434 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2437 XHCI_EPCTX_1_HID_SET(0) |
2438 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2439 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2442 * Always enable the "three strikes and you are gone" feature
2443 * except for ISOCHRONOUS endpoints. This is suggested by
2444 * section 4.3.3 in the XHCI specification about device slot
2447 if (type != UE_ISOCHRONOUS)
2448 temp |= XHCI_EPCTX_1_CERR_SET(3);
2452 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2454 case UE_ISOCHRONOUS:
2455 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2458 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2461 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2465 /* check for IN direction */
2467 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2469 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2470 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2472 switch (edesc->bmAttributes & UE_XFERTYPE) {
2474 case UE_ISOCHRONOUS:
2475 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2476 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2480 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2483 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2487 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2490 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2492 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2494 return (0); /* success */
2498 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2500 struct xhci_endpoint_ext *pepext;
2501 struct usb_endpoint_ss_comp_descriptor *ecomp;
2504 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2505 xfer->endpoint->edesc);
2507 ecomp = xfer->endpoint->ecomp;
2509 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2512 /* halt any transfers */
2513 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2515 /* compute start of TRB ring for stream "x" */
2516 temp = pepext->physaddr +
2517 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2518 XHCI_SCTX_0_SCT_SEC_TR_RING;
2520 /* make tree structure */
2521 pepext->trb[(XHCI_MAX_TRANSFERS *
2522 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2524 /* reserved fields */
2525 pepext->trb[(XHCI_MAX_TRANSFERS *
2526 XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2527 pepext->trb[(XHCI_MAX_TRANSFERS *
2528 XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2530 usb_pc_cpu_flush(pepext->page_cache);
2532 return (xhci_configure_endpoint(xfer->xroot->udev,
2533 xfer->endpoint->edesc, pepext,
2534 xfer->interval, xfer->max_packet_count,
2535 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2536 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2537 xfer->max_frame_size, xfer->endpoint->ep_mode));
2541 xhci_configure_device(struct usb_device *udev)
2543 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2544 struct usb_page_search buf_inp;
2545 struct usb_page_cache *pcinp;
2546 struct xhci_input_dev_ctx *pinp;
2547 struct usb_device *hubdev;
2555 index = udev->controller_slot_id;
2557 DPRINTF("index=%u\n", index);
2559 pcinp = &sc->sc_hw.devs[index].input_pc;
2561 usbd_get_page(pcinp, 0, &buf_inp);
2563 pinp = buf_inp.buffer;
2568 /* figure out route string and root HUB port number */
2570 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2572 if (hubdev->parent_hub == NULL)
2575 depth = hubdev->parent_hub->depth;
2578 * NOTE: HS/FS/LS devices and the SS root HUB can have
2579 * more than 15 ports
2582 rh_port = hubdev->port_no;
2591 route |= rh_port << (4 * (depth - 1));
2594 DPRINTF("Route=0x%08x\n", route);
2596 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2597 XHCI_SCTX_0_CTX_NUM_SET(
2598 sc->sc_hw.devs[index].context_num + 1);
2600 switch (udev->speed) {
2602 temp |= XHCI_SCTX_0_SPEED_SET(2);
2603 if (udev->parent_hs_hub != NULL &&
2604 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2606 DPRINTF("Device inherits MTT\n");
2607 temp |= XHCI_SCTX_0_MTT_SET(1);
2610 case USB_SPEED_HIGH:
2611 temp |= XHCI_SCTX_0_SPEED_SET(3);
2612 if (sc->sc_hw.devs[index].nports != 0 &&
2613 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2614 DPRINTF("HUB supports MTT\n");
2615 temp |= XHCI_SCTX_0_MTT_SET(1);
2618 case USB_SPEED_FULL:
2619 temp |= XHCI_SCTX_0_SPEED_SET(1);
2620 if (udev->parent_hs_hub != NULL &&
2621 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2623 DPRINTF("Device inherits MTT\n");
2624 temp |= XHCI_SCTX_0_MTT_SET(1);
2628 temp |= XHCI_SCTX_0_SPEED_SET(4);
2632 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2633 (udev->speed == USB_SPEED_SUPER ||
2634 udev->speed == USB_SPEED_HIGH);
2637 temp |= XHCI_SCTX_0_HUB_SET(1);
2639 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2641 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2644 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2645 sc->sc_hw.devs[index].nports);
2648 switch (udev->speed) {
2649 case USB_SPEED_SUPER:
2650 switch (sc->sc_hw.devs[index].state) {
2651 case XHCI_ST_ADDRESSED:
2652 case XHCI_ST_CONFIGURED:
2653 /* enable power save */
2654 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2657 /* disable power save */
2665 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2667 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2670 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2671 sc->sc_hw.devs[index].tt);
2674 hubdev = udev->parent_hs_hub;
2676 /* check if we should activate the transaction translator */
2677 switch (udev->speed) {
2678 case USB_SPEED_FULL:
2680 if (hubdev != NULL) {
2681 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2682 hubdev->controller_slot_id);
2683 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2691 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2694 * These fields should be initialized to zero, according to
2695 * XHCI section 6.2.2 - slot context:
2697 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2698 XHCI_SCTX_3_SLOT_STATE_SET(0);
2700 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2703 xhci_dump_device(sc, &pinp->ctx_slot);
2705 usb_pc_cpu_flush(pcinp);
2707 return (0); /* success */
2711 xhci_alloc_device_ext(struct usb_device *udev)
2713 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2714 struct usb_page_search buf_dev;
2715 struct usb_page_search buf_ep;
2716 struct xhci_trb *trb;
2717 struct usb_page_cache *pc;
2718 struct usb_page *pg;
2723 index = udev->controller_slot_id;
2725 pc = &sc->sc_hw.devs[index].device_pc;
2726 pg = &sc->sc_hw.devs[index].device_pg;
2728 /* need to initialize the page cache */
2729 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2731 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2732 (2 * sizeof(struct xhci_dev_ctx)) :
2733 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2736 usbd_get_page(pc, 0, &buf_dev);
2738 pc = &sc->sc_hw.devs[index].input_pc;
2739 pg = &sc->sc_hw.devs[index].input_pg;
2741 /* need to initialize the page cache */
2742 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2744 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2745 (2 * sizeof(struct xhci_input_dev_ctx)) :
2746 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2750 /* initialize all endpoint LINK TRBs */
2752 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2754 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2755 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2757 /* need to initialize the page cache */
2758 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2760 if (usb_pc_alloc_mem(pc, pg,
2761 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2765 /* lookup endpoint TRB ring */
2766 usbd_get_page(pc, 0, &buf_ep);
2768 /* get TRB pointer */
2769 trb = buf_ep.buffer;
2770 trb += XHCI_MAX_TRANSFERS - 1;
2772 /* get TRB start address */
2773 addr = buf_ep.physaddr;
2775 /* create LINK TRB */
2776 trb->qwTrb0 = htole64(addr);
2777 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2778 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2779 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2781 usb_pc_cpu_flush(pc);
2784 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2789 xhci_free_device_ext(udev);
2791 return (USB_ERR_NOMEM);
2795 xhci_free_device_ext(struct usb_device *udev)
2797 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2801 index = udev->controller_slot_id;
2802 xhci_set_slot_pointer(sc, index, 0);
2804 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2805 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2806 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2807 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2810 static struct xhci_endpoint_ext *
2811 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2813 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2814 struct xhci_endpoint_ext *pepext;
2815 struct usb_page_cache *pc;
2816 struct usb_page_search buf_ep;
2820 epno = edesc->bEndpointAddress;
2821 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2824 epno = XHCI_EPNO2EPID(epno);
2826 index = udev->controller_slot_id;
2828 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2830 usbd_get_page(pc, 0, &buf_ep);
2832 pepext = &sc->sc_hw.devs[index].endp[epno];
2833 pepext->page_cache = pc;
2834 pepext->trb = buf_ep.buffer;
2835 pepext->physaddr = buf_ep.physaddr;
2841 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2843 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2847 epno = xfer->endpointno;
2848 if (xfer->flags_int.control_xfr)
2851 epno = XHCI_EPNO2EPID(epno);
2852 index = xfer->xroot->udev->controller_slot_id;
2854 if (xfer->xroot->udev->flags.self_suspended == 0) {
2855 XWRITE4(sc, door, XHCI_DOORBELL(index),
2856 epno | XHCI_DB_SID_SET(xfer->stream_id));
2861 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2863 struct xhci_endpoint_ext *pepext;
2865 if (xfer->flags_int.bandwidth_reclaimed) {
2866 xfer->flags_int.bandwidth_reclaimed = 0;
2868 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2869 xfer->endpoint->edesc);
2871 pepext->trb_used[xfer->stream_id]--;
2873 pepext->xfer[xfer->qh_pos] = NULL;
2875 if (error && pepext->trb_running != 0) {
2876 pepext->trb_halted = 1;
2877 pepext->trb_running = 0;
2883 xhci_transfer_insert(struct usb_xfer *xfer)
2885 struct xhci_td *td_first;
2886 struct xhci_td *td_last;
2887 struct xhci_trb *trb_link;
2888 struct xhci_endpoint_ext *pepext;
2897 id = xfer->stream_id;
2899 /* check if already inserted */
2900 if (xfer->flags_int.bandwidth_reclaimed) {
2901 DPRINTFN(8, "Already in schedule\n");
2905 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2906 xfer->endpoint->edesc);
2908 td_first = xfer->td_transfer_first;
2909 td_last = xfer->td_transfer_last;
2910 addr = pepext->physaddr;
2912 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2915 /* single buffered */
2919 /* multi buffered */
2920 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2924 if (pepext->trb_used[id] >= trb_limit) {
2925 DPRINTFN(8, "Too many TDs queued.\n");
2926 return (USB_ERR_NOMEM);
2929 /* check if bMaxPacketSize changed */
2930 if (xfer->flags_int.control_xfr != 0 &&
2931 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2933 DPRINTFN(8, "Reconfigure control endpoint\n");
2935 /* force driver to reconfigure endpoint */
2936 pepext->trb_halted = 1;
2937 pepext->trb_running = 0;
2940 /* check for stopped condition, after putting transfer on interrupt queue */
2941 if (pepext->trb_running == 0) {
2942 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2944 DPRINTFN(8, "Not running\n");
2946 /* start configuration */
2947 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2948 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2952 pepext->trb_used[id]++;
2954 /* get current TRB index */
2955 i = pepext->trb_index[id];
2957 /* get next TRB index */
2960 /* the last entry of the ring is a hardcoded link TRB */
2961 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2964 /* store next TRB index, before stream ID offset is added */
2965 pepext->trb_index[id] = inext;
2967 /* offset for stream */
2968 i += id * XHCI_MAX_TRANSFERS;
2969 inext += id * XHCI_MAX_TRANSFERS;
2971 /* compute terminating return address */
2972 addr += (inext * sizeof(struct xhci_trb));
2974 /* compute link TRB pointer */
2975 trb_link = td_last->td_trb + td_last->ntrb;
2977 /* update next pointer of last link TRB */
2978 trb_link->qwTrb0 = htole64(addr);
2979 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2980 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2981 XHCI_TRB_3_CYCLE_BIT |
2982 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2985 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2987 usb_pc_cpu_flush(td_last->page_cache);
2989 /* write ahead chain end marker */
2991 pepext->trb[inext].qwTrb0 = 0;
2992 pepext->trb[inext].dwTrb2 = 0;
2993 pepext->trb[inext].dwTrb3 = 0;
2995 /* update next pointer of link TRB */
2997 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2998 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3001 xhci_dump_trb(&pepext->trb[i]);
3003 usb_pc_cpu_flush(pepext->page_cache);
3005 /* toggle cycle bit which activates the transfer chain */
3007 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
3008 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3010 usb_pc_cpu_flush(pepext->page_cache);
3012 DPRINTF("qh_pos = %u\n", i);
3014 pepext->xfer[i] = xfer;
3018 xfer->flags_int.bandwidth_reclaimed = 1;
3020 xhci_endpoint_doorbell(xfer);
3026 xhci_root_intr(struct xhci_softc *sc)
3030 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3032 /* clear any old interrupt data */
3033 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3035 for (i = 1; i <= sc->sc_noport; i++) {
3036 /* pick out CHANGE bits from the status register */
3037 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3038 XHCI_PS_CSC | XHCI_PS_PEC |
3039 XHCI_PS_OCC | XHCI_PS_WRC |
3040 XHCI_PS_PRC | XHCI_PS_PLC |
3042 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3043 DPRINTF("port %d changed\n", i);
3046 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3047 sizeof(sc->sc_hub_idata));
3050 /*------------------------------------------------------------------------*
3051 * xhci_device_done - XHCI done handler
3053 * NOTE: This function can be called two times in a row on
3054 * the same USB transfer. From close and from interrupt.
3055 *------------------------------------------------------------------------*/
3057 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3059 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3060 xfer, xfer->endpoint, error);
3062 /* remove transfer from HW queue */
3063 xhci_transfer_remove(xfer, error);
3065 /* dequeue transfer and start next transfer */
3066 usbd_transfer_done(xfer, error);
3069 /*------------------------------------------------------------------------*
3070 * XHCI data transfer support (generic type)
3071 *------------------------------------------------------------------------*/
3073 xhci_device_generic_open(struct usb_xfer *xfer)
3075 if (xfer->flags_int.isochronous_xfr) {
3076 switch (xfer->xroot->udev->speed) {
3077 case USB_SPEED_FULL:
3080 usb_hs_bandwidth_alloc(xfer);
3087 xhci_device_generic_close(struct usb_xfer *xfer)
3091 xhci_device_done(xfer, USB_ERR_CANCELLED);
3093 if (xfer->flags_int.isochronous_xfr) {
3094 switch (xfer->xroot->udev->speed) {
3095 case USB_SPEED_FULL:
3098 usb_hs_bandwidth_free(xfer);
3105 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3106 usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3108 struct usb_xfer *xfer;
3110 /* check if there is a current transfer */
3111 xfer = ep->endpoint_q[stream_id].curr;
3116 * Check if the current transfer is started and then pickup
3117 * the next one, if any. Else wait for next start event due to
3118 * block on failure feature.
3120 if (!xfer->flags_int.bandwidth_reclaimed)
3123 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3126 * In case of enter we have to consider that the
3127 * transfer is queued by the USB core after the enter
3136 /* try to multi buffer */
3137 xhci_transfer_insert(xfer);
3141 xhci_device_generic_enter(struct usb_xfer *xfer)
3145 /* set up TD's and QH */
3146 xhci_setup_generic_chain(xfer);
3148 xhci_device_generic_multi_enter(xfer->endpoint,
3149 xfer->stream_id, xfer);
3153 xhci_device_generic_start(struct usb_xfer *xfer)
3157 /* try to insert xfer on HW queue */
3158 xhci_transfer_insert(xfer);
3160 /* try to multi buffer */
3161 xhci_device_generic_multi_enter(xfer->endpoint,
3162 xfer->stream_id, NULL);
3164 /* add transfer last on interrupt queue */
3165 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3167 /* start timeout, if any */
3168 if (xfer->timeout != 0)
3169 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3172 static const struct usb_pipe_methods xhci_device_generic_methods =
3174 .open = xhci_device_generic_open,
3175 .close = xhci_device_generic_close,
3176 .enter = xhci_device_generic_enter,
3177 .start = xhci_device_generic_start,
3180 /*------------------------------------------------------------------------*
3181 * xhci root HUB support
3182 *------------------------------------------------------------------------*
3183 * Simulate a hardware HUB by handling all the necessary requests.
3184 *------------------------------------------------------------------------*/
3186 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3189 struct usb_device_descriptor xhci_devd =
3191 .bLength = sizeof(xhci_devd),
3192 .bDescriptorType = UDESC_DEVICE, /* type */
3193 HSETW(.bcdUSB, 0x0300), /* USB version */
3194 .bDeviceClass = UDCLASS_HUB, /* class */
3195 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3196 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3197 .bMaxPacketSize = 9, /* max packet size */
3198 HSETW(.idVendor, 0x0000), /* vendor */
3199 HSETW(.idProduct, 0x0000), /* product */
3200 HSETW(.bcdDevice, 0x0100), /* device version */
3204 .bNumConfigurations = 1, /* # of configurations */
3208 struct xhci_bos_desc xhci_bosd = {
3210 .bLength = sizeof(xhci_bosd.bosd),
3211 .bDescriptorType = UDESC_BOS,
3212 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3213 .bNumDeviceCaps = 3,
3216 .bLength = sizeof(xhci_bosd.usb2extd),
3217 .bDescriptorType = 1,
3218 .bDevCapabilityType = 2,
3219 .bmAttributes[0] = 2,
3222 .bLength = sizeof(xhci_bosd.usbdcd),
3223 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3224 .bDevCapabilityType = 3,
3225 .bmAttributes = 0, /* XXX */
3226 HSETW(.wSpeedsSupported, 0x000C),
3227 .bFunctionalitySupport = 8,
3228 .bU1DevExitLat = 255, /* dummy - not used */
3229 .wU2DevExitLat = { 0x00, 0x08 },
3232 .bLength = sizeof(xhci_bosd.cidd),
3233 .bDescriptorType = 1,
3234 .bDevCapabilityType = 4,
3236 .bContainerID = 0, /* XXX */
3241 struct xhci_config_desc xhci_confd = {
3243 .bLength = sizeof(xhci_confd.confd),
3244 .bDescriptorType = UDESC_CONFIG,
3245 .wTotalLength[0] = sizeof(xhci_confd),
3247 .bConfigurationValue = 1,
3248 .iConfiguration = 0,
3249 .bmAttributes = UC_SELF_POWERED,
3250 .bMaxPower = 0 /* max power */
3253 .bLength = sizeof(xhci_confd.ifcd),
3254 .bDescriptorType = UDESC_INTERFACE,
3256 .bInterfaceClass = UICLASS_HUB,
3257 .bInterfaceSubClass = UISUBCLASS_HUB,
3258 .bInterfaceProtocol = 0,
3261 .bLength = sizeof(xhci_confd.endpd),
3262 .bDescriptorType = UDESC_ENDPOINT,
3263 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3264 .bmAttributes = UE_INTERRUPT,
3265 .wMaxPacketSize[0] = 2, /* max 15 ports */
3269 .bLength = sizeof(xhci_confd.endpcd),
3270 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3277 struct usb_hub_ss_descriptor xhci_hubd = {
3278 .bLength = sizeof(xhci_hubd),
3279 .bDescriptorType = UDESC_SS_HUB,
3283 xhci_roothub_exec(struct usb_device *udev,
3284 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3286 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3287 const char *str_ptr;
3298 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3301 ptr = (const void *)&sc->sc_hub_desc;
3305 value = UGETW(req->wValue);
3306 index = UGETW(req->wIndex);
3308 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3309 "wValue=0x%04x wIndex=0x%04x\n",
3310 req->bmRequestType, req->bRequest,
3311 UGETW(req->wLength), value, index);
3313 #define C(x,y) ((x) | ((y) << 8))
3314 switch (C(req->bRequest, req->bmRequestType)) {
3315 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3316 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3317 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3319 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3320 * for the integrated root hub.
3323 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3325 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3327 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3328 switch (value >> 8) {
3330 if ((value & 0xff) != 0) {
3331 err = USB_ERR_IOERROR;
3334 len = sizeof(xhci_devd);
3335 ptr = (const void *)&xhci_devd;
3339 if ((value & 0xff) != 0) {
3340 err = USB_ERR_IOERROR;
3343 len = sizeof(xhci_bosd);
3344 ptr = (const void *)&xhci_bosd;
3348 if ((value & 0xff) != 0) {
3349 err = USB_ERR_IOERROR;
3352 len = sizeof(xhci_confd);
3353 ptr = (const void *)&xhci_confd;
3357 switch (value & 0xff) {
3358 case 0: /* Language table */
3362 case 1: /* Vendor */
3363 str_ptr = sc->sc_vendor;
3366 case 2: /* Product */
3367 str_ptr = "XHCI root HUB";
3375 len = usb_make_str_desc(
3376 sc->sc_hub_desc.temp,
3377 sizeof(sc->sc_hub_desc.temp),
3382 err = USB_ERR_IOERROR;
3386 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3388 sc->sc_hub_desc.temp[0] = 0;
3390 case C(UR_GET_STATUS, UT_READ_DEVICE):
3392 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3394 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3395 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3397 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3399 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3400 if (value >= XHCI_MAX_DEVICES) {
3401 err = USB_ERR_IOERROR;
3405 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3406 if (value != 0 && value != 1) {
3407 err = USB_ERR_IOERROR;
3410 sc->sc_conf = value;
3412 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3414 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3415 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3416 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3417 err = USB_ERR_IOERROR;
3419 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3421 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3424 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3426 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3427 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3430 (index > sc->sc_noport)) {
3431 err = USB_ERR_IOERROR;
3434 port = XHCI_PORTSC(index);
3436 v = XREAD4(sc, oper, port);
3437 i = XHCI_PS_PLS_GET(v);
3438 v &= ~XHCI_PS_CLEAR;
3441 case UHF_C_BH_PORT_RESET:
3442 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3444 case UHF_C_PORT_CONFIG_ERROR:
3445 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3447 case UHF_C_PORT_SUSPEND:
3448 case UHF_C_PORT_LINK_STATE:
3449 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3451 case UHF_C_PORT_CONNECTION:
3452 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3454 case UHF_C_PORT_ENABLE:
3455 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3457 case UHF_C_PORT_OVER_CURRENT:
3458 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3460 case UHF_C_PORT_RESET:
3461 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3463 case UHF_PORT_ENABLE:
3464 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3466 case UHF_PORT_POWER:
3467 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3469 case UHF_PORT_INDICATOR:
3470 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3472 case UHF_PORT_SUSPEND:
3476 XWRITE4(sc, oper, port, v |
3477 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3480 /* wait 20ms for resume sequence to complete */
3481 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3484 XWRITE4(sc, oper, port, v |
3485 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3488 err = USB_ERR_IOERROR;
3493 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3494 if ((value & 0xff) != 0) {
3495 err = USB_ERR_IOERROR;
3499 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3501 sc->sc_hub_desc.hubd = xhci_hubd;
3503 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3505 if (XHCI_HCS0_PPC(v))
3506 i = UHD_PWR_INDIVIDUAL;
3510 if (XHCI_HCS0_PIND(v))
3513 i |= UHD_OC_INDIVIDUAL;
3515 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3517 /* see XHCI section 5.4.9: */
3518 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3520 for (j = 1; j <= sc->sc_noport; j++) {
3522 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3523 if (v & XHCI_PS_DR) {
3524 sc->sc_hub_desc.hubd.
3525 DeviceRemovable[j / 8] |= 1U << (j % 8);
3528 len = sc->sc_hub_desc.hubd.bLength;
3531 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3533 memset(sc->sc_hub_desc.temp, 0, 16);
3536 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3537 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3540 (index > sc->sc_noport)) {
3541 err = USB_ERR_IOERROR;
3545 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3547 DPRINTFN(9, "port status=0x%08x\n", v);
3549 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3551 switch (XHCI_PS_SPEED_GET(v)) {
3553 i |= UPS_HIGH_SPEED;
3562 i |= UPS_OTHER_SPEED;
3566 if (v & XHCI_PS_CCS)
3567 i |= UPS_CURRENT_CONNECT_STATUS;
3568 if (v & XHCI_PS_PED)
3569 i |= UPS_PORT_ENABLED;
3570 if (v & XHCI_PS_OCA)
3571 i |= UPS_OVERCURRENT_INDICATOR;
3574 if (v & XHCI_PS_PP) {
3576 * The USB 3.0 RH is using the
3577 * USB 2.0's power bit
3579 i |= UPS_PORT_POWER;
3581 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3584 if (v & XHCI_PS_CSC)
3585 i |= UPS_C_CONNECT_STATUS;
3586 if (v & XHCI_PS_PEC)
3587 i |= UPS_C_PORT_ENABLED;
3588 if (v & XHCI_PS_OCC)
3589 i |= UPS_C_OVERCURRENT_INDICATOR;
3590 if (v & XHCI_PS_WRC)
3591 i |= UPS_C_BH_PORT_RESET;
3592 if (v & XHCI_PS_PRC)
3593 i |= UPS_C_PORT_RESET;
3594 if (v & XHCI_PS_PLC)
3595 i |= UPS_C_PORT_LINK_STATE;
3596 if (v & XHCI_PS_CEC)
3597 i |= UPS_C_PORT_CONFIG_ERROR;
3599 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3600 len = sizeof(sc->sc_hub_desc.ps);
3603 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3604 err = USB_ERR_IOERROR;
3607 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3610 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3616 (index > sc->sc_noport)) {
3617 err = USB_ERR_IOERROR;
3621 port = XHCI_PORTSC(index);
3622 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3625 case UHF_PORT_U1_TIMEOUT:
3626 if (XHCI_PS_SPEED_GET(v) != 4) {
3627 err = USB_ERR_IOERROR;
3630 port = XHCI_PORTPMSC(index);
3631 v = XREAD4(sc, oper, port);
3632 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3633 v |= XHCI_PM3_U1TO_SET(i);
3634 XWRITE4(sc, oper, port, v);
3636 case UHF_PORT_U2_TIMEOUT:
3637 if (XHCI_PS_SPEED_GET(v) != 4) {
3638 err = USB_ERR_IOERROR;
3641 port = XHCI_PORTPMSC(index);
3642 v = XREAD4(sc, oper, port);
3643 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3644 v |= XHCI_PM3_U2TO_SET(i);
3645 XWRITE4(sc, oper, port, v);
3647 case UHF_BH_PORT_RESET:
3648 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3650 case UHF_PORT_LINK_STATE:
3651 XWRITE4(sc, oper, port, v |
3652 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3653 /* 4ms settle time */
3654 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3656 case UHF_PORT_ENABLE:
3657 DPRINTFN(3, "set port enable %d\n", index);
3659 case UHF_PORT_SUSPEND:
3660 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3661 j = XHCI_PS_SPEED_GET(v);
3662 if ((j < 1) || (j > 3)) {
3663 /* non-supported speed */
3664 err = USB_ERR_IOERROR;
3667 XWRITE4(sc, oper, port, v |
3668 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3670 case UHF_PORT_RESET:
3671 DPRINTFN(6, "reset port %d\n", index);
3672 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3674 case UHF_PORT_POWER:
3675 DPRINTFN(3, "set port power %d\n", index);
3676 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3679 DPRINTFN(3, "set port test %d\n", index);
3681 case UHF_PORT_INDICATOR:
3682 DPRINTFN(3, "set port indicator %d\n", index);
3684 v &= ~XHCI_PS_PIC_SET(3);
3685 v |= XHCI_PS_PIC_SET(1);
3687 XWRITE4(sc, oper, port, v);
3690 err = USB_ERR_IOERROR;
3695 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3696 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3697 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3698 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3701 err = USB_ERR_IOERROR;
3711 xhci_xfer_setup(struct usb_setup_params *parm)
3713 struct usb_page_search page_info;
3714 struct usb_page_cache *pc;
3715 struct xhci_softc *sc;
3716 struct usb_xfer *xfer;
3721 sc = XHCI_BUS2SC(parm->udev->bus);
3722 xfer = parm->curr_xfer;
3725 * The proof for the "ntd" formula is illustrated like this:
3727 * +------------------------------------+
3731 * | | xxx | x | frm 0 |
3733 * | | xxx | xx | frm 1 |
3736 * +------------------------------------+
3738 * "xxx" means a completely full USB transfer descriptor
3740 * "x" and "xx" means a short USB packet
3742 * For the remainder of an USB transfer modulo
3743 * "max_data_length" we need two USB transfer descriptors.
3744 * One to transfer the remaining data and one to finalise with
3745 * a zero length packet in case the "force_short_xfer" flag is
3746 * set. We only need two USB transfer descriptors in the case
3747 * where the transfer length of the first one is a factor of
3748 * "max_frame_size". The rest of the needed USB transfer
3749 * descriptors is given by the buffer size divided by the
3750 * maximum data payload.
3752 parm->hc_max_packet_size = 0x400;
3753 parm->hc_max_packet_count = 16 * 3;
3754 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3756 xfer->flags_int.bdma_enable = 1;
3758 usbd_transfer_setup_sub(parm);
3760 if (xfer->flags_int.isochronous_xfr) {
3761 ntd = ((1 * xfer->nframes)
3762 + (xfer->max_data_length / xfer->max_hc_frame_size));
3763 } else if (xfer->flags_int.control_xfr) {
3764 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3765 + (xfer->max_data_length / xfer->max_hc_frame_size));
3767 ntd = ((2 * xfer->nframes)
3768 + (xfer->max_data_length / xfer->max_hc_frame_size));
3777 * Allocate queue heads and transfer descriptors
3781 if (usbd_transfer_setup_sub_malloc(
3782 parm, &pc, sizeof(struct xhci_td),
3783 XHCI_TD_ALIGN, ntd)) {
3784 parm->err = USB_ERR_NOMEM;
3788 for (n = 0; n != ntd; n++) {
3791 usbd_get_page(pc + n, 0, &page_info);
3793 td = page_info.buffer;
3796 td->td_self = page_info.physaddr;
3797 td->obj_next = last_obj;
3798 td->page_cache = pc + n;
3802 usb_pc_cpu_flush(pc + n);
3805 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3807 if (!xfer->flags_int.curr_dma_set) {
3808 xfer->flags_int.curr_dma_set = 1;
3814 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3816 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3817 struct usb_page_search buf_inp;
3818 struct usb_device *udev;
3819 struct xhci_endpoint_ext *pepext;
3820 struct usb_endpoint_descriptor *edesc;
3821 struct usb_page_cache *pcinp;
3823 usb_stream_t stream_id;
3827 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3828 xfer->endpoint->edesc);
3830 udev = xfer->xroot->udev;
3831 index = udev->controller_slot_id;
3833 pcinp = &sc->sc_hw.devs[index].input_pc;
3835 usbd_get_page(pcinp, 0, &buf_inp);
3837 edesc = xfer->endpoint->edesc;
3839 epno = edesc->bEndpointAddress;
3840 stream_id = xfer->stream_id;
3842 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3845 epno = XHCI_EPNO2EPID(epno);
3848 return (USB_ERR_NO_PIPE); /* invalid */
3852 /* configure endpoint */
3854 err = xhci_configure_endpoint_by_xfer(xfer);
3857 XHCI_CMD_UNLOCK(sc);
3862 * Get the endpoint into the stopped state according to the
3863 * endpoint context state diagram in the XHCI specification:
3866 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3869 DPRINTF("Could not stop endpoint %u\n", epno);
3871 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3874 DPRINTF("Could not reset endpoint %u\n", epno);
3876 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3877 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3878 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3879 stream_id, epno, index);
3882 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3885 * Get the endpoint into the running state according to the
3886 * endpoint context state diagram in the XHCI specification:
3889 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3892 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3894 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3897 DPRINTF("Could not configure endpoint %u\n", epno);
3899 XHCI_CMD_UNLOCK(sc);
3905 xhci_xfer_unsetup(struct usb_xfer *xfer)
3911 xhci_start_dma_delay(struct usb_xfer *xfer)
3913 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3915 /* put transfer on interrupt queue (again) */
3916 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3918 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3919 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3923 xhci_configure_msg(struct usb_proc_msg *pm)
3925 struct xhci_softc *sc;
3926 struct xhci_endpoint_ext *pepext;
3927 struct usb_xfer *xfer;
3929 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3932 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3934 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3935 xfer->endpoint->edesc);
3937 if ((pepext->trb_halted != 0) ||
3938 (pepext->trb_running == 0)) {
3942 /* clear halted and running */
3943 pepext->trb_halted = 0;
3944 pepext->trb_running = 0;
3946 /* nuke remaining buffered transfers */
3948 for (i = 0; i != (XHCI_MAX_TRANSFERS *
3949 XHCI_MAX_STREAMS); i++) {
3951 * NOTE: We need to use the timeout
3952 * error code here else existing
3953 * isochronous clients can get
3956 if (pepext->xfer[i] != NULL) {
3957 xhci_device_done(pepext->xfer[i],
3963 * NOTE: The USB transfer cannot vanish in
3967 USB_BUS_UNLOCK(&sc->sc_bus);
3969 xhci_configure_reset_endpoint(xfer);
3971 USB_BUS_LOCK(&sc->sc_bus);
3973 /* check if halted is still cleared */
3974 if (pepext->trb_halted == 0) {
3975 pepext->trb_running = 1;
3976 memset(pepext->trb_index, 0,
3977 sizeof(pepext->trb_index));
3982 if (xfer->flags_int.did_dma_delay) {
3984 /* remove transfer from interrupt queue (again) */
3985 usbd_transfer_dequeue(xfer);
3987 /* we are finally done */
3988 usb_dma_delay_done_cb(xfer);
3990 /* queue changed - restart */
3995 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3997 /* try to insert xfer on HW queue */
3998 xhci_transfer_insert(xfer);
4000 /* try to multi buffer */
4001 xhci_device_generic_multi_enter(xfer->endpoint,
4002 xfer->stream_id, NULL);
4007 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4008 struct usb_endpoint *ep)
4010 struct xhci_endpoint_ext *pepext;
4012 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4013 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4015 if (udev->parent_hub == NULL) {
4016 /* root HUB has special endpoint handling */
4020 ep->methods = &xhci_device_generic_methods;
4022 pepext = xhci_get_endpoint_ext(udev, edesc);
4024 USB_BUS_LOCK(udev->bus);
4025 pepext->trb_halted = 1;
4026 pepext->trb_running = 0;
4027 USB_BUS_UNLOCK(udev->bus);
4031 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4037 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4039 struct xhci_endpoint_ext *pepext;
4043 if (udev->flags.usb_mode != USB_MODE_HOST) {
4047 if (udev->parent_hub == NULL) {
4048 /* root HUB has special endpoint handling */
4052 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4054 USB_BUS_LOCK(udev->bus);
4055 pepext->trb_halted = 1;
4056 pepext->trb_running = 0;
4057 USB_BUS_UNLOCK(udev->bus);
4061 xhci_device_init(struct usb_device *udev)
4063 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4067 /* no init for root HUB */
4068 if (udev->parent_hub == NULL)
4073 /* set invalid default */
4075 udev->controller_slot_id = sc->sc_noslot + 1;
4077 /* try to get a new slot ID from the XHCI */
4079 err = xhci_cmd_enable_slot(sc, &temp);
4082 XHCI_CMD_UNLOCK(sc);
4086 if (temp > sc->sc_noslot) {
4087 XHCI_CMD_UNLOCK(sc);
4088 return (USB_ERR_BAD_ADDRESS);
4091 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4092 DPRINTF("slot %u already allocated.\n", temp);
4093 XHCI_CMD_UNLOCK(sc);
4094 return (USB_ERR_BAD_ADDRESS);
4097 /* store slot ID for later reference */
4099 udev->controller_slot_id = temp;
4101 /* reset data structure */
4103 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4105 /* set mark slot allocated */
4107 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4109 err = xhci_alloc_device_ext(udev);
4111 XHCI_CMD_UNLOCK(sc);
4113 /* get device into default state */
4116 err = xhci_set_address(udev, NULL, 0);
4122 xhci_device_uninit(struct usb_device *udev)
4124 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4127 /* no init for root HUB */
4128 if (udev->parent_hub == NULL)
4133 index = udev->controller_slot_id;
4135 if (index <= sc->sc_noslot) {
4136 xhci_cmd_disable_slot(sc, index);
4137 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4139 /* free device extension */
4140 xhci_free_device_ext(udev);
4143 XHCI_CMD_UNLOCK(sc);
4147 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4150 * Wait until the hardware has finished any possible use of
4151 * the transfer descriptor(s)
4153 *pus = 2048; /* microseconds */
4157 xhci_device_resume(struct usb_device *udev)
4159 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4166 /* check for root HUB */
4167 if (udev->parent_hub == NULL)
4170 index = udev->controller_slot_id;
4174 /* blindly resume all endpoints */
4176 USB_BUS_LOCK(udev->bus);
4178 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4179 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4180 XWRITE4(sc, door, XHCI_DOORBELL(index),
4181 n | XHCI_DB_SID_SET(p));
4185 USB_BUS_UNLOCK(udev->bus);
4187 XHCI_CMD_UNLOCK(sc);
4191 xhci_device_suspend(struct usb_device *udev)
4193 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4200 /* check for root HUB */
4201 if (udev->parent_hub == NULL)
4204 index = udev->controller_slot_id;
4208 /* blindly suspend all endpoints */
4210 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4211 err = xhci_cmd_stop_ep(sc, 1, n, index);
4213 DPRINTF("Failed to suspend endpoint "
4214 "%u on slot %u (ignored).\n", n, index);
4218 XHCI_CMD_UNLOCK(sc);
4222 xhci_set_hw_power(struct usb_bus *bus)
4228 xhci_device_state_change(struct usb_device *udev)
4230 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4231 struct usb_page_search buf_inp;
4235 /* check for root HUB */
4236 if (udev->parent_hub == NULL)
4239 index = udev->controller_slot_id;
4243 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4244 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4245 &sc->sc_hw.devs[index].tt);
4247 sc->sc_hw.devs[index].nports = 0;
4252 switch (usb_get_device_state(udev)) {
4253 case USB_STATE_POWERED:
4254 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4257 /* set default state */
4258 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4260 /* reset number of contexts */
4261 sc->sc_hw.devs[index].context_num = 0;
4263 err = xhci_cmd_reset_dev(sc, index);
4266 DPRINTF("Device reset failed "
4267 "for slot %u.\n", index);
4271 case USB_STATE_ADDRESSED:
4272 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4275 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4277 /* set configure mask to slot only */
4278 xhci_configure_mask(udev, 1, 0);
4280 /* deconfigure all endpoints, except EP0 */
4281 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4284 DPRINTF("Failed to deconfigure "
4285 "slot %u.\n", index);
4289 case USB_STATE_CONFIGURED:
4290 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4293 /* set configured state */
4294 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4296 /* reset number of contexts */
4297 sc->sc_hw.devs[index].context_num = 0;
4299 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4301 xhci_configure_mask(udev, 3, 0);
4303 err = xhci_configure_device(udev);
4305 DPRINTF("Could not configure device "
4306 "at slot %u.\n", index);
4309 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4311 DPRINTF("Could not evaluate device "
4312 "context at slot %u.\n", index);
4319 XHCI_CMD_UNLOCK(sc);
4323 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4327 case USB_EP_MODE_DEFAULT:
4329 case USB_EP_MODE_STREAMS:
4330 if (xhcistreams == 0 ||
4331 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4332 udev->speed != USB_SPEED_SUPER)
4333 return (USB_ERR_INVAL);
4336 return (USB_ERR_INVAL);
4340 static const struct usb_bus_methods xhci_bus_methods = {
4341 .endpoint_init = xhci_ep_init,
4342 .endpoint_uninit = xhci_ep_uninit,
4343 .xfer_setup = xhci_xfer_setup,
4344 .xfer_unsetup = xhci_xfer_unsetup,
4345 .get_dma_delay = xhci_get_dma_delay,
4346 .device_init = xhci_device_init,
4347 .device_uninit = xhci_device_uninit,
4348 .device_resume = xhci_device_resume,
4349 .device_suspend = xhci_device_suspend,
4350 .set_hw_power = xhci_set_hw_power,
4351 .roothub_exec = xhci_roothub_exec,
4352 .xfer_poll = xhci_do_poll,
4353 .start_dma_delay = xhci_start_dma_delay,
4354 .set_address = xhci_set_address,
4355 .clear_stall = xhci_ep_clear_stall,
4356 .device_state_change = xhci_device_state_change,
4357 .set_hw_power_sleep = xhci_set_hw_power_sleep,
4358 .set_endpoint_mode = xhci_set_endpoint_mode,