sys/dev/usb/controller/xhci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   4  *
   5  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  31  *
  32  * The XHCI 1.0 spec can be found at
  33  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  34  * and the USB 3.0 spec at
  35  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  36  */
  37
  38 /*
  39  * A few words about the design implementation: This driver emulates
  40  * the concept about TDs which is found in EHCI specification. This
  41  * way we achieve that the USB controller drivers look similar to
  42  * eachother which makes it easier to understand the code.
  43  */
  44
  45 #ifdef USB_GLOBAL_INCLUDE_FILE
  46 #include USB_GLOBAL_INCLUDE_FILE
  47 #else
  48 #include <sys/stdint.h>
  49 #include <sys/stddef.h>
  50 #include <sys/param.h>
  51 #include <sys/queue.h>
  52 #include <sys/types.h>
  53 #include <sys/systm.h>
  54 #include <sys/kernel.h>
  55 #include <sys/bus.h>
  56 #include <sys/module.h>
  57 #include <sys/lock.h>
  58 #include <sys/mutex.h>
  59 #include <sys/condvar.h>
  60 #include <sys/sysctl.h>
  61 #include <sys/sx.h>
  62 #include <sys/unistd.h>
  63 #include <sys/callout.h>
  64 #include <sys/malloc.h>
  65 #include <sys/priv.h>
  66
  67 #include <dev/usb/usb.h>
  68 #include <dev/usb/usbdi.h>
  69
  70 #define USB_DEBUG_VAR xhcidebug
  71
  72 #include <dev/usb/usb_core.h>
  73 #include <dev/usb/usb_debug.h>
  74 #include <dev/usb/usb_busdma.h>
  75 #include <dev/usb/usb_process.h>
  76 #include <dev/usb/usb_transfer.h>
  77 #include <dev/usb/usb_device.h>
  78 #include <dev/usb/usb_hub.h>
  79 #include <dev/usb/usb_util.h>
  80
  81 #include <dev/usb/usb_controller.h>
  82 #include <dev/usb/usb_bus.h>
  83 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  84
  85 #include <dev/usb/controller/xhci.h>
  86 #include <dev/usb/controller/xhcireg.h>
  87
  88 #define XHCI_BUS2SC(bus) \
  89    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  90     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  91
  92 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  93
  94 static int xhcistreams;
  95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN,
  96     &xhcistreams, 0, "Set to enable streams mode support");
  97
  98 static int xhcictlquirk = 1;
  99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN,
 100     &xhcictlquirk, 0, "Set to enable control endpoint quirk");
 101
 102 #ifdef USB_DEBUG
 103 static int xhcidebug;
 104 static int xhciroute;
 105 static int xhcipolling;
 106 static int xhcidma32;
 107 static int xhcictlstep;
 108
 109 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN,
 110     &xhcidebug, 0, "Debug level");
 111 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN,
 112     &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
 113 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN,
 114     &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
 115 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
 116     &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
 117 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
 118     &xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
 119 #else
 120 #define xhciroute 0
 121 #define xhcidma32 0
 122 #define xhcictlstep 0
 123 #endif
 124
 125 #define XHCI_INTR_ENDPT 1
 126
 127 struct xhci_std_temp {
 128         struct xhci_softc       *sc;
 129         struct usb_page_cache   *pc;
 130         struct xhci_td          *td;
 131         struct xhci_td          *td_next;
 132         uint32_t                len;
 133         uint32_t                offset;
 134         uint32_t                max_packet_size;
 135         uint32_t                average;
 136         uint16_t                isoc_delta;
 137         uint16_t                isoc_frame;
 138         uint8_t                 shortpkt;
 139         uint8_t                 multishort;
 140         uint8_t                 last_frame;
 141         uint8_t                 trb_type;
 142         uint8_t                 direction;
 143         uint8_t                 tbc;
 144         uint8_t                 tlbpc;
 145         uint8_t                 step_td;
 146         uint8_t                 do_isoc_sync;
 147 };
 148
 149 static void     xhci_do_poll(struct usb_bus *);
 150 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 151 static void     xhci_root_intr(struct xhci_softc *);
 152 static void     xhci_free_device_ext(struct usb_device *);
 153 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 154                     struct usb_endpoint_descriptor *);
 155 static usb_proc_callback_t xhci_configure_msg;
 156 static usb_error_t xhci_configure_device(struct usb_device *);
 157 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 158                    struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 159                    uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
 160                    uint8_t);
 161 static usb_error_t xhci_configure_mask(struct usb_device *,
 162                     uint32_t, uint8_t);
 163 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 164                     uint64_t, uint8_t);
 165 static void xhci_endpoint_doorbell(struct usb_xfer *);
 166 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 167 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 168 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 169 #ifdef USB_DEBUG
 170 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 171 #endif
 172
 173 static const struct usb_bus_methods xhci_bus_methods;
 174
 175 #ifdef USB_DEBUG
 176 static void
 177 xhci_dump_trb(struct xhci_trb *trb)
 178 {
 179         DPRINTFN(5, "trb = %p\n", trb);
 180         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 181         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 182         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 183 }
 184
 185 static void
 186 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 187 {
 188         DPRINTFN(5, "pep = %p\n", pep);
 189         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 190         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 191         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 192         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 193         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 194         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 195         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 196 }
 197
 198 static void
 199 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 200 {
 201         DPRINTFN(5, "psl = %p\n", psl);
 202         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 203         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 204         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 205         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 206 }
 207 #endif
 208
 209 uint8_t
 210 xhci_use_polling(void)
 211 {
 212 #ifdef USB_DEBUG
 213         return (xhcipolling != 0);
 214 #else
 215         return (0);
 216 #endif
 217 }
 218
 219 static void
 220 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 221 {
 222         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 223         uint16_t i;
 224
 225         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 226            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 227
 228         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 229            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 230
 231         for (i = 0; i != sc->sc_noscratch; i++) {
 232                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 233                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 234         }
 235 }
 236
 237 static void
 238 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 239 {
 240         if (sc->sc_ctx_is_64_byte) {
 241                 uint32_t offset;
 242                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 243                 /* all contexts are initially 32-bytes */
 244                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 245                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 246         }
 247         *ptr = htole32(val);
 248 }
 249
 250 static uint32_t
 251 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 252 {
 253         if (sc->sc_ctx_is_64_byte) {
 254                 uint32_t offset;
 255                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 256                 /* all contexts are initially 32-bytes */
 257                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 258                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 259         }
 260         return (le32toh(*ptr));
 261 }
 262
 263 static void
 264 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 265 {
 266         if (sc->sc_ctx_is_64_byte) {
 267                 uint32_t offset;
 268                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 269                 /* all contexts are initially 32-bytes */
 270                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 271                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 272         }
 273         *ptr = htole64(val);
 274 }
 275
 276 #ifdef USB_DEBUG
 277 static uint64_t
 278 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 279 {
 280         if (sc->sc_ctx_is_64_byte) {
 281                 uint32_t offset;
 282                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 283                 /* all contexts are initially 32-bytes */
 284                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 285                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 286         }
 287         return (le64toh(*ptr));
 288 }
 289 #endif
 290
 291 static int
 292 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 293 {
 294         struct usb_page_search buf_res;
 295         struct xhci_hw_root *phwr;
 296         uint64_t addr;
 297         uint32_t temp;
 298
 299         DPRINTF("\n");
 300
 301         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 302         if (temp & XHCI_CRCR_LO_CRR) {
 303                 DPRINTF("Command ring running\n");
 304                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 305
 306                 /*
 307                  * Try to abort the last command as per section
 308                  * 4.6.1.2 "Aborting a Command" of the XHCI
 309                  * specification:
 310                  */
 311
 312                 /* stop and cancel */
 313                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 314                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 315
 316                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 317                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 318
 319                 /* wait 250ms */
 320                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 321
 322                 /* check if command ring is still running */
 323                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 324                 if (temp & XHCI_CRCR_LO_CRR) {
 325                         DPRINTF("Comand ring still running\n");
 326                         return (USB_ERR_IOERROR);
 327                 }
 328         }
 329
 330         /* reset command ring */
 331         sc->sc_command_ccs = 1;
 332         sc->sc_command_idx = 0;
 333
 334         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 335
 336         /* set up command ring control base address */
 337         addr = buf_res.physaddr;
 338         phwr = buf_res.buffer;
 339         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 340
 341         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 342
 343         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 344         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 345
 346         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 347
 348         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 349         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 350
 351         return (0);
 352 }
 353
 354 usb_error_t
 355 xhci_start_controller(struct xhci_softc *sc)
 356 {
 357         struct usb_page_search buf_res;
 358         struct xhci_hw_root *phwr;
 359         struct xhci_dev_ctx_addr *pdctxa;
 360         usb_error_t err;
 361         uint64_t addr;
 362         uint32_t temp;
 363         uint16_t i;
 364
 365         DPRINTF("\n");
 366
 367         sc->sc_event_ccs = 1;
 368         sc->sc_event_idx = 0;
 369         sc->sc_command_ccs = 1;
 370         sc->sc_command_idx = 0;
 371
 372         err = xhci_reset_controller(sc);
 373         if (err)
 374                 return (err);
 375
 376         /* set up number of device slots */
 377         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 378             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 379
 380         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 381
 382         temp = XREAD4(sc, oper, XHCI_USBSTS);
 383
 384         /* clear interrupts */
 385         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 386         /* disable all device notifications */
 387         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 388
 389         /* set up device context base address */
 390         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 391         pdctxa = buf_res.buffer;
 392         memset(pdctxa, 0, sizeof(*pdctxa));
 393
 394         addr = buf_res.physaddr;
 395         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 396
 397         /* slot 0 points to the table of scratchpad pointers */
 398         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 399
 400         for (i = 0; i != sc->sc_noscratch; i++) {
 401                 struct usb_page_search buf_scp;
 402                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 403                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 404         }
 405
 406         addr = buf_res.physaddr;
 407
 408         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 409         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 410         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 411         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 412
 413         /* set up event table size */
 414         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 415             XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
 416
 417         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
 418
 419         /* set up interrupt rate */
 420         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 421
 422         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 423
 424         phwr = buf_res.buffer;
 425         addr = buf_res.physaddr;
 426         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 427
 428         /* reset hardware root structure */
 429         memset(phwr, 0, sizeof(*phwr));
 430
 431         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 432         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 433
 434         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 435
 436         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 437         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 438
 439         addr = buf_res.physaddr;
 440
 441         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 442
 443         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 444         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 445
 446         /* set up interrupter registers */
 447         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 448         temp |= XHCI_IMAN_INTR_ENA;
 449         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 450
 451         /* set up command ring control base address */
 452         addr = buf_res.physaddr;
 453         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 454
 455         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 456
 457         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 458         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 459
 460         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 461
 462         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 463
 464         /* Go! */
 465         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 466             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 467
 468         for (i = 0; i != 100; i++) {
 469                 usb_pause_mtx(NULL, hz / 100);
 470                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 471                 if (!temp)
 472                         break;
 473         }
 474         if (temp) {
 475                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 476                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 477                 return (USB_ERR_IOERROR);
 478         }
 479
 480         /* catch any lost interrupts */
 481         xhci_do_poll(&sc->sc_bus);
 482
 483         if (sc->sc_port_route != NULL) {
 484                 /* Route all ports to the XHCI by default */
 485                 sc->sc_port_route(sc->sc_bus.parent,
 486                     ~xhciroute, xhciroute);
 487         }
 488         return (0);
 489 }
 490
 491 usb_error_t
 492 xhci_halt_controller(struct xhci_softc *sc)
 493 {
 494         uint32_t temp;
 495         uint16_t i;
 496
 497         DPRINTF("\n");
 498
 499         sc->sc_capa_off = 0;
 500         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 501         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 502         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 503
 504         /* Halt controller */
 505         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 506
 507         for (i = 0; i != 100; i++) {
 508                 usb_pause_mtx(NULL, hz / 100);
 509                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 510                 if (temp)
 511                         break;
 512         }
 513
 514         if (!temp) {
 515                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 516                 return (USB_ERR_IOERROR);
 517         }
 518         return (0);
 519 }
 520
 521 usb_error_t
 522 xhci_reset_controller(struct xhci_softc *sc)
 523 {
 524         uint32_t temp = 0;
 525         uint16_t i;
 526
 527         DPRINTF("\n");
 528
 529         /* Reset controller */
 530         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 531
 532         for (i = 0; i != 100; i++) {
 533                 usb_pause_mtx(NULL, hz / 100);
 534                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 535                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 536                 if (!temp)
 537                         break;
 538         }
 539
 540         if (temp) {
 541                 device_printf(sc->sc_bus.parent, "Controller "
 542                     "reset timeout.\n");
 543                 return (USB_ERR_IOERROR);
 544         }
 545         return (0);
 546 }
 547
 548 usb_error_t
 549 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
 550 {
 551         uint32_t temp;
 552
 553         DPRINTF("\n");
 554
 555         /* initialize some bus fields */
 556         sc->sc_bus.parent = self;
 557
 558         /* set the bus revision */
 559         sc->sc_bus.usbrev = USB_REV_3_0;
 560
 561         /* set up the bus struct */
 562         sc->sc_bus.methods = &xhci_bus_methods;
 563
 564         /* set up devices array */
 565         sc->sc_bus.devices = sc->sc_devices;
 566         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 567
 568         /* set default cycle state in case of early interrupts */
 569         sc->sc_event_ccs = 1;
 570         sc->sc_command_ccs = 1;
 571
 572         /* set up bus space offsets */
 573         sc->sc_capa_off = 0;
 574         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 575         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 576         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 577
 578         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 579         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 580         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 581
 582         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 583
 584         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 585                 device_printf(sc->sc_bus.parent, "Controller does "
 586                     "not support 4K page size.\n");
 587                 return (ENXIO);
 588         }
 589
 590         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 591
 592         DPRINTF("HCS0 = 0x%08x\n", temp);
 593
 594         /* set up context size */
 595         if (XHCI_HCS0_CSZ(temp)) {
 596                 sc->sc_ctx_is_64_byte = 1;
 597         } else {
 598                 sc->sc_ctx_is_64_byte = 0;
 599         }
 600
 601         /* get DMA bits */
 602         sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
 603             xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
 604
 605         device_printf(self, "%d bytes context size, %d-bit DMA\n",
 606             sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
 607
 608         /* enable 64Kbyte control endpoint quirk */
 609         sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0);
 610
 611         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 612
 613         /* get number of device slots */
 614         sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
 615
 616         if (sc->sc_noport == 0) {
 617                 device_printf(sc->sc_bus.parent, "Invalid number "
 618                     "of ports: %u\n", sc->sc_noport);
 619                 return (ENXIO);
 620         }
 621
 622         sc->sc_noport = sc->sc_noport;
 623         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 624
 625         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 626
 627         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 628                 sc->sc_noslot = XHCI_MAX_DEVICES;
 629
 630         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 631
 632         DPRINTF("HCS2=0x%08x\n", temp);
 633
 634         /* get number of scratchpads */
 635         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 636
 637         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 638                 device_printf(sc->sc_bus.parent, "XHCI request "
 639                     "too many scratchpads\n");
 640                 return (ENOMEM);
 641         }
 642
 643         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 644
 645         /* get event table size */
 646         sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
 647         if (sc->sc_erst_max > XHCI_MAX_RSEG)
 648                 sc->sc_erst_max = XHCI_MAX_RSEG;
 649
 650         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 651
 652         /* get maximum exit latency */
 653         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 654             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 655
 656         /* Check if we should use the default IMOD value. */
 657         if (sc->sc_imod_default == 0)
 658                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 659
 660         /* get all DMA memory */
 661         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 662             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 663                 return (ENOMEM);
 664         }
 665
 666         /* set up command queue mutex and condition varible */
 667         cv_init(&sc->sc_cmd_cv, "CMDQ");
 668         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 669
 670         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 671         sc->sc_config_msg[0].bus = &sc->sc_bus;
 672         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 673         sc->sc_config_msg[1].bus = &sc->sc_bus;
 674
 675         return (0);
 676 }
 677
 678 void
 679 xhci_uninit(struct xhci_softc *sc)
 680 {
 681         /*
 682          * NOTE: At this point the control transfer process is gone
 683          * and "xhci_configure_msg" is no longer called. Consequently
 684          * waiting for the configuration messages to complete is not
 685          * needed.
 686          */
 687         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 688
 689         cv_destroy(&sc->sc_cmd_cv);
 690         sx_destroy(&sc->sc_cmd_sx);
 691 }
 692
 693 static void
 694 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 695 {
 696         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 697
 698         switch (state) {
 699         case USB_HW_POWER_SUSPEND:
 700                 DPRINTF("Stopping the XHCI\n");
 701                 xhci_halt_controller(sc);
 702                 xhci_reset_controller(sc);
 703                 break;
 704         case USB_HW_POWER_SHUTDOWN:
 705                 DPRINTF("Stopping the XHCI\n");
 706                 xhci_halt_controller(sc);
 707                 xhci_reset_controller(sc);
 708                 break;
 709         case USB_HW_POWER_RESUME:
 710                 DPRINTF("Starting the XHCI\n");
 711                 xhci_start_controller(sc);
 712                 break;
 713         default:
 714                 break;
 715         }
 716 }
 717
 718 static usb_error_t
 719 xhci_generic_done_sub(struct usb_xfer *xfer)
 720 {
 721         struct xhci_td *td;
 722         struct xhci_td *td_alt_next;
 723         uint32_t len;
 724         uint8_t status;
 725
 726         td = xfer->td_transfer_cache;
 727         td_alt_next = td->alt_next;
 728
 729         if (xfer->aframes != xfer->nframes)
 730                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 731
 732         while (1) {
 733
 734                 usb_pc_cpu_invalidate(td->page_cache);
 735
 736                 status = td->status;
 737                 len = td->remainder;
 738
 739                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 740                     xfer, (unsigned int)xfer->aframes,
 741                     (unsigned int)xfer->nframes,
 742                     (unsigned int)len, (unsigned int)td->len,
 743                     (unsigned int)status);
 744
 745                 /*
 746                  * Verify the status length and
 747                  * add the length to "frlengths[]":
 748                  */
 749                 if (len > td->len) {
 750                         /* should not happen */
 751                         DPRINTF("Invalid status length, "
 752                             "0x%04x/0x%04x bytes\n", len, td->len);
 753                         status = XHCI_TRB_ERROR_LENGTH;
 754                 } else if (xfer->aframes != xfer->nframes) {
 755                         xfer->frlengths[xfer->aframes] += td->len - len;
 756                 }
 757                 /* Check for last transfer */
 758                 if (((void *)td) == xfer->td_transfer_last) {
 759                         td = NULL;
 760                         break;
 761                 }
 762                 /* Check for transfer error */
 763                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 764                     status != XHCI_TRB_ERROR_SUCCESS) {
 765                         /* the transfer is finished */
 766                         td = NULL;
 767                         break;
 768                 }
 769                 /* Check for short transfer */
 770                 if (len > 0) {
 771                         if (xfer->flags_int.short_frames_ok ||
 772                             xfer->flags_int.isochronous_xfr ||
 773                             xfer->flags_int.control_xfr) {
 774                                 /* follow alt next */
 775                                 td = td->alt_next;
 776                         } else {
 777                                 /* the transfer is finished */
 778                                 td = NULL;
 779                         }
 780                         break;
 781                 }
 782                 td = td->obj_next;
 783
 784                 if (td->alt_next != td_alt_next) {
 785                         /* this USB frame is complete */
 786                         break;
 787                 }
 788         }
 789
 790         /* update transfer cache */
 791
 792         xfer->td_transfer_cache = td;
 793
 794         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 795             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 796             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 797             USB_ERR_NORMAL_COMPLETION);
 798 }
 799
 800 static void
 801 xhci_generic_done(struct usb_xfer *xfer)
 802 {
 803         usb_error_t err = 0;
 804
 805         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 806             xfer, xfer->endpoint);
 807
 808         /* reset scanner */
 809
 810         xfer->td_transfer_cache = xfer->td_transfer_first;
 811
 812         if (xfer->flags_int.control_xfr) {
 813
 814                 if (xfer->flags_int.control_hdr)
 815                         err = xhci_generic_done_sub(xfer);
 816
 817                 xfer->aframes = 1;
 818
 819                 if (xfer->td_transfer_cache == NULL)
 820                         goto done;
 821         }
 822
 823         while (xfer->aframes != xfer->nframes) {
 824
 825                 err = xhci_generic_done_sub(xfer);
 826                 xfer->aframes++;
 827
 828                 if (xfer->td_transfer_cache == NULL)
 829                         goto done;
 830         }
 831
 832         if (xfer->flags_int.control_xfr &&
 833             !xfer->flags_int.control_act)
 834                 err = xhci_generic_done_sub(xfer);
 835 done:
 836         /* transfer is complete */
 837         xhci_device_done(xfer, err);
 838 }
 839
 840 static void
 841 xhci_activate_transfer(struct usb_xfer *xfer)
 842 {
 843         struct xhci_td *td;
 844
 845         td = xfer->td_transfer_cache;
 846
 847         usb_pc_cpu_invalidate(td->page_cache);
 848
 849         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 850
 851                 /* activate the transfer */
 852
 853                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 854                 usb_pc_cpu_flush(td->page_cache);
 855
 856                 xhci_endpoint_doorbell(xfer);
 857         }
 858 }
 859
 860 static void
 861 xhci_skip_transfer(struct usb_xfer *xfer)
 862 {
 863         struct xhci_td *td;
 864         struct xhci_td *td_last;
 865
 866         td = xfer->td_transfer_cache;
 867         td_last = xfer->td_transfer_last;
 868
 869         td = td->alt_next;
 870
 871         usb_pc_cpu_invalidate(td->page_cache);
 872
 873         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 874
 875                 usb_pc_cpu_invalidate(td_last->page_cache);
 876
 877                 /* copy LINK TRB to current waiting location */
 878
 879                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 880                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 881                 usb_pc_cpu_flush(td->page_cache);
 882
 883                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 884                 usb_pc_cpu_flush(td->page_cache);
 885
 886                 xhci_endpoint_doorbell(xfer);
 887         }
 888 }
 889
 890 /*------------------------------------------------------------------------*
 891  *      xhci_check_transfer
 892  *------------------------------------------------------------------------*/
 893 static void
 894 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 895 {
 896         struct xhci_endpoint_ext *pepext;
 897         int64_t offset;
 898         uint64_t td_event;
 899         uint32_t temp;
 900         uint32_t remainder;
 901         uint16_t stream_id = 0;
 902         uint16_t i;
 903         uint8_t status;
 904         uint8_t halted;
 905         uint8_t epno;
 906         uint8_t index;
 907
 908         /* decode TRB */
 909         td_event = le64toh(trb->qwTrb0);
 910         temp = le32toh(trb->dwTrb2);
 911
 912         remainder = XHCI_TRB_2_REM_GET(temp);
 913         status = XHCI_TRB_2_ERROR_GET(temp);
 914
 915         temp = le32toh(trb->dwTrb3);
 916         epno = XHCI_TRB_3_EP_GET(temp);
 917         index = XHCI_TRB_3_SLOT_GET(temp);
 918
 919         /* check if error means halted */
 920         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 921             status != XHCI_TRB_ERROR_SUCCESS);
 922
 923         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 924             index, epno, remainder, status);
 925
 926         if (index > sc->sc_noslot) {
 927                 DPRINTF("Invalid slot.\n");
 928                 return;
 929         }
 930
 931         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 932                 DPRINTF("Invalid endpoint.\n");
 933                 return;
 934         }
 935
 936         pepext = &sc->sc_hw.devs[index].endp[epno];
 937
 938         /* try to find the USB transfer that generated the event */
 939         for (i = 0;; i++) {
 940                 struct usb_xfer *xfer;
 941                 struct xhci_td *td;
 942
 943                 if (i == (XHCI_MAX_TRANSFERS - 1)) {
 944                         if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS ||
 945                             stream_id == (XHCI_MAX_STREAMS - 1))
 946                                 break;
 947                         stream_id++;
 948                         i = 0;
 949                         DPRINTFN(5, "stream_id=%u\n", stream_id);
 950                 }
 951
 952                 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
 953                 if (xfer == NULL)
 954                         continue;
 955
 956                 td = xfer->td_transfer_cache;
 957
 958                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 959                         (long long)td_event,
 960                         (long long)td->td_self,
 961                         (long long)td->td_self + sizeof(td->td_trb));
 962
 963                 /*
 964                  * NOTE: Some XHCI implementations might not trigger
 965                  * an event on the last LINK TRB so we need to
 966                  * consider both the last and second last event
 967                  * address as conditions for a successful transfer.
 968                  *
 969                  * NOTE: We assume that the XHCI will only trigger one
 970                  * event per chain of TRBs.
 971                  */
 972
 973                 offset = td_event - td->td_self;
 974
 975                 if (offset >= 0 &&
 976                     offset < (int64_t)sizeof(td->td_trb)) {
 977
 978                         usb_pc_cpu_invalidate(td->page_cache);
 979
 980                         /* compute rest of remainder, if any */
 981                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 982                                 temp = le32toh(td->td_trb[i].dwTrb2);
 983                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 984                         }
 985
 986                         DPRINTFN(5, "New remainder: %u\n", remainder);
 987
 988                         /* clear isochronous transfer errors */
 989                         if (xfer->flags_int.isochronous_xfr) {
 990                                 if (halted) {
 991                                         halted = 0;
 992                                         status = XHCI_TRB_ERROR_SUCCESS;
 993                                         remainder = td->len;
 994                                 }
 995                         }
 996
 997                         /* "td->remainder" is verified later */
 998                         td->remainder = remainder;
 999                         td->status = status;
1000
1001                         usb_pc_cpu_flush(td->page_cache);
1002
1003                         /*
1004                          * 1) Last transfer descriptor makes the
1005                          * transfer done
1006                          */
1007                         if (((void *)td) == xfer->td_transfer_last) {
1008                                 DPRINTF("TD is last\n");
1009                                 xhci_generic_done(xfer);
1010                                 break;
1011                         }
1012
1013                         /*
1014                          * 2) Any kind of error makes the transfer
1015                          * done
1016                          */
1017                         if (halted) {
1018                                 DPRINTF("TD has I/O error\n");
1019                                 xhci_generic_done(xfer);
1020                                 break;
1021                         }
1022
1023                         /*
1024                          * 3) If there is no alternate next transfer,
1025                          * a short packet also makes the transfer done
1026                          */
1027                         if (td->remainder > 0) {
1028                                 if (td->alt_next == NULL) {
1029                                         DPRINTF(
1030                                             "short TD has no alternate next\n");
1031                                         xhci_generic_done(xfer);
1032                                         break;
1033                                 }
1034                                 DPRINTF("TD has short pkt\n");
1035                                 if (xfer->flags_int.short_frames_ok ||
1036                                     xfer->flags_int.isochronous_xfr ||
1037                                     xfer->flags_int.control_xfr) {
1038                                         /* follow the alt next */
1039                                         xfer->td_transfer_cache = td->alt_next;
1040                                         xhci_activate_transfer(xfer);
1041                                         break;
1042                                 }
1043                                 xhci_skip_transfer(xfer);
1044                                 xhci_generic_done(xfer);
1045                                 break;
1046                         }
1047
1048                         /*
1049                          * 4) Transfer complete - go to next TD
1050                          */
1051                         DPRINTF("Following next TD\n");
1052                         xfer->td_transfer_cache = td->obj_next;
1053                         xhci_activate_transfer(xfer);
1054                         break;          /* there should only be one match */
1055                 }
1056         }
1057 }
1058
1059 static int
1060 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1061 {
1062         if (sc->sc_cmd_addr == trb->qwTrb0) {
1063                 DPRINTF("Received command event\n");
1064                 sc->sc_cmd_result[0] = trb->dwTrb2;
1065                 sc->sc_cmd_result[1] = trb->dwTrb3;
1066                 cv_signal(&sc->sc_cmd_cv);
1067                 return (1);     /* command match */
1068         }
1069         return (0);
1070 }
1071
1072 static int
1073 xhci_interrupt_poll(struct xhci_softc *sc)
1074 {
1075         struct usb_page_search buf_res;
1076         struct xhci_hw_root *phwr;
1077         uint64_t addr;
1078         uint32_t temp;
1079         int retval = 0;
1080         uint16_t i;
1081         uint8_t event;
1082         uint8_t j;
1083         uint8_t k;
1084         uint8_t t;
1085
1086         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1087
1088         phwr = buf_res.buffer;
1089
1090         /* Receive any events */
1091
1092         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1093
1094         i = sc->sc_event_idx;
1095         j = sc->sc_event_ccs;
1096         t = 2;
1097
1098         while (1) {
1099
1100                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1101
1102                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1103
1104                 if (j != k)
1105                         break;
1106
1107                 event = XHCI_TRB_3_TYPE_GET(temp);
1108
1109                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1110                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1111                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1112                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1113
1114                 switch (event) {
1115                 case XHCI_TRB_EVENT_TRANSFER:
1116                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1117                         break;
1118                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1119                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1120                         break;
1121                 default:
1122                         DPRINTF("Unhandled event = %u\n", event);
1123                         break;
1124                 }
1125
1126                 i++;
1127
1128                 if (i == XHCI_MAX_EVENTS) {
1129                         i = 0;
1130                         j ^= 1;
1131
1132                         /* check for timeout */
1133                         if (!--t)
1134                                 break;
1135                 }
1136         }
1137
1138         sc->sc_event_idx = i;
1139         sc->sc_event_ccs = j;
1140
1141         /*
1142          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1143          * latched. That means to activate the register we need to
1144          * write both the low and high double word of the 64-bit
1145          * register.
1146          */
1147
1148         addr = buf_res.physaddr;
1149         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1150
1151         /* try to clear busy bit */
1152         addr |= XHCI_ERDP_LO_BUSY;
1153
1154         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1155         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1156
1157         return (retval);
1158 }
1159
1160 static usb_error_t
1161 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1162     uint16_t timeout_ms)
1163 {
1164         struct usb_page_search buf_res;
1165         struct xhci_hw_root *phwr;
1166         uint64_t addr;
1167         uint32_t temp;
1168         uint8_t i;
1169         uint8_t j;
1170         uint8_t timeout = 0;
1171         int err;
1172
1173         XHCI_CMD_ASSERT_LOCKED(sc);
1174
1175         /* get hardware root structure */
1176
1177         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1178
1179         phwr = buf_res.buffer;
1180
1181         /* Queue command */
1182
1183         USB_BUS_LOCK(&sc->sc_bus);
1184 retry:
1185         i = sc->sc_command_idx;
1186         j = sc->sc_command_ccs;
1187
1188         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1189             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1190             (long long)le64toh(trb->qwTrb0),
1191             (long)le32toh(trb->dwTrb2),
1192             (long)le32toh(trb->dwTrb3));
1193
1194         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1195         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1196
1197         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1198
1199         temp = trb->dwTrb3;
1200
1201         if (j)
1202                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1203         else
1204                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1205
1206         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1207
1208         phwr->hwr_commands[i].dwTrb3 = temp;
1209
1210         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1211
1212         addr = buf_res.physaddr;
1213         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1214
1215         sc->sc_cmd_addr = htole64(addr);
1216
1217         i++;
1218
1219         if (i == (XHCI_MAX_COMMANDS - 1)) {
1220
1221                 if (j) {
1222                         temp = htole32(XHCI_TRB_3_TC_BIT |
1223                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1224                             XHCI_TRB_3_CYCLE_BIT);
1225                 } else {
1226                         temp = htole32(XHCI_TRB_3_TC_BIT |
1227                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1228                 }
1229
1230                 phwr->hwr_commands[i].dwTrb3 = temp;
1231
1232                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1233
1234                 i = 0;
1235                 j ^= 1;
1236         }
1237
1238         sc->sc_command_idx = i;
1239         sc->sc_command_ccs = j;
1240
1241         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1242
1243         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1244             USB_MS_TO_TICKS(timeout_ms));
1245
1246         /*
1247          * In some error cases event interrupts are not generated.
1248          * Poll one time to see if the command has completed.
1249          */
1250         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1251                 DPRINTF("Command was completed when polling\n");
1252                 err = 0;
1253         }
1254         if (err != 0) {
1255                 DPRINTF("Command timeout!\n");
1256                 /*
1257                  * After some weeks of continuous operation, it has
1258                  * been observed that the ASMedia Technology, ASM1042
1259                  * SuperSpeed USB Host Controller can suddenly stop
1260                  * accepting commands via the command queue. Try to
1261                  * first reset the command queue. If that fails do a
1262                  * host controller reset.
1263                  */
1264                 if (timeout == 0 &&
1265                     xhci_reset_command_queue_locked(sc) == 0) {
1266                         temp = le32toh(trb->dwTrb3);
1267
1268                         /*
1269                          * Avoid infinite XHCI reset loops if the set
1270                          * address command fails to respond due to a
1271                          * non-enumerating device:
1272                          */
1273                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1274                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1275                                 DPRINTF("Set address timeout\n");
1276                         } else {
1277                                 timeout = 1;
1278                                 goto retry;
1279                         }
1280                 } else {
1281                         DPRINTF("Controller reset!\n");
1282                         usb_bus_reset_async_locked(&sc->sc_bus);
1283                 }
1284                 err = USB_ERR_TIMEOUT;
1285                 trb->dwTrb2 = 0;
1286                 trb->dwTrb3 = 0;
1287         } else {
1288                 temp = le32toh(sc->sc_cmd_result[0]);
1289                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1290                         err = USB_ERR_IOERROR;
1291
1292                 trb->dwTrb2 = sc->sc_cmd_result[0];
1293                 trb->dwTrb3 = sc->sc_cmd_result[1];
1294         }
1295
1296         USB_BUS_UNLOCK(&sc->sc_bus);
1297
1298         return (err);
1299 }
1300
1301 #if 0
1302 static usb_error_t
1303 xhci_cmd_nop(struct xhci_softc *sc)
1304 {
1305         struct xhci_trb trb;
1306         uint32_t temp;
1307
1308         DPRINTF("\n");
1309
1310         trb.qwTrb0 = 0;
1311         trb.dwTrb2 = 0;
1312         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1313
1314         trb.dwTrb3 = htole32(temp);
1315
1316         return (xhci_do_command(sc, &trb, 100 /* ms */));
1317 }
1318 #endif
1319
1320 static usb_error_t
1321 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1322 {
1323         struct xhci_trb trb;
1324         uint32_t temp;
1325         usb_error_t err;
1326
1327         DPRINTF("\n");
1328
1329         trb.qwTrb0 = 0;
1330         trb.dwTrb2 = 0;
1331         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1332
1333         err = xhci_do_command(sc, &trb, 100 /* ms */);
1334         if (err)
1335                 goto done;
1336
1337         temp = le32toh(trb.dwTrb3);
1338
1339         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1340
1341 done:
1342         return (err);
1343 }
1344
1345 static usb_error_t
1346 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1347 {
1348         struct xhci_trb trb;
1349         uint32_t temp;
1350
1351         DPRINTF("\n");
1352
1353         trb.qwTrb0 = 0;
1354         trb.dwTrb2 = 0;
1355         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1356             XHCI_TRB_3_SLOT_SET(slot_id);
1357
1358         trb.dwTrb3 = htole32(temp);
1359
1360         return (xhci_do_command(sc, &trb, 100 /* ms */));
1361 }
1362
1363 static usb_error_t
1364 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1365     uint8_t bsr, uint8_t slot_id)
1366 {
1367         struct xhci_trb trb;
1368         uint32_t temp;
1369
1370         DPRINTF("\n");
1371
1372         trb.qwTrb0 = htole64(input_ctx);
1373         trb.dwTrb2 = 0;
1374         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1375             XHCI_TRB_3_SLOT_SET(slot_id);
1376
1377         if (bsr)
1378                 temp |= XHCI_TRB_3_BSR_BIT;
1379
1380         trb.dwTrb3 = htole32(temp);
1381
1382         return (xhci_do_command(sc, &trb, 500 /* ms */));
1383 }
1384
1385 static usb_error_t
1386 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1387 {
1388         struct usb_page_search buf_inp;
1389         struct usb_page_search buf_dev;
1390         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1391         struct xhci_hw_dev *hdev;
1392         struct xhci_dev_ctx *pdev;
1393         struct xhci_endpoint_ext *pepext;
1394         uint32_t temp;
1395         uint16_t mps;
1396         usb_error_t err;
1397         uint8_t index;
1398
1399         /* the root HUB case is not handled here */
1400         if (udev->parent_hub == NULL)
1401                 return (USB_ERR_INVAL);
1402
1403         index = udev->controller_slot_id;
1404
1405         hdev =  &sc->sc_hw.devs[index];
1406
1407         if (mtx != NULL)
1408                 mtx_unlock(mtx);
1409
1410         XHCI_CMD_LOCK(sc);
1411
1412         switch (hdev->state) {
1413         case XHCI_ST_DEFAULT:
1414         case XHCI_ST_ENABLED:
1415
1416                 hdev->state = XHCI_ST_ENABLED;
1417
1418                 /* set configure mask to slot and EP0 */
1419                 xhci_configure_mask(udev, 3, 0);
1420
1421                 /* configure input slot context structure */
1422                 err = xhci_configure_device(udev);
1423
1424                 if (err != 0) {
1425                         DPRINTF("Could not configure device\n");
1426                         break;
1427                 }
1428
1429                 /* configure input endpoint context structure */
1430                 switch (udev->speed) {
1431                 case USB_SPEED_LOW:
1432                 case USB_SPEED_FULL:
1433                         mps = 8;
1434                         break;
1435                 case USB_SPEED_HIGH:
1436                         mps = 64;
1437                         break;
1438                 default:
1439                         mps = 512;
1440                         break;
1441                 }
1442
1443                 pepext = xhci_get_endpoint_ext(udev,
1444                     &udev->ctrl_ep_desc);
1445
1446                 /* ensure the control endpoint is setup again */
1447                 USB_BUS_LOCK(udev->bus);
1448                 pepext->trb_halted = 1;
1449                 pepext->trb_running = 0;
1450                 USB_BUS_UNLOCK(udev->bus);
1451
1452                 err = xhci_configure_endpoint(udev,
1453                     &udev->ctrl_ep_desc, pepext,
1454                     0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1455
1456                 if (err != 0) {
1457                         DPRINTF("Could not configure default endpoint\n");
1458                         break;
1459                 }
1460
1461                 /* execute set address command */
1462                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1463
1464                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1465                     (address == 0), index);
1466
1467                 if (err != 0) {
1468                         temp = le32toh(sc->sc_cmd_result[0]);
1469                         if (address == 0 && sc->sc_port_route != NULL &&
1470                             XHCI_TRB_2_ERROR_GET(temp) ==
1471                             XHCI_TRB_ERROR_PARAMETER) {
1472                                 /* LynxPoint XHCI - ports are not switchable */
1473                                 /* Un-route all ports from the XHCI */
1474                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1475                         }
1476                         DPRINTF("Could not set address "
1477                             "for slot %u.\n", index);
1478                         if (address != 0)
1479                                 break;
1480                 }
1481
1482                 /* update device address to new value */
1483
1484                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1485                 pdev = buf_dev.buffer;
1486                 usb_pc_cpu_invalidate(&hdev->device_pc);
1487
1488                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1489                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1490
1491                 /* update device state to new value */
1492
1493                 if (address != 0)
1494                         hdev->state = XHCI_ST_ADDRESSED;
1495                 else
1496                         hdev->state = XHCI_ST_DEFAULT;
1497                 break;
1498
1499         default:
1500                 DPRINTF("Wrong state for set address.\n");
1501                 err = USB_ERR_IOERROR;
1502                 break;
1503         }
1504         XHCI_CMD_UNLOCK(sc);
1505
1506         if (mtx != NULL)
1507                 mtx_lock(mtx);
1508
1509         return (err);
1510 }
1511
1512 static usb_error_t
1513 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1514     uint8_t deconfigure, uint8_t slot_id)
1515 {
1516         struct xhci_trb trb;
1517         uint32_t temp;
1518
1519         DPRINTF("\n");
1520
1521         trb.qwTrb0 = htole64(input_ctx);
1522         trb.dwTrb2 = 0;
1523         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1524             XHCI_TRB_3_SLOT_SET(slot_id);
1525
1526         if (deconfigure)
1527                 temp |= XHCI_TRB_3_DCEP_BIT;
1528
1529         trb.dwTrb3 = htole32(temp);
1530
1531         return (xhci_do_command(sc, &trb, 100 /* ms */));
1532 }
1533
1534 static usb_error_t
1535 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1536     uint8_t slot_id)
1537 {
1538         struct xhci_trb trb;
1539         uint32_t temp;
1540
1541         DPRINTF("\n");
1542
1543         trb.qwTrb0 = htole64(input_ctx);
1544         trb.dwTrb2 = 0;
1545         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1546             XHCI_TRB_3_SLOT_SET(slot_id);
1547         trb.dwTrb3 = htole32(temp);
1548
1549         return (xhci_do_command(sc, &trb, 100 /* ms */));
1550 }
1551
1552 static usb_error_t
1553 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1554     uint8_t ep_id, uint8_t slot_id)
1555 {
1556         struct xhci_trb trb;
1557         uint32_t temp;
1558
1559         DPRINTF("\n");
1560
1561         trb.qwTrb0 = 0;
1562         trb.dwTrb2 = 0;
1563         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1564             XHCI_TRB_3_SLOT_SET(slot_id) |
1565             XHCI_TRB_3_EP_SET(ep_id);
1566
1567         if (preserve)
1568                 temp |= XHCI_TRB_3_PRSV_BIT;
1569
1570         trb.dwTrb3 = htole32(temp);
1571
1572         return (xhci_do_command(sc, &trb, 100 /* ms */));
1573 }
1574
1575 static usb_error_t
1576 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1577     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1578 {
1579         struct xhci_trb trb;
1580         uint32_t temp;
1581
1582         DPRINTF("\n");
1583
1584         trb.qwTrb0 = htole64(dequeue_ptr);
1585
1586         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1587         trb.dwTrb2 = htole32(temp);
1588
1589         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1590             XHCI_TRB_3_SLOT_SET(slot_id) |
1591             XHCI_TRB_3_EP_SET(ep_id);
1592         trb.dwTrb3 = htole32(temp);
1593
1594         return (xhci_do_command(sc, &trb, 100 /* ms */));
1595 }
1596
1597 static usb_error_t
1598 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1599     uint8_t ep_id, uint8_t slot_id)
1600 {
1601         struct xhci_trb trb;
1602         uint32_t temp;
1603
1604         DPRINTF("\n");
1605
1606         trb.qwTrb0 = 0;
1607         trb.dwTrb2 = 0;
1608         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1609             XHCI_TRB_3_SLOT_SET(slot_id) |
1610             XHCI_TRB_3_EP_SET(ep_id);
1611
1612         if (suspend)
1613                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1614
1615         trb.dwTrb3 = htole32(temp);
1616
1617         return (xhci_do_command(sc, &trb, 100 /* ms */));
1618 }
1619
1620 static usb_error_t
1621 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1622 {
1623         struct xhci_trb trb;
1624         uint32_t temp;
1625
1626         DPRINTF("\n");
1627
1628         trb.qwTrb0 = 0;
1629         trb.dwTrb2 = 0;
1630         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1631             XHCI_TRB_3_SLOT_SET(slot_id);
1632
1633         trb.dwTrb3 = htole32(temp);
1634
1635         return (xhci_do_command(sc, &trb, 100 /* ms */));
1636 }
1637
1638 /*------------------------------------------------------------------------*
1639  *      xhci_interrupt - XHCI interrupt handler
1640  *------------------------------------------------------------------------*/
1641 void
1642 xhci_interrupt(struct xhci_softc *sc)
1643 {
1644         uint32_t status;
1645         uint32_t temp;
1646
1647         USB_BUS_LOCK(&sc->sc_bus);
1648
1649         status = XREAD4(sc, oper, XHCI_USBSTS);
1650
1651         /* acknowledge interrupts, if any */
1652         if (status != 0) {
1653                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1654                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1655         }
1656
1657         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1658
1659         /* force clearing of pending interrupts */
1660         if (temp & XHCI_IMAN_INTR_PEND)
1661                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1662
1663         /* check for event(s) */
1664         xhci_interrupt_poll(sc);
1665
1666         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1667             XHCI_STS_HSE | XHCI_STS_HCE)) {
1668
1669                 if (status & XHCI_STS_PCD) {
1670                         xhci_root_intr(sc);
1671                 }
1672
1673                 if (status & XHCI_STS_HCH) {
1674                         printf("%s: host controller halted\n",
1675                             __FUNCTION__);
1676                 }
1677
1678                 if (status & XHCI_STS_HSE) {
1679                         printf("%s: host system error\n",
1680                             __FUNCTION__);
1681                 }
1682
1683                 if (status & XHCI_STS_HCE) {
1684                         printf("%s: host controller error\n",
1685                            __FUNCTION__);
1686                 }
1687         }
1688         USB_BUS_UNLOCK(&sc->sc_bus);
1689 }
1690
1691 /*------------------------------------------------------------------------*
1692  *      xhci_timeout - XHCI timeout handler
1693  *------------------------------------------------------------------------*/
1694 static void
1695 xhci_timeout(void *arg)
1696 {
1697         struct usb_xfer *xfer = arg;
1698
1699         DPRINTF("xfer=%p\n", xfer);
1700
1701         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1702
1703         /* transfer is transferred */
1704         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1705 }
1706
1707 static void
1708 xhci_do_poll(struct usb_bus *bus)
1709 {
1710         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1711
1712         USB_BUS_LOCK(&sc->sc_bus);
1713         xhci_interrupt_poll(sc);
1714         USB_BUS_UNLOCK(&sc->sc_bus);
1715 }
1716
1717 static void
1718 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1719 {
1720         struct usb_page_search buf_res;
1721         struct xhci_td *td;
1722         struct xhci_td *td_next;
1723         struct xhci_td *td_alt_next;
1724         struct xhci_td *td_first;
1725         uint32_t buf_offset;
1726         uint32_t average;
1727         uint32_t len_old;
1728         uint32_t npkt_off;
1729         uint32_t dword;
1730         uint8_t shortpkt_old;
1731         uint8_t precompute;
1732         uint8_t x;
1733
1734         td_alt_next = NULL;
1735         buf_offset = 0;
1736         shortpkt_old = temp->shortpkt;
1737         len_old = temp->len;
1738         npkt_off = 0;
1739         precompute = 1;
1740
1741 restart:
1742
1743         td = temp->td;
1744         td_next = td_first = temp->td_next;
1745
1746         while (1) {
1747
1748                 if (temp->len == 0) {
1749
1750                         if (temp->shortpkt)
1751                                 break;
1752
1753                         /* send a Zero Length Packet, ZLP, last */
1754
1755                         temp->shortpkt = 1;
1756                         average = 0;
1757
1758                 } else {
1759
1760                         average = temp->average;
1761
1762                         if (temp->len < average) {
1763                                 if (temp->len % temp->max_packet_size) {
1764                                         temp->shortpkt = 1;
1765                                 }
1766                                 average = temp->len;
1767                         }
1768                 }
1769
1770                 if (td_next == NULL)
1771                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1772
1773                 /* get next TD */
1774
1775                 td = td_next;
1776                 td_next = td->obj_next;
1777
1778                 /* check if we are pre-computing */
1779
1780                 if (precompute) {
1781
1782                         /* update remaining length */
1783
1784                         temp->len -= average;
1785
1786                         continue;
1787                 }
1788                 /* fill out current TD */
1789
1790                 td->len = average;
1791                 td->remainder = 0;
1792                 td->status = 0;
1793
1794                 /* update remaining length */
1795
1796                 temp->len -= average;
1797
1798                 /* reset TRB index */
1799
1800                 x = 0;
1801
1802                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1803                         /* immediate data */
1804
1805                         if (average > 8)
1806                                 average = 8;
1807
1808                         td->td_trb[0].qwTrb0 = 0;
1809
1810                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1811                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1812                            average);
1813
1814                         dword = XHCI_TRB_2_BYTES_SET(8) |
1815                             XHCI_TRB_2_TDSZ_SET(0) |
1816                             XHCI_TRB_2_IRQ_SET(0);
1817
1818                         td->td_trb[0].dwTrb2 = htole32(dword);
1819
1820                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1821                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1822
1823                         /* check wLength */
1824                         if (td->td_trb[0].qwTrb0 &
1825                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1826                                 if (td->td_trb[0].qwTrb0 &
1827                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1828                                         dword |= XHCI_TRB_3_TRT_IN;
1829                                 else
1830                                         dword |= XHCI_TRB_3_TRT_OUT;
1831                         }
1832
1833                         td->td_trb[0].dwTrb3 = htole32(dword);
1834 #ifdef USB_DEBUG
1835                         xhci_dump_trb(&td->td_trb[x]);
1836 #endif
1837                         x++;
1838
1839                 } else do {
1840
1841                         uint32_t npkt;
1842
1843                         /* fill out buffer pointers */
1844
1845                         if (average == 0) {
1846                                 memset(&buf_res, 0, sizeof(buf_res));
1847                         } else {
1848                                 usbd_get_page(temp->pc, temp->offset +
1849                                     buf_offset, &buf_res);
1850
1851                                 /* get length to end of page */
1852                                 if (buf_res.length > average)
1853                                         buf_res.length = average;
1854
1855                                 /* check for maximum length */
1856                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1857                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1858
1859                                 npkt_off += buf_res.length;
1860                         }
1861
1862                         /* set up npkt */
1863                         npkt = howmany(len_old - npkt_off,
1864                                        temp->max_packet_size);
1865
1866                         if (npkt == 0)
1867                                 npkt = 1;
1868                         else if (npkt > 31)
1869                                 npkt = 31;
1870
1871                         /* fill out TRB's */
1872                         td->td_trb[x].qwTrb0 =
1873                             htole64((uint64_t)buf_res.physaddr);
1874
1875                         dword =
1876                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1877                           XHCI_TRB_2_TDSZ_SET(npkt) |
1878                           XHCI_TRB_2_IRQ_SET(0);
1879
1880                         td->td_trb[x].dwTrb2 = htole32(dword);
1881
1882                         switch (temp->trb_type) {
1883                         case XHCI_TRB_TYPE_ISOCH:
1884                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1885                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1886                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1887                                 if (td != td_first) {
1888                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1889                                 } else if (temp->do_isoc_sync != 0) {
1890                                         temp->do_isoc_sync = 0;
1891                                         /* wait until "isoc_frame" */
1892                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1893                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1894                                 } else {
1895                                         /* start data transfer at next interval */
1896                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1897                                             XHCI_TRB_3_ISO_SIA_BIT;
1898                                 }
1899                                 if (temp->direction == UE_DIR_IN)
1900                                         dword |= XHCI_TRB_3_ISP_BIT;
1901                                 break;
1902                         case XHCI_TRB_TYPE_DATA_STAGE:
1903                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1904                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1905                                 if (temp->direction == UE_DIR_IN)
1906                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1907                                 /*
1908                                  * Section 3.2.9 in the XHCI
1909                                  * specification about control
1910                                  * transfers says that we should use a
1911                                  * normal-TRB if there are more TRBs
1912                                  * extending the data-stage
1913                                  * TRB. Update the "trb_type".
1914                                  */
1915                                 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1916                                 break;
1917                         case XHCI_TRB_TYPE_STATUS_STAGE:
1918                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1919                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1920                                 if (temp->direction == UE_DIR_IN)
1921                                         dword |= XHCI_TRB_3_DIR_IN;
1922                                 break;
1923                         default:        /* XHCI_TRB_TYPE_NORMAL */
1924                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1925                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1926                                 if (temp->direction == UE_DIR_IN)
1927                                         dword |= XHCI_TRB_3_ISP_BIT;
1928                                 break;
1929                         }
1930                         td->td_trb[x].dwTrb3 = htole32(dword);
1931
1932                         average -= buf_res.length;
1933                         buf_offset += buf_res.length;
1934 #ifdef USB_DEBUG
1935                         xhci_dump_trb(&td->td_trb[x]);
1936 #endif
1937                         x++;
1938
1939                 } while (average != 0);
1940
1941                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1942
1943                 /* store number of data TRB's */
1944
1945                 td->ntrb = x;
1946
1947                 DPRINTF("NTRB=%u\n", x);
1948
1949                 /* fill out link TRB */
1950
1951                 if (td_next != NULL) {
1952                         /* link the current TD with the next one */
1953                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1954                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1955                 } else {
1956                         /* this field will get updated later */
1957                         DPRINTF("NOLINK\n");
1958                 }
1959
1960                 dword = XHCI_TRB_2_IRQ_SET(0);
1961
1962                 td->td_trb[x].dwTrb2 = htole32(dword);
1963
1964                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1965                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1966                     /*
1967                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1968                      * frame only receives a single short packet event
1969                      * by setting the CHAIN bit in the LINK field. In
1970                      * addition some XHCI controllers have problems
1971                      * sending a ZLP unless the CHAIN-BIT is set in
1972                      * the LINK TRB.
1973                      */
1974                     XHCI_TRB_3_CHAIN_BIT;
1975
1976                 td->td_trb[x].dwTrb3 = htole32(dword);
1977
1978                 td->alt_next = td_alt_next;
1979 #ifdef USB_DEBUG
1980                 xhci_dump_trb(&td->td_trb[x]);
1981 #endif
1982                 usb_pc_cpu_flush(td->page_cache);
1983         }
1984
1985         if (precompute) {
1986                 precompute = 0;
1987
1988                 /* set up alt next pointer, if any */
1989                 if (temp->last_frame) {
1990                         td_alt_next = NULL;
1991                 } else {
1992                         /* we use this field internally */
1993                         td_alt_next = td_next;
1994                 }
1995
1996                 /* restore */
1997                 temp->shortpkt = shortpkt_old;
1998                 temp->len = len_old;
1999                 goto restart;
2000         }
2001
2002         /*
2003          * Remove cycle bit from the first TRB if we are
2004          * stepping them:
2005          */
2006         if (temp->step_td != 0) {
2007                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
2008                 usb_pc_cpu_flush(td_first->page_cache);
2009         }
2010
2011         /* clear TD SIZE to zero, hence this is the last TRB */
2012         /* remove chain bit because this is the last data TRB in the chain */
2013         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31));
2014         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2015         /* remove CHAIN-BIT from last LINK TRB */
2016         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2017
2018         usb_pc_cpu_flush(td->page_cache);
2019
2020         temp->td = td;
2021         temp->td_next = td_next;
2022 }
2023
2024 static void
2025 xhci_setup_generic_chain(struct usb_xfer *xfer)
2026 {
2027         struct xhci_std_temp temp;
2028         struct xhci_td *td;
2029         uint32_t x;
2030         uint32_t y;
2031         uint8_t mult;
2032
2033         temp.do_isoc_sync = 0;
2034         temp.step_td = 0;
2035         temp.tbc = 0;
2036         temp.tlbpc = 0;
2037         temp.average = xfer->max_hc_frame_size;
2038         temp.max_packet_size = xfer->max_packet_size;
2039         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2040         temp.pc = NULL;
2041         temp.last_frame = 0;
2042         temp.offset = 0;
2043         temp.multishort = xfer->flags_int.isochronous_xfr ||
2044             xfer->flags_int.control_xfr ||
2045             xfer->flags_int.short_frames_ok;
2046
2047         /* toggle the DMA set we are using */
2048         xfer->flags_int.curr_dma_set ^= 1;
2049
2050         /* get next DMA set */
2051         td = xfer->td_start[xfer->flags_int.curr_dma_set];
2052
2053         temp.td = NULL;
2054         temp.td_next = td;
2055
2056         xfer->td_transfer_first = td;
2057         xfer->td_transfer_cache = td;
2058
2059         if (xfer->flags_int.isochronous_xfr) {
2060                 uint8_t shift;
2061
2062                 /* compute multiplier for ISOCHRONOUS transfers */
2063                 mult = xfer->endpoint->ecomp ?
2064                     UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2065                     : 0;
2066                 /* check for USB 2.0 multiplier */
2067                 if (mult == 0) {
2068                         mult = (xfer->endpoint->edesc->
2069                             wMaxPacketSize[1] >> 3) & 3;
2070                 }
2071                 /* range check */
2072                 if (mult > 2)
2073                         mult = 3;
2074                 else
2075                         mult++;
2076
2077                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2078
2079                 DPRINTF("MFINDEX=0x%08x\n", x);
2080
2081                 switch (usbd_get_speed(xfer->xroot->udev)) {
2082                 case USB_SPEED_FULL:
2083                         shift = 3;
2084                         temp.isoc_delta = 8;    /* 1ms */
2085                         x += temp.isoc_delta - 1;
2086                         x &= ~(temp.isoc_delta - 1);
2087                         break;
2088                 default:
2089                         shift = usbd_xfer_get_fps_shift(xfer);
2090                         temp.isoc_delta = 1U << shift;
2091                         x += temp.isoc_delta - 1;
2092                         x &= ~(temp.isoc_delta - 1);
2093                         /* simple frame load balancing */
2094                         x += xfer->endpoint->usb_uframe;
2095                         break;
2096                 }
2097
2098                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2099
2100                 if ((xfer->endpoint->is_synced == 0) ||
2101                     (y < (xfer->nframes << shift)) ||
2102                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2103                         /*
2104                          * If there is data underflow or the pipe
2105                          * queue is empty we schedule the transfer a
2106                          * few frames ahead of the current frame
2107                          * position. Else two isochronous transfers
2108                          * might overlap.
2109                          */
2110                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2111                         xfer->endpoint->is_synced = 1;
2112                         temp.do_isoc_sync = 1;
2113
2114                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2115                 }
2116
2117                 /* compute isochronous completion time */
2118
2119                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2120
2121                 xfer->isoc_time_complete =
2122                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2123                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2124
2125                 x = 0;
2126                 temp.isoc_frame = xfer->endpoint->isoc_next;
2127                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2128
2129                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2130
2131         } else if (xfer->flags_int.control_xfr) {
2132
2133                 /* check if we should prepend a setup message */
2134
2135                 if (xfer->flags_int.control_hdr) {
2136
2137                         temp.len = xfer->frlengths[0];
2138                         temp.pc = xfer->frbuffers + 0;
2139                         temp.shortpkt = temp.len ? 1 : 0;
2140                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2141                         temp.direction = 0;
2142
2143                         /* check for last frame */
2144                         if (xfer->nframes == 1) {
2145                                 /* no STATUS stage yet, SETUP is last */
2146                                 if (xfer->flags_int.control_act)
2147                                         temp.last_frame = 1;
2148                         }
2149
2150                         xhci_setup_generic_chain_sub(&temp);
2151                 }
2152                 x = 1;
2153                 mult = 1;
2154                 temp.isoc_delta = 0;
2155                 temp.isoc_frame = 0;
2156                 temp.trb_type = xfer->flags_int.control_did_data ?
2157                     XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2158         } else {
2159                 x = 0;
2160                 mult = 1;
2161                 temp.isoc_delta = 0;
2162                 temp.isoc_frame = 0;
2163                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2164         }
2165
2166         if (x != xfer->nframes) {
2167                 /* set up page_cache pointer */
2168                 temp.pc = xfer->frbuffers + x;
2169                 /* set endpoint direction */
2170                 temp.direction = UE_GET_DIR(xfer->endpointno);
2171         }
2172
2173         while (x != xfer->nframes) {
2174
2175                 /* DATA0 / DATA1 message */
2176
2177                 temp.len = xfer->frlengths[x];
2178                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2179                     x != 0 && temp.multishort == 0);
2180
2181                 x++;
2182
2183                 if (x == xfer->nframes) {
2184                         if (xfer->flags_int.control_xfr) {
2185                                 /* no STATUS stage yet, DATA is last */
2186                                 if (xfer->flags_int.control_act)
2187                                         temp.last_frame = 1;
2188                         } else {
2189                                 temp.last_frame = 1;
2190                         }
2191                 }
2192                 if (temp.len == 0) {
2193
2194                         /* make sure that we send an USB packet */
2195
2196                         temp.shortpkt = 0;
2197
2198                         temp.tbc = 0;
2199                         temp.tlbpc = mult - 1;
2200
2201                 } else if (xfer->flags_int.isochronous_xfr) {
2202
2203                         uint8_t tdpc;
2204
2205                         /*
2206                          * Isochronous transfers don't have short
2207                          * packet termination:
2208                          */
2209
2210                         temp.shortpkt = 1;
2211
2212                         /* isochronous transfers have a transfer limit */
2213
2214                         if (temp.len > xfer->max_frame_size)
2215                                 temp.len = xfer->max_frame_size;
2216
2217                         /* compute TD packet count */
2218                         tdpc = howmany(temp.len, xfer->max_packet_size);
2219
2220                         temp.tbc = howmany(tdpc, mult) - 1;
2221                         temp.tlbpc = (tdpc % mult);
2222
2223                         if (temp.tlbpc == 0)
2224                                 temp.tlbpc = mult - 1;
2225                         else
2226                                 temp.tlbpc--;
2227                 } else {
2228
2229                         /* regular data transfer */
2230
2231                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2232                 }
2233
2234                 xhci_setup_generic_chain_sub(&temp);
2235
2236                 if (xfer->flags_int.isochronous_xfr) {
2237                         temp.offset += xfer->frlengths[x - 1];
2238                         temp.isoc_frame += temp.isoc_delta;
2239                 } else {
2240                         /* get next Page Cache pointer */
2241                         temp.pc = xfer->frbuffers + x;
2242                 }
2243         }
2244
2245         /* check if we should append a status stage */
2246
2247         if (xfer->flags_int.control_xfr &&
2248             !xfer->flags_int.control_act) {
2249
2250                 /*
2251                  * Send a DATA1 message and invert the current
2252                  * endpoint direction.
2253                  */
2254                 if (xhcictlstep || temp.sc->sc_ctlstep) {
2255                         /*
2256                          * Some XHCI controllers will not delay the
2257                          * status stage until the next SOF. Force this
2258                          * behaviour to avoid failed control
2259                          * transfers.
2260                          */
2261                         temp.step_td = (xfer->nframes != 0);
2262                 } else {
2263                         temp.step_td = 0;
2264                 }
2265                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2266                 temp.len = 0;
2267                 temp.pc = NULL;
2268                 temp.shortpkt = 0;
2269                 temp.last_frame = 1;
2270                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2271
2272                 xhci_setup_generic_chain_sub(&temp);
2273         }
2274
2275         td = temp.td;
2276
2277         /* must have at least one frame! */
2278
2279         xfer->td_transfer_last = td;
2280
2281         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2282 }
2283
2284 static void
2285 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2286 {
2287         struct usb_page_search buf_res;
2288         struct xhci_dev_ctx_addr *pdctxa;
2289
2290         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2291
2292         pdctxa = buf_res.buffer;
2293
2294         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2295
2296         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2297
2298         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2299 }
2300
2301 static usb_error_t
2302 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2303 {
2304         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2305         struct usb_page_search buf_inp;
2306         struct xhci_input_dev_ctx *pinp;
2307         uint32_t temp;
2308         uint8_t index;
2309         uint8_t x;
2310
2311         index = udev->controller_slot_id;
2312
2313         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2314
2315         pinp = buf_inp.buffer;
2316
2317         if (drop) {
2318                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2319                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2320                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2321         } else {
2322                 /*
2323                  * Some hardware requires that we drop the endpoint
2324                  * context before adding it again:
2325                  */
2326                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2327                     mask & XHCI_INCTX_NON_CTRL_MASK);
2328
2329                 /* Add new endpoint context */
2330                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2331
2332                 /* find most significant set bit */
2333                 for (x = 31; x != 1; x--) {
2334                         if (mask & (1 << x))
2335                                 break;
2336                 }
2337
2338                 /* adjust */
2339                 x--;
2340
2341                 /* figure out the maximum number of contexts */
2342                 if (x > sc->sc_hw.devs[index].context_num)
2343                         sc->sc_hw.devs[index].context_num = x;
2344                 else
2345                         x = sc->sc_hw.devs[index].context_num;
2346
2347                 /* update number of contexts */
2348                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2349                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2350                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2351                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2352         }
2353         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2354         return (0);
2355 }
2356
2357 static usb_error_t
2358 xhci_configure_endpoint(struct usb_device *udev,
2359     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2360     uint16_t interval, uint8_t max_packet_count,
2361     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2362     uint16_t max_frame_size, uint8_t ep_mode)
2363 {
2364         struct usb_page_search buf_inp;
2365         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2366         struct xhci_input_dev_ctx *pinp;
2367         uint64_t ring_addr = pepext->physaddr;
2368         uint32_t temp;
2369         uint8_t index;
2370         uint8_t epno;
2371         uint8_t type;
2372
2373         index = udev->controller_slot_id;
2374
2375         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2376
2377         pinp = buf_inp.buffer;
2378
2379         epno = edesc->bEndpointAddress;
2380         type = edesc->bmAttributes & UE_XFERTYPE;
2381
2382         if (type == UE_CONTROL)
2383                 epno |= UE_DIR_IN;
2384
2385         epno = XHCI_EPNO2EPID(epno);
2386
2387         if (epno == 0)
2388                 return (USB_ERR_NO_PIPE);               /* invalid */
2389
2390         if (max_packet_count == 0)
2391                 return (USB_ERR_BAD_BUFSIZE);
2392
2393         max_packet_count--;
2394
2395         if (mult == 0)
2396                 return (USB_ERR_BAD_BUFSIZE);
2397
2398         /* store endpoint mode */
2399         pepext->trb_ep_mode = ep_mode;
2400         /* store bMaxPacketSize for control endpoints */
2401         pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2402         usb_pc_cpu_flush(pepext->page_cache);
2403
2404         if (ep_mode == USB_EP_MODE_STREAMS) {
2405                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2406                     XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2407                     XHCI_EPCTX_0_LSA_SET(1);
2408
2409                 ring_addr += sizeof(struct xhci_trb) *
2410                     XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2411         } else {
2412                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2413                     XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2414                     XHCI_EPCTX_0_LSA_SET(0);
2415
2416                 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2417         }
2418
2419         switch (udev->speed) {
2420         case USB_SPEED_FULL:
2421         case USB_SPEED_LOW:
2422                 /* 1ms -> 125us */
2423                 fps_shift += 3;
2424                 break;
2425         default:
2426                 break;
2427         }
2428
2429         switch (type) {
2430         case UE_INTERRUPT:
2431                 if (fps_shift > 3)
2432                         fps_shift--;
2433                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2434                 break;
2435         case UE_ISOCHRONOUS:
2436                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2437
2438                 switch (udev->speed) {
2439                 case USB_SPEED_SUPER:
2440                         if (mult > 3)
2441                                 mult = 3;
2442                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2443                         max_packet_count /= mult;
2444                         break;
2445                 default:
2446                         break;
2447                 }
2448                 break;
2449         default:
2450                 break;
2451         }
2452
2453         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2454
2455         temp =
2456             XHCI_EPCTX_1_HID_SET(0) |
2457             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2458             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2459
2460         /*
2461          * Always enable the "three strikes and you are gone" feature
2462          * except for ISOCHRONOUS endpoints. This is suggested by
2463          * section 4.3.3 in the XHCI specification about device slot
2464          * initialisation.
2465          */
2466         if (type != UE_ISOCHRONOUS)
2467                 temp |= XHCI_EPCTX_1_CERR_SET(3);
2468
2469         switch (type) {
2470         case UE_CONTROL:
2471                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2472                 break;
2473         case UE_ISOCHRONOUS:
2474                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2475                 break;
2476         case UE_BULK:
2477                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2478                 break;
2479         default:
2480                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2481                 break;
2482         }
2483
2484         /* check for IN direction */
2485         if (epno & 1)
2486                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2487
2488         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2489         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2490
2491         switch (edesc->bmAttributes & UE_XFERTYPE) {
2492         case UE_INTERRUPT:
2493         case UE_ISOCHRONOUS:
2494                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2495                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2496                     max_frame_size));
2497                 break;
2498         case UE_CONTROL:
2499                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2500                 break;
2501         default:
2502                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2503                 break;
2504         }
2505
2506         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2507
2508 #ifdef USB_DEBUG
2509         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2510 #endif
2511         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2512
2513         return (0);             /* success */
2514 }
2515
2516 static usb_error_t
2517 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2518 {
2519         struct xhci_endpoint_ext *pepext;
2520         struct usb_endpoint_ss_comp_descriptor *ecomp;
2521         usb_stream_t x;
2522
2523         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2524             xfer->endpoint->edesc);
2525
2526         ecomp = xfer->endpoint->ecomp;
2527
2528         for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2529                 uint64_t temp;
2530
2531                 /* halt any transfers */
2532                 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2533
2534                 /* compute start of TRB ring for stream "x" */
2535                 temp = pepext->physaddr +
2536                     (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2537                     XHCI_SCTX_0_SCT_SEC_TR_RING;
2538
2539                 /* make tree structure */
2540                 pepext->trb[(XHCI_MAX_TRANSFERS *
2541                     XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2542
2543                 /* reserved fields */
2544                 pepext->trb[(XHCI_MAX_TRANSFERS *
2545                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2546                 pepext->trb[(XHCI_MAX_TRANSFERS *
2547                     XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2548         }
2549         usb_pc_cpu_flush(pepext->page_cache);
2550
2551         return (xhci_configure_endpoint(xfer->xroot->udev,
2552             xfer->endpoint->edesc, pepext,
2553             xfer->interval, xfer->max_packet_count,
2554             (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2555             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2556             xfer->max_frame_size, xfer->endpoint->ep_mode));
2557 }
2558
2559 static usb_error_t
2560 xhci_configure_device(struct usb_device *udev)
2561 {
2562         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2563         struct usb_page_search buf_inp;
2564         struct usb_page_cache *pcinp;
2565         struct xhci_input_dev_ctx *pinp;
2566         struct usb_device *hubdev;
2567         uint32_t temp;
2568         uint32_t route;
2569         uint32_t rh_port;
2570         uint8_t is_hub;
2571         uint8_t index;
2572         uint8_t depth;
2573
2574         index = udev->controller_slot_id;
2575
2576         DPRINTF("index=%u\n", index);
2577
2578         pcinp = &sc->sc_hw.devs[index].input_pc;
2579
2580         usbd_get_page(pcinp, 0, &buf_inp);
2581
2582         pinp = buf_inp.buffer;
2583
2584         rh_port = 0;
2585         route = 0;
2586
2587         /* figure out route string and root HUB port number */
2588
2589         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2590
2591                 if (hubdev->parent_hub == NULL)
2592                         break;
2593
2594                 depth = hubdev->parent_hub->depth;
2595
2596                 /*
2597                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2598                  * more than 15 ports
2599                  */
2600
2601                 rh_port = hubdev->port_no;
2602
2603                 if (depth == 0)
2604                         break;
2605
2606                 if (rh_port > 15)
2607                         rh_port = 15;
2608
2609                 if (depth < 6)
2610                         route |= rh_port << (4 * (depth - 1));
2611         }
2612
2613         DPRINTF("Route=0x%08x\n", route);
2614
2615         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2616             XHCI_SCTX_0_CTX_NUM_SET(
2617             sc->sc_hw.devs[index].context_num + 1);
2618
2619         switch (udev->speed) {
2620         case USB_SPEED_LOW:
2621                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2622                 if (udev->parent_hs_hub != NULL &&
2623                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2624                     UDPROTO_HSHUBMTT) {
2625                         DPRINTF("Device inherits MTT\n");
2626                         temp |= XHCI_SCTX_0_MTT_SET(1);
2627                 }
2628                 break;
2629         case USB_SPEED_HIGH:
2630                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2631                 if (sc->sc_hw.devs[index].nports != 0 &&
2632                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2633                         DPRINTF("HUB supports MTT\n");
2634                         temp |= XHCI_SCTX_0_MTT_SET(1);
2635                 }
2636                 break;
2637         case USB_SPEED_FULL:
2638                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2639                 if (udev->parent_hs_hub != NULL &&
2640                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2641                     UDPROTO_HSHUBMTT) {
2642                         DPRINTF("Device inherits MTT\n");
2643                         temp |= XHCI_SCTX_0_MTT_SET(1);
2644                 }
2645                 break;
2646         default:
2647                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2648                 break;
2649         }
2650
2651         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2652             (udev->speed == USB_SPEED_SUPER ||
2653             udev->speed == USB_SPEED_HIGH);
2654
2655         if (is_hub)
2656                 temp |= XHCI_SCTX_0_HUB_SET(1);
2657
2658         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2659
2660         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2661
2662         if (is_hub) {
2663                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2664                     sc->sc_hw.devs[index].nports);
2665         }
2666
2667         switch (udev->speed) {
2668         case USB_SPEED_SUPER:
2669                 switch (sc->sc_hw.devs[index].state) {
2670                 case XHCI_ST_ADDRESSED:
2671                 case XHCI_ST_CONFIGURED:
2672                         /* enable power save */
2673                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2674                         break;
2675                 default:
2676                         /* disable power save */
2677                         break;
2678                 }
2679                 break;
2680         default:
2681                 break;
2682         }
2683
2684         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2685
2686         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2687
2688         if (is_hub) {
2689                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2690                     sc->sc_hw.devs[index].tt);
2691         }
2692
2693         hubdev = udev->parent_hs_hub;
2694
2695         /* check if we should activate the transaction translator */
2696         switch (udev->speed) {
2697         case USB_SPEED_FULL:
2698         case USB_SPEED_LOW:
2699                 if (hubdev != NULL) {
2700                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2701                             hubdev->controller_slot_id);
2702                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2703                             udev->hs_port_no);
2704                 }
2705                 break;
2706         default:
2707                 break;
2708         }
2709
2710         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2711
2712         /*
2713          * These fields should be initialized to zero, according to
2714          * XHCI section 6.2.2 - slot context:
2715          */
2716         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2717             XHCI_SCTX_3_SLOT_STATE_SET(0);
2718
2719         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2720
2721 #ifdef USB_DEBUG
2722         xhci_dump_device(sc, &pinp->ctx_slot);
2723 #endif
2724         usb_pc_cpu_flush(pcinp);
2725
2726         return (0);             /* success */
2727 }
2728
2729 static usb_error_t
2730 xhci_alloc_device_ext(struct usb_device *udev)
2731 {
2732         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2733         struct usb_page_search buf_dev;
2734         struct usb_page_search buf_ep;
2735         struct xhci_trb *trb;
2736         struct usb_page_cache *pc;
2737         struct usb_page *pg;
2738         uint64_t addr;
2739         uint8_t index;
2740         uint8_t i;
2741
2742         index = udev->controller_slot_id;
2743
2744         pc = &sc->sc_hw.devs[index].device_pc;
2745         pg = &sc->sc_hw.devs[index].device_pg;
2746
2747         /* need to initialize the page cache */
2748         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2749
2750         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2751             (2 * sizeof(struct xhci_dev_ctx)) :
2752             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2753                 goto error;
2754
2755         usbd_get_page(pc, 0, &buf_dev);
2756
2757         pc = &sc->sc_hw.devs[index].input_pc;
2758         pg = &sc->sc_hw.devs[index].input_pg;
2759
2760         /* need to initialize the page cache */
2761         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2762
2763         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2764             (2 * sizeof(struct xhci_input_dev_ctx)) :
2765             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2766                 goto error;
2767         }
2768
2769         /* initialize all endpoint LINK TRBs */
2770
2771         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2772
2773                 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2774                 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2775
2776                 /* need to initialize the page cache */
2777                 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2778
2779                 if (usb_pc_alloc_mem(pc, pg,
2780                     sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2781                         goto error;
2782                 }
2783
2784                 /* lookup endpoint TRB ring */
2785                 usbd_get_page(pc, 0, &buf_ep);
2786
2787                 /* get TRB pointer */
2788                 trb = buf_ep.buffer;
2789                 trb += XHCI_MAX_TRANSFERS - 1;
2790
2791                 /* get TRB start address */
2792                 addr = buf_ep.physaddr;
2793
2794                 /* create LINK TRB */
2795                 trb->qwTrb0 = htole64(addr);
2796                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2797                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2798                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2799
2800                 usb_pc_cpu_flush(pc);
2801         }
2802
2803         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2804
2805         return (0);
2806
2807 error:
2808         xhci_free_device_ext(udev);
2809
2810         return (USB_ERR_NOMEM);
2811 }
2812
2813 static void
2814 xhci_free_device_ext(struct usb_device *udev)
2815 {
2816         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2817         uint8_t index;
2818         uint8_t i;
2819
2820         index = udev->controller_slot_id;
2821         xhci_set_slot_pointer(sc, index, 0);
2822
2823         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2824         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2825         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2826                 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2827 }
2828
2829 static struct xhci_endpoint_ext *
2830 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2831 {
2832         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2833         struct xhci_endpoint_ext *pepext;
2834         struct usb_page_cache *pc;
2835         struct usb_page_search buf_ep;
2836         uint8_t epno;
2837         uint8_t index;
2838
2839         epno = edesc->bEndpointAddress;
2840         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2841                 epno |= UE_DIR_IN;
2842
2843         epno = XHCI_EPNO2EPID(epno);
2844
2845         index = udev->controller_slot_id;
2846
2847         pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2848
2849         usbd_get_page(pc, 0, &buf_ep);
2850
2851         pepext = &sc->sc_hw.devs[index].endp[epno];
2852         pepext->page_cache = pc;
2853         pepext->trb = buf_ep.buffer;
2854         pepext->physaddr = buf_ep.physaddr;
2855
2856         return (pepext);
2857 }
2858
2859 static void
2860 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2861 {
2862         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2863         uint8_t epno;
2864         uint8_t index;
2865
2866         epno = xfer->endpointno;
2867         if (xfer->flags_int.control_xfr)
2868                 epno |= UE_DIR_IN;
2869
2870         epno = XHCI_EPNO2EPID(epno);
2871         index = xfer->xroot->udev->controller_slot_id;
2872
2873         if (xfer->xroot->udev->flags.self_suspended == 0) {
2874                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2875                     epno | XHCI_DB_SID_SET(xfer->stream_id));
2876         }
2877 }
2878
2879 static void
2880 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2881 {
2882         struct xhci_endpoint_ext *pepext;
2883
2884         if (xfer->flags_int.bandwidth_reclaimed) {
2885                 xfer->flags_int.bandwidth_reclaimed = 0;
2886
2887                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2888                     xfer->endpoint->edesc);
2889
2890                 pepext->trb_used[xfer->stream_id]--;
2891
2892                 pepext->xfer[xfer->qh_pos] = NULL;
2893
2894                 if (error && pepext->trb_running != 0) {
2895                         pepext->trb_halted = 1;
2896                         pepext->trb_running = 0;
2897                 }
2898         }
2899 }
2900
2901 static usb_error_t
2902 xhci_transfer_insert(struct usb_xfer *xfer)
2903 {
2904         struct xhci_td *td_first;
2905         struct xhci_td *td_last;
2906         struct xhci_trb *trb_link;
2907         struct xhci_endpoint_ext *pepext;
2908         uint64_t addr;
2909         usb_stream_t id;
2910         uint8_t i;
2911         uint8_t inext;
2912         uint8_t trb_limit;
2913
2914         DPRINTFN(8, "\n");
2915
2916         id = xfer->stream_id;
2917
2918         /* check if already inserted */
2919         if (xfer->flags_int.bandwidth_reclaimed) {
2920                 DPRINTFN(8, "Already in schedule\n");
2921                 return (0);
2922         }
2923
2924         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2925             xfer->endpoint->edesc);
2926
2927         td_first = xfer->td_transfer_first;
2928         td_last = xfer->td_transfer_last;
2929         addr = pepext->physaddr;
2930
2931         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2932         case UE_CONTROL:
2933         case UE_INTERRUPT:
2934                 /* single buffered */
2935                 trb_limit = 1;
2936                 break;
2937         default:
2938                 /* multi buffered */
2939                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2940                 break;
2941         }
2942
2943         if (pepext->trb_used[id] >= trb_limit) {
2944                 DPRINTFN(8, "Too many TDs queued.\n");
2945                 return (USB_ERR_NOMEM);
2946         }
2947
2948         /* check if bMaxPacketSize changed */
2949         if (xfer->flags_int.control_xfr != 0 &&
2950             pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2951
2952                 DPRINTFN(8, "Reconfigure control endpoint\n");
2953
2954                 /* force driver to reconfigure endpoint */
2955                 pepext->trb_halted = 1;
2956                 pepext->trb_running = 0;
2957         }
2958
2959         /* check for stopped condition, after putting transfer on interrupt queue */
2960         if (pepext->trb_running == 0) {
2961                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2962
2963                 DPRINTFN(8, "Not running\n");
2964
2965                 /* start configuration */
2966                 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2967                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2968                 return (0);
2969         }
2970
2971         pepext->trb_used[id]++;
2972
2973         /* get current TRB index */
2974         i = pepext->trb_index[id];
2975
2976         /* get next TRB index */
2977         inext = (i + 1);
2978
2979         /* the last entry of the ring is a hardcoded link TRB */
2980         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2981                 inext = 0;
2982
2983         /* store next TRB index, before stream ID offset is added */
2984         pepext->trb_index[id] = inext;
2985
2986         /* offset for stream */
2987         i += id * XHCI_MAX_TRANSFERS;
2988         inext += id * XHCI_MAX_TRANSFERS;
2989
2990         /* compute terminating return address */
2991         addr += (inext * sizeof(struct xhci_trb));
2992
2993         /* compute link TRB pointer */
2994         trb_link = td_last->td_trb + td_last->ntrb;
2995
2996         /* update next pointer of last link TRB */
2997         trb_link->qwTrb0 = htole64(addr);
2998         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2999         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
3000             XHCI_TRB_3_CYCLE_BIT |
3001             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3002
3003 #ifdef USB_DEBUG
3004         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
3005 #endif
3006         usb_pc_cpu_flush(td_last->page_cache);
3007
3008         /* write ahead chain end marker */
3009
3010         pepext->trb[inext].qwTrb0 = 0;
3011         pepext->trb[inext].dwTrb2 = 0;
3012         pepext->trb[inext].dwTrb3 = 0;
3013
3014         /* update next pointer of link TRB */
3015
3016         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
3017         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3018
3019 #ifdef USB_DEBUG
3020         xhci_dump_trb(&pepext->trb[i]);
3021 #endif
3022         usb_pc_cpu_flush(pepext->page_cache);
3023
3024         /* toggle cycle bit which activates the transfer chain */
3025
3026         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
3027             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3028
3029         usb_pc_cpu_flush(pepext->page_cache);
3030
3031         DPRINTF("qh_pos = %u\n", i);
3032
3033         pepext->xfer[i] = xfer;
3034
3035         xfer->qh_pos = i;
3036
3037         xfer->flags_int.bandwidth_reclaimed = 1;
3038
3039         xhci_endpoint_doorbell(xfer);
3040
3041         return (0);
3042 }
3043
3044 static void
3045 xhci_root_intr(struct xhci_softc *sc)
3046 {
3047         uint16_t i;
3048
3049         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3050
3051         /* clear any old interrupt data */
3052         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3053
3054         for (i = 1; i <= sc->sc_noport; i++) {
3055                 /* pick out CHANGE bits from the status register */
3056                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3057                     XHCI_PS_CSC | XHCI_PS_PEC |
3058                     XHCI_PS_OCC | XHCI_PS_WRC |
3059                     XHCI_PS_PRC | XHCI_PS_PLC |
3060                     XHCI_PS_CEC)) {
3061                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3062                         DPRINTF("port %d changed\n", i);
3063                 }
3064         }
3065         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3066             sizeof(sc->sc_hub_idata));
3067 }
3068
3069 /*------------------------------------------------------------------------*
3070  *      xhci_device_done - XHCI done handler
3071  *
3072  * NOTE: This function can be called two times in a row on
3073  * the same USB transfer. From close and from interrupt.
3074  *------------------------------------------------------------------------*/
3075 static void
3076 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3077 {
3078         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3079             xfer, xfer->endpoint, error);
3080
3081         /* remove transfer from HW queue */
3082         xhci_transfer_remove(xfer, error);
3083
3084         /* dequeue transfer and start next transfer */
3085         usbd_transfer_done(xfer, error);
3086 }
3087
3088 /*------------------------------------------------------------------------*
3089  * XHCI data transfer support (generic type)
3090  *------------------------------------------------------------------------*/
3091 static void
3092 xhci_device_generic_open(struct usb_xfer *xfer)
3093 {
3094         if (xfer->flags_int.isochronous_xfr) {
3095                 switch (xfer->xroot->udev->speed) {
3096                 case USB_SPEED_FULL:
3097                         break;
3098                 default:
3099                         usb_hs_bandwidth_alloc(xfer);
3100                         break;
3101                 }
3102         }
3103 }
3104
3105 static void
3106 xhci_device_generic_close(struct usb_xfer *xfer)
3107 {
3108         DPRINTF("\n");
3109
3110         xhci_device_done(xfer, USB_ERR_CANCELLED);
3111
3112         if (xfer->flags_int.isochronous_xfr) {
3113                 switch (xfer->xroot->udev->speed) {
3114                 case USB_SPEED_FULL:
3115                         break;
3116                 default:
3117                         usb_hs_bandwidth_free(xfer);
3118                         break;
3119                 }
3120         }
3121 }
3122
3123 static void
3124 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3125     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3126 {
3127         struct usb_xfer *xfer;
3128
3129         /* check if there is a current transfer */
3130         xfer = ep->endpoint_q[stream_id].curr;
3131         if (xfer == NULL)
3132                 return;
3133
3134         /*
3135          * Check if the current transfer is started and then pickup
3136          * the next one, if any. Else wait for next start event due to
3137          * block on failure feature.
3138          */
3139         if (!xfer->flags_int.bandwidth_reclaimed)
3140                 return;
3141
3142         xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3143         if (xfer == NULL) {
3144                 /*
3145                  * In case of enter we have to consider that the
3146                  * transfer is queued by the USB core after the enter
3147                  * method is called.
3148                  */
3149                 xfer = enter_xfer;
3150
3151                 if (xfer == NULL)
3152                         return;
3153         }
3154
3155         /* try to multi buffer */
3156         xhci_transfer_insert(xfer);
3157 }
3158
3159 static void
3160 xhci_device_generic_enter(struct usb_xfer *xfer)
3161 {
3162         DPRINTF("\n");
3163
3164         /* set up TD's and QH */
3165         xhci_setup_generic_chain(xfer);
3166
3167         xhci_device_generic_multi_enter(xfer->endpoint,
3168             xfer->stream_id, xfer);
3169 }
3170
3171 static void
3172 xhci_device_generic_start(struct usb_xfer *xfer)
3173 {
3174         DPRINTF("\n");
3175
3176         /* try to insert xfer on HW queue */
3177         xhci_transfer_insert(xfer);
3178
3179         /* try to multi buffer */
3180         xhci_device_generic_multi_enter(xfer->endpoint,
3181             xfer->stream_id, NULL);
3182
3183         /* add transfer last on interrupt queue */
3184         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3185
3186         /* start timeout, if any */
3187         if (xfer->timeout != 0)
3188                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3189 }
3190
3191 static const struct usb_pipe_methods xhci_device_generic_methods =
3192 {
3193         .open = xhci_device_generic_open,
3194         .close = xhci_device_generic_close,
3195         .enter = xhci_device_generic_enter,
3196         .start = xhci_device_generic_start,
3197 };
3198
3199 /*------------------------------------------------------------------------*
3200  * xhci root HUB support
3201  *------------------------------------------------------------------------*
3202  * Simulate a hardware HUB by handling all the necessary requests.
3203  *------------------------------------------------------------------------*/
3204
3205 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3206
3207 static const
3208 struct usb_device_descriptor xhci_devd =
3209 {
3210         .bLength = sizeof(xhci_devd),
3211         .bDescriptorType = UDESC_DEVICE,        /* type */
3212         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3213         .bDeviceClass = UDCLASS_HUB,            /* class */
3214         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3215         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3216         .bMaxPacketSize = 9,                    /* max packet size */
3217         HSETW(.idVendor, 0x0000),               /* vendor */
3218         HSETW(.idProduct, 0x0000),              /* product */
3219         HSETW(.bcdDevice, 0x0100),              /* device version */
3220         .iManufacturer = 1,
3221         .iProduct = 2,
3222         .iSerialNumber = 0,
3223         .bNumConfigurations = 1,                /* # of configurations */
3224 };
3225
3226 static const
3227 struct xhci_bos_desc xhci_bosd = {
3228         .bosd = {
3229                 .bLength = sizeof(xhci_bosd.bosd),
3230                 .bDescriptorType = UDESC_BOS,
3231                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3232                 .bNumDeviceCaps = 3,
3233         },
3234         .usb2extd = {
3235                 .bLength = sizeof(xhci_bosd.usb2extd),
3236                 .bDescriptorType = 1,
3237                 .bDevCapabilityType = 2,
3238                 .bmAttributes[0] = 2,
3239         },
3240         .usbdcd = {
3241                 .bLength = sizeof(xhci_bosd.usbdcd),
3242                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3243                 .bDevCapabilityType = 3,
3244                 .bmAttributes = 0, /* XXX */
3245                 HSETW(.wSpeedsSupported, 0x000C),
3246                 .bFunctionalitySupport = 8,
3247                 .bU1DevExitLat = 255,   /* dummy - not used */
3248                 .wU2DevExitLat = { 0x00, 0x08 },
3249         },
3250         .cidd = {
3251                 .bLength = sizeof(xhci_bosd.cidd),
3252                 .bDescriptorType = 1,
3253                 .bDevCapabilityType = 4,
3254                 .bReserved = 0,
3255                 .bContainerID = 0, /* XXX */
3256         },
3257 };
3258
3259 static const
3260 struct xhci_config_desc xhci_confd = {
3261         .confd = {
3262                 .bLength = sizeof(xhci_confd.confd),
3263                 .bDescriptorType = UDESC_CONFIG,
3264                 .wTotalLength[0] = sizeof(xhci_confd),
3265                 .bNumInterface = 1,
3266                 .bConfigurationValue = 1,
3267                 .iConfiguration = 0,
3268                 .bmAttributes = UC_SELF_POWERED,
3269                 .bMaxPower = 0          /* max power */
3270         },
3271         .ifcd = {
3272                 .bLength = sizeof(xhci_confd.ifcd),
3273                 .bDescriptorType = UDESC_INTERFACE,
3274                 .bNumEndpoints = 1,
3275                 .bInterfaceClass = UICLASS_HUB,
3276                 .bInterfaceSubClass = UISUBCLASS_HUB,
3277                 .bInterfaceProtocol = 0,
3278         },
3279         .endpd = {
3280                 .bLength = sizeof(xhci_confd.endpd),
3281                 .bDescriptorType = UDESC_ENDPOINT,
3282                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3283                 .bmAttributes = UE_INTERRUPT,
3284                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3285                 .bInterval = 255,
3286         },
3287         .endpcd = {
3288                 .bLength = sizeof(xhci_confd.endpcd),
3289                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3290                 .bMaxBurst = 0,
3291                 .bmAttributes = 0,
3292         },
3293 };
3294
3295 static const
3296 struct usb_hub_ss_descriptor xhci_hubd = {
3297         .bLength = sizeof(xhci_hubd),
3298         .bDescriptorType = UDESC_SS_HUB,
3299 };
3300
3301 static usb_error_t
3302 xhci_roothub_exec(struct usb_device *udev,
3303     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3304 {
3305         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3306         const char *str_ptr;
3307         const void *ptr;
3308         uint32_t port;
3309         uint32_t v;
3310         uint16_t len;
3311         uint16_t i;
3312         uint16_t value;
3313         uint16_t index;
3314         uint8_t j;
3315         usb_error_t err;
3316
3317         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3318
3319         /* buffer reset */
3320         ptr = (const void *)&sc->sc_hub_desc;
3321         len = 0;
3322         err = 0;
3323
3324         value = UGETW(req->wValue);
3325         index = UGETW(req->wIndex);
3326
3327         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3328             "wValue=0x%04x wIndex=0x%04x\n",
3329             req->bmRequestType, req->bRequest,
3330             UGETW(req->wLength), value, index);
3331
3332 #define C(x,y) ((x) | ((y) << 8))
3333         switch (C(req->bRequest, req->bmRequestType)) {
3334         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3335         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3336         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3337                 /*
3338                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3339                  * for the integrated root hub.
3340                  */
3341                 break;
3342         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3343                 len = 1;
3344                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3345                 break;
3346         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3347                 switch (value >> 8) {
3348                 case UDESC_DEVICE:
3349                         if ((value & 0xff) != 0) {
3350                                 err = USB_ERR_IOERROR;
3351                                 goto done;
3352                         }
3353                         len = sizeof(xhci_devd);
3354                         ptr = (const void *)&xhci_devd;
3355                         break;
3356
3357                 case UDESC_BOS:
3358                         if ((value & 0xff) != 0) {
3359                                 err = USB_ERR_IOERROR;
3360                                 goto done;
3361                         }
3362                         len = sizeof(xhci_bosd);
3363                         ptr = (const void *)&xhci_bosd;
3364                         break;
3365
3366                 case UDESC_CONFIG:
3367                         if ((value & 0xff) != 0) {
3368                                 err = USB_ERR_IOERROR;
3369                                 goto done;
3370                         }
3371                         len = sizeof(xhci_confd);
3372                         ptr = (const void *)&xhci_confd;
3373                         break;
3374
3375                 case UDESC_STRING:
3376                         switch (value & 0xff) {
3377                         case 0: /* Language table */
3378                                 str_ptr = "\001";
3379                                 break;
3380
3381                         case 1: /* Vendor */
3382                                 str_ptr = sc->sc_vendor;
3383                                 break;
3384
3385                         case 2: /* Product */
3386                                 str_ptr = "XHCI root HUB";
3387                                 break;
3388
3389                         default:
3390                                 str_ptr = "";
3391                                 break;
3392                         }
3393
3394                         len = usb_make_str_desc(
3395                             sc->sc_hub_desc.temp,
3396                             sizeof(sc->sc_hub_desc.temp),
3397                             str_ptr);
3398                         break;
3399
3400                 default:
3401                         err = USB_ERR_IOERROR;
3402                         goto done;
3403                 }
3404                 break;
3405         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3406                 len = 1;
3407                 sc->sc_hub_desc.temp[0] = 0;
3408                 break;
3409         case C(UR_GET_STATUS, UT_READ_DEVICE):
3410                 len = 2;
3411                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3412                 break;
3413         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3414         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3415                 len = 2;
3416                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3417                 break;
3418         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3419                 if (value >= XHCI_MAX_DEVICES) {
3420                         err = USB_ERR_IOERROR;
3421                         goto done;
3422                 }
3423                 break;
3424         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3425                 if (value != 0 && value != 1) {
3426                         err = USB_ERR_IOERROR;
3427                         goto done;
3428                 }
3429                 sc->sc_conf = value;
3430                 break;
3431         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3432                 break;
3433         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3434         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3435         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3436                 err = USB_ERR_IOERROR;
3437                 goto done;
3438         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3439                 break;
3440         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3441                 break;
3442                 /* Hub requests */
3443         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3444                 break;
3445         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3446                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3447
3448                 if ((index < 1) ||
3449                     (index > sc->sc_noport)) {
3450                         err = USB_ERR_IOERROR;
3451                         goto done;
3452                 }
3453                 port = XHCI_PORTSC(index);
3454
3455                 v = XREAD4(sc, oper, port);
3456                 i = XHCI_PS_PLS_GET(v);
3457                 v &= ~XHCI_PS_CLEAR;
3458
3459                 switch (value) {
3460                 case UHF_C_BH_PORT_RESET:
3461                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3462                         break;
3463                 case UHF_C_PORT_CONFIG_ERROR:
3464                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3465                         break;
3466                 case UHF_C_PORT_SUSPEND:
3467                 case UHF_C_PORT_LINK_STATE:
3468                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3469                         break;
3470                 case UHF_C_PORT_CONNECTION:
3471                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3472                         break;
3473                 case UHF_C_PORT_ENABLE:
3474                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3475                         break;
3476                 case UHF_C_PORT_OVER_CURRENT:
3477                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3478                         break;
3479                 case UHF_C_PORT_RESET:
3480                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3481                         break;
3482                 case UHF_PORT_ENABLE:
3483                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3484                         break;
3485                 case UHF_PORT_POWER:
3486                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3487                         break;
3488                 case UHF_PORT_INDICATOR:
3489                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3490                         break;
3491                 case UHF_PORT_SUSPEND:
3492
3493                         /* U3 -> U15 */
3494                         if (i == 3) {
3495                                 XWRITE4(sc, oper, port, v |
3496                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3497                         }
3498
3499                         /* wait 20ms for resume sequence to complete */
3500                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3501
3502                         /* U0 */
3503                         XWRITE4(sc, oper, port, v |
3504                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3505                         break;
3506                 default:
3507                         err = USB_ERR_IOERROR;
3508                         goto done;
3509                 }
3510                 break;
3511
3512         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3513                 if ((value & 0xff) != 0) {
3514                         err = USB_ERR_IOERROR;
3515                         goto done;
3516                 }
3517
3518                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3519
3520                 sc->sc_hub_desc.hubd = xhci_hubd;
3521
3522                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3523
3524                 if (XHCI_HCS0_PPC(v))
3525                         i = UHD_PWR_INDIVIDUAL;
3526                 else
3527                         i = UHD_PWR_GANGED;
3528
3529                 if (XHCI_HCS0_PIND(v))
3530                         i |= UHD_PORT_IND;
3531
3532                 i |= UHD_OC_INDIVIDUAL;
3533
3534                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3535
3536                 /* see XHCI section 5.4.9: */
3537                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3538
3539                 for (j = 1; j <= sc->sc_noport; j++) {
3540
3541                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3542                         if (v & XHCI_PS_DR) {
3543                                 sc->sc_hub_desc.hubd.
3544                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3545                         }
3546                 }
3547                 len = sc->sc_hub_desc.hubd.bLength;
3548                 break;
3549
3550         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3551                 len = 16;
3552                 memset(sc->sc_hub_desc.temp, 0, 16);
3553                 break;
3554
3555         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3556                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3557
3558                 if ((index < 1) ||
3559                     (index > sc->sc_noport)) {
3560                         err = USB_ERR_IOERROR;
3561                         goto done;
3562                 }
3563
3564                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3565
3566                 DPRINTFN(9, "port status=0x%08x\n", v);
3567
3568                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3569
3570                 switch (XHCI_PS_SPEED_GET(v)) {
3571                 case 3:
3572                         i |= UPS_HIGH_SPEED;
3573                         break;
3574                 case 2:
3575                         i |= UPS_LOW_SPEED;
3576                         break;
3577                 case 1:
3578                         /* FULL speed */
3579                         break;
3580                 default:
3581                         i |= UPS_OTHER_SPEED;
3582                         break;
3583                 }
3584
3585                 if (v & XHCI_PS_CCS)
3586                         i |= UPS_CURRENT_CONNECT_STATUS;
3587                 if (v & XHCI_PS_PED)
3588                         i |= UPS_PORT_ENABLED;
3589                 if (v & XHCI_PS_OCA)
3590                         i |= UPS_OVERCURRENT_INDICATOR;
3591                 if (v & XHCI_PS_PR)
3592                         i |= UPS_RESET;
3593                 if (v & XHCI_PS_PP) {
3594                         /*
3595                          * The USB 3.0 RH is using the
3596                          * USB 2.0's power bit
3597                          */
3598                         i |= UPS_PORT_POWER;
3599                 }
3600                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3601
3602                 i = 0;
3603                 if (v & XHCI_PS_CSC)
3604                         i |= UPS_C_CONNECT_STATUS;
3605                 if (v & XHCI_PS_PEC)
3606                         i |= UPS_C_PORT_ENABLED;
3607                 if (v & XHCI_PS_OCC)
3608                         i |= UPS_C_OVERCURRENT_INDICATOR;
3609                 if (v & XHCI_PS_WRC)
3610                         i |= UPS_C_BH_PORT_RESET;
3611                 if (v & XHCI_PS_PRC)
3612                         i |= UPS_C_PORT_RESET;
3613                 if (v & XHCI_PS_PLC)
3614                         i |= UPS_C_PORT_LINK_STATE;
3615                 if (v & XHCI_PS_CEC)
3616                         i |= UPS_C_PORT_CONFIG_ERROR;
3617
3618                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3619                 len = sizeof(sc->sc_hub_desc.ps);
3620                 break;
3621
3622         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3623                 err = USB_ERR_IOERROR;
3624                 goto done;
3625
3626         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3627                 break;
3628
3629         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3630
3631                 i = index >> 8;
3632                 index &= 0x00FF;
3633
3634                 if ((index < 1) ||
3635                     (index > sc->sc_noport)) {
3636                         err = USB_ERR_IOERROR;
3637                         goto done;
3638                 }
3639
3640                 port = XHCI_PORTSC(index);
3641                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3642
3643                 switch (value) {
3644                 case UHF_PORT_U1_TIMEOUT:
3645                         if (XHCI_PS_SPEED_GET(v) != 4) {
3646                                 err = USB_ERR_IOERROR;
3647                                 goto done;
3648                         }
3649                         port = XHCI_PORTPMSC(index);
3650                         v = XREAD4(sc, oper, port);
3651                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3652                         v |= XHCI_PM3_U1TO_SET(i);
3653                         XWRITE4(sc, oper, port, v);
3654                         break;
3655                 case UHF_PORT_U2_TIMEOUT:
3656                         if (XHCI_PS_SPEED_GET(v) != 4) {
3657                                 err = USB_ERR_IOERROR;
3658                                 goto done;
3659                         }
3660                         port = XHCI_PORTPMSC(index);
3661                         v = XREAD4(sc, oper, port);
3662                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3663                         v |= XHCI_PM3_U2TO_SET(i);
3664                         XWRITE4(sc, oper, port, v);
3665                         break;
3666                 case UHF_BH_PORT_RESET:
3667                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3668                         break;
3669                 case UHF_PORT_LINK_STATE:
3670                         XWRITE4(sc, oper, port, v |
3671                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3672                         /* 4ms settle time */
3673                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3674                         break;
3675                 case UHF_PORT_ENABLE:
3676                         DPRINTFN(3, "set port enable %d\n", index);
3677                         break;
3678                 case UHF_PORT_SUSPEND:
3679                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3680                         j = XHCI_PS_SPEED_GET(v);
3681                         if ((j < 1) || (j > 3)) {
3682                                 /* non-supported speed */
3683                                 err = USB_ERR_IOERROR;
3684                                 goto done;
3685                         }
3686                         XWRITE4(sc, oper, port, v |
3687                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3688                         break;
3689                 case UHF_PORT_RESET:
3690                         DPRINTFN(6, "reset port %d\n", index);
3691                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3692                         break;
3693                 case UHF_PORT_POWER:
3694                         DPRINTFN(3, "set port power %d\n", index);
3695                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3696                         break;
3697                 case UHF_PORT_TEST:
3698                         DPRINTFN(3, "set port test %d\n", index);
3699                         break;
3700                 case UHF_PORT_INDICATOR:
3701                         DPRINTFN(3, "set port indicator %d\n", index);
3702
3703                         v &= ~XHCI_PS_PIC_SET(3);
3704                         v |= XHCI_PS_PIC_SET(1);
3705
3706                         XWRITE4(sc, oper, port, v);
3707                         break;
3708                 default:
3709                         err = USB_ERR_IOERROR;
3710                         goto done;
3711                 }
3712                 break;
3713
3714         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3715         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3716         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3717         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3718                 break;
3719         default:
3720                 err = USB_ERR_IOERROR;
3721                 goto done;
3722         }
3723 done:
3724         *plength = len;
3725         *pptr = ptr;
3726         return (err);
3727 }
3728
3729 static void
3730 xhci_xfer_setup(struct usb_setup_params *parm)
3731 {
3732         struct usb_page_search page_info;
3733         struct usb_page_cache *pc;
3734         struct usb_xfer *xfer;
3735         void *last_obj;
3736         uint32_t ntd;
3737         uint32_t n;
3738
3739         xfer = parm->curr_xfer;
3740
3741         /*
3742          * The proof for the "ntd" formula is illustrated like this:
3743          *
3744          * +------------------------------------+
3745          * |                                    |
3746          * |         |remainder ->              |
3747          * |   +-----+---+                      |
3748          * |   | xxx | x | frm 0                |
3749          * |   +-----+---++                     |
3750          * |   | xxx | xx | frm 1               |
3751          * |   +-----+----+                     |
3752          * |            ...                     |
3753          * +------------------------------------+
3754          *
3755          * "xxx" means a completely full USB transfer descriptor
3756          *
3757          * "x" and "xx" means a short USB packet
3758          *
3759          * For the remainder of an USB transfer modulo
3760          * "max_data_length" we need two USB transfer descriptors.
3761          * One to transfer the remaining data and one to finalise with
3762          * a zero length packet in case the "force_short_xfer" flag is
3763          * set. We only need two USB transfer descriptors in the case
3764          * where the transfer length of the first one is a factor of
3765          * "max_frame_size". The rest of the needed USB transfer
3766          * descriptors is given by the buffer size divided by the
3767          * maximum data payload.
3768          */
3769         parm->hc_max_packet_size = 0x400;
3770         parm->hc_max_packet_count = 16 * 3;
3771         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3772
3773         xfer->flags_int.bdma_enable = 1;
3774
3775         usbd_transfer_setup_sub(parm);
3776
3777         if (xfer->flags_int.isochronous_xfr) {
3778                 ntd = ((1 * xfer->nframes)
3779                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3780         } else if (xfer->flags_int.control_xfr) {
3781                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3782                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3783         } else {
3784                 ntd = ((2 * xfer->nframes)
3785                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3786         }
3787
3788 alloc_dma_set:
3789
3790         if (parm->err)
3791                 return;
3792
3793         /*
3794          * Allocate queue heads and transfer descriptors
3795          */
3796         last_obj = NULL;
3797
3798         if (usbd_transfer_setup_sub_malloc(
3799             parm, &pc, sizeof(struct xhci_td),
3800             XHCI_TD_ALIGN, ntd)) {
3801                 parm->err = USB_ERR_NOMEM;
3802                 return;
3803         }
3804         if (parm->buf) {
3805                 for (n = 0; n != ntd; n++) {
3806                         struct xhci_td *td;
3807
3808                         usbd_get_page(pc + n, 0, &page_info);
3809
3810                         td = page_info.buffer;
3811
3812                         /* init TD */
3813                         td->td_self = page_info.physaddr;
3814                         td->obj_next = last_obj;
3815                         td->page_cache = pc + n;
3816
3817                         last_obj = td;
3818
3819                         usb_pc_cpu_flush(pc + n);
3820                 }
3821         }
3822         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3823
3824         if (!xfer->flags_int.curr_dma_set) {
3825                 xfer->flags_int.curr_dma_set = 1;
3826                 goto alloc_dma_set;
3827         }
3828 }
3829
3830 static usb_error_t
3831 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3832 {
3833         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3834         struct usb_page_search buf_inp;
3835         struct usb_device *udev;
3836         struct xhci_endpoint_ext *pepext;
3837         struct usb_endpoint_descriptor *edesc;
3838         struct usb_page_cache *pcinp;
3839         usb_error_t err;
3840         usb_stream_t stream_id;
3841         uint8_t index;
3842         uint8_t epno;
3843
3844         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3845             xfer->endpoint->edesc);
3846
3847         udev = xfer->xroot->udev;
3848         index = udev->controller_slot_id;
3849
3850         pcinp = &sc->sc_hw.devs[index].input_pc;
3851
3852         usbd_get_page(pcinp, 0, &buf_inp);
3853
3854         edesc = xfer->endpoint->edesc;
3855
3856         epno = edesc->bEndpointAddress;
3857         stream_id = xfer->stream_id;
3858
3859         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3860                 epno |= UE_DIR_IN;
3861
3862         epno = XHCI_EPNO2EPID(epno);
3863
3864         if (epno == 0)
3865                 return (USB_ERR_NO_PIPE);               /* invalid */
3866
3867         XHCI_CMD_LOCK(sc);
3868
3869         /* configure endpoint */
3870
3871         err = xhci_configure_endpoint_by_xfer(xfer);
3872
3873         if (err != 0) {
3874                 XHCI_CMD_UNLOCK(sc);
3875                 return (err);
3876         }
3877
3878         /*
3879          * Get the endpoint into the stopped state according to the
3880          * endpoint context state diagram in the XHCI specification:
3881          */
3882
3883         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3884
3885         if (err != 0)
3886                 DPRINTF("Could not stop endpoint %u\n", epno);
3887
3888         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3889
3890         if (err != 0)
3891                 DPRINTF("Could not reset endpoint %u\n", epno);
3892
3893         err = xhci_cmd_set_tr_dequeue_ptr(sc,
3894             (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3895             XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3896             stream_id, epno, index);
3897
3898         if (err != 0)
3899                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3900
3901         /*
3902          * Get the endpoint into the running state according to the
3903          * endpoint context state diagram in the XHCI specification:
3904          */
3905
3906         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3907
3908         if (epno > 1)
3909                 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3910         else
3911                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3912
3913         if (err != 0)
3914                 DPRINTF("Could not configure endpoint %u\n", epno);
3915
3916         XHCI_CMD_UNLOCK(sc);
3917
3918         return (0);
3919 }
3920
3921 static void
3922 xhci_xfer_unsetup(struct usb_xfer *xfer)
3923 {
3924         return;
3925 }
3926
3927 static void
3928 xhci_start_dma_delay(struct usb_xfer *xfer)
3929 {
3930         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3931
3932         /* put transfer on interrupt queue (again) */
3933         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3934
3935         (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3936             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3937 }
3938
3939 static void
3940 xhci_configure_msg(struct usb_proc_msg *pm)
3941 {
3942         struct xhci_softc *sc;
3943         struct xhci_endpoint_ext *pepext;
3944         struct usb_xfer *xfer;
3945
3946         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3947
3948 restart:
3949         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3950
3951                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3952                     xfer->endpoint->edesc);
3953
3954                 if ((pepext->trb_halted != 0) ||
3955                     (pepext->trb_running == 0)) {
3956
3957                         uint16_t i;
3958
3959                         /* clear halted and running */
3960                         pepext->trb_halted = 0;
3961                         pepext->trb_running = 0;
3962
3963                         /* nuke remaining buffered transfers */
3964
3965                         for (i = 0; i != (XHCI_MAX_TRANSFERS *
3966                             XHCI_MAX_STREAMS); i++) {
3967                                 /*
3968                                  * NOTE: We need to use the timeout
3969                                  * error code here else existing
3970                                  * isochronous clients can get
3971                                  * confused:
3972                                  */
3973                                 if (pepext->xfer[i] != NULL) {
3974                                         xhci_device_done(pepext->xfer[i],
3975                                             USB_ERR_TIMEOUT);
3976                                 }
3977                         }
3978
3979                         /*
3980                          * NOTE: The USB transfer cannot vanish in
3981                          * this state!
3982                          */
3983
3984                         USB_BUS_UNLOCK(&sc->sc_bus);
3985
3986                         xhci_configure_reset_endpoint(xfer);
3987
3988                         USB_BUS_LOCK(&sc->sc_bus);
3989
3990                         /* check if halted is still cleared */
3991                         if (pepext->trb_halted == 0) {
3992                                 pepext->trb_running = 1;
3993                                 memset(pepext->trb_index, 0,
3994                                     sizeof(pepext->trb_index));
3995                         }
3996                         goto restart;
3997                 }
3998
3999                 if (xfer->flags_int.did_dma_delay) {
4000
4001                         /* remove transfer from interrupt queue (again) */
4002                         usbd_transfer_dequeue(xfer);
4003
4004                         /* we are finally done */
4005                         usb_dma_delay_done_cb(xfer);
4006
4007                         /* queue changed - restart */
4008                         goto restart;
4009                 }
4010         }
4011
4012         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
4013
4014                 /* try to insert xfer on HW queue */
4015                 xhci_transfer_insert(xfer);
4016
4017                 /* try to multi buffer */
4018                 xhci_device_generic_multi_enter(xfer->endpoint,
4019                     xfer->stream_id, NULL);
4020         }
4021 }
4022
4023 static void
4024 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4025     struct usb_endpoint *ep)
4026 {
4027         struct xhci_endpoint_ext *pepext;
4028
4029         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4030             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4031
4032         if (udev->parent_hub == NULL) {
4033                 /* root HUB has special endpoint handling */
4034                 return;
4035         }
4036
4037         ep->methods = &xhci_device_generic_methods;
4038
4039         pepext = xhci_get_endpoint_ext(udev, edesc);
4040
4041         USB_BUS_LOCK(udev->bus);
4042         pepext->trb_halted = 1;
4043         pepext->trb_running = 0;
4044         USB_BUS_UNLOCK(udev->bus);
4045 }
4046
4047 static void
4048 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4049 {
4050
4051 }
4052
4053 static void
4054 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4055 {
4056         struct xhci_endpoint_ext *pepext;
4057
4058         DPRINTF("\n");
4059
4060         if (udev->flags.usb_mode != USB_MODE_HOST) {
4061                 /* not supported */
4062                 return;
4063         }
4064         if (udev->parent_hub == NULL) {
4065                 /* root HUB has special endpoint handling */
4066                 return;
4067         }
4068
4069         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4070
4071         USB_BUS_LOCK(udev->bus);
4072         pepext->trb_halted = 1;
4073         pepext->trb_running = 0;
4074         USB_BUS_UNLOCK(udev->bus);
4075 }
4076
4077 static usb_error_t
4078 xhci_device_init(struct usb_device *udev)
4079 {
4080         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4081         usb_error_t err;
4082         uint8_t temp;
4083
4084         /* no init for root HUB */
4085         if (udev->parent_hub == NULL)
4086                 return (0);
4087
4088         XHCI_CMD_LOCK(sc);
4089
4090         /* set invalid default */
4091
4092         udev->controller_slot_id = sc->sc_noslot + 1;
4093
4094         /* try to get a new slot ID from the XHCI */
4095
4096         err = xhci_cmd_enable_slot(sc, &temp);
4097
4098         if (err) {
4099                 XHCI_CMD_UNLOCK(sc);
4100                 return (err);
4101         }
4102
4103         if (temp > sc->sc_noslot) {
4104                 XHCI_CMD_UNLOCK(sc);
4105                 return (USB_ERR_BAD_ADDRESS);
4106         }
4107
4108         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4109                 DPRINTF("slot %u already allocated.\n", temp);
4110                 XHCI_CMD_UNLOCK(sc);
4111                 return (USB_ERR_BAD_ADDRESS);
4112         }
4113
4114         /* store slot ID for later reference */
4115
4116         udev->controller_slot_id = temp;
4117
4118         /* reset data structure */
4119
4120         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4121
4122         /* set mark slot allocated */
4123
4124         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4125
4126         err = xhci_alloc_device_ext(udev);
4127
4128         XHCI_CMD_UNLOCK(sc);
4129
4130         /* get device into default state */
4131
4132         if (err == 0)
4133                 err = xhci_set_address(udev, NULL, 0);
4134
4135         return (err);
4136 }
4137
4138 static void
4139 xhci_device_uninit(struct usb_device *udev)
4140 {
4141         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4142         uint8_t index;
4143
4144         /* no init for root HUB */
4145         if (udev->parent_hub == NULL)
4146                 return;
4147
4148         XHCI_CMD_LOCK(sc);
4149
4150         index = udev->controller_slot_id;
4151
4152         if (index <= sc->sc_noslot) {
4153                 xhci_cmd_disable_slot(sc, index);
4154                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4155
4156                 /* free device extension */
4157                 xhci_free_device_ext(udev);
4158         }
4159
4160         XHCI_CMD_UNLOCK(sc);
4161 }
4162
4163 static void
4164 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4165 {
4166         /*
4167          * Wait until the hardware has finished any possible use of
4168          * the transfer descriptor(s)
4169          */
4170         *pus = 2048;                    /* microseconds */
4171 }
4172
4173 static void
4174 xhci_device_resume(struct usb_device *udev)
4175 {
4176         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4177         uint8_t index;
4178         uint8_t n;
4179         uint8_t p;
4180
4181         DPRINTF("\n");
4182
4183         /* check for root HUB */
4184         if (udev->parent_hub == NULL)
4185                 return;
4186
4187         index = udev->controller_slot_id;
4188
4189         XHCI_CMD_LOCK(sc);
4190
4191         /* blindly resume all endpoints */
4192
4193         USB_BUS_LOCK(udev->bus);
4194
4195         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4196                 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4197                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4198                             n | XHCI_DB_SID_SET(p));
4199                 }
4200         }
4201
4202         USB_BUS_UNLOCK(udev->bus);
4203
4204         XHCI_CMD_UNLOCK(sc);
4205 }
4206
4207 static void
4208 xhci_device_suspend(struct usb_device *udev)
4209 {
4210         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4211         uint8_t index;
4212         uint8_t n;
4213         usb_error_t err;
4214
4215         DPRINTF("\n");
4216
4217         /* check for root HUB */
4218         if (udev->parent_hub == NULL)
4219                 return;
4220
4221         index = udev->controller_slot_id;
4222
4223         XHCI_CMD_LOCK(sc);
4224
4225         /* blindly suspend all endpoints */
4226
4227         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4228                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4229                 if (err != 0) {
4230                         DPRINTF("Failed to suspend endpoint "
4231                             "%u on slot %u (ignored).\n", n, index);
4232                 }
4233         }
4234
4235         XHCI_CMD_UNLOCK(sc);
4236 }
4237
4238 static void
4239 xhci_set_hw_power(struct usb_bus *bus)
4240 {
4241         DPRINTF("\n");
4242 }
4243
4244 static void
4245 xhci_device_state_change(struct usb_device *udev)
4246 {
4247         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4248         struct usb_page_search buf_inp;
4249         usb_error_t err;
4250         uint8_t index;
4251
4252         /* check for root HUB */
4253         if (udev->parent_hub == NULL)
4254                 return;
4255
4256         index = udev->controller_slot_id;
4257
4258         DPRINTF("\n");
4259
4260         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4261                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4262                     &sc->sc_hw.devs[index].tt);
4263                 if (err != 0)
4264                         sc->sc_hw.devs[index].nports = 0;
4265         }
4266
4267         XHCI_CMD_LOCK(sc);
4268
4269         switch (usb_get_device_state(udev)) {
4270         case USB_STATE_POWERED:
4271                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4272                         break;
4273
4274                 /* set default state */
4275                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4276
4277                 /* reset number of contexts */
4278                 sc->sc_hw.devs[index].context_num = 0;
4279
4280                 err = xhci_cmd_reset_dev(sc, index);
4281
4282                 if (err != 0) {
4283                         DPRINTF("Device reset failed "
4284                             "for slot %u.\n", index);
4285                 }
4286                 break;
4287
4288         case USB_STATE_ADDRESSED:
4289                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4290                         break;
4291
4292                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4293
4294                 /* set configure mask to slot only */
4295                 xhci_configure_mask(udev, 1, 0);
4296
4297                 /* deconfigure all endpoints, except EP0 */
4298                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4299
4300                 if (err) {
4301                         DPRINTF("Failed to deconfigure "
4302                             "slot %u.\n", index);
4303                 }
4304                 break;
4305
4306         case USB_STATE_CONFIGURED:
4307                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4308                         break;
4309
4310                 /* set configured state */
4311                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4312
4313                 /* reset number of contexts */
4314                 sc->sc_hw.devs[index].context_num = 0;
4315
4316                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4317
4318                 xhci_configure_mask(udev, 3, 0);
4319
4320                 err = xhci_configure_device(udev);
4321                 if (err != 0) {
4322                         DPRINTF("Could not configure device "
4323                             "at slot %u.\n", index);
4324                 }
4325
4326                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4327                 if (err != 0) {
4328                         DPRINTF("Could not evaluate device "
4329                             "context at slot %u.\n", index);
4330                 }
4331                 break;
4332
4333         default:
4334                 break;
4335         }
4336         XHCI_CMD_UNLOCK(sc);
4337 }
4338
4339 static usb_error_t
4340 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4341     uint8_t ep_mode)
4342 {
4343         switch (ep_mode) {
4344         case USB_EP_MODE_DEFAULT:
4345                 return (0);
4346         case USB_EP_MODE_STREAMS:
4347                 if (xhcistreams == 0 ||
4348                     (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4349                     udev->speed != USB_SPEED_SUPER)
4350                         return (USB_ERR_INVAL);
4351                 return (0);
4352         default:
4353                 return (USB_ERR_INVAL);
4354         }
4355 }
4356
4357 static const struct usb_bus_methods xhci_bus_methods = {
4358         .endpoint_init = xhci_ep_init,
4359         .endpoint_uninit = xhci_ep_uninit,
4360         .xfer_setup = xhci_xfer_setup,
4361         .xfer_unsetup = xhci_xfer_unsetup,
4362         .get_dma_delay = xhci_get_dma_delay,
4363         .device_init = xhci_device_init,
4364         .device_uninit = xhci_device_uninit,
4365         .device_resume = xhci_device_resume,
4366         .device_suspend = xhci_device_suspend,
4367         .set_hw_power = xhci_set_hw_power,
4368         .roothub_exec = xhci_roothub_exec,
4369         .xfer_poll = xhci_do_poll,
4370         .start_dma_delay = xhci_start_dma_delay,
4371         .set_address = xhci_set_address,
4372         .clear_stall = xhci_ep_clear_stall,
4373         .device_state_change = xhci_device_state_change,
4374         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4375         .set_endpoint_mode = xhci_set_endpoint_mode,
4376 };