sys/dev/usb/controller/xhci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   4  *
   5  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  31  *
  32  * The XHCI 1.0 spec can be found at
  33  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  34  * and the USB 3.0 spec at
  35  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  36  */
  37
  38 /*
  39  * A few words about the design implementation: This driver emulates
  40  * the concept about TDs which is found in EHCI specification. This
  41  * way we achieve that the USB controller drivers look similar to
  42  * eachother which makes it easier to understand the code.
  43  */
  44
  45 #ifdef USB_GLOBAL_INCLUDE_FILE
  46 #include USB_GLOBAL_INCLUDE_FILE
  47 #else
  48 #include <sys/stdint.h>
  49 #include <sys/stddef.h>
  50 #include <sys/param.h>
  51 #include <sys/queue.h>
  52 #include <sys/types.h>
  53 #include <sys/systm.h>
  54 #include <sys/kernel.h>
  55 #include <sys/bus.h>
  56 #include <sys/module.h>
  57 #include <sys/lock.h>
  58 #include <sys/mutex.h>
  59 #include <sys/condvar.h>
  60 #include <sys/sysctl.h>
  61 #include <sys/sx.h>
  62 #include <sys/unistd.h>
  63 #include <sys/callout.h>
  64 #include <sys/malloc.h>
  65 #include <sys/priv.h>
  66
  67 #include <dev/usb/usb.h>
  68 #include <dev/usb/usbdi.h>
  69
  70 #define USB_DEBUG_VAR xhcidebug
  71
  72 #include <dev/usb/usb_core.h>
  73 #include <dev/usb/usb_debug.h>
  74 #include <dev/usb/usb_busdma.h>
  75 #include <dev/usb/usb_process.h>
  76 #include <dev/usb/usb_transfer.h>
  77 #include <dev/usb/usb_device.h>
  78 #include <dev/usb/usb_hub.h>
  79 #include <dev/usb/usb_util.h>
  80
  81 #include <dev/usb/usb_controller.h>
  82 #include <dev/usb/usb_bus.h>
  83 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  84
  85 #include <dev/usb/controller/xhci.h>
  86 #include <dev/usb/controller/xhcireg.h>
  87
  88 #define XHCI_BUS2SC(bus) \
  89    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  90     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  91
  92 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  93
  94 static int xhcistreams;
  95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN,
  96     &xhcistreams, 0, "Set to enable streams mode support");
  97
  98 static int xhcictlquirk = 1;
  99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN,
 100     &xhcictlquirk, 0, "Set to enable control endpoint quirk");
 101
 102 #ifdef USB_DEBUG
 103 static int xhcidebug;
 104 static int xhciroute;
 105 static int xhcipolling;
 106 static int xhcidma32;
 107 static int xhcictlstep;
 108
 109 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN,
 110     &xhcidebug, 0, "Debug level");
 111 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN,
 112     &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
 113 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN,
 114     &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
 115 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
 116     &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
 117 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
 118     &xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
 119 #else
 120 #define xhciroute 0
 121 #define xhcidma32 0
 122 #define xhcictlstep 0
 123 #endif
 124
 125 #define XHCI_INTR_ENDPT 1
 126
 127 struct xhci_std_temp {
 128         struct xhci_softc       *sc;
 129         struct usb_page_cache   *pc;
 130         struct xhci_td          *td;
 131         struct xhci_td          *td_next;
 132         uint32_t                len;
 133         uint32_t                offset;
 134         uint32_t                max_packet_size;
 135         uint32_t                average;
 136         uint16_t                isoc_delta;
 137         uint16_t                isoc_frame;
 138         uint8_t                 shortpkt;
 139         uint8_t                 multishort;
 140         uint8_t                 last_frame;
 141         uint8_t                 trb_type;
 142         uint8_t                 direction;
 143         uint8_t                 tbc;
 144         uint8_t                 tlbpc;
 145         uint8_t                 step_td;
 146         uint8_t                 do_isoc_sync;
 147 };
 148
 149 static void     xhci_do_poll(struct usb_bus *);
 150 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 151 static void     xhci_root_intr(struct xhci_softc *);
 152 static void     xhci_free_device_ext(struct usb_device *);
 153 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 154                     struct usb_endpoint_descriptor *);
 155 static usb_proc_callback_t xhci_configure_msg;
 156 static usb_error_t xhci_configure_device(struct usb_device *);
 157 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 158                    struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 159                    uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
 160                    uint8_t);
 161 static usb_error_t xhci_configure_mask(struct usb_device *,
 162                     uint32_t, uint8_t);
 163 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 164                     uint64_t, uint8_t);
 165 static void xhci_endpoint_doorbell(struct usb_xfer *);
 166 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 167 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 168 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 169 #ifdef USB_DEBUG
 170 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 171 #endif
 172
 173 static const struct usb_bus_methods xhci_bus_methods;
 174
 175 #ifdef USB_DEBUG
 176 static void
 177 xhci_dump_trb(struct xhci_trb *trb)
 178 {
 179         DPRINTFN(5, "trb = %p\n", trb);
 180         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 181         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 182         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 183 }
 184
 185 static void
 186 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 187 {
 188         DPRINTFN(5, "pep = %p\n", pep);
 189         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 190         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 191         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 192         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 193         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 194         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 195         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 196 }
 197
 198 static void
 199 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 200 {
 201         DPRINTFN(5, "psl = %p\n", psl);
 202         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 203         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 204         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 205         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 206 }
 207 #endif
 208
 209 uint8_t
 210 xhci_use_polling(void)
 211 {
 212 #ifdef USB_DEBUG
 213         return (xhcipolling != 0);
 214 #else
 215         return (0);
 216 #endif
 217 }
 218
 219 static void
 220 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 221 {
 222         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 223         uint16_t i;
 224
 225         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 226            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 227
 228         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 229            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 230
 231         for (i = 0; i != sc->sc_noscratch; i++) {
 232                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 233                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 234         }
 235 }
 236
 237 static void
 238 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 239 {
 240         if (sc->sc_ctx_is_64_byte) {
 241                 uint32_t offset;
 242                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 243                 /* all contexts are initially 32-bytes */
 244                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 245                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 246         }
 247         *ptr = htole32(val);
 248 }
 249
 250 static uint32_t
 251 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 252 {
 253         if (sc->sc_ctx_is_64_byte) {
 254                 uint32_t offset;
 255                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 256                 /* all contexts are initially 32-bytes */
 257                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 258                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 259         }
 260         return (le32toh(*ptr));
 261 }
 262
 263 static void
 264 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 265 {
 266         if (sc->sc_ctx_is_64_byte) {
 267                 uint32_t offset;
 268                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 269                 /* all contexts are initially 32-bytes */
 270                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 271                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 272         }
 273         *ptr = htole64(val);
 274 }
 275
 276 #ifdef USB_DEBUG
 277 static uint64_t
 278 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 279 {
 280         if (sc->sc_ctx_is_64_byte) {
 281                 uint32_t offset;
 282                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 283                 /* all contexts are initially 32-bytes */
 284                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 285                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 286         }
 287         return (le64toh(*ptr));
 288 }
 289 #endif
 290
 291 static int
 292 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 293 {
 294         struct usb_page_search buf_res;
 295         struct xhci_hw_root *phwr;
 296         uint64_t addr;
 297         uint32_t temp;
 298
 299         DPRINTF("\n");
 300
 301         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 302         if (temp & XHCI_CRCR_LO_CRR) {
 303                 DPRINTF("Command ring running\n");
 304                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 305
 306                 /*
 307                  * Try to abort the last command as per section
 308                  * 4.6.1.2 "Aborting a Command" of the XHCI
 309                  * specification:
 310                  */
 311
 312                 /* stop and cancel */
 313                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 314                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 315
 316                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 317                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 318
 319                 /* wait 250ms */
 320                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 321
 322                 /* check if command ring is still running */
 323                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 324                 if (temp & XHCI_CRCR_LO_CRR) {
 325                         DPRINTF("Comand ring still running\n");
 326                         return (USB_ERR_IOERROR);
 327                 }
 328         }
 329
 330         /* reset command ring */
 331         sc->sc_command_ccs = 1;
 332         sc->sc_command_idx = 0;
 333
 334         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 335
 336         /* set up command ring control base address */
 337         addr = buf_res.physaddr;
 338         phwr = buf_res.buffer;
 339         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 340
 341         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 342
 343         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 344         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 345
 346         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 347
 348         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 349         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 350
 351         return (0);
 352 }
 353
 354 usb_error_t
 355 xhci_start_controller(struct xhci_softc *sc)
 356 {
 357         struct usb_page_search buf_res;
 358         struct xhci_hw_root *phwr;
 359         struct xhci_dev_ctx_addr *pdctxa;
 360         usb_error_t err;
 361         uint64_t addr;
 362         uint32_t temp;
 363         uint16_t i;
 364
 365         DPRINTF("\n");
 366
 367         sc->sc_event_ccs = 1;
 368         sc->sc_event_idx = 0;
 369         sc->sc_command_ccs = 1;
 370         sc->sc_command_idx = 0;
 371
 372         err = xhci_reset_controller(sc);
 373         if (err)
 374                 return (err);
 375
 376         /* set up number of device slots */
 377         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 378             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 379
 380         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 381
 382         temp = XREAD4(sc, oper, XHCI_USBSTS);
 383
 384         /* clear interrupts */
 385         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 386         /* disable all device notifications */
 387         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 388
 389         /* set up device context base address */
 390         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 391         pdctxa = buf_res.buffer;
 392         memset(pdctxa, 0, sizeof(*pdctxa));
 393
 394         addr = buf_res.physaddr;
 395         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 396
 397         /* slot 0 points to the table of scratchpad pointers */
 398         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 399
 400         for (i = 0; i != sc->sc_noscratch; i++) {
 401                 struct usb_page_search buf_scp;
 402                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 403                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 404         }
 405
 406         addr = buf_res.physaddr;
 407
 408         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 409         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 410         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 411         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 412
 413         /* set up event table size */
 414         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 415             XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
 416
 417         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
 418
 419         /* set up interrupt rate */
 420         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 421
 422         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 423
 424         phwr = buf_res.buffer;
 425         addr = buf_res.physaddr;
 426         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 427
 428         /* reset hardware root structure */
 429         memset(phwr, 0, sizeof(*phwr));
 430
 431         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 432         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 433
 434         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 435
 436         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 437         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 438
 439         addr = buf_res.physaddr;
 440
 441         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 442
 443         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 444         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 445
 446         /* set up interrupter registers */
 447         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 448         temp |= XHCI_IMAN_INTR_ENA;
 449         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 450
 451         /* set up command ring control base address */
 452         addr = buf_res.physaddr;
 453         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 454
 455         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 456
 457         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 458         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 459
 460         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 461
 462         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 463
 464         /* Go! */
 465         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 466             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 467
 468         for (i = 0; i != 100; i++) {
 469                 usb_pause_mtx(NULL, hz / 100);
 470                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 471                 if (!temp)
 472                         break;
 473         }
 474         if (temp) {
 475                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 476                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 477                 return (USB_ERR_IOERROR);
 478         }
 479
 480         /* catch any lost interrupts */
 481         xhci_do_poll(&sc->sc_bus);
 482
 483         if (sc->sc_port_route != NULL) {
 484                 /* Route all ports to the XHCI by default */
 485                 sc->sc_port_route(sc->sc_bus.parent,
 486                     ~xhciroute, xhciroute);
 487         }
 488         return (0);
 489 }
 490
 491 usb_error_t
 492 xhci_halt_controller(struct xhci_softc *sc)
 493 {
 494         uint32_t temp;
 495         uint16_t i;
 496
 497         DPRINTF("\n");
 498
 499         sc->sc_capa_off = 0;
 500         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 501         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 502         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 503
 504         /* Halt controller */
 505         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 506
 507         for (i = 0; i != 100; i++) {
 508                 usb_pause_mtx(NULL, hz / 100);
 509                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 510                 if (temp)
 511                         break;
 512         }
 513
 514         if (!temp) {
 515                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 516                 return (USB_ERR_IOERROR);
 517         }
 518         return (0);
 519 }
 520
 521 usb_error_t
 522 xhci_reset_controller(struct xhci_softc *sc)
 523 {
 524         uint32_t temp = 0;
 525         uint16_t i;
 526
 527         DPRINTF("\n");
 528
 529         /* Reset controller */
 530         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 531
 532         for (i = 0; i != 100; i++) {
 533                 usb_pause_mtx(NULL, hz / 100);
 534                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 535                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 536                 if (!temp)
 537                         break;
 538         }
 539
 540         if (temp) {
 541                 device_printf(sc->sc_bus.parent, "Controller "
 542                     "reset timeout.\n");
 543                 return (USB_ERR_IOERROR);
 544         }
 545         return (0);
 546 }
 547
 548 usb_error_t
 549 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
 550 {
 551         uint32_t temp;
 552
 553         DPRINTF("\n");
 554
 555         /* initialize some bus fields */
 556         sc->sc_bus.parent = self;
 557
 558         /* set the bus revision */
 559         sc->sc_bus.usbrev = USB_REV_3_0;
 560
 561         /* set up the bus struct */
 562         sc->sc_bus.methods = &xhci_bus_methods;
 563
 564         /* set up devices array */
 565         sc->sc_bus.devices = sc->sc_devices;
 566         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 567
 568         /* set default cycle state in case of early interrupts */
 569         sc->sc_event_ccs = 1;
 570         sc->sc_command_ccs = 1;
 571
 572         /* set up bus space offsets */
 573         sc->sc_capa_off = 0;
 574         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 575         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 576         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 577
 578         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 579         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 580         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 581
 582         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 583
 584         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 585                 device_printf(sc->sc_bus.parent, "Controller does "
 586                     "not support 4K page size.\n");
 587                 return (ENXIO);
 588         }
 589
 590         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 591
 592         DPRINTF("HCS0 = 0x%08x\n", temp);
 593
 594         /* set up context size */
 595         if (XHCI_HCS0_CSZ(temp)) {
 596                 sc->sc_ctx_is_64_byte = 1;
 597         } else {
 598                 sc->sc_ctx_is_64_byte = 0;
 599         }
 600
 601         /* get DMA bits */
 602         sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
 603             xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
 604
 605         device_printf(self, "%d bytes context size, %d-bit DMA\n",
 606             sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
 607
 608         /* enable 64Kbyte control endpoint quirk */
 609         sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0);
 610
 611         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 612
 613         /* get number of device slots */
 614         sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
 615
 616         if (sc->sc_noport == 0) {
 617                 device_printf(sc->sc_bus.parent, "Invalid number "
 618                     "of ports: %u\n", sc->sc_noport);
 619                 return (ENXIO);
 620         }
 621
 622         sc->sc_noport = sc->sc_noport;
 623         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 624
 625         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 626
 627         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 628                 sc->sc_noslot = XHCI_MAX_DEVICES;
 629
 630         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 631
 632         DPRINTF("HCS2=0x%08x\n", temp);
 633
 634         /* get number of scratchpads */
 635         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 636
 637         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 638                 device_printf(sc->sc_bus.parent, "XHCI request "
 639                     "too many scratchpads\n");
 640                 return (ENOMEM);
 641         }
 642
 643         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 644
 645         /* get event table size */
 646         sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
 647         if (sc->sc_erst_max > XHCI_MAX_RSEG)
 648                 sc->sc_erst_max = XHCI_MAX_RSEG;
 649
 650         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 651
 652         /* get maximum exit latency */
 653         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 654             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 655
 656         /* Check if we should use the default IMOD value. */
 657         if (sc->sc_imod_default == 0)
 658                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 659
 660         /* get all DMA memory */
 661         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 662             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 663                 return (ENOMEM);
 664         }
 665
 666         /* set up command queue mutex and condition varible */
 667         cv_init(&sc->sc_cmd_cv, "CMDQ");
 668         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 669
 670         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 671         sc->sc_config_msg[0].bus = &sc->sc_bus;
 672         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 673         sc->sc_config_msg[1].bus = &sc->sc_bus;
 674
 675         return (0);
 676 }
 677
 678 void
 679 xhci_uninit(struct xhci_softc *sc)
 680 {
 681         /*
 682          * NOTE: At this point the control transfer process is gone
 683          * and "xhci_configure_msg" is no longer called. Consequently
 684          * waiting for the configuration messages to complete is not
 685          * needed.
 686          */
 687         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 688
 689         cv_destroy(&sc->sc_cmd_cv);
 690         sx_destroy(&sc->sc_cmd_sx);
 691 }
 692
 693 static void
 694 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 695 {
 696         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 697
 698         switch (state) {
 699         case USB_HW_POWER_SUSPEND:
 700                 DPRINTF("Stopping the XHCI\n");
 701                 xhci_halt_controller(sc);
 702                 xhci_reset_controller(sc);
 703                 break;
 704         case USB_HW_POWER_SHUTDOWN:
 705                 DPRINTF("Stopping the XHCI\n");
 706                 xhci_halt_controller(sc);
 707                 xhci_reset_controller(sc);
 708                 break;
 709         case USB_HW_POWER_RESUME:
 710                 DPRINTF("Starting the XHCI\n");
 711                 xhci_start_controller(sc);
 712                 break;
 713         default:
 714                 break;
 715         }
 716 }
 717
 718 static usb_error_t
 719 xhci_generic_done_sub(struct usb_xfer *xfer)
 720 {
 721         struct xhci_td *td;
 722         struct xhci_td *td_alt_next;
 723         uint32_t len;
 724         uint8_t status;
 725
 726         td = xfer->td_transfer_cache;
 727         td_alt_next = td->alt_next;
 728
 729         if (xfer->aframes != xfer->nframes)
 730                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 731
 732         while (1) {
 733
 734                 usb_pc_cpu_invalidate(td->page_cache);
 735
 736                 status = td->status;
 737                 len = td->remainder;
 738
 739                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 740                     xfer, (unsigned int)xfer->aframes,
 741                     (unsigned int)xfer->nframes,
 742                     (unsigned int)len, (unsigned int)td->len,
 743                     (unsigned int)status);
 744
 745                 /*
 746                  * Verify the status length and
 747                  * add the length to "frlengths[]":
 748                  */
 749                 if (len > td->len) {
 750                         /* should not happen */
 751                         DPRINTF("Invalid status length, "
 752                             "0x%04x/0x%04x bytes\n", len, td->len);
 753                         status = XHCI_TRB_ERROR_LENGTH;
 754                 } else if (xfer->aframes != xfer->nframes) {
 755                         xfer->frlengths[xfer->aframes] += td->len - len;
 756                 }
 757                 /* Check for last transfer */
 758                 if (((void *)td) == xfer->td_transfer_last) {
 759                         td = NULL;
 760                         break;
 761                 }
 762                 /* Check for transfer error */
 763                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 764                     status != XHCI_TRB_ERROR_SUCCESS) {
 765                         /* the transfer is finished */
 766                         td = NULL;
 767                         break;
 768                 }
 769                 /* Check for short transfer */
 770                 if (len > 0) {
 771                         if (xfer->flags_int.short_frames_ok ||
 772                             xfer->flags_int.isochronous_xfr ||
 773                             xfer->flags_int.control_xfr) {
 774                                 /* follow alt next */
 775                                 td = td->alt_next;
 776                         } else {
 777                                 /* the transfer is finished */
 778                                 td = NULL;
 779                         }
 780                         break;
 781                 }
 782                 td = td->obj_next;
 783
 784                 if (td->alt_next != td_alt_next) {
 785                         /* this USB frame is complete */
 786                         break;
 787                 }
 788         }
 789
 790         /* update transfer cache */
 791
 792         xfer->td_transfer_cache = td;
 793
 794         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 795             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 796             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 797             USB_ERR_NORMAL_COMPLETION);
 798 }
 799
 800 static void
 801 xhci_generic_done(struct usb_xfer *xfer)
 802 {
 803         usb_error_t err = 0;
 804
 805         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 806             xfer, xfer->endpoint);
 807
 808         /* reset scanner */
 809
 810         xfer->td_transfer_cache = xfer->td_transfer_first;
 811
 812         if (xfer->flags_int.control_xfr) {
 813
 814                 if (xfer->flags_int.control_hdr)
 815                         err = xhci_generic_done_sub(xfer);
 816
 817                 xfer->aframes = 1;
 818
 819                 if (xfer->td_transfer_cache == NULL)
 820                         goto done;
 821         }
 822
 823         while (xfer->aframes != xfer->nframes) {
 824
 825                 err = xhci_generic_done_sub(xfer);
 826                 xfer->aframes++;
 827
 828                 if (xfer->td_transfer_cache == NULL)
 829                         goto done;
 830         }
 831
 832         if (xfer->flags_int.control_xfr &&
 833             !xfer->flags_int.control_act)
 834                 err = xhci_generic_done_sub(xfer);
 835 done:
 836         /* transfer is complete */
 837         xhci_device_done(xfer, err);
 838 }
 839
 840 static void
 841 xhci_activate_transfer(struct usb_xfer *xfer)
 842 {
 843         struct xhci_td *td;
 844
 845         td = xfer->td_transfer_cache;
 846
 847         usb_pc_cpu_invalidate(td->page_cache);
 848
 849         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 850
 851                 /* activate the transfer */
 852
 853                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 854                 usb_pc_cpu_flush(td->page_cache);
 855
 856                 xhci_endpoint_doorbell(xfer);
 857         }
 858 }
 859
 860 static void
 861 xhci_skip_transfer(struct usb_xfer *xfer)
 862 {
 863         struct xhci_td *td;
 864         struct xhci_td *td_last;
 865
 866         td = xfer->td_transfer_cache;
 867         td_last = xfer->td_transfer_last;
 868
 869         td = td->alt_next;
 870
 871         usb_pc_cpu_invalidate(td->page_cache);
 872
 873         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 874
 875                 usb_pc_cpu_invalidate(td_last->page_cache);
 876
 877                 /* copy LINK TRB to current waiting location */
 878
 879                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 880                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 881                 usb_pc_cpu_flush(td->page_cache);
 882
 883                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 884                 usb_pc_cpu_flush(td->page_cache);
 885
 886                 xhci_endpoint_doorbell(xfer);
 887         }
 888 }
 889
 890 /*------------------------------------------------------------------------*
 891  *      xhci_check_transfer
 892  *------------------------------------------------------------------------*/
 893 static void
 894 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 895 {
 896         struct xhci_endpoint_ext *pepext;
 897         int64_t offset;
 898         uint64_t td_event;
 899         uint32_t temp;
 900         uint32_t remainder;
 901         uint16_t stream_id = 0;
 902         uint16_t i;
 903         uint8_t status;
 904         uint8_t halted;
 905         uint8_t epno;
 906         uint8_t index;
 907
 908         /* decode TRB */
 909         td_event = le64toh(trb->qwTrb0);
 910         temp = le32toh(trb->dwTrb2);
 911
 912         remainder = XHCI_TRB_2_REM_GET(temp);
 913         status = XHCI_TRB_2_ERROR_GET(temp);
 914
 915         temp = le32toh(trb->dwTrb3);
 916         epno = XHCI_TRB_3_EP_GET(temp);
 917         index = XHCI_TRB_3_SLOT_GET(temp);
 918
 919         /* check if error means halted */
 920         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 921             status != XHCI_TRB_ERROR_SUCCESS);
 922
 923         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 924             index, epno, remainder, status);
 925
 926         if (index > sc->sc_noslot) {
 927                 DPRINTF("Invalid slot.\n");
 928                 return;
 929         }
 930
 931         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 932                 DPRINTF("Invalid endpoint.\n");
 933                 return;
 934         }
 935
 936         pepext = &sc->sc_hw.devs[index].endp[epno];
 937
 938         /* try to find the USB transfer that generated the event */
 939         for (i = 0;; i++) {
 940                 struct usb_xfer *xfer;
 941                 struct xhci_td *td;
 942
 943                 if (i == (XHCI_MAX_TRANSFERS - 1)) {
 944                         if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS ||
 945                             stream_id == (XHCI_MAX_STREAMS - 1))
 946                                 break;
 947                         stream_id++;
 948                         i = 0;
 949                         DPRINTFN(5, "stream_id=%u\n", stream_id);
 950                 }
 951
 952                 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
 953                 if (xfer == NULL)
 954                         continue;
 955
 956                 td = xfer->td_transfer_cache;
 957
 958                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 959                         (long long)td_event,
 960                         (long long)td->td_self,
 961                         (long long)td->td_self + sizeof(td->td_trb));
 962
 963                 /*
 964                  * NOTE: Some XHCI implementations might not trigger
 965                  * an event on the last LINK TRB so we need to
 966                  * consider both the last and second last event
 967                  * address as conditions for a successful transfer.
 968                  *
 969                  * NOTE: We assume that the XHCI will only trigger one
 970                  * event per chain of TRBs.
 971                  */
 972
 973                 offset = td_event - td->td_self;
 974
 975                 if (offset >= 0 &&
 976                     offset < (int64_t)sizeof(td->td_trb)) {
 977
 978                         usb_pc_cpu_invalidate(td->page_cache);
 979
 980                         /* compute rest of remainder, if any */
 981                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 982                                 temp = le32toh(td->td_trb[i].dwTrb2);
 983                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 984                         }
 985
 986                         DPRINTFN(5, "New remainder: %u\n", remainder);
 987
 988                         /* clear isochronous transfer errors */
 989                         if (xfer->flags_int.isochronous_xfr) {
 990                                 if (halted) {
 991                                         halted = 0;
 992                                         status = XHCI_TRB_ERROR_SUCCESS;
 993                                         remainder = td->len;
 994                                 }
 995                         }
 996
 997                         /* "td->remainder" is verified later */
 998                         td->remainder = remainder;
 999                         td->status = status;
1000
1001                         usb_pc_cpu_flush(td->page_cache);
1002
1003                         /*
1004                          * 1) Last transfer descriptor makes the
1005                          * transfer done
1006                          */
1007                         if (((void *)td) == xfer->td_transfer_last) {
1008                                 DPRINTF("TD is last\n");
1009                                 xhci_generic_done(xfer);
1010                                 break;
1011                         }
1012
1013                         /*
1014                          * 2) Any kind of error makes the transfer
1015                          * done
1016                          */
1017                         if (halted) {
1018                                 DPRINTF("TD has I/O error\n");
1019                                 xhci_generic_done(xfer);
1020                                 break;
1021                         }
1022
1023                         /*
1024                          * 3) If there is no alternate next transfer,
1025                          * a short packet also makes the transfer done
1026                          */
1027                         if (td->remainder > 0) {
1028                                 if (td->alt_next == NULL) {
1029                                         DPRINTF(
1030                                             "short TD has no alternate next\n");
1031                                         xhci_generic_done(xfer);
1032                                         break;
1033                                 }
1034                                 DPRINTF("TD has short pkt\n");
1035                                 if (xfer->flags_int.short_frames_ok ||
1036                                     xfer->flags_int.isochronous_xfr ||
1037                                     xfer->flags_int.control_xfr) {
1038                                         /* follow the alt next */
1039                                         xfer->td_transfer_cache = td->alt_next;
1040                                         xhci_activate_transfer(xfer);
1041                                         break;
1042                                 }
1043                                 xhci_skip_transfer(xfer);
1044                                 xhci_generic_done(xfer);
1045                                 break;
1046                         }
1047
1048                         /*
1049                          * 4) Transfer complete - go to next TD
1050                          */
1051                         DPRINTF("Following next TD\n");
1052                         xfer->td_transfer_cache = td->obj_next;
1053                         xhci_activate_transfer(xfer);
1054                         break;          /* there should only be one match */
1055                 }
1056         }
1057 }
1058
1059 static int
1060 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1061 {
1062         if (sc->sc_cmd_addr == trb->qwTrb0) {
1063                 DPRINTF("Received command event\n");
1064                 sc->sc_cmd_result[0] = trb->dwTrb2;
1065                 sc->sc_cmd_result[1] = trb->dwTrb3;
1066                 cv_signal(&sc->sc_cmd_cv);
1067                 return (1);     /* command match */
1068         }
1069         return (0);
1070 }
1071
1072 static int
1073 xhci_interrupt_poll(struct xhci_softc *sc)
1074 {
1075         struct usb_page_search buf_res;
1076         struct xhci_hw_root *phwr;
1077         uint64_t addr;
1078         uint32_t temp;
1079         int retval = 0;
1080         uint16_t i;
1081         uint8_t event;
1082         uint8_t j;
1083         uint8_t k;
1084         uint8_t t;
1085
1086         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1087
1088         phwr = buf_res.buffer;
1089
1090         /* Receive any events */
1091
1092         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1093
1094         i = sc->sc_event_idx;
1095         j = sc->sc_event_ccs;
1096         t = 2;
1097
1098         while (1) {
1099
1100                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1101
1102                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1103
1104                 if (j != k)
1105                         break;
1106
1107                 event = XHCI_TRB_3_TYPE_GET(temp);
1108
1109                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1110                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1111                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1112                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1113
1114                 switch (event) {
1115                 case XHCI_TRB_EVENT_TRANSFER:
1116                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1117                         break;
1118                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1119                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1120                         break;
1121                 default:
1122                         DPRINTF("Unhandled event = %u\n", event);
1123                         break;
1124                 }
1125
1126                 i++;
1127
1128                 if (i == XHCI_MAX_EVENTS) {
1129                         i = 0;
1130                         j ^= 1;
1131
1132                         /* check for timeout */
1133                         if (!--t)
1134                                 break;
1135                 }
1136         }
1137
1138         sc->sc_event_idx = i;
1139         sc->sc_event_ccs = j;
1140
1141         /*
1142          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1143          * latched. That means to activate the register we need to
1144          * write both the low and high double word of the 64-bit
1145          * register.
1146          */
1147
1148         addr = buf_res.physaddr;
1149         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1150
1151         /* try to clear busy bit */
1152         addr |= XHCI_ERDP_LO_BUSY;
1153
1154         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1155         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1156
1157         return (retval);
1158 }
1159
1160 static usb_error_t
1161 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1162     uint16_t timeout_ms)
1163 {
1164         struct usb_page_search buf_res;
1165         struct xhci_hw_root *phwr;
1166         uint64_t addr;
1167         uint32_t temp;
1168         uint8_t i;
1169         uint8_t j;
1170         uint8_t timeout = 0;
1171         int err;
1172
1173         XHCI_CMD_ASSERT_LOCKED(sc);
1174
1175         /* get hardware root structure */
1176
1177         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1178
1179         phwr = buf_res.buffer;
1180
1181         /* Queue command */
1182
1183         USB_BUS_LOCK(&sc->sc_bus);
1184 retry:
1185         i = sc->sc_command_idx;
1186         j = sc->sc_command_ccs;
1187
1188         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1189             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1190             (long long)le64toh(trb->qwTrb0),
1191             (long)le32toh(trb->dwTrb2),
1192             (long)le32toh(trb->dwTrb3));
1193
1194         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1195         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1196
1197         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1198
1199         temp = trb->dwTrb3;
1200
1201         if (j)
1202                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1203         else
1204                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1205
1206         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1207
1208         phwr->hwr_commands[i].dwTrb3 = temp;
1209
1210         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1211
1212         addr = buf_res.physaddr;
1213         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1214
1215         sc->sc_cmd_addr = htole64(addr);
1216
1217         i++;
1218
1219         if (i == (XHCI_MAX_COMMANDS - 1)) {
1220
1221                 if (j) {
1222                         temp = htole32(XHCI_TRB_3_TC_BIT |
1223                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1224                             XHCI_TRB_3_CYCLE_BIT);
1225                 } else {
1226                         temp = htole32(XHCI_TRB_3_TC_BIT |
1227                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1228                 }
1229
1230                 phwr->hwr_commands[i].dwTrb3 = temp;
1231
1232                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1233
1234                 i = 0;
1235                 j ^= 1;
1236         }
1237
1238         sc->sc_command_idx = i;
1239         sc->sc_command_ccs = j;
1240
1241         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1242
1243         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1244             USB_MS_TO_TICKS(timeout_ms));
1245
1246         /*
1247          * In some error cases event interrupts are not generated.
1248          * Poll one time to see if the command has completed.
1249          */
1250         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1251                 DPRINTF("Command was completed when polling\n");
1252                 err = 0;
1253         }
1254         if (err != 0) {
1255                 DPRINTF("Command timeout!\n");
1256                 /*
1257                  * After some weeks of continuous operation, it has
1258                  * been observed that the ASMedia Technology, ASM1042
1259                  * SuperSpeed USB Host Controller can suddenly stop
1260                  * accepting commands via the command queue. Try to
1261                  * first reset the command queue. If that fails do a
1262                  * host controller reset.
1263                  */
1264                 if (timeout == 0 &&
1265                     xhci_reset_command_queue_locked(sc) == 0) {
1266                         temp = le32toh(trb->dwTrb3);
1267
1268                         /*
1269                          * Avoid infinite XHCI reset loops if the set
1270                          * address command fails to respond due to a
1271                          * non-enumerating device:
1272                          */
1273                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1274                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1275                                 DPRINTF("Set address timeout\n");
1276                         } else {
1277                                 timeout = 1;
1278                                 goto retry;
1279                         }
1280                 } else {
1281                         DPRINTF("Controller reset!\n");
1282                         usb_bus_reset_async_locked(&sc->sc_bus);
1283                 }
1284                 err = USB_ERR_TIMEOUT;
1285                 trb->dwTrb2 = 0;
1286                 trb->dwTrb3 = 0;
1287         } else {
1288                 temp = le32toh(sc->sc_cmd_result[0]);
1289                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1290                         err = USB_ERR_IOERROR;
1291
1292                 trb->dwTrb2 = sc->sc_cmd_result[0];
1293                 trb->dwTrb3 = sc->sc_cmd_result[1];
1294         }
1295
1296         USB_BUS_UNLOCK(&sc->sc_bus);
1297
1298         return (err);
1299 }
1300
1301 #if 0
1302 static usb_error_t
1303 xhci_cmd_nop(struct xhci_softc *sc)
1304 {
1305         struct xhci_trb trb;
1306         uint32_t temp;
1307
1308         DPRINTF("\n");
1309
1310         trb.qwTrb0 = 0;
1311         trb.dwTrb2 = 0;
1312         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1313
1314         trb.dwTrb3 = htole32(temp);
1315
1316         return (xhci_do_command(sc, &trb, 100 /* ms */));
1317 }
1318 #endif
1319
1320 static usb_error_t
1321 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1322 {
1323         struct xhci_trb trb;
1324         uint32_t temp;
1325         usb_error_t err;
1326
1327         DPRINTF("\n");
1328
1329         trb.qwTrb0 = 0;
1330         trb.dwTrb2 = 0;
1331         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1332
1333         err = xhci_do_command(sc, &trb, 100 /* ms */);
1334         if (err)
1335                 goto done;
1336
1337         temp = le32toh(trb.dwTrb3);
1338
1339         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1340
1341 done:
1342         return (err);
1343 }
1344
1345 static usb_error_t
1346 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1347 {
1348         struct xhci_trb trb;
1349         uint32_t temp;
1350
1351         DPRINTF("\n");
1352
1353         trb.qwTrb0 = 0;
1354         trb.dwTrb2 = 0;
1355         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1356             XHCI_TRB_3_SLOT_SET(slot_id);
1357
1358         trb.dwTrb3 = htole32(temp);
1359
1360         return (xhci_do_command(sc, &trb, 100 /* ms */));
1361 }
1362
1363 static usb_error_t
1364 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1365     uint8_t bsr, uint8_t slot_id)
1366 {
1367         struct xhci_trb trb;
1368         uint32_t temp;
1369
1370         DPRINTF("\n");
1371
1372         trb.qwTrb0 = htole64(input_ctx);
1373         trb.dwTrb2 = 0;
1374         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1375             XHCI_TRB_3_SLOT_SET(slot_id);
1376
1377         if (bsr)
1378                 temp |= XHCI_TRB_3_BSR_BIT;
1379
1380         trb.dwTrb3 = htole32(temp);
1381
1382         return (xhci_do_command(sc, &trb, 500 /* ms */));
1383 }
1384
1385 static usb_error_t
1386 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1387 {
1388         struct usb_page_search buf_inp;
1389         struct usb_page_search buf_dev;
1390         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1391         struct xhci_hw_dev *hdev;
1392         struct xhci_dev_ctx *pdev;
1393         struct xhci_endpoint_ext *pepext;
1394         uint32_t temp;
1395         uint16_t mps;
1396         usb_error_t err;
1397         uint8_t index;
1398
1399         /* the root HUB case is not handled here */
1400         if (udev->parent_hub == NULL)
1401                 return (USB_ERR_INVAL);
1402
1403         index = udev->controller_slot_id;
1404
1405         hdev =  &sc->sc_hw.devs[index];
1406
1407         if (mtx != NULL)
1408                 mtx_unlock(mtx);
1409
1410         XHCI_CMD_LOCK(sc);
1411
1412         switch (hdev->state) {
1413         case XHCI_ST_DEFAULT:
1414         case XHCI_ST_ENABLED:
1415
1416                 hdev->state = XHCI_ST_ENABLED;
1417
1418                 /* set configure mask to slot and EP0 */
1419                 xhci_configure_mask(udev, 3, 0);
1420
1421                 /* configure input slot context structure */
1422                 err = xhci_configure_device(udev);
1423
1424                 if (err != 0) {
1425                         DPRINTF("Could not configure device\n");
1426                         break;
1427                 }
1428
1429                 /* configure input endpoint context structure */
1430                 switch (udev->speed) {
1431                 case USB_SPEED_LOW:
1432                 case USB_SPEED_FULL:
1433                         mps = 8;
1434                         break;
1435                 case USB_SPEED_HIGH:
1436                         mps = 64;
1437                         break;
1438                 default:
1439                         mps = 512;
1440                         break;
1441                 }
1442
1443                 pepext = xhci_get_endpoint_ext(udev,
1444                     &udev->ctrl_ep_desc);
1445
1446                 /* ensure the control endpoint is setup again */
1447                 USB_BUS_LOCK(udev->bus);
1448                 pepext->trb_halted = 1;
1449                 pepext->trb_running = 0;
1450                 USB_BUS_UNLOCK(udev->bus);
1451
1452                 err = xhci_configure_endpoint(udev,
1453                     &udev->ctrl_ep_desc, pepext,
1454                     0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1455
1456                 if (err != 0) {
1457                         DPRINTF("Could not configure default endpoint\n");
1458                         break;
1459                 }
1460
1461                 /* execute set address command */
1462                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1463
1464                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1465                     (address == 0), index);
1466
1467                 if (err != 0) {
1468                         temp = le32toh(sc->sc_cmd_result[0]);
1469                         if (address == 0 && sc->sc_port_route != NULL &&
1470                             XHCI_TRB_2_ERROR_GET(temp) ==
1471                             XHCI_TRB_ERROR_PARAMETER) {
1472                                 /* LynxPoint XHCI - ports are not switchable */
1473                                 /* Un-route all ports from the XHCI */
1474                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1475                         }
1476                         DPRINTF("Could not set address "
1477                             "for slot %u.\n", index);
1478                         if (address != 0)
1479                                 break;
1480                 }
1481
1482                 /* update device address to new value */
1483
1484                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1485                 pdev = buf_dev.buffer;
1486                 usb_pc_cpu_invalidate(&hdev->device_pc);
1487
1488                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1489                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1490
1491                 /* update device state to new value */
1492
1493                 if (address != 0)
1494                         hdev->state = XHCI_ST_ADDRESSED;
1495                 else
1496                         hdev->state = XHCI_ST_DEFAULT;
1497                 break;
1498
1499         default:
1500                 DPRINTF("Wrong state for set address.\n");
1501                 err = USB_ERR_IOERROR;
1502                 break;
1503         }
1504         XHCI_CMD_UNLOCK(sc);
1505
1506         if (mtx != NULL)
1507                 mtx_lock(mtx);
1508
1509         return (err);
1510 }
1511
1512 static usb_error_t
1513 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1514     uint8_t deconfigure, uint8_t slot_id)
1515 {
1516         struct xhci_trb trb;
1517         uint32_t temp;
1518
1519         DPRINTF("\n");
1520
1521         trb.qwTrb0 = htole64(input_ctx);
1522         trb.dwTrb2 = 0;
1523         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1524             XHCI_TRB_3_SLOT_SET(slot_id);
1525
1526         if (deconfigure)
1527                 temp |= XHCI_TRB_3_DCEP_BIT;
1528
1529         trb.dwTrb3 = htole32(temp);
1530
1531         return (xhci_do_command(sc, &trb, 100 /* ms */));
1532 }
1533
1534 static usb_error_t
1535 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1536     uint8_t slot_id)
1537 {
1538         struct xhci_trb trb;
1539         uint32_t temp;
1540
1541         DPRINTF("\n");
1542
1543         trb.qwTrb0 = htole64(input_ctx);
1544         trb.dwTrb2 = 0;
1545         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1546             XHCI_TRB_3_SLOT_SET(slot_id);
1547         trb.dwTrb3 = htole32(temp);
1548
1549         return (xhci_do_command(sc, &trb, 100 /* ms */));
1550 }
1551
1552 static usb_error_t
1553 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1554     uint8_t ep_id, uint8_t slot_id)
1555 {
1556         struct xhci_trb trb;
1557         uint32_t temp;
1558
1559         DPRINTF("\n");
1560
1561         trb.qwTrb0 = 0;
1562         trb.dwTrb2 = 0;
1563         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1564             XHCI_TRB_3_SLOT_SET(slot_id) |
1565             XHCI_TRB_3_EP_SET(ep_id);
1566
1567         if (preserve)
1568                 temp |= XHCI_TRB_3_PRSV_BIT;
1569
1570         trb.dwTrb3 = htole32(temp);
1571
1572         return (xhci_do_command(sc, &trb, 100 /* ms */));
1573 }
1574
1575 static usb_error_t
1576 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1577     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1578 {
1579         struct xhci_trb trb;
1580         uint32_t temp;
1581
1582         DPRINTF("\n");
1583
1584         trb.qwTrb0 = htole64(dequeue_ptr);
1585
1586         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1587         trb.dwTrb2 = htole32(temp);
1588
1589         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1590             XHCI_TRB_3_SLOT_SET(slot_id) |
1591             XHCI_TRB_3_EP_SET(ep_id);
1592         trb.dwTrb3 = htole32(temp);
1593
1594         return (xhci_do_command(sc, &trb, 100 /* ms */));
1595 }
1596
1597 static usb_error_t
1598 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1599     uint8_t ep_id, uint8_t slot_id)
1600 {
1601         struct usb_page_search buf_dev;
1602         struct xhci_dev_ctx *pdev;
1603         struct xhci_trb trb;
1604         uint32_t temp;
1605
1606         DPRINTF("\n");
1607
1608         usbd_get_page(&sc->sc_hw.devs[slot_id].device_pc, 0, &buf_dev);
1609         pdev = buf_dev.buffer;
1610         usb_pc_cpu_invalidate(&sc->sc_hw.devs[slot_id].device_pc);
1611
1612         switch (XHCI_EPCTX_0_EPSTATE_GET(pdev->ctx_ep[ep_id - 1].dwEpCtx0)) {
1613         case XHCI_EPCTX_0_EPSTATE_DISABLED:
1614         case XHCI_EPCTX_0_EPSTATE_STOPPED:
1615                 DPRINTF("Endpoint %u on slot %u is already stopped\n",
1616                     ep_id, slot_id);
1617                 return (USB_ERR_NORMAL_COMPLETION);
1618         default:
1619                 break;
1620         }
1621
1622         trb.qwTrb0 = 0;
1623         trb.dwTrb2 = 0;
1624         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1625             XHCI_TRB_3_SLOT_SET(slot_id) |
1626             XHCI_TRB_3_EP_SET(ep_id);
1627
1628         if (suspend)
1629                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1630
1631         trb.dwTrb3 = htole32(temp);
1632
1633         return (xhci_do_command(sc, &trb, 100 /* ms */));
1634 }
1635
1636 static usb_error_t
1637 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1638 {
1639         struct xhci_trb trb;
1640         uint32_t temp;
1641
1642         DPRINTF("\n");
1643
1644         trb.qwTrb0 = 0;
1645         trb.dwTrb2 = 0;
1646         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1647             XHCI_TRB_3_SLOT_SET(slot_id);
1648
1649         trb.dwTrb3 = htole32(temp);
1650
1651         return (xhci_do_command(sc, &trb, 100 /* ms */));
1652 }
1653
1654 /*------------------------------------------------------------------------*
1655  *      xhci_interrupt - XHCI interrupt handler
1656  *------------------------------------------------------------------------*/
1657 void
1658 xhci_interrupt(struct xhci_softc *sc)
1659 {
1660         uint32_t status;
1661         uint32_t temp;
1662
1663         USB_BUS_LOCK(&sc->sc_bus);
1664
1665         status = XREAD4(sc, oper, XHCI_USBSTS);
1666
1667         /* acknowledge interrupts, if any */
1668         if (status != 0) {
1669                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1670                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1671         }
1672
1673         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1674
1675         /* force clearing of pending interrupts */
1676         if (temp & XHCI_IMAN_INTR_PEND)
1677                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1678
1679         /* check for event(s) */
1680         xhci_interrupt_poll(sc);
1681
1682         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1683             XHCI_STS_HSE | XHCI_STS_HCE)) {
1684
1685                 if (status & XHCI_STS_PCD) {
1686                         xhci_root_intr(sc);
1687                 }
1688
1689                 if (status & XHCI_STS_HCH) {
1690                         printf("%s: host controller halted\n",
1691                             __FUNCTION__);
1692                 }
1693
1694                 if (status & XHCI_STS_HSE) {
1695                         printf("%s: host system error\n",
1696                             __FUNCTION__);
1697                 }
1698
1699                 if (status & XHCI_STS_HCE) {
1700                         printf("%s: host controller error\n",
1701                            __FUNCTION__);
1702                 }
1703         }
1704         USB_BUS_UNLOCK(&sc->sc_bus);
1705 }
1706
1707 /*------------------------------------------------------------------------*
1708  *      xhci_timeout - XHCI timeout handler
1709  *------------------------------------------------------------------------*/
1710 static void
1711 xhci_timeout(void *arg)
1712 {
1713         struct usb_xfer *xfer = arg;
1714
1715         DPRINTF("xfer=%p\n", xfer);
1716
1717         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1718
1719         /* transfer is transferred */
1720         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1721 }
1722
1723 static void
1724 xhci_do_poll(struct usb_bus *bus)
1725 {
1726         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1727
1728         USB_BUS_LOCK(&sc->sc_bus);
1729         xhci_interrupt_poll(sc);
1730         USB_BUS_UNLOCK(&sc->sc_bus);
1731 }
1732
1733 static void
1734 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1735 {
1736         struct usb_page_search buf_res;
1737         struct xhci_td *td;
1738         struct xhci_td *td_next;
1739         struct xhci_td *td_alt_next;
1740         struct xhci_td *td_first;
1741         uint32_t buf_offset;
1742         uint32_t average;
1743         uint32_t len_old;
1744         uint32_t npkt_off;
1745         uint32_t dword;
1746         uint8_t shortpkt_old;
1747         uint8_t precompute;
1748         uint8_t x;
1749
1750         td_alt_next = NULL;
1751         buf_offset = 0;
1752         shortpkt_old = temp->shortpkt;
1753         len_old = temp->len;
1754         npkt_off = 0;
1755         precompute = 1;
1756
1757 restart:
1758
1759         td = temp->td;
1760         td_next = td_first = temp->td_next;
1761
1762         while (1) {
1763
1764                 if (temp->len == 0) {
1765
1766                         if (temp->shortpkt)
1767                                 break;
1768
1769                         /* send a Zero Length Packet, ZLP, last */
1770
1771                         temp->shortpkt = 1;
1772                         average = 0;
1773
1774                 } else {
1775
1776                         average = temp->average;
1777
1778                         if (temp->len < average) {
1779                                 if (temp->len % temp->max_packet_size) {
1780                                         temp->shortpkt = 1;
1781                                 }
1782                                 average = temp->len;
1783                         }
1784                 }
1785
1786                 if (td_next == NULL)
1787                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1788
1789                 /* get next TD */
1790
1791                 td = td_next;
1792                 td_next = td->obj_next;
1793
1794                 /* check if we are pre-computing */
1795
1796                 if (precompute) {
1797
1798                         /* update remaining length */
1799
1800                         temp->len -= average;
1801
1802                         continue;
1803                 }
1804                 /* fill out current TD */
1805
1806                 td->len = average;
1807                 td->remainder = 0;
1808                 td->status = 0;
1809
1810                 /* update remaining length */
1811
1812                 temp->len -= average;
1813
1814                 /* reset TRB index */
1815
1816                 x = 0;
1817
1818                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1819                         /* immediate data */
1820
1821                         if (average > 8)
1822                                 average = 8;
1823
1824                         td->td_trb[0].qwTrb0 = 0;
1825
1826                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1827                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1828                            average);
1829
1830                         dword = XHCI_TRB_2_BYTES_SET(8) |
1831                             XHCI_TRB_2_TDSZ_SET(0) |
1832                             XHCI_TRB_2_IRQ_SET(0);
1833
1834                         td->td_trb[0].dwTrb2 = htole32(dword);
1835
1836                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1837                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1838
1839                         /* check wLength */
1840                         if (td->td_trb[0].qwTrb0 &
1841                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1842                                 if (td->td_trb[0].qwTrb0 &
1843                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1844                                         dword |= XHCI_TRB_3_TRT_IN;
1845                                 else
1846                                         dword |= XHCI_TRB_3_TRT_OUT;
1847                         }
1848
1849                         td->td_trb[0].dwTrb3 = htole32(dword);
1850 #ifdef USB_DEBUG
1851                         xhci_dump_trb(&td->td_trb[x]);
1852 #endif
1853                         x++;
1854
1855                 } else do {
1856
1857                         uint32_t npkt;
1858
1859                         /* fill out buffer pointers */
1860
1861                         if (average == 0) {
1862                                 memset(&buf_res, 0, sizeof(buf_res));
1863                         } else {
1864                                 usbd_get_page(temp->pc, temp->offset +
1865                                     buf_offset, &buf_res);
1866
1867                                 /* get length to end of page */
1868                                 if (buf_res.length > average)
1869                                         buf_res.length = average;
1870
1871                                 /* check for maximum length */
1872                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1873                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1874
1875                                 npkt_off += buf_res.length;
1876                         }
1877
1878                         /* set up npkt */
1879                         npkt = howmany(len_old - npkt_off,
1880                                        temp->max_packet_size);
1881
1882                         if (npkt == 0)
1883                                 npkt = 1;
1884                         else if (npkt > 31)
1885                                 npkt = 31;
1886
1887                         /* fill out TRB's */
1888                         td->td_trb[x].qwTrb0 =
1889                             htole64((uint64_t)buf_res.physaddr);
1890
1891                         dword =
1892                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1893                           XHCI_TRB_2_TDSZ_SET(npkt) |
1894                           XHCI_TRB_2_IRQ_SET(0);
1895
1896                         td->td_trb[x].dwTrb2 = htole32(dword);
1897
1898                         switch (temp->trb_type) {
1899                         case XHCI_TRB_TYPE_ISOCH:
1900                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1901                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1902                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1903                                 if (td != td_first) {
1904                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1905                                 } else if (temp->do_isoc_sync != 0) {
1906                                         temp->do_isoc_sync = 0;
1907                                         /* wait until "isoc_frame" */
1908                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1909                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1910                                 } else {
1911                                         /* start data transfer at next interval */
1912                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1913                                             XHCI_TRB_3_ISO_SIA_BIT;
1914                                 }
1915                                 if (temp->direction == UE_DIR_IN)
1916                                         dword |= XHCI_TRB_3_ISP_BIT;
1917                                 break;
1918                         case XHCI_TRB_TYPE_DATA_STAGE:
1919                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1920                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1921                                 if (temp->direction == UE_DIR_IN)
1922                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1923                                 /*
1924                                  * Section 3.2.9 in the XHCI
1925                                  * specification about control
1926                                  * transfers says that we should use a
1927                                  * normal-TRB if there are more TRBs
1928                                  * extending the data-stage
1929                                  * TRB. Update the "trb_type".
1930                                  */
1931                                 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1932                                 break;
1933                         case XHCI_TRB_TYPE_STATUS_STAGE:
1934                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1935                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1936                                 if (temp->direction == UE_DIR_IN)
1937                                         dword |= XHCI_TRB_3_DIR_IN;
1938                                 break;
1939                         default:        /* XHCI_TRB_TYPE_NORMAL */
1940                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1941                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1942                                 if (temp->direction == UE_DIR_IN)
1943                                         dword |= XHCI_TRB_3_ISP_BIT;
1944                                 break;
1945                         }
1946                         td->td_trb[x].dwTrb3 = htole32(dword);
1947
1948                         average -= buf_res.length;
1949                         buf_offset += buf_res.length;
1950 #ifdef USB_DEBUG
1951                         xhci_dump_trb(&td->td_trb[x]);
1952 #endif
1953                         x++;
1954
1955                 } while (average != 0);
1956
1957                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1958
1959                 /* store number of data TRB's */
1960
1961                 td->ntrb = x;
1962
1963                 DPRINTF("NTRB=%u\n", x);
1964
1965                 /* fill out link TRB */
1966
1967                 if (td_next != NULL) {
1968                         /* link the current TD with the next one */
1969                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1970                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1971                 } else {
1972                         /* this field will get updated later */
1973                         DPRINTF("NOLINK\n");
1974                 }
1975
1976                 dword = XHCI_TRB_2_IRQ_SET(0);
1977
1978                 td->td_trb[x].dwTrb2 = htole32(dword);
1979
1980                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1981                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1982                     /*
1983                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1984                      * frame only receives a single short packet event
1985                      * by setting the CHAIN bit in the LINK field. In
1986                      * addition some XHCI controllers have problems
1987                      * sending a ZLP unless the CHAIN-BIT is set in
1988                      * the LINK TRB.
1989                      */
1990                     XHCI_TRB_3_CHAIN_BIT;
1991
1992                 td->td_trb[x].dwTrb3 = htole32(dword);
1993
1994                 td->alt_next = td_alt_next;
1995 #ifdef USB_DEBUG
1996                 xhci_dump_trb(&td->td_trb[x]);
1997 #endif
1998                 usb_pc_cpu_flush(td->page_cache);
1999         }
2000
2001         if (precompute) {
2002                 precompute = 0;
2003
2004                 /* set up alt next pointer, if any */
2005                 if (temp->last_frame) {
2006                         td_alt_next = NULL;
2007                 } else {
2008                         /* we use this field internally */
2009                         td_alt_next = td_next;
2010                 }
2011
2012                 /* restore */
2013                 temp->shortpkt = shortpkt_old;
2014                 temp->len = len_old;
2015                 goto restart;
2016         }
2017
2018         /*
2019          * Remove cycle bit from the first TRB if we are
2020          * stepping them:
2021          */
2022         if (temp->step_td != 0) {
2023                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
2024                 usb_pc_cpu_flush(td_first->page_cache);
2025         }
2026
2027         /* clear TD SIZE to zero, hence this is the last TRB */
2028         /* remove chain bit because this is the last data TRB in the chain */
2029         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31));
2030         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2031         /* remove CHAIN-BIT from last LINK TRB */
2032         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2033
2034         usb_pc_cpu_flush(td->page_cache);
2035
2036         temp->td = td;
2037         temp->td_next = td_next;
2038 }
2039
2040 static void
2041 xhci_setup_generic_chain(struct usb_xfer *xfer)
2042 {
2043         struct xhci_std_temp temp;
2044         struct xhci_td *td;
2045         uint32_t x;
2046         uint32_t y;
2047         uint8_t mult;
2048
2049         temp.do_isoc_sync = 0;
2050         temp.step_td = 0;
2051         temp.tbc = 0;
2052         temp.tlbpc = 0;
2053         temp.average = xfer->max_hc_frame_size;
2054         temp.max_packet_size = xfer->max_packet_size;
2055         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2056         temp.pc = NULL;
2057         temp.last_frame = 0;
2058         temp.offset = 0;
2059         temp.multishort = xfer->flags_int.isochronous_xfr ||
2060             xfer->flags_int.control_xfr ||
2061             xfer->flags_int.short_frames_ok;
2062
2063         /* toggle the DMA set we are using */
2064         xfer->flags_int.curr_dma_set ^= 1;
2065
2066         /* get next DMA set */
2067         td = xfer->td_start[xfer->flags_int.curr_dma_set];
2068
2069         temp.td = NULL;
2070         temp.td_next = td;
2071
2072         xfer->td_transfer_first = td;
2073         xfer->td_transfer_cache = td;
2074
2075         if (xfer->flags_int.isochronous_xfr) {
2076                 uint8_t shift;
2077
2078                 /* compute multiplier for ISOCHRONOUS transfers */
2079                 mult = xfer->endpoint->ecomp ?
2080                     UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2081                     : 0;
2082                 /* check for USB 2.0 multiplier */
2083                 if (mult == 0) {
2084                         mult = (xfer->endpoint->edesc->
2085                             wMaxPacketSize[1] >> 3) & 3;
2086                 }
2087                 /* range check */
2088                 if (mult > 2)
2089                         mult = 3;
2090                 else
2091                         mult++;
2092
2093                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2094
2095                 DPRINTF("MFINDEX=0x%08x\n", x);
2096
2097                 switch (usbd_get_speed(xfer->xroot->udev)) {
2098                 case USB_SPEED_FULL:
2099                         shift = 3;
2100                         temp.isoc_delta = 8;    /* 1ms */
2101                         x += temp.isoc_delta - 1;
2102                         x &= ~(temp.isoc_delta - 1);
2103                         break;
2104                 default:
2105                         shift = usbd_xfer_get_fps_shift(xfer);
2106                         temp.isoc_delta = 1U << shift;
2107                         x += temp.isoc_delta - 1;
2108                         x &= ~(temp.isoc_delta - 1);
2109                         /* simple frame load balancing */
2110                         x += xfer->endpoint->usb_uframe;
2111                         break;
2112                 }
2113
2114                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2115
2116                 if ((xfer->endpoint->is_synced == 0) ||
2117                     (y < (xfer->nframes << shift)) ||
2118                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2119                         /*
2120                          * If there is data underflow or the pipe
2121                          * queue is empty we schedule the transfer a
2122                          * few frames ahead of the current frame
2123                          * position. Else two isochronous transfers
2124                          * might overlap.
2125                          */
2126                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2127                         xfer->endpoint->is_synced = 1;
2128                         temp.do_isoc_sync = 1;
2129
2130                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2131                 }
2132
2133                 /* compute isochronous completion time */
2134
2135                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2136
2137                 xfer->isoc_time_complete =
2138                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2139                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2140
2141                 x = 0;
2142                 temp.isoc_frame = xfer->endpoint->isoc_next;
2143                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2144
2145                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2146
2147         } else if (xfer->flags_int.control_xfr) {
2148
2149                 /* check if we should prepend a setup message */
2150
2151                 if (xfer->flags_int.control_hdr) {
2152
2153                         temp.len = xfer->frlengths[0];
2154                         temp.pc = xfer->frbuffers + 0;
2155                         temp.shortpkt = temp.len ? 1 : 0;
2156                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2157                         temp.direction = 0;
2158
2159                         /* check for last frame */
2160                         if (xfer->nframes == 1) {
2161                                 /* no STATUS stage yet, SETUP is last */
2162                                 if (xfer->flags_int.control_act)
2163                                         temp.last_frame = 1;
2164                         }
2165
2166                         xhci_setup_generic_chain_sub(&temp);
2167                 }
2168                 x = 1;
2169                 mult = 1;
2170                 temp.isoc_delta = 0;
2171                 temp.isoc_frame = 0;
2172                 temp.trb_type = xfer->flags_int.control_did_data ?
2173                     XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2174         } else {
2175                 x = 0;
2176                 mult = 1;
2177                 temp.isoc_delta = 0;
2178                 temp.isoc_frame = 0;
2179                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2180         }
2181
2182         if (x != xfer->nframes) {
2183                 /* set up page_cache pointer */
2184                 temp.pc = xfer->frbuffers + x;
2185                 /* set endpoint direction */
2186                 temp.direction = UE_GET_DIR(xfer->endpointno);
2187         }
2188
2189         while (x != xfer->nframes) {
2190
2191                 /* DATA0 / DATA1 message */
2192
2193                 temp.len = xfer->frlengths[x];
2194                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2195                     x != 0 && temp.multishort == 0);
2196
2197                 x++;
2198
2199                 if (x == xfer->nframes) {
2200                         if (xfer->flags_int.control_xfr) {
2201                                 /* no STATUS stage yet, DATA is last */
2202                                 if (xfer->flags_int.control_act)
2203                                         temp.last_frame = 1;
2204                         } else {
2205                                 temp.last_frame = 1;
2206                         }
2207                 }
2208                 if (temp.len == 0) {
2209
2210                         /* make sure that we send an USB packet */
2211
2212                         temp.shortpkt = 0;
2213
2214                         temp.tbc = 0;
2215                         temp.tlbpc = mult - 1;
2216
2217                 } else if (xfer->flags_int.isochronous_xfr) {
2218
2219                         uint8_t tdpc;
2220
2221                         /*
2222                          * Isochronous transfers don't have short
2223                          * packet termination:
2224                          */
2225
2226                         temp.shortpkt = 1;
2227
2228                         /* isochronous transfers have a transfer limit */
2229
2230                         if (temp.len > xfer->max_frame_size)
2231                                 temp.len = xfer->max_frame_size;
2232
2233                         /* compute TD packet count */
2234                         tdpc = howmany(temp.len, xfer->max_packet_size);
2235
2236                         temp.tbc = howmany(tdpc, mult) - 1;
2237                         temp.tlbpc = (tdpc % mult);
2238
2239                         if (temp.tlbpc == 0)
2240                                 temp.tlbpc = mult - 1;
2241                         else
2242                                 temp.tlbpc--;
2243                 } else {
2244
2245                         /* regular data transfer */
2246
2247                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2248                 }
2249
2250                 xhci_setup_generic_chain_sub(&temp);
2251
2252                 if (xfer->flags_int.isochronous_xfr) {
2253                         temp.offset += xfer->frlengths[x - 1];
2254                         temp.isoc_frame += temp.isoc_delta;
2255                 } else {
2256                         /* get next Page Cache pointer */
2257                         temp.pc = xfer->frbuffers + x;
2258                 }
2259         }
2260
2261         /* check if we should append a status stage */
2262
2263         if (xfer->flags_int.control_xfr &&
2264             !xfer->flags_int.control_act) {
2265
2266                 /*
2267                  * Send a DATA1 message and invert the current
2268                  * endpoint direction.
2269                  */
2270                 if (xhcictlstep || temp.sc->sc_ctlstep) {
2271                         /*
2272                          * Some XHCI controllers will not delay the
2273                          * status stage until the next SOF. Force this
2274                          * behaviour to avoid failed control
2275                          * transfers.
2276                          */
2277                         temp.step_td = (xfer->nframes != 0);
2278                 } else {
2279                         temp.step_td = 0;
2280                 }
2281                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2282                 temp.len = 0;
2283                 temp.pc = NULL;
2284                 temp.shortpkt = 0;
2285                 temp.last_frame = 1;
2286                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2287
2288                 xhci_setup_generic_chain_sub(&temp);
2289         }
2290
2291         td = temp.td;
2292
2293         /* must have at least one frame! */
2294
2295         xfer->td_transfer_last = td;
2296
2297         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2298 }
2299
2300 static void
2301 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2302 {
2303         struct usb_page_search buf_res;
2304         struct xhci_dev_ctx_addr *pdctxa;
2305
2306         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2307
2308         pdctxa = buf_res.buffer;
2309
2310         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2311
2312         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2313
2314         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2315 }
2316
2317 static usb_error_t
2318 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2319 {
2320         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2321         struct usb_page_search buf_inp;
2322         struct xhci_input_dev_ctx *pinp;
2323         uint32_t temp;
2324         uint8_t index;
2325         uint8_t x;
2326
2327         index = udev->controller_slot_id;
2328
2329         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2330
2331         pinp = buf_inp.buffer;
2332
2333         if (drop) {
2334                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2335                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2336                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2337         } else {
2338                 /*
2339                  * Some hardware requires that we drop the endpoint
2340                  * context before adding it again:
2341                  */
2342                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2343                     mask & XHCI_INCTX_NON_CTRL_MASK);
2344
2345                 /* Add new endpoint context */
2346                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2347
2348                 /* find most significant set bit */
2349                 for (x = 31; x != 1; x--) {
2350                         if (mask & (1 << x))
2351                                 break;
2352                 }
2353
2354                 /* adjust */
2355                 x--;
2356
2357                 /* figure out the maximum number of contexts */
2358                 if (x > sc->sc_hw.devs[index].context_num)
2359                         sc->sc_hw.devs[index].context_num = x;
2360                 else
2361                         x = sc->sc_hw.devs[index].context_num;
2362
2363                 /* update number of contexts */
2364                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2365                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2366                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2367                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2368         }
2369         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2370         return (0);
2371 }
2372
2373 static usb_error_t
2374 xhci_configure_endpoint(struct usb_device *udev,
2375     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2376     uint16_t interval, uint8_t max_packet_count,
2377     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2378     uint16_t max_frame_size, uint8_t ep_mode)
2379 {
2380         struct usb_page_search buf_inp;
2381         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2382         struct xhci_input_dev_ctx *pinp;
2383         uint64_t ring_addr = pepext->physaddr;
2384         uint32_t temp;
2385         uint8_t index;
2386         uint8_t epno;
2387         uint8_t type;
2388
2389         index = udev->controller_slot_id;
2390
2391         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2392
2393         pinp = buf_inp.buffer;
2394
2395         epno = edesc->bEndpointAddress;
2396         type = edesc->bmAttributes & UE_XFERTYPE;
2397
2398         if (type == UE_CONTROL)
2399                 epno |= UE_DIR_IN;
2400
2401         epno = XHCI_EPNO2EPID(epno);
2402
2403         if (epno == 0)
2404                 return (USB_ERR_NO_PIPE);               /* invalid */
2405
2406         if (max_packet_count == 0)
2407                 return (USB_ERR_BAD_BUFSIZE);
2408
2409         max_packet_count--;
2410
2411         if (mult == 0)
2412                 return (USB_ERR_BAD_BUFSIZE);
2413
2414         /* store endpoint mode */
2415         pepext->trb_ep_mode = ep_mode;
2416         /* store bMaxPacketSize for control endpoints */
2417         pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2418         usb_pc_cpu_flush(pepext->page_cache);
2419
2420         if (ep_mode == USB_EP_MODE_STREAMS) {
2421                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2422                     XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2423                     XHCI_EPCTX_0_LSA_SET(1);
2424
2425                 ring_addr += sizeof(struct xhci_trb) *
2426                     XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2427         } else {
2428                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2429                     XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2430                     XHCI_EPCTX_0_LSA_SET(0);
2431
2432                 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2433         }
2434
2435         switch (udev->speed) {
2436         case USB_SPEED_FULL:
2437         case USB_SPEED_LOW:
2438                 /* 1ms -> 125us */
2439                 fps_shift += 3;
2440                 break;
2441         default:
2442                 break;
2443         }
2444
2445         switch (type) {
2446         case UE_INTERRUPT:
2447                 if (fps_shift > 3)
2448                         fps_shift--;
2449                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2450                 break;
2451         case UE_ISOCHRONOUS:
2452                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2453
2454                 switch (udev->speed) {
2455                 case USB_SPEED_SUPER:
2456                         if (mult > 3)
2457                                 mult = 3;
2458                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2459                         max_packet_count /= mult;
2460                         break;
2461                 default:
2462                         break;
2463                 }
2464                 break;
2465         default:
2466                 break;
2467         }
2468
2469         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2470
2471         temp =
2472             XHCI_EPCTX_1_HID_SET(0) |
2473             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2474             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2475
2476         /*
2477          * Always enable the "three strikes and you are gone" feature
2478          * except for ISOCHRONOUS endpoints. This is suggested by
2479          * section 4.3.3 in the XHCI specification about device slot
2480          * initialisation.
2481          */
2482         if (type != UE_ISOCHRONOUS)
2483                 temp |= XHCI_EPCTX_1_CERR_SET(3);
2484
2485         switch (type) {
2486         case UE_CONTROL:
2487                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2488                 break;
2489         case UE_ISOCHRONOUS:
2490                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2491                 break;
2492         case UE_BULK:
2493                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2494                 break;
2495         default:
2496                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2497                 break;
2498         }
2499
2500         /* check for IN direction */
2501         if (epno & 1)
2502                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2503
2504         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2505         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2506
2507         switch (edesc->bmAttributes & UE_XFERTYPE) {
2508         case UE_INTERRUPT:
2509         case UE_ISOCHRONOUS:
2510                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2511                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2512                     max_frame_size));
2513                 break;
2514         case UE_CONTROL:
2515                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2516                 break;
2517         default:
2518                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2519                 break;
2520         }
2521
2522         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2523
2524 #ifdef USB_DEBUG
2525         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2526 #endif
2527         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2528
2529         return (0);             /* success */
2530 }
2531
2532 static usb_error_t
2533 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2534 {
2535         struct xhci_endpoint_ext *pepext;
2536         struct usb_endpoint_ss_comp_descriptor *ecomp;
2537         usb_stream_t x;
2538
2539         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2540             xfer->endpoint->edesc);
2541
2542         ecomp = xfer->endpoint->ecomp;
2543
2544         for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2545                 uint64_t temp;
2546
2547                 /* halt any transfers */
2548                 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2549
2550                 /* compute start of TRB ring for stream "x" */
2551                 temp = pepext->physaddr +
2552                     (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2553                     XHCI_SCTX_0_SCT_SEC_TR_RING;
2554
2555                 /* make tree structure */
2556                 pepext->trb[(XHCI_MAX_TRANSFERS *
2557                     XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2558
2559                 /* reserved fields */
2560                 pepext->trb[(XHCI_MAX_TRANSFERS *
2561                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2562                 pepext->trb[(XHCI_MAX_TRANSFERS *
2563                     XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2564         }
2565         usb_pc_cpu_flush(pepext->page_cache);
2566
2567         return (xhci_configure_endpoint(xfer->xroot->udev,
2568             xfer->endpoint->edesc, pepext,
2569             xfer->interval, xfer->max_packet_count,
2570             (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2571             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2572             xfer->max_frame_size, xfer->endpoint->ep_mode));
2573 }
2574
2575 static usb_error_t
2576 xhci_configure_device(struct usb_device *udev)
2577 {
2578         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2579         struct usb_page_search buf_inp;
2580         struct usb_page_cache *pcinp;
2581         struct xhci_input_dev_ctx *pinp;
2582         struct usb_device *hubdev;
2583         uint32_t temp;
2584         uint32_t route;
2585         uint32_t rh_port;
2586         uint8_t is_hub;
2587         uint8_t index;
2588         uint8_t depth;
2589
2590         index = udev->controller_slot_id;
2591
2592         DPRINTF("index=%u\n", index);
2593
2594         pcinp = &sc->sc_hw.devs[index].input_pc;
2595
2596         usbd_get_page(pcinp, 0, &buf_inp);
2597
2598         pinp = buf_inp.buffer;
2599
2600         rh_port = 0;
2601         route = 0;
2602
2603         /* figure out route string and root HUB port number */
2604
2605         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2606
2607                 if (hubdev->parent_hub == NULL)
2608                         break;
2609
2610                 depth = hubdev->parent_hub->depth;
2611
2612                 /*
2613                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2614                  * more than 15 ports
2615                  */
2616
2617                 rh_port = hubdev->port_no;
2618
2619                 if (depth == 0)
2620                         break;
2621
2622                 if (rh_port > 15)
2623                         rh_port = 15;
2624
2625                 if (depth < 6)
2626                         route |= rh_port << (4 * (depth - 1));
2627         }
2628
2629         DPRINTF("Route=0x%08x\n", route);
2630
2631         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2632             XHCI_SCTX_0_CTX_NUM_SET(
2633             sc->sc_hw.devs[index].context_num + 1);
2634
2635         switch (udev->speed) {
2636         case USB_SPEED_LOW:
2637                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2638                 if (udev->parent_hs_hub != NULL &&
2639                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2640                     UDPROTO_HSHUBMTT) {
2641                         DPRINTF("Device inherits MTT\n");
2642                         temp |= XHCI_SCTX_0_MTT_SET(1);
2643                 }
2644                 break;
2645         case USB_SPEED_HIGH:
2646                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2647                 if (sc->sc_hw.devs[index].nports != 0 &&
2648                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2649                         DPRINTF("HUB supports MTT\n");
2650                         temp |= XHCI_SCTX_0_MTT_SET(1);
2651                 }
2652                 break;
2653         case USB_SPEED_FULL:
2654                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2655                 if (udev->parent_hs_hub != NULL &&
2656                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2657                     UDPROTO_HSHUBMTT) {
2658                         DPRINTF("Device inherits MTT\n");
2659                         temp |= XHCI_SCTX_0_MTT_SET(1);
2660                 }
2661                 break;
2662         default:
2663                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2664                 break;
2665         }
2666
2667         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2668             (udev->speed == USB_SPEED_SUPER ||
2669             udev->speed == USB_SPEED_HIGH);
2670
2671         if (is_hub)
2672                 temp |= XHCI_SCTX_0_HUB_SET(1);
2673
2674         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2675
2676         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2677
2678         if (is_hub) {
2679                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2680                     sc->sc_hw.devs[index].nports);
2681         }
2682
2683         switch (udev->speed) {
2684         case USB_SPEED_SUPER:
2685                 switch (sc->sc_hw.devs[index].state) {
2686                 case XHCI_ST_ADDRESSED:
2687                 case XHCI_ST_CONFIGURED:
2688                         /* enable power save */
2689                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2690                         break;
2691                 default:
2692                         /* disable power save */
2693                         break;
2694                 }
2695                 break;
2696         default:
2697                 break;
2698         }
2699
2700         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2701
2702         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2703
2704         if (is_hub) {
2705                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2706                     sc->sc_hw.devs[index].tt);
2707         }
2708
2709         hubdev = udev->parent_hs_hub;
2710
2711         /* check if we should activate the transaction translator */
2712         switch (udev->speed) {
2713         case USB_SPEED_FULL:
2714         case USB_SPEED_LOW:
2715                 if (hubdev != NULL) {
2716                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2717                             hubdev->controller_slot_id);
2718                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2719                             udev->hs_port_no);
2720                 }
2721                 break;
2722         default:
2723                 break;
2724         }
2725
2726         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2727
2728         /*
2729          * These fields should be initialized to zero, according to
2730          * XHCI section 6.2.2 - slot context:
2731          */
2732         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2733             XHCI_SCTX_3_SLOT_STATE_SET(0);
2734
2735         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2736
2737 #ifdef USB_DEBUG
2738         xhci_dump_device(sc, &pinp->ctx_slot);
2739 #endif
2740         usb_pc_cpu_flush(pcinp);
2741
2742         return (0);             /* success */
2743 }
2744
2745 static usb_error_t
2746 xhci_alloc_device_ext(struct usb_device *udev)
2747 {
2748         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2749         struct usb_page_search buf_dev;
2750         struct usb_page_search buf_ep;
2751         struct xhci_trb *trb;
2752         struct usb_page_cache *pc;
2753         struct usb_page *pg;
2754         uint64_t addr;
2755         uint8_t index;
2756         uint8_t i;
2757
2758         index = udev->controller_slot_id;
2759
2760         pc = &sc->sc_hw.devs[index].device_pc;
2761         pg = &sc->sc_hw.devs[index].device_pg;
2762
2763         /* need to initialize the page cache */
2764         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2765
2766         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2767             (2 * sizeof(struct xhci_dev_ctx)) :
2768             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2769                 goto error;
2770
2771         usbd_get_page(pc, 0, &buf_dev);
2772
2773         pc = &sc->sc_hw.devs[index].input_pc;
2774         pg = &sc->sc_hw.devs[index].input_pg;
2775
2776         /* need to initialize the page cache */
2777         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2778
2779         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2780             (2 * sizeof(struct xhci_input_dev_ctx)) :
2781             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2782                 goto error;
2783         }
2784
2785         /* initialize all endpoint LINK TRBs */
2786
2787         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2788
2789                 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2790                 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2791
2792                 /* need to initialize the page cache */
2793                 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2794
2795                 if (usb_pc_alloc_mem(pc, pg,
2796                     sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2797                         goto error;
2798                 }
2799
2800                 /* lookup endpoint TRB ring */
2801                 usbd_get_page(pc, 0, &buf_ep);
2802
2803                 /* get TRB pointer */
2804                 trb = buf_ep.buffer;
2805                 trb += XHCI_MAX_TRANSFERS - 1;
2806
2807                 /* get TRB start address */
2808                 addr = buf_ep.physaddr;
2809
2810                 /* create LINK TRB */
2811                 trb->qwTrb0 = htole64(addr);
2812                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2813                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2814                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2815
2816                 usb_pc_cpu_flush(pc);
2817         }
2818
2819         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2820
2821         return (0);
2822
2823 error:
2824         xhci_free_device_ext(udev);
2825
2826         return (USB_ERR_NOMEM);
2827 }
2828
2829 static void
2830 xhci_free_device_ext(struct usb_device *udev)
2831 {
2832         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2833         uint8_t index;
2834         uint8_t i;
2835
2836         index = udev->controller_slot_id;
2837         xhci_set_slot_pointer(sc, index, 0);
2838
2839         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2840         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2841         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2842                 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2843 }
2844
2845 static struct xhci_endpoint_ext *
2846 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2847 {
2848         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2849         struct xhci_endpoint_ext *pepext;
2850         struct usb_page_cache *pc;
2851         struct usb_page_search buf_ep;
2852         uint8_t epno;
2853         uint8_t index;
2854
2855         epno = edesc->bEndpointAddress;
2856         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2857                 epno |= UE_DIR_IN;
2858
2859         epno = XHCI_EPNO2EPID(epno);
2860
2861         index = udev->controller_slot_id;
2862
2863         pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2864
2865         usbd_get_page(pc, 0, &buf_ep);
2866
2867         pepext = &sc->sc_hw.devs[index].endp[epno];
2868         pepext->page_cache = pc;
2869         pepext->trb = buf_ep.buffer;
2870         pepext->physaddr = buf_ep.physaddr;
2871
2872         return (pepext);
2873 }
2874
2875 static void
2876 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2877 {
2878         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2879         uint8_t epno;
2880         uint8_t index;
2881
2882         epno = xfer->endpointno;
2883         if (xfer->flags_int.control_xfr)
2884                 epno |= UE_DIR_IN;
2885
2886         epno = XHCI_EPNO2EPID(epno);
2887         index = xfer->xroot->udev->controller_slot_id;
2888
2889         if (xfer->xroot->udev->flags.self_suspended == 0) {
2890                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2891                     epno | XHCI_DB_SID_SET(xfer->stream_id));
2892         }
2893 }
2894
2895 static void
2896 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2897 {
2898         struct xhci_endpoint_ext *pepext;
2899
2900         if (xfer->flags_int.bandwidth_reclaimed) {
2901                 xfer->flags_int.bandwidth_reclaimed = 0;
2902
2903                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2904                     xfer->endpoint->edesc);
2905
2906                 pepext->trb_used[xfer->stream_id]--;
2907
2908                 pepext->xfer[xfer->qh_pos] = NULL;
2909
2910                 if (error && pepext->trb_running != 0) {
2911                         pepext->trb_halted = 1;
2912                         pepext->trb_running = 0;
2913                 }
2914         }
2915 }
2916
2917 static usb_error_t
2918 xhci_transfer_insert(struct usb_xfer *xfer)
2919 {
2920         struct xhci_td *td_first;
2921         struct xhci_td *td_last;
2922         struct xhci_trb *trb_link;
2923         struct xhci_endpoint_ext *pepext;
2924         uint64_t addr;
2925         usb_stream_t id;
2926         uint8_t i;
2927         uint8_t inext;
2928         uint8_t trb_limit;
2929
2930         DPRINTFN(8, "\n");
2931
2932         id = xfer->stream_id;
2933
2934         /* check if already inserted */
2935         if (xfer->flags_int.bandwidth_reclaimed) {
2936                 DPRINTFN(8, "Already in schedule\n");
2937                 return (0);
2938         }
2939
2940         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2941             xfer->endpoint->edesc);
2942
2943         td_first = xfer->td_transfer_first;
2944         td_last = xfer->td_transfer_last;
2945         addr = pepext->physaddr;
2946
2947         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2948         case UE_CONTROL:
2949         case UE_INTERRUPT:
2950                 /* single buffered */
2951                 trb_limit = 1;
2952                 break;
2953         default:
2954                 /* multi buffered */
2955                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2956                 break;
2957         }
2958
2959         if (pepext->trb_used[id] >= trb_limit) {
2960                 DPRINTFN(8, "Too many TDs queued.\n");
2961                 return (USB_ERR_NOMEM);
2962         }
2963
2964         /* check if bMaxPacketSize changed */
2965         if (xfer->flags_int.control_xfr != 0 &&
2966             pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2967
2968                 DPRINTFN(8, "Reconfigure control endpoint\n");
2969
2970                 /* force driver to reconfigure endpoint */
2971                 pepext->trb_halted = 1;
2972                 pepext->trb_running = 0;
2973         }
2974
2975         /* check for stopped condition, after putting transfer on interrupt queue */
2976         if (pepext->trb_running == 0) {
2977                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2978
2979                 DPRINTFN(8, "Not running\n");
2980
2981                 /* start configuration */
2982                 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2983                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2984                 return (0);
2985         }
2986
2987         pepext->trb_used[id]++;
2988
2989         /* get current TRB index */
2990         i = pepext->trb_index[id];
2991
2992         /* get next TRB index */
2993         inext = (i + 1);
2994
2995         /* the last entry of the ring is a hardcoded link TRB */
2996         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2997                 inext = 0;
2998
2999         /* store next TRB index, before stream ID offset is added */
3000         pepext->trb_index[id] = inext;
3001
3002         /* offset for stream */
3003         i += id * XHCI_MAX_TRANSFERS;
3004         inext += id * XHCI_MAX_TRANSFERS;
3005
3006         /* compute terminating return address */
3007         addr += (inext * sizeof(struct xhci_trb));
3008
3009         /* compute link TRB pointer */
3010         trb_link = td_last->td_trb + td_last->ntrb;
3011
3012         /* update next pointer of last link TRB */
3013         trb_link->qwTrb0 = htole64(addr);
3014         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3015         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
3016             XHCI_TRB_3_CYCLE_BIT |
3017             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3018
3019 #ifdef USB_DEBUG
3020         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
3021 #endif
3022         usb_pc_cpu_flush(td_last->page_cache);
3023
3024         /* write ahead chain end marker */
3025
3026         pepext->trb[inext].qwTrb0 = 0;
3027         pepext->trb[inext].dwTrb2 = 0;
3028         pepext->trb[inext].dwTrb3 = 0;
3029
3030         /* update next pointer of link TRB */
3031
3032         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
3033         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3034
3035 #ifdef USB_DEBUG
3036         xhci_dump_trb(&pepext->trb[i]);
3037 #endif
3038         usb_pc_cpu_flush(pepext->page_cache);
3039
3040         /* toggle cycle bit which activates the transfer chain */
3041
3042         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
3043             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3044
3045         usb_pc_cpu_flush(pepext->page_cache);
3046
3047         DPRINTF("qh_pos = %u\n", i);
3048
3049         pepext->xfer[i] = xfer;
3050
3051         xfer->qh_pos = i;
3052
3053         xfer->flags_int.bandwidth_reclaimed = 1;
3054
3055         xhci_endpoint_doorbell(xfer);
3056
3057         return (0);
3058 }
3059
3060 static void
3061 xhci_root_intr(struct xhci_softc *sc)
3062 {
3063         uint16_t i;
3064
3065         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3066
3067         /* clear any old interrupt data */
3068         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3069
3070         for (i = 1; i <= sc->sc_noport; i++) {
3071                 /* pick out CHANGE bits from the status register */
3072                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3073                     XHCI_PS_CSC | XHCI_PS_PEC |
3074                     XHCI_PS_OCC | XHCI_PS_WRC |
3075                     XHCI_PS_PRC | XHCI_PS_PLC |
3076                     XHCI_PS_CEC)) {
3077                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3078                         DPRINTF("port %d changed\n", i);
3079                 }
3080         }
3081         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3082             sizeof(sc->sc_hub_idata));
3083 }
3084
3085 /*------------------------------------------------------------------------*
3086  *      xhci_device_done - XHCI done handler
3087  *
3088  * NOTE: This function can be called two times in a row on
3089  * the same USB transfer. From close and from interrupt.
3090  *------------------------------------------------------------------------*/
3091 static void
3092 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3093 {
3094         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3095             xfer, xfer->endpoint, error);
3096
3097         /* remove transfer from HW queue */
3098         xhci_transfer_remove(xfer, error);
3099
3100         /* dequeue transfer and start next transfer */
3101         usbd_transfer_done(xfer, error);
3102 }
3103
3104 /*------------------------------------------------------------------------*
3105  * XHCI data transfer support (generic type)
3106  *------------------------------------------------------------------------*/
3107 static void
3108 xhci_device_generic_open(struct usb_xfer *xfer)
3109 {
3110         if (xfer->flags_int.isochronous_xfr) {
3111                 switch (xfer->xroot->udev->speed) {
3112                 case USB_SPEED_FULL:
3113                         break;
3114                 default:
3115                         usb_hs_bandwidth_alloc(xfer);
3116                         break;
3117                 }
3118         }
3119 }
3120
3121 static void
3122 xhci_device_generic_close(struct usb_xfer *xfer)
3123 {
3124         DPRINTF("\n");
3125
3126         xhci_device_done(xfer, USB_ERR_CANCELLED);
3127
3128         if (xfer->flags_int.isochronous_xfr) {
3129                 switch (xfer->xroot->udev->speed) {
3130                 case USB_SPEED_FULL:
3131                         break;
3132                 default:
3133                         usb_hs_bandwidth_free(xfer);
3134                         break;
3135                 }
3136         }
3137 }
3138
3139 static void
3140 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3141     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3142 {
3143         struct usb_xfer *xfer;
3144
3145         /* check if there is a current transfer */
3146         xfer = ep->endpoint_q[stream_id].curr;
3147         if (xfer == NULL)
3148                 return;
3149
3150         /*
3151          * Check if the current transfer is started and then pickup
3152          * the next one, if any. Else wait for next start event due to
3153          * block on failure feature.
3154          */
3155         if (!xfer->flags_int.bandwidth_reclaimed)
3156                 return;
3157
3158         xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3159         if (xfer == NULL) {
3160                 /*
3161                  * In case of enter we have to consider that the
3162                  * transfer is queued by the USB core after the enter
3163                  * method is called.
3164                  */
3165                 xfer = enter_xfer;
3166
3167                 if (xfer == NULL)
3168                         return;
3169         }
3170
3171         /* try to multi buffer */
3172         xhci_transfer_insert(xfer);
3173 }
3174
3175 static void
3176 xhci_device_generic_enter(struct usb_xfer *xfer)
3177 {
3178         DPRINTF("\n");
3179
3180         /* set up TD's and QH */
3181         xhci_setup_generic_chain(xfer);
3182
3183         xhci_device_generic_multi_enter(xfer->endpoint,
3184             xfer->stream_id, xfer);
3185 }
3186
3187 static void
3188 xhci_device_generic_start(struct usb_xfer *xfer)
3189 {
3190         DPRINTF("\n");
3191
3192         /* try to insert xfer on HW queue */
3193         xhci_transfer_insert(xfer);
3194
3195         /* try to multi buffer */
3196         xhci_device_generic_multi_enter(xfer->endpoint,
3197             xfer->stream_id, NULL);
3198
3199         /* add transfer last on interrupt queue */
3200         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3201
3202         /* start timeout, if any */
3203         if (xfer->timeout != 0)
3204                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3205 }
3206
3207 static const struct usb_pipe_methods xhci_device_generic_methods =
3208 {
3209         .open = xhci_device_generic_open,
3210         .close = xhci_device_generic_close,
3211         .enter = xhci_device_generic_enter,
3212         .start = xhci_device_generic_start,
3213 };
3214
3215 /*------------------------------------------------------------------------*
3216  * xhci root HUB support
3217  *------------------------------------------------------------------------*
3218  * Simulate a hardware HUB by handling all the necessary requests.
3219  *------------------------------------------------------------------------*/
3220
3221 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3222
3223 static const
3224 struct usb_device_descriptor xhci_devd =
3225 {
3226         .bLength = sizeof(xhci_devd),
3227         .bDescriptorType = UDESC_DEVICE,        /* type */
3228         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3229         .bDeviceClass = UDCLASS_HUB,            /* class */
3230         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3231         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3232         .bMaxPacketSize = 9,                    /* max packet size */
3233         HSETW(.idVendor, 0x0000),               /* vendor */
3234         HSETW(.idProduct, 0x0000),              /* product */
3235         HSETW(.bcdDevice, 0x0100),              /* device version */
3236         .iManufacturer = 1,
3237         .iProduct = 2,
3238         .iSerialNumber = 0,
3239         .bNumConfigurations = 1,                /* # of configurations */
3240 };
3241
3242 static const
3243 struct xhci_bos_desc xhci_bosd = {
3244         .bosd = {
3245                 .bLength = sizeof(xhci_bosd.bosd),
3246                 .bDescriptorType = UDESC_BOS,
3247                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3248                 .bNumDeviceCaps = 3,
3249         },
3250         .usb2extd = {
3251                 .bLength = sizeof(xhci_bosd.usb2extd),
3252                 .bDescriptorType = 1,
3253                 .bDevCapabilityType = 2,
3254                 .bmAttributes[0] = 2,
3255         },
3256         .usbdcd = {
3257                 .bLength = sizeof(xhci_bosd.usbdcd),
3258                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3259                 .bDevCapabilityType = 3,
3260                 .bmAttributes = 0, /* XXX */
3261                 HSETW(.wSpeedsSupported, 0x000C),
3262                 .bFunctionalitySupport = 8,
3263                 .bU1DevExitLat = 255,   /* dummy - not used */
3264                 .wU2DevExitLat = { 0x00, 0x08 },
3265         },
3266         .cidd = {
3267                 .bLength = sizeof(xhci_bosd.cidd),
3268                 .bDescriptorType = 1,
3269                 .bDevCapabilityType = 4,
3270                 .bReserved = 0,
3271                 .bContainerID = 0, /* XXX */
3272         },
3273 };
3274
3275 static const
3276 struct xhci_config_desc xhci_confd = {
3277         .confd = {
3278                 .bLength = sizeof(xhci_confd.confd),
3279                 .bDescriptorType = UDESC_CONFIG,
3280                 .wTotalLength[0] = sizeof(xhci_confd),
3281                 .bNumInterface = 1,
3282                 .bConfigurationValue = 1,
3283                 .iConfiguration = 0,
3284                 .bmAttributes = UC_SELF_POWERED,
3285                 .bMaxPower = 0          /* max power */
3286         },
3287         .ifcd = {
3288                 .bLength = sizeof(xhci_confd.ifcd),
3289                 .bDescriptorType = UDESC_INTERFACE,
3290                 .bNumEndpoints = 1,
3291                 .bInterfaceClass = UICLASS_HUB,
3292                 .bInterfaceSubClass = UISUBCLASS_HUB,
3293                 .bInterfaceProtocol = 0,
3294         },
3295         .endpd = {
3296                 .bLength = sizeof(xhci_confd.endpd),
3297                 .bDescriptorType = UDESC_ENDPOINT,
3298                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3299                 .bmAttributes = UE_INTERRUPT,
3300                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3301                 .bInterval = 255,
3302         },
3303         .endpcd = {
3304                 .bLength = sizeof(xhci_confd.endpcd),
3305                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3306                 .bMaxBurst = 0,
3307                 .bmAttributes = 0,
3308         },
3309 };
3310
3311 static const
3312 struct usb_hub_ss_descriptor xhci_hubd = {
3313         .bLength = sizeof(xhci_hubd),
3314         .bDescriptorType = UDESC_SS_HUB,
3315 };
3316
3317 static usb_error_t
3318 xhci_roothub_exec(struct usb_device *udev,
3319     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3320 {
3321         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3322         const char *str_ptr;
3323         const void *ptr;
3324         uint32_t port;
3325         uint32_t v;
3326         uint16_t len;
3327         uint16_t i;
3328         uint16_t value;
3329         uint16_t index;
3330         uint8_t j;
3331         usb_error_t err;
3332
3333         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3334
3335         /* buffer reset */
3336         ptr = (const void *)&sc->sc_hub_desc;
3337         len = 0;
3338         err = 0;
3339
3340         value = UGETW(req->wValue);
3341         index = UGETW(req->wIndex);
3342
3343         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3344             "wValue=0x%04x wIndex=0x%04x\n",
3345             req->bmRequestType, req->bRequest,
3346             UGETW(req->wLength), value, index);
3347
3348 #define C(x,y) ((x) | ((y) << 8))
3349         switch (C(req->bRequest, req->bmRequestType)) {
3350         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3351         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3352         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3353                 /*
3354                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3355                  * for the integrated root hub.
3356                  */
3357                 break;
3358         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3359                 len = 1;
3360                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3361                 break;
3362         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3363                 switch (value >> 8) {
3364                 case UDESC_DEVICE:
3365                         if ((value & 0xff) != 0) {
3366                                 err = USB_ERR_IOERROR;
3367                                 goto done;
3368                         }
3369                         len = sizeof(xhci_devd);
3370                         ptr = (const void *)&xhci_devd;
3371                         break;
3372
3373                 case UDESC_BOS:
3374                         if ((value & 0xff) != 0) {
3375                                 err = USB_ERR_IOERROR;
3376                                 goto done;
3377                         }
3378                         len = sizeof(xhci_bosd);
3379                         ptr = (const void *)&xhci_bosd;
3380                         break;
3381
3382                 case UDESC_CONFIG:
3383                         if ((value & 0xff) != 0) {
3384                                 err = USB_ERR_IOERROR;
3385                                 goto done;
3386                         }
3387                         len = sizeof(xhci_confd);
3388                         ptr = (const void *)&xhci_confd;
3389                         break;
3390
3391                 case UDESC_STRING:
3392                         switch (value & 0xff) {
3393                         case 0: /* Language table */
3394                                 str_ptr = "\001";
3395                                 break;
3396
3397                         case 1: /* Vendor */
3398                                 str_ptr = sc->sc_vendor;
3399                                 break;
3400
3401                         case 2: /* Product */
3402                                 str_ptr = "XHCI root HUB";
3403                                 break;
3404
3405                         default:
3406                                 str_ptr = "";
3407                                 break;
3408                         }
3409
3410                         len = usb_make_str_desc(
3411                             sc->sc_hub_desc.temp,
3412                             sizeof(sc->sc_hub_desc.temp),
3413                             str_ptr);
3414                         break;
3415
3416                 default:
3417                         err = USB_ERR_IOERROR;
3418                         goto done;
3419                 }
3420                 break;
3421         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3422                 len = 1;
3423                 sc->sc_hub_desc.temp[0] = 0;
3424                 break;
3425         case C(UR_GET_STATUS, UT_READ_DEVICE):
3426                 len = 2;
3427                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3428                 break;
3429         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3430         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3431                 len = 2;
3432                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3433                 break;
3434         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3435                 if (value >= XHCI_MAX_DEVICES) {
3436                         err = USB_ERR_IOERROR;
3437                         goto done;
3438                 }
3439                 break;
3440         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3441                 if (value != 0 && value != 1) {
3442                         err = USB_ERR_IOERROR;
3443                         goto done;
3444                 }
3445                 sc->sc_conf = value;
3446                 break;
3447         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3448                 break;
3449         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3450         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3451         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3452                 err = USB_ERR_IOERROR;
3453                 goto done;
3454         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3455                 break;
3456         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3457                 break;
3458                 /* Hub requests */
3459         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3460                 break;
3461         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3462                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3463
3464                 if ((index < 1) ||
3465                     (index > sc->sc_noport)) {
3466                         err = USB_ERR_IOERROR;
3467                         goto done;
3468                 }
3469                 port = XHCI_PORTSC(index);
3470
3471                 v = XREAD4(sc, oper, port);
3472                 i = XHCI_PS_PLS_GET(v);
3473                 v &= ~XHCI_PS_CLEAR;
3474
3475                 switch (value) {
3476                 case UHF_C_BH_PORT_RESET:
3477                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3478                         break;
3479                 case UHF_C_PORT_CONFIG_ERROR:
3480                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3481                         break;
3482                 case UHF_C_PORT_SUSPEND:
3483                 case UHF_C_PORT_LINK_STATE:
3484                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3485                         break;
3486                 case UHF_C_PORT_CONNECTION:
3487                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3488                         break;
3489                 case UHF_C_PORT_ENABLE:
3490                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3491                         break;
3492                 case UHF_C_PORT_OVER_CURRENT:
3493                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3494                         break;
3495                 case UHF_C_PORT_RESET:
3496                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3497                         break;
3498                 case UHF_PORT_ENABLE:
3499                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3500                         break;
3501                 case UHF_PORT_POWER:
3502                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3503                         break;
3504                 case UHF_PORT_INDICATOR:
3505                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3506                         break;
3507                 case UHF_PORT_SUSPEND:
3508
3509                         /* U3 -> U15 */
3510                         if (i == 3) {
3511                                 XWRITE4(sc, oper, port, v |
3512                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3513                         }
3514
3515                         /* wait 20ms for resume sequence to complete */
3516                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3517
3518                         /* U0 */
3519                         XWRITE4(sc, oper, port, v |
3520                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3521                         break;
3522                 default:
3523                         err = USB_ERR_IOERROR;
3524                         goto done;
3525                 }
3526                 break;
3527
3528         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3529                 if ((value & 0xff) != 0) {
3530                         err = USB_ERR_IOERROR;
3531                         goto done;
3532                 }
3533
3534                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3535
3536                 sc->sc_hub_desc.hubd = xhci_hubd;
3537
3538                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3539
3540                 if (XHCI_HCS0_PPC(v))
3541                         i = UHD_PWR_INDIVIDUAL;
3542                 else
3543                         i = UHD_PWR_GANGED;
3544
3545                 if (XHCI_HCS0_PIND(v))
3546                         i |= UHD_PORT_IND;
3547
3548                 i |= UHD_OC_INDIVIDUAL;
3549
3550                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3551
3552                 /* see XHCI section 5.4.9: */
3553                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3554
3555                 for (j = 1; j <= sc->sc_noport; j++) {
3556
3557                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3558                         if (v & XHCI_PS_DR) {
3559                                 sc->sc_hub_desc.hubd.
3560                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3561                         }
3562                 }
3563                 len = sc->sc_hub_desc.hubd.bLength;
3564                 break;
3565
3566         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3567                 len = 16;
3568                 memset(sc->sc_hub_desc.temp, 0, 16);
3569                 break;
3570
3571         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3572                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3573
3574                 if ((index < 1) ||
3575                     (index > sc->sc_noport)) {
3576                         err = USB_ERR_IOERROR;
3577                         goto done;
3578                 }
3579
3580                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3581
3582                 DPRINTFN(9, "port status=0x%08x\n", v);
3583
3584                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3585
3586                 switch (XHCI_PS_SPEED_GET(v)) {
3587                 case 3:
3588                         i |= UPS_HIGH_SPEED;
3589                         break;
3590                 case 2:
3591                         i |= UPS_LOW_SPEED;
3592                         break;
3593                 case 1:
3594                         /* FULL speed */
3595                         break;
3596                 default:
3597                         i |= UPS_OTHER_SPEED;
3598                         break;
3599                 }
3600
3601                 if (v & XHCI_PS_CCS)
3602                         i |= UPS_CURRENT_CONNECT_STATUS;
3603                 if (v & XHCI_PS_PED)
3604                         i |= UPS_PORT_ENABLED;
3605                 if (v & XHCI_PS_OCA)
3606                         i |= UPS_OVERCURRENT_INDICATOR;
3607                 if (v & XHCI_PS_PR)
3608                         i |= UPS_RESET;
3609                 if (v & XHCI_PS_PP) {
3610                         /*
3611                          * The USB 3.0 RH is using the
3612                          * USB 2.0's power bit
3613                          */
3614                         i |= UPS_PORT_POWER;
3615                 }
3616                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3617
3618                 i = 0;
3619                 if (v & XHCI_PS_CSC)
3620                         i |= UPS_C_CONNECT_STATUS;
3621                 if (v & XHCI_PS_PEC)
3622                         i |= UPS_C_PORT_ENABLED;
3623                 if (v & XHCI_PS_OCC)
3624                         i |= UPS_C_OVERCURRENT_INDICATOR;
3625                 if (v & XHCI_PS_WRC)
3626                         i |= UPS_C_BH_PORT_RESET;
3627                 if (v & XHCI_PS_PRC)
3628                         i |= UPS_C_PORT_RESET;
3629                 if (v & XHCI_PS_PLC)
3630                         i |= UPS_C_PORT_LINK_STATE;
3631                 if (v & XHCI_PS_CEC)
3632                         i |= UPS_C_PORT_CONFIG_ERROR;
3633
3634                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3635                 len = sizeof(sc->sc_hub_desc.ps);
3636                 break;
3637
3638         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3639                 err = USB_ERR_IOERROR;
3640                 goto done;
3641
3642         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3643                 break;
3644
3645         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3646
3647                 i = index >> 8;
3648                 index &= 0x00FF;
3649
3650                 if ((index < 1) ||
3651                     (index > sc->sc_noport)) {
3652                         err = USB_ERR_IOERROR;
3653                         goto done;
3654                 }
3655
3656                 port = XHCI_PORTSC(index);
3657                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3658
3659                 switch (value) {
3660                 case UHF_PORT_U1_TIMEOUT:
3661                         if (XHCI_PS_SPEED_GET(v) != 4) {
3662                                 err = USB_ERR_IOERROR;
3663                                 goto done;
3664                         }
3665                         port = XHCI_PORTPMSC(index);
3666                         v = XREAD4(sc, oper, port);
3667                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3668                         v |= XHCI_PM3_U1TO_SET(i);
3669                         XWRITE4(sc, oper, port, v);
3670                         break;
3671                 case UHF_PORT_U2_TIMEOUT:
3672                         if (XHCI_PS_SPEED_GET(v) != 4) {
3673                                 err = USB_ERR_IOERROR;
3674                                 goto done;
3675                         }
3676                         port = XHCI_PORTPMSC(index);
3677                         v = XREAD4(sc, oper, port);
3678                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3679                         v |= XHCI_PM3_U2TO_SET(i);
3680                         XWRITE4(sc, oper, port, v);
3681                         break;
3682                 case UHF_BH_PORT_RESET:
3683                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3684                         break;
3685                 case UHF_PORT_LINK_STATE:
3686                         XWRITE4(sc, oper, port, v |
3687                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3688                         /* 4ms settle time */
3689                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3690                         break;
3691                 case UHF_PORT_ENABLE:
3692                         DPRINTFN(3, "set port enable %d\n", index);
3693                         break;
3694                 case UHF_PORT_SUSPEND:
3695                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3696                         j = XHCI_PS_SPEED_GET(v);
3697                         if ((j < 1) || (j > 3)) {
3698                                 /* non-supported speed */
3699                                 err = USB_ERR_IOERROR;
3700                                 goto done;
3701                         }
3702                         XWRITE4(sc, oper, port, v |
3703                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3704                         break;
3705                 case UHF_PORT_RESET:
3706                         DPRINTFN(6, "reset port %d\n", index);
3707                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3708                         break;
3709                 case UHF_PORT_POWER:
3710                         DPRINTFN(3, "set port power %d\n", index);
3711                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3712                         break;
3713                 case UHF_PORT_TEST:
3714                         DPRINTFN(3, "set port test %d\n", index);
3715                         break;
3716                 case UHF_PORT_INDICATOR:
3717                         DPRINTFN(3, "set port indicator %d\n", index);
3718
3719                         v &= ~XHCI_PS_PIC_SET(3);
3720                         v |= XHCI_PS_PIC_SET(1);
3721
3722                         XWRITE4(sc, oper, port, v);
3723                         break;
3724                 default:
3725                         err = USB_ERR_IOERROR;
3726                         goto done;
3727                 }
3728                 break;
3729
3730         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3731         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3732         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3733         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3734                 break;
3735         default:
3736                 err = USB_ERR_IOERROR;
3737                 goto done;
3738         }
3739 done:
3740         *plength = len;
3741         *pptr = ptr;
3742         return (err);
3743 }
3744
3745 static void
3746 xhci_xfer_setup(struct usb_setup_params *parm)
3747 {
3748         struct usb_page_search page_info;
3749         struct usb_page_cache *pc;
3750         struct usb_xfer *xfer;
3751         void *last_obj;
3752         uint32_t ntd;
3753         uint32_t n;
3754
3755         xfer = parm->curr_xfer;
3756
3757         /*
3758          * The proof for the "ntd" formula is illustrated like this:
3759          *
3760          * +------------------------------------+
3761          * |                                    |
3762          * |         |remainder ->              |
3763          * |   +-----+---+                      |
3764          * |   | xxx | x | frm 0                |
3765          * |   +-----+---++                     |
3766          * |   | xxx | xx | frm 1               |
3767          * |   +-----+----+                     |
3768          * |            ...                     |
3769          * +------------------------------------+
3770          *
3771          * "xxx" means a completely full USB transfer descriptor
3772          *
3773          * "x" and "xx" means a short USB packet
3774          *
3775          * For the remainder of an USB transfer modulo
3776          * "max_data_length" we need two USB transfer descriptors.
3777          * One to transfer the remaining data and one to finalise with
3778          * a zero length packet in case the "force_short_xfer" flag is
3779          * set. We only need two USB transfer descriptors in the case
3780          * where the transfer length of the first one is a factor of
3781          * "max_frame_size". The rest of the needed USB transfer
3782          * descriptors is given by the buffer size divided by the
3783          * maximum data payload.
3784          */
3785         parm->hc_max_packet_size = 0x400;
3786         parm->hc_max_packet_count = 16 * 3;
3787         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3788
3789         xfer->flags_int.bdma_enable = 1;
3790
3791         usbd_transfer_setup_sub(parm);
3792
3793         if (xfer->flags_int.isochronous_xfr) {
3794                 ntd = ((1 * xfer->nframes)
3795                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3796         } else if (xfer->flags_int.control_xfr) {
3797                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3798                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3799         } else {
3800                 ntd = ((2 * xfer->nframes)
3801                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3802         }
3803
3804 alloc_dma_set:
3805
3806         if (parm->err)
3807                 return;
3808
3809         /*
3810          * Allocate queue heads and transfer descriptors
3811          */
3812         last_obj = NULL;
3813
3814         if (usbd_transfer_setup_sub_malloc(
3815             parm, &pc, sizeof(struct xhci_td),
3816             XHCI_TD_ALIGN, ntd)) {
3817                 parm->err = USB_ERR_NOMEM;
3818                 return;
3819         }
3820         if (parm->buf) {
3821                 for (n = 0; n != ntd; n++) {
3822                         struct xhci_td *td;
3823
3824                         usbd_get_page(pc + n, 0, &page_info);
3825
3826                         td = page_info.buffer;
3827
3828                         /* init TD */
3829                         td->td_self = page_info.physaddr;
3830                         td->obj_next = last_obj;
3831                         td->page_cache = pc + n;
3832
3833                         last_obj = td;
3834
3835                         usb_pc_cpu_flush(pc + n);
3836                 }
3837         }
3838         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3839
3840         if (!xfer->flags_int.curr_dma_set) {
3841                 xfer->flags_int.curr_dma_set = 1;
3842                 goto alloc_dma_set;
3843         }
3844 }
3845
3846 static usb_error_t
3847 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3848 {
3849         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3850         struct usb_page_search buf_inp;
3851         struct usb_device *udev;
3852         struct xhci_endpoint_ext *pepext;
3853         struct usb_endpoint_descriptor *edesc;
3854         struct usb_page_cache *pcinp;
3855         usb_error_t err;
3856         usb_stream_t stream_id;
3857         uint32_t mask;
3858         uint8_t index;
3859         uint8_t epno;
3860
3861         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3862             xfer->endpoint->edesc);
3863
3864         udev = xfer->xroot->udev;
3865         index = udev->controller_slot_id;
3866
3867         pcinp = &sc->sc_hw.devs[index].input_pc;
3868
3869         usbd_get_page(pcinp, 0, &buf_inp);
3870
3871         edesc = xfer->endpoint->edesc;
3872
3873         epno = edesc->bEndpointAddress;
3874         stream_id = xfer->stream_id;
3875
3876         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3877                 epno |= UE_DIR_IN;
3878
3879         epno = XHCI_EPNO2EPID(epno);
3880
3881         if (epno == 0)
3882                 return (USB_ERR_NO_PIPE);               /* invalid */
3883
3884         XHCI_CMD_LOCK(sc);
3885
3886         /* configure endpoint */
3887
3888         err = xhci_configure_endpoint_by_xfer(xfer);
3889
3890         if (err != 0) {
3891                 XHCI_CMD_UNLOCK(sc);
3892                 return (err);
3893         }
3894
3895         /*
3896          * Get the endpoint into the stopped state according to the
3897          * endpoint context state diagram in the XHCI specification:
3898          */
3899
3900         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3901
3902         if (err != 0)
3903                 DPRINTF("Could not stop endpoint %u\n", epno);
3904
3905         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3906
3907         if (err != 0)
3908                 DPRINTF("Could not reset endpoint %u\n", epno);
3909
3910         err = xhci_cmd_set_tr_dequeue_ptr(sc,
3911             (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3912             XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3913             stream_id, epno, index);
3914
3915         if (err != 0)
3916                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3917
3918         /*
3919          * Get the endpoint into the running state according to the
3920          * endpoint context state diagram in the XHCI specification:
3921          */
3922
3923         mask = (1U << epno);
3924         xhci_configure_mask(udev, mask | 1U, 0);
3925
3926         if (!(sc->sc_hw.devs[index].ep_configured & mask)) {
3927                 sc->sc_hw.devs[index].ep_configured |= mask;
3928                 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3929         } else {
3930                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3931         }
3932
3933         if (err != 0) {
3934                 DPRINTF("Could not configure "
3935                     "endpoint %u at slot %u.\n", epno, index);
3936         }
3937         XHCI_CMD_UNLOCK(sc);
3938
3939         return (0);
3940 }
3941
3942 static void
3943 xhci_xfer_unsetup(struct usb_xfer *xfer)
3944 {
3945         return;
3946 }
3947
3948 static void
3949 xhci_start_dma_delay(struct usb_xfer *xfer)
3950 {
3951         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3952
3953         /* put transfer on interrupt queue (again) */
3954         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3955
3956         (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3957             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3958 }
3959
3960 static void
3961 xhci_configure_msg(struct usb_proc_msg *pm)
3962 {
3963         struct xhci_softc *sc;
3964         struct xhci_endpoint_ext *pepext;
3965         struct usb_xfer *xfer;
3966
3967         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3968
3969 restart:
3970         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3971
3972                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3973                     xfer->endpoint->edesc);
3974
3975                 if ((pepext->trb_halted != 0) ||
3976                     (pepext->trb_running == 0)) {
3977
3978                         uint16_t i;
3979
3980                         /* clear halted and running */
3981                         pepext->trb_halted = 0;
3982                         pepext->trb_running = 0;
3983
3984                         /* nuke remaining buffered transfers */
3985
3986                         for (i = 0; i != (XHCI_MAX_TRANSFERS *
3987                             XHCI_MAX_STREAMS); i++) {
3988                                 /*
3989                                  * NOTE: We need to use the timeout
3990                                  * error code here else existing
3991                                  * isochronous clients can get
3992                                  * confused:
3993                                  */
3994                                 if (pepext->xfer[i] != NULL) {
3995                                         xhci_device_done(pepext->xfer[i],
3996                                             USB_ERR_TIMEOUT);
3997                                 }
3998                         }
3999
4000                         /*
4001                          * NOTE: The USB transfer cannot vanish in
4002                          * this state!
4003                          */
4004
4005                         USB_BUS_UNLOCK(&sc->sc_bus);
4006
4007                         xhci_configure_reset_endpoint(xfer);
4008
4009                         USB_BUS_LOCK(&sc->sc_bus);
4010
4011                         /* check if halted is still cleared */
4012                         if (pepext->trb_halted == 0) {
4013                                 pepext->trb_running = 1;
4014                                 memset(pepext->trb_index, 0,
4015                                     sizeof(pepext->trb_index));
4016                         }
4017                         goto restart;
4018                 }
4019
4020                 if (xfer->flags_int.did_dma_delay) {
4021
4022                         /* remove transfer from interrupt queue (again) */
4023                         usbd_transfer_dequeue(xfer);
4024
4025                         /* we are finally done */
4026                         usb_dma_delay_done_cb(xfer);
4027
4028                         /* queue changed - restart */
4029                         goto restart;
4030                 }
4031         }
4032
4033         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
4034
4035                 /* try to insert xfer on HW queue */
4036                 xhci_transfer_insert(xfer);
4037
4038                 /* try to multi buffer */
4039                 xhci_device_generic_multi_enter(xfer->endpoint,
4040                     xfer->stream_id, NULL);
4041         }
4042 }
4043
4044 static void
4045 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4046     struct usb_endpoint *ep)
4047 {
4048         struct xhci_endpoint_ext *pepext;
4049
4050         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4051             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4052
4053         if (udev->parent_hub == NULL) {
4054                 /* root HUB has special endpoint handling */
4055                 return;
4056         }
4057
4058         ep->methods = &xhci_device_generic_methods;
4059
4060         pepext = xhci_get_endpoint_ext(udev, edesc);
4061
4062         USB_BUS_LOCK(udev->bus);
4063         pepext->trb_halted = 1;
4064         pepext->trb_running = 0;
4065         USB_BUS_UNLOCK(udev->bus);
4066 }
4067
4068 static void
4069 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4070 {
4071
4072 }
4073
4074 static void
4075 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4076 {
4077         struct xhci_endpoint_ext *pepext;
4078
4079         DPRINTF("\n");
4080
4081         if (udev->flags.usb_mode != USB_MODE_HOST) {
4082                 /* not supported */
4083                 return;
4084         }
4085         if (udev->parent_hub == NULL) {
4086                 /* root HUB has special endpoint handling */
4087                 return;
4088         }
4089
4090         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4091
4092         USB_BUS_LOCK(udev->bus);
4093         pepext->trb_halted = 1;
4094         pepext->trb_running = 0;
4095         USB_BUS_UNLOCK(udev->bus);
4096 }
4097
4098 static usb_error_t
4099 xhci_device_init(struct usb_device *udev)
4100 {
4101         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4102         usb_error_t err;
4103         uint8_t temp;
4104
4105         /* no init for root HUB */
4106         if (udev->parent_hub == NULL)
4107                 return (0);
4108
4109         XHCI_CMD_LOCK(sc);
4110
4111         /* set invalid default */
4112
4113         udev->controller_slot_id = sc->sc_noslot + 1;
4114
4115         /* try to get a new slot ID from the XHCI */
4116
4117         err = xhci_cmd_enable_slot(sc, &temp);
4118
4119         if (err) {
4120                 XHCI_CMD_UNLOCK(sc);
4121                 return (err);
4122         }
4123
4124         if (temp > sc->sc_noslot) {
4125                 XHCI_CMD_UNLOCK(sc);
4126                 return (USB_ERR_BAD_ADDRESS);
4127         }
4128
4129         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4130                 DPRINTF("slot %u already allocated.\n", temp);
4131                 XHCI_CMD_UNLOCK(sc);
4132                 return (USB_ERR_BAD_ADDRESS);
4133         }
4134
4135         /* store slot ID for later reference */
4136
4137         udev->controller_slot_id = temp;
4138
4139         /* reset data structure */
4140
4141         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4142
4143         /* set mark slot allocated */
4144
4145         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4146
4147         err = xhci_alloc_device_ext(udev);
4148
4149         XHCI_CMD_UNLOCK(sc);
4150
4151         /* get device into default state */
4152
4153         if (err == 0)
4154                 err = xhci_set_address(udev, NULL, 0);
4155
4156         return (err);
4157 }
4158
4159 static void
4160 xhci_device_uninit(struct usb_device *udev)
4161 {
4162         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4163         uint8_t index;
4164
4165         /* no init for root HUB */
4166         if (udev->parent_hub == NULL)
4167                 return;
4168
4169         XHCI_CMD_LOCK(sc);
4170
4171         index = udev->controller_slot_id;
4172
4173         if (index <= sc->sc_noslot) {
4174                 xhci_cmd_disable_slot(sc, index);
4175                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4176
4177                 /* free device extension */
4178                 xhci_free_device_ext(udev);
4179         }
4180
4181         XHCI_CMD_UNLOCK(sc);
4182 }
4183
4184 static void
4185 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4186 {
4187         /*
4188          * Wait until the hardware has finished any possible use of
4189          * the transfer descriptor(s)
4190          */
4191         *pus = 2048;                    /* microseconds */
4192 }
4193
4194 static void
4195 xhci_device_resume(struct usb_device *udev)
4196 {
4197         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4198         uint8_t index;
4199         uint8_t n;
4200         uint8_t p;
4201
4202         DPRINTF("\n");
4203
4204         /* check for root HUB */
4205         if (udev->parent_hub == NULL)
4206                 return;
4207
4208         index = udev->controller_slot_id;
4209
4210         XHCI_CMD_LOCK(sc);
4211
4212         /* blindly resume all endpoints */
4213
4214         USB_BUS_LOCK(udev->bus);
4215
4216         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4217                 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4218                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4219                             n | XHCI_DB_SID_SET(p));
4220                 }
4221         }
4222
4223         USB_BUS_UNLOCK(udev->bus);
4224
4225         XHCI_CMD_UNLOCK(sc);
4226 }
4227
4228 static void
4229 xhci_device_suspend(struct usb_device *udev)
4230 {
4231         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4232         uint8_t index;
4233         uint8_t n;
4234         usb_error_t err;
4235
4236         DPRINTF("\n");
4237
4238         /* check for root HUB */
4239         if (udev->parent_hub == NULL)
4240                 return;
4241
4242         index = udev->controller_slot_id;
4243
4244         XHCI_CMD_LOCK(sc);
4245
4246         /* blindly suspend all endpoints */
4247
4248         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4249                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4250                 if (err != 0) {
4251                         DPRINTF("Failed to suspend endpoint "
4252                             "%u on slot %u (ignored).\n", n, index);
4253                 }
4254         }
4255
4256         XHCI_CMD_UNLOCK(sc);
4257 }
4258
4259 static void
4260 xhci_set_hw_power(struct usb_bus *bus)
4261 {
4262         DPRINTF("\n");
4263 }
4264
4265 static void
4266 xhci_device_state_change(struct usb_device *udev)
4267 {
4268         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4269         struct usb_page_search buf_inp;
4270         usb_error_t err;
4271         uint8_t index;
4272
4273         /* check for root HUB */
4274         if (udev->parent_hub == NULL)
4275                 return;
4276
4277         index = udev->controller_slot_id;
4278
4279         DPRINTF("\n");
4280
4281         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4282                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4283                     &sc->sc_hw.devs[index].tt);
4284                 if (err != 0)
4285                         sc->sc_hw.devs[index].nports = 0;
4286         }
4287
4288         XHCI_CMD_LOCK(sc);
4289
4290         switch (usb_get_device_state(udev)) {
4291         case USB_STATE_POWERED:
4292                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4293                         break;
4294
4295                 /* set default state */
4296                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4297                 sc->sc_hw.devs[index].ep_configured = 3U;
4298
4299                 /* reset number of contexts */
4300                 sc->sc_hw.devs[index].context_num = 0;
4301
4302                 err = xhci_cmd_reset_dev(sc, index);
4303
4304                 if (err != 0) {
4305                         DPRINTF("Device reset failed "
4306                             "for slot %u.\n", index);
4307                 }
4308                 break;
4309
4310         case USB_STATE_ADDRESSED:
4311                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4312                         break;
4313
4314                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4315                 sc->sc_hw.devs[index].ep_configured = 3U;
4316
4317                 /* set configure mask to slot only */
4318                 xhci_configure_mask(udev, 1, 0);
4319
4320                 /* deconfigure all endpoints, except EP0 */
4321                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4322
4323                 if (err) {
4324                         DPRINTF("Failed to deconfigure "
4325                             "slot %u.\n", index);
4326                 }
4327                 break;
4328
4329         case USB_STATE_CONFIGURED:
4330                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) {
4331                         /* deconfigure all endpoints, except EP0 */
4332                         err = xhci_cmd_configure_ep(sc, 0, 1, index);
4333
4334                         if (err) {
4335                                 DPRINTF("Failed to deconfigure "
4336                                     "slot %u.\n", index);
4337                         }
4338                 }
4339
4340                 /* set configured state */
4341                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4342                 sc->sc_hw.devs[index].ep_configured = 3U;
4343
4344                 /* reset number of contexts */
4345                 sc->sc_hw.devs[index].context_num = 0;
4346
4347                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4348
4349                 xhci_configure_mask(udev, 3, 0);
4350
4351                 err = xhci_configure_device(udev);
4352                 if (err != 0) {
4353                         DPRINTF("Could not configure device "
4354                             "at slot %u.\n", index);
4355                 }
4356
4357                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4358                 if (err != 0) {
4359                         DPRINTF("Could not evaluate device "
4360                             "context at slot %u.\n", index);
4361                 }
4362                 break;
4363
4364         default:
4365                 break;
4366         }
4367         XHCI_CMD_UNLOCK(sc);
4368 }
4369
4370 static usb_error_t
4371 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4372     uint8_t ep_mode)
4373 {
4374         switch (ep_mode) {
4375         case USB_EP_MODE_DEFAULT:
4376                 return (0);
4377         case USB_EP_MODE_STREAMS:
4378                 if (xhcistreams == 0 ||
4379                     (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4380                     udev->speed != USB_SPEED_SUPER)
4381                         return (USB_ERR_INVAL);
4382                 return (0);
4383         default:
4384                 return (USB_ERR_INVAL);
4385         }
4386 }
4387
4388 static const struct usb_bus_methods xhci_bus_methods = {
4389         .endpoint_init = xhci_ep_init,
4390         .endpoint_uninit = xhci_ep_uninit,
4391         .xfer_setup = xhci_xfer_setup,
4392         .xfer_unsetup = xhci_xfer_unsetup,
4393         .get_dma_delay = xhci_get_dma_delay,
4394         .device_init = xhci_device_init,
4395         .device_uninit = xhci_device_uninit,
4396         .device_resume = xhci_device_resume,
4397         .device_suspend = xhci_device_suspend,
4398         .set_hw_power = xhci_set_hw_power,
4399         .roothub_exec = xhci_roothub_exec,
4400         .xfer_poll = xhci_do_poll,
4401         .start_dma_delay = xhci_start_dma_delay,
4402         .set_address = xhci_set_address,
4403         .clear_stall = xhci_ep_clear_stall,
4404         .device_state_change = xhci_device_state_change,
4405         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4406         .set_endpoint_mode = xhci_set_endpoint_mode,
4407 };