3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
32 * The XHCI 1.0 spec can be found at
33 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
34 * and the USB 3.0 spec at
35 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
39 * A few words about the design implementation: This driver emulates
40 * the concept about TDs which is found in EHCI specification. This
41 * way we achieve that the USB controller drivers look similar to
42 * eachother which makes it easier to understand the code.
45 #ifdef USB_GLOBAL_INCLUDE_FILE
46 #include USB_GLOBAL_INCLUDE_FILE
48 #include <sys/stdint.h>
49 #include <sys/stddef.h>
50 #include <sys/param.h>
51 #include <sys/queue.h>
52 #include <sys/types.h>
53 #include <sys/systm.h>
54 #include <sys/kernel.h>
56 #include <sys/module.h>
58 #include <sys/mutex.h>
59 #include <sys/condvar.h>
60 #include <sys/sysctl.h>
62 #include <sys/unistd.h>
63 #include <sys/callout.h>
64 #include <sys/malloc.h>
67 #include <dev/usb/usb.h>
68 #include <dev/usb/usbdi.h>
70 #define USB_DEBUG_VAR xhcidebug
72 #include <dev/usb/usb_core.h>
73 #include <dev/usb/usb_debug.h>
74 #include <dev/usb/usb_busdma.h>
75 #include <dev/usb/usb_process.h>
76 #include <dev/usb/usb_transfer.h>
77 #include <dev/usb/usb_device.h>
78 #include <dev/usb/usb_hub.h>
79 #include <dev/usb/usb_util.h>
81 #include <dev/usb/usb_controller.h>
82 #include <dev/usb/usb_bus.h>
83 #endif /* USB_GLOBAL_INCLUDE_FILE */
85 #include <dev/usb/controller/xhci.h>
86 #include <dev/usb/controller/xhcireg.h>
88 #define XHCI_BUS2SC(bus) \
89 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
90 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
92 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
95 static int xhcistreams;
96 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN,
97 &xhcistreams, 0, "Set to enable streams mode support");
99 static int xhcictlquirk = 1;
100 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlquirk, CTLFLAG_RWTUN,
101 &xhcictlquirk, 0, "Set to enable control endpoint quirk");
104 static int xhcidebug;
105 static int xhciroute;
106 static int xhcipolling;
107 static int xhcidma32;
108 static int xhcictlstep;
110 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN,
111 &xhcidebug, 0, "Debug level");
112 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN,
113 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
114 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN,
115 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
116 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
117 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
118 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
119 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
123 #define xhcictlstep 0
126 #define XHCI_INTR_ENDPT 1
128 struct xhci_std_temp {
129 struct xhci_softc *sc;
130 struct usb_page_cache *pc;
132 struct xhci_td *td_next;
135 uint32_t max_packet_size;
147 uint8_t do_isoc_sync;
150 static void xhci_do_poll(struct usb_bus *);
151 static void xhci_device_done(struct usb_xfer *, usb_error_t);
152 static void xhci_root_intr(struct xhci_softc *);
153 static void xhci_free_device_ext(struct usb_device *);
154 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
155 struct usb_endpoint_descriptor *);
156 static usb_proc_callback_t xhci_configure_msg;
157 static usb_error_t xhci_configure_device(struct usb_device *);
158 static usb_error_t xhci_configure_endpoint(struct usb_device *,
159 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
160 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
162 static usb_error_t xhci_configure_mask(struct usb_device *,
164 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
166 static void xhci_endpoint_doorbell(struct usb_xfer *);
167 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
168 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
169 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
171 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
174 static const struct usb_bus_methods xhci_bus_methods;
178 xhci_dump_trb(struct xhci_trb *trb)
180 DPRINTFN(5, "trb = %p\n", trb);
181 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
182 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
183 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
187 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
189 DPRINTFN(5, "pep = %p\n", pep);
190 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
191 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
192 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
193 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
194 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
195 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
196 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
200 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
202 DPRINTFN(5, "psl = %p\n", psl);
203 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
204 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
205 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
206 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
211 xhci_use_polling(void)
214 return (xhcipolling != 0);
221 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
223 struct xhci_softc *sc = XHCI_BUS2SC(bus);
226 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
227 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
229 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
230 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
232 for (i = 0; i != sc->sc_noscratch; i++) {
233 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
234 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
239 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
241 if (sc->sc_ctx_is_64_byte) {
243 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
244 /* all contexts are initially 32-bytes */
245 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
246 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
252 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
254 if (sc->sc_ctx_is_64_byte) {
256 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
257 /* all contexts are initially 32-bytes */
258 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
259 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
261 return (le32toh(*ptr));
265 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
267 if (sc->sc_ctx_is_64_byte) {
269 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
270 /* all contexts are initially 32-bytes */
271 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
272 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
279 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
281 if (sc->sc_ctx_is_64_byte) {
283 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
284 /* all contexts are initially 32-bytes */
285 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
286 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
288 return (le64toh(*ptr));
293 xhci_reset_command_queue_locked(struct xhci_softc *sc)
295 struct usb_page_search buf_res;
296 struct xhci_hw_root *phwr;
302 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
303 if (temp & XHCI_CRCR_LO_CRR) {
304 DPRINTF("Command ring running\n");
305 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
308 * Try to abort the last command as per section
309 * 4.6.1.2 "Aborting a Command" of the XHCI
313 /* stop and cancel */
314 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
315 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
317 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
318 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
321 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
323 /* check if command ring is still running */
324 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
325 if (temp & XHCI_CRCR_LO_CRR) {
326 DPRINTF("Comand ring still running\n");
327 return (USB_ERR_IOERROR);
331 /* reset command ring */
332 sc->sc_command_ccs = 1;
333 sc->sc_command_idx = 0;
335 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
337 /* set up command ring control base address */
338 addr = buf_res.physaddr;
339 phwr = buf_res.buffer;
340 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
342 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
344 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
345 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
347 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
349 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
350 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
356 xhci_start_controller(struct xhci_softc *sc)
358 struct usb_page_search buf_res;
359 struct xhci_hw_root *phwr;
360 struct xhci_dev_ctx_addr *pdctxa;
368 sc->sc_event_ccs = 1;
369 sc->sc_event_idx = 0;
370 sc->sc_command_ccs = 1;
371 sc->sc_command_idx = 0;
373 err = xhci_reset_controller(sc);
377 /* set up number of device slots */
378 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
379 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
381 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
383 temp = XREAD4(sc, oper, XHCI_USBSTS);
385 /* clear interrupts */
386 XWRITE4(sc, oper, XHCI_USBSTS, temp);
387 /* disable all device notifications */
388 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
390 /* set up device context base address */
391 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
392 pdctxa = buf_res.buffer;
393 memset(pdctxa, 0, sizeof(*pdctxa));
395 addr = buf_res.physaddr;
396 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
398 /* slot 0 points to the table of scratchpad pointers */
399 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
401 for (i = 0; i != sc->sc_noscratch; i++) {
402 struct usb_page_search buf_scp;
403 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
404 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
407 addr = buf_res.physaddr;
409 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
410 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
411 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
412 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
414 /* set up event table size */
415 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
416 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
418 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
420 /* set up interrupt rate */
421 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
423 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
425 phwr = buf_res.buffer;
426 addr = buf_res.physaddr;
427 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
429 /* reset hardware root structure */
430 memset(phwr, 0, sizeof(*phwr));
432 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
433 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
435 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
437 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
438 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
440 addr = buf_res.physaddr;
442 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
444 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
445 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
447 /* set up interrupter registers */
448 temp = XREAD4(sc, runt, XHCI_IMAN(0));
449 temp |= XHCI_IMAN_INTR_ENA;
450 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
452 /* set up command ring control base address */
453 addr = buf_res.physaddr;
454 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
456 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
458 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
459 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
461 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
463 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
466 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
467 XHCI_CMD_INTE | XHCI_CMD_HSEE);
469 for (i = 0; i != 100; i++) {
470 usb_pause_mtx(NULL, hz / 100);
471 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
476 XWRITE4(sc, oper, XHCI_USBCMD, 0);
477 device_printf(sc->sc_bus.parent, "Run timeout.\n");
478 return (USB_ERR_IOERROR);
481 /* catch any lost interrupts */
482 xhci_do_poll(&sc->sc_bus);
484 if (sc->sc_port_route != NULL) {
485 /* Route all ports to the XHCI by default */
486 sc->sc_port_route(sc->sc_bus.parent,
487 ~xhciroute, xhciroute);
493 xhci_halt_controller(struct xhci_softc *sc)
501 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
502 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
503 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
505 /* Halt controller */
506 XWRITE4(sc, oper, XHCI_USBCMD, 0);
508 for (i = 0; i != 100; i++) {
509 usb_pause_mtx(NULL, hz / 100);
510 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
516 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
517 return (USB_ERR_IOERROR);
523 xhci_reset_controller(struct xhci_softc *sc)
530 /* Reset controller */
531 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
533 for (i = 0; i != 100; i++) {
534 usb_pause_mtx(NULL, hz / 100);
535 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
536 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
542 device_printf(sc->sc_bus.parent, "Controller "
544 return (USB_ERR_IOERROR);
550 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
556 /* initialize some bus fields */
557 sc->sc_bus.parent = self;
559 /* set the bus revision */
560 sc->sc_bus.usbrev = USB_REV_3_0;
562 /* set up the bus struct */
563 sc->sc_bus.methods = &xhci_bus_methods;
565 /* set up devices array */
566 sc->sc_bus.devices = sc->sc_devices;
567 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
569 /* set default cycle state in case of early interrupts */
570 sc->sc_event_ccs = 1;
571 sc->sc_command_ccs = 1;
573 /* set up bus space offsets */
575 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
576 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
577 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
579 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
580 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
581 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
583 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
585 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
586 device_printf(sc->sc_bus.parent, "Controller does "
587 "not support 4K page size.\n");
591 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
593 DPRINTF("HCS0 = 0x%08x\n", temp);
595 /* set up context size */
596 if (XHCI_HCS0_CSZ(temp)) {
597 sc->sc_ctx_is_64_byte = 1;
599 sc->sc_ctx_is_64_byte = 0;
603 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
604 xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
606 device_printf(self, "%d bytes context size, %d-bit DMA\n",
607 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
609 /* enable 64Kbyte control endpoint quirk */
610 sc->sc_bus.control_ep_quirk = (xhcictlquirk ? 1 : 0);
612 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
614 /* get number of device slots */
615 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
617 if (sc->sc_noport == 0) {
618 device_printf(sc->sc_bus.parent, "Invalid number "
619 "of ports: %u\n", sc->sc_noport);
623 sc->sc_noport = sc->sc_noport;
624 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
626 DPRINTF("Max slots: %u\n", sc->sc_noslot);
628 if (sc->sc_noslot > XHCI_MAX_DEVICES)
629 sc->sc_noslot = XHCI_MAX_DEVICES;
631 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
633 DPRINTF("HCS2=0x%08x\n", temp);
635 /* get number of scratchpads */
636 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
638 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
639 device_printf(sc->sc_bus.parent, "XHCI request "
640 "too many scratchpads\n");
644 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
646 /* get event table size */
647 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
648 if (sc->sc_erst_max > XHCI_MAX_RSEG)
649 sc->sc_erst_max = XHCI_MAX_RSEG;
651 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
653 /* get maximum exit latency */
654 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
655 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
657 /* Check if we should use the default IMOD value. */
658 if (sc->sc_imod_default == 0)
659 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
661 /* get all DMA memory */
662 if (usb_bus_mem_alloc_all(&sc->sc_bus,
663 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
667 /* set up command queue mutex and condition varible */
668 cv_init(&sc->sc_cmd_cv, "CMDQ");
669 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
671 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
672 sc->sc_config_msg[0].bus = &sc->sc_bus;
673 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
674 sc->sc_config_msg[1].bus = &sc->sc_bus;
680 xhci_uninit(struct xhci_softc *sc)
683 * NOTE: At this point the control transfer process is gone
684 * and "xhci_configure_msg" is no longer called. Consequently
685 * waiting for the configuration messages to complete is not
688 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
690 cv_destroy(&sc->sc_cmd_cv);
691 sx_destroy(&sc->sc_cmd_sx);
695 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
697 struct xhci_softc *sc = XHCI_BUS2SC(bus);
700 case USB_HW_POWER_SUSPEND:
701 DPRINTF("Stopping the XHCI\n");
702 xhci_halt_controller(sc);
703 xhci_reset_controller(sc);
705 case USB_HW_POWER_SHUTDOWN:
706 DPRINTF("Stopping the XHCI\n");
707 xhci_halt_controller(sc);
708 xhci_reset_controller(sc);
710 case USB_HW_POWER_RESUME:
711 DPRINTF("Starting the XHCI\n");
712 xhci_start_controller(sc);
720 xhci_generic_done_sub(struct usb_xfer *xfer)
723 struct xhci_td *td_alt_next;
727 td = xfer->td_transfer_cache;
728 td_alt_next = td->alt_next;
730 if (xfer->aframes != xfer->nframes)
731 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
735 usb_pc_cpu_invalidate(td->page_cache);
740 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
741 xfer, (unsigned int)xfer->aframes,
742 (unsigned int)xfer->nframes,
743 (unsigned int)len, (unsigned int)td->len,
744 (unsigned int)status);
747 * Verify the status length and
748 * add the length to "frlengths[]":
751 /* should not happen */
752 DPRINTF("Invalid status length, "
753 "0x%04x/0x%04x bytes\n", len, td->len);
754 status = XHCI_TRB_ERROR_LENGTH;
755 } else if (xfer->aframes != xfer->nframes) {
756 xfer->frlengths[xfer->aframes] += td->len - len;
758 /* Check for last transfer */
759 if (((void *)td) == xfer->td_transfer_last) {
763 /* Check for transfer error */
764 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
765 status != XHCI_TRB_ERROR_SUCCESS) {
766 /* the transfer is finished */
770 /* Check for short transfer */
772 if (xfer->flags_int.short_frames_ok ||
773 xfer->flags_int.isochronous_xfr ||
774 xfer->flags_int.control_xfr) {
775 /* follow alt next */
778 /* the transfer is finished */
785 if (td->alt_next != td_alt_next) {
786 /* this USB frame is complete */
791 /* update transfer cache */
793 xfer->td_transfer_cache = td;
795 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
796 (status != XHCI_TRB_ERROR_SHORT_PKT &&
797 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
798 USB_ERR_NORMAL_COMPLETION);
802 xhci_generic_done(struct usb_xfer *xfer)
806 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
807 xfer, xfer->endpoint);
811 xfer->td_transfer_cache = xfer->td_transfer_first;
813 if (xfer->flags_int.control_xfr) {
815 if (xfer->flags_int.control_hdr)
816 err = xhci_generic_done_sub(xfer);
820 if (xfer->td_transfer_cache == NULL)
824 while (xfer->aframes != xfer->nframes) {
826 err = xhci_generic_done_sub(xfer);
829 if (xfer->td_transfer_cache == NULL)
833 if (xfer->flags_int.control_xfr &&
834 !xfer->flags_int.control_act)
835 err = xhci_generic_done_sub(xfer);
837 /* transfer is complete */
838 xhci_device_done(xfer, err);
842 xhci_activate_transfer(struct usb_xfer *xfer)
846 td = xfer->td_transfer_cache;
848 usb_pc_cpu_invalidate(td->page_cache);
850 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
852 /* activate the transfer */
854 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
855 usb_pc_cpu_flush(td->page_cache);
857 xhci_endpoint_doorbell(xfer);
862 xhci_skip_transfer(struct usb_xfer *xfer)
865 struct xhci_td *td_last;
867 td = xfer->td_transfer_cache;
868 td_last = xfer->td_transfer_last;
872 usb_pc_cpu_invalidate(td->page_cache);
874 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
876 usb_pc_cpu_invalidate(td_last->page_cache);
878 /* copy LINK TRB to current waiting location */
880 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
881 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
882 usb_pc_cpu_flush(td->page_cache);
884 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
885 usb_pc_cpu_flush(td->page_cache);
887 xhci_endpoint_doorbell(xfer);
891 /*------------------------------------------------------------------------*
892 * xhci_check_transfer
893 *------------------------------------------------------------------------*/
895 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
897 struct xhci_endpoint_ext *pepext;
902 uint16_t stream_id = 0;
910 td_event = le64toh(trb->qwTrb0);
911 temp = le32toh(trb->dwTrb2);
913 remainder = XHCI_TRB_2_REM_GET(temp);
914 status = XHCI_TRB_2_ERROR_GET(temp);
916 temp = le32toh(trb->dwTrb3);
917 epno = XHCI_TRB_3_EP_GET(temp);
918 index = XHCI_TRB_3_SLOT_GET(temp);
920 /* check if error means halted */
921 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
922 status != XHCI_TRB_ERROR_SUCCESS);
924 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
925 index, epno, remainder, status);
927 if (index > sc->sc_noslot) {
928 DPRINTF("Invalid slot.\n");
932 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
933 DPRINTF("Invalid endpoint.\n");
937 pepext = &sc->sc_hw.devs[index].endp[epno];
939 /* try to find the USB transfer that generated the event */
941 struct usb_xfer *xfer;
944 if (i == (XHCI_MAX_TRANSFERS - 1)) {
945 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS ||
946 stream_id == (XHCI_MAX_STREAMS - 1))
950 DPRINTFN(5, "stream_id=%u\n", stream_id);
953 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
957 td = xfer->td_transfer_cache;
959 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
961 (long long)td->td_self,
962 (long long)td->td_self + sizeof(td->td_trb));
965 * NOTE: Some XHCI implementations might not trigger
966 * an event on the last LINK TRB so we need to
967 * consider both the last and second last event
968 * address as conditions for a successful transfer.
970 * NOTE: We assume that the XHCI will only trigger one
971 * event per chain of TRBs.
974 offset = td_event - td->td_self;
977 offset < (int64_t)sizeof(td->td_trb)) {
979 usb_pc_cpu_invalidate(td->page_cache);
981 /* compute rest of remainder, if any */
982 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
983 temp = le32toh(td->td_trb[i].dwTrb2);
984 remainder += XHCI_TRB_2_BYTES_GET(temp);
987 DPRINTFN(5, "New remainder: %u\n", remainder);
989 /* clear isochronous transfer errors */
990 if (xfer->flags_int.isochronous_xfr) {
993 status = XHCI_TRB_ERROR_SUCCESS;
998 /* "td->remainder" is verified later */
999 td->remainder = remainder;
1000 td->status = status;
1002 usb_pc_cpu_flush(td->page_cache);
1005 * 1) Last transfer descriptor makes the
1008 if (((void *)td) == xfer->td_transfer_last) {
1009 DPRINTF("TD is last\n");
1010 xhci_generic_done(xfer);
1015 * 2) Any kind of error makes the transfer
1019 DPRINTF("TD has I/O error\n");
1020 xhci_generic_done(xfer);
1025 * 3) If there is no alternate next transfer,
1026 * a short packet also makes the transfer done
1028 if (td->remainder > 0) {
1029 if (td->alt_next == NULL) {
1031 "short TD has no alternate next\n");
1032 xhci_generic_done(xfer);
1035 DPRINTF("TD has short pkt\n");
1036 if (xfer->flags_int.short_frames_ok ||
1037 xfer->flags_int.isochronous_xfr ||
1038 xfer->flags_int.control_xfr) {
1039 /* follow the alt next */
1040 xfer->td_transfer_cache = td->alt_next;
1041 xhci_activate_transfer(xfer);
1044 xhci_skip_transfer(xfer);
1045 xhci_generic_done(xfer);
1050 * 4) Transfer complete - go to next TD
1052 DPRINTF("Following next TD\n");
1053 xfer->td_transfer_cache = td->obj_next;
1054 xhci_activate_transfer(xfer);
1055 break; /* there should only be one match */
1061 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1063 if (sc->sc_cmd_addr == trb->qwTrb0) {
1064 DPRINTF("Received command event\n");
1065 sc->sc_cmd_result[0] = trb->dwTrb2;
1066 sc->sc_cmd_result[1] = trb->dwTrb3;
1067 cv_signal(&sc->sc_cmd_cv);
1068 return (1); /* command match */
1074 xhci_interrupt_poll(struct xhci_softc *sc)
1076 struct usb_page_search buf_res;
1077 struct xhci_hw_root *phwr;
1087 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1089 phwr = buf_res.buffer;
1091 /* Receive any events */
1093 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1095 i = sc->sc_event_idx;
1096 j = sc->sc_event_ccs;
1101 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1103 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1108 event = XHCI_TRB_3_TYPE_GET(temp);
1110 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1111 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1112 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1113 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1116 case XHCI_TRB_EVENT_TRANSFER:
1117 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1119 case XHCI_TRB_EVENT_CMD_COMPLETE:
1120 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1123 DPRINTF("Unhandled event = %u\n", event);
1129 if (i == XHCI_MAX_EVENTS) {
1133 /* check for timeout */
1139 sc->sc_event_idx = i;
1140 sc->sc_event_ccs = j;
1143 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1144 * latched. That means to activate the register we need to
1145 * write both the low and high double word of the 64-bit
1149 addr = buf_res.physaddr;
1150 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1152 /* try to clear busy bit */
1153 addr |= XHCI_ERDP_LO_BUSY;
1155 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1156 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1162 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1163 uint16_t timeout_ms)
1165 struct usb_page_search buf_res;
1166 struct xhci_hw_root *phwr;
1171 uint8_t timeout = 0;
1174 XHCI_CMD_ASSERT_LOCKED(sc);
1176 /* get hardware root structure */
1178 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1180 phwr = buf_res.buffer;
1184 USB_BUS_LOCK(&sc->sc_bus);
1186 i = sc->sc_command_idx;
1187 j = sc->sc_command_ccs;
1189 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1190 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1191 (long long)le64toh(trb->qwTrb0),
1192 (long)le32toh(trb->dwTrb2),
1193 (long)le32toh(trb->dwTrb3));
1195 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1196 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1198 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1203 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1205 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1207 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1209 phwr->hwr_commands[i].dwTrb3 = temp;
1211 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1213 addr = buf_res.physaddr;
1214 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1216 sc->sc_cmd_addr = htole64(addr);
1220 if (i == (XHCI_MAX_COMMANDS - 1)) {
1223 temp = htole32(XHCI_TRB_3_TC_BIT |
1224 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1225 XHCI_TRB_3_CYCLE_BIT);
1227 temp = htole32(XHCI_TRB_3_TC_BIT |
1228 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1231 phwr->hwr_commands[i].dwTrb3 = temp;
1233 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1239 sc->sc_command_idx = i;
1240 sc->sc_command_ccs = j;
1242 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1244 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1245 USB_MS_TO_TICKS(timeout_ms));
1248 * In some error cases event interrupts are not generated.
1249 * Poll one time to see if the command has completed.
1251 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1252 DPRINTF("Command was completed when polling\n");
1256 DPRINTF("Command timeout!\n");
1258 * After some weeks of continuous operation, it has
1259 * been observed that the ASMedia Technology, ASM1042
1260 * SuperSpeed USB Host Controller can suddenly stop
1261 * accepting commands via the command queue. Try to
1262 * first reset the command queue. If that fails do a
1263 * host controller reset.
1266 xhci_reset_command_queue_locked(sc) == 0) {
1267 temp = le32toh(trb->dwTrb3);
1270 * Avoid infinite XHCI reset loops if the set
1271 * address command fails to respond due to a
1272 * non-enumerating device:
1274 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1275 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1276 DPRINTF("Set address timeout\n");
1282 DPRINTF("Controller reset!\n");
1283 usb_bus_reset_async_locked(&sc->sc_bus);
1285 err = USB_ERR_TIMEOUT;
1289 temp = le32toh(sc->sc_cmd_result[0]);
1290 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1291 err = USB_ERR_IOERROR;
1293 trb->dwTrb2 = sc->sc_cmd_result[0];
1294 trb->dwTrb3 = sc->sc_cmd_result[1];
1297 USB_BUS_UNLOCK(&sc->sc_bus);
1304 xhci_cmd_nop(struct xhci_softc *sc)
1306 struct xhci_trb trb;
1313 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1315 trb.dwTrb3 = htole32(temp);
1317 return (xhci_do_command(sc, &trb, 100 /* ms */));
1322 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1324 struct xhci_trb trb;
1332 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1334 err = xhci_do_command(sc, &trb, 100 /* ms */);
1338 temp = le32toh(trb.dwTrb3);
1340 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1347 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1349 struct xhci_trb trb;
1356 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1357 XHCI_TRB_3_SLOT_SET(slot_id);
1359 trb.dwTrb3 = htole32(temp);
1361 return (xhci_do_command(sc, &trb, 100 /* ms */));
1365 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1366 uint8_t bsr, uint8_t slot_id)
1368 struct xhci_trb trb;
1373 trb.qwTrb0 = htole64(input_ctx);
1375 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1376 XHCI_TRB_3_SLOT_SET(slot_id);
1379 temp |= XHCI_TRB_3_BSR_BIT;
1381 trb.dwTrb3 = htole32(temp);
1383 return (xhci_do_command(sc, &trb, 500 /* ms */));
1387 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1389 struct usb_page_search buf_inp;
1390 struct usb_page_search buf_dev;
1391 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1392 struct xhci_hw_dev *hdev;
1393 struct xhci_dev_ctx *pdev;
1394 struct xhci_endpoint_ext *pepext;
1400 /* the root HUB case is not handled here */
1401 if (udev->parent_hub == NULL)
1402 return (USB_ERR_INVAL);
1404 index = udev->controller_slot_id;
1406 hdev = &sc->sc_hw.devs[index];
1413 switch (hdev->state) {
1414 case XHCI_ST_DEFAULT:
1415 case XHCI_ST_ENABLED:
1417 hdev->state = XHCI_ST_ENABLED;
1419 /* set configure mask to slot and EP0 */
1420 xhci_configure_mask(udev, 3, 0);
1422 /* configure input slot context structure */
1423 err = xhci_configure_device(udev);
1426 DPRINTF("Could not configure device\n");
1430 /* configure input endpoint context structure */
1431 switch (udev->speed) {
1433 case USB_SPEED_FULL:
1436 case USB_SPEED_HIGH:
1444 pepext = xhci_get_endpoint_ext(udev,
1445 &udev->ctrl_ep_desc);
1447 /* ensure the control endpoint is setup again */
1448 USB_BUS_LOCK(udev->bus);
1449 pepext->trb_halted = 1;
1450 pepext->trb_running = 0;
1451 USB_BUS_UNLOCK(udev->bus);
1453 err = xhci_configure_endpoint(udev,
1454 &udev->ctrl_ep_desc, pepext,
1455 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1458 DPRINTF("Could not configure default endpoint\n");
1462 /* execute set address command */
1463 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1465 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1466 (address == 0), index);
1469 temp = le32toh(sc->sc_cmd_result[0]);
1470 if (address == 0 && sc->sc_port_route != NULL &&
1471 XHCI_TRB_2_ERROR_GET(temp) ==
1472 XHCI_TRB_ERROR_PARAMETER) {
1473 /* LynxPoint XHCI - ports are not switchable */
1474 /* Un-route all ports from the XHCI */
1475 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1477 DPRINTF("Could not set address "
1478 "for slot %u.\n", index);
1483 /* update device address to new value */
1485 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1486 pdev = buf_dev.buffer;
1487 usb_pc_cpu_invalidate(&hdev->device_pc);
1489 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1490 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1492 /* update device state to new value */
1495 hdev->state = XHCI_ST_ADDRESSED;
1497 hdev->state = XHCI_ST_DEFAULT;
1501 DPRINTF("Wrong state for set address.\n");
1502 err = USB_ERR_IOERROR;
1505 XHCI_CMD_UNLOCK(sc);
1514 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1515 uint8_t deconfigure, uint8_t slot_id)
1517 struct xhci_trb trb;
1522 trb.qwTrb0 = htole64(input_ctx);
1524 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1525 XHCI_TRB_3_SLOT_SET(slot_id);
1528 temp |= XHCI_TRB_3_DCEP_BIT;
1530 trb.dwTrb3 = htole32(temp);
1532 return (xhci_do_command(sc, &trb, 100 /* ms */));
1536 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1539 struct xhci_trb trb;
1544 trb.qwTrb0 = htole64(input_ctx);
1546 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1547 XHCI_TRB_3_SLOT_SET(slot_id);
1548 trb.dwTrb3 = htole32(temp);
1550 return (xhci_do_command(sc, &trb, 100 /* ms */));
1554 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1555 uint8_t ep_id, uint8_t slot_id)
1557 struct xhci_trb trb;
1564 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1565 XHCI_TRB_3_SLOT_SET(slot_id) |
1566 XHCI_TRB_3_EP_SET(ep_id);
1569 temp |= XHCI_TRB_3_PRSV_BIT;
1571 trb.dwTrb3 = htole32(temp);
1573 return (xhci_do_command(sc, &trb, 100 /* ms */));
1577 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1578 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1580 struct xhci_trb trb;
1585 trb.qwTrb0 = htole64(dequeue_ptr);
1587 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1588 trb.dwTrb2 = htole32(temp);
1590 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1591 XHCI_TRB_3_SLOT_SET(slot_id) |
1592 XHCI_TRB_3_EP_SET(ep_id);
1593 trb.dwTrb3 = htole32(temp);
1595 return (xhci_do_command(sc, &trb, 100 /* ms */));
1599 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1600 uint8_t ep_id, uint8_t slot_id)
1602 struct xhci_trb trb;
1609 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1610 XHCI_TRB_3_SLOT_SET(slot_id) |
1611 XHCI_TRB_3_EP_SET(ep_id);
1614 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1616 trb.dwTrb3 = htole32(temp);
1618 return (xhci_do_command(sc, &trb, 100 /* ms */));
1622 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1624 struct xhci_trb trb;
1631 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1632 XHCI_TRB_3_SLOT_SET(slot_id);
1634 trb.dwTrb3 = htole32(temp);
1636 return (xhci_do_command(sc, &trb, 100 /* ms */));
1639 /*------------------------------------------------------------------------*
1640 * xhci_interrupt - XHCI interrupt handler
1641 *------------------------------------------------------------------------*/
1643 xhci_interrupt(struct xhci_softc *sc)
1648 USB_BUS_LOCK(&sc->sc_bus);
1650 status = XREAD4(sc, oper, XHCI_USBSTS);
1652 /* acknowledge interrupts, if any */
1654 XWRITE4(sc, oper, XHCI_USBSTS, status);
1655 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1658 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1660 /* force clearing of pending interrupts */
1661 if (temp & XHCI_IMAN_INTR_PEND)
1662 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1664 /* check for event(s) */
1665 xhci_interrupt_poll(sc);
1667 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1668 XHCI_STS_HSE | XHCI_STS_HCE)) {
1670 if (status & XHCI_STS_PCD) {
1674 if (status & XHCI_STS_HCH) {
1675 printf("%s: host controller halted\n",
1679 if (status & XHCI_STS_HSE) {
1680 printf("%s: host system error\n",
1684 if (status & XHCI_STS_HCE) {
1685 printf("%s: host controller error\n",
1689 USB_BUS_UNLOCK(&sc->sc_bus);
1692 /*------------------------------------------------------------------------*
1693 * xhci_timeout - XHCI timeout handler
1694 *------------------------------------------------------------------------*/
1696 xhci_timeout(void *arg)
1698 struct usb_xfer *xfer = arg;
1700 DPRINTF("xfer=%p\n", xfer);
1702 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1704 /* transfer is transferred */
1705 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1709 xhci_do_poll(struct usb_bus *bus)
1711 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1713 USB_BUS_LOCK(&sc->sc_bus);
1714 xhci_interrupt_poll(sc);
1715 USB_BUS_UNLOCK(&sc->sc_bus);
1719 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1721 struct usb_page_search buf_res;
1723 struct xhci_td *td_next;
1724 struct xhci_td *td_alt_next;
1725 struct xhci_td *td_first;
1726 uint32_t buf_offset;
1731 uint8_t shortpkt_old;
1737 shortpkt_old = temp->shortpkt;
1738 len_old = temp->len;
1745 td_next = td_first = temp->td_next;
1749 if (temp->len == 0) {
1754 /* send a Zero Length Packet, ZLP, last */
1761 average = temp->average;
1763 if (temp->len < average) {
1764 if (temp->len % temp->max_packet_size) {
1767 average = temp->len;
1771 if (td_next == NULL)
1772 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1777 td_next = td->obj_next;
1779 /* check if we are pre-computing */
1783 /* update remaining length */
1785 temp->len -= average;
1789 /* fill out current TD */
1795 /* update remaining length */
1797 temp->len -= average;
1799 /* reset TRB index */
1803 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1804 /* immediate data */
1809 td->td_trb[0].qwTrb0 = 0;
1811 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1812 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1815 dword = XHCI_TRB_2_BYTES_SET(8) |
1816 XHCI_TRB_2_TDSZ_SET(0) |
1817 XHCI_TRB_2_IRQ_SET(0);
1819 td->td_trb[0].dwTrb2 = htole32(dword);
1821 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1822 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1825 if (td->td_trb[0].qwTrb0 &
1826 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1827 if (td->td_trb[0].qwTrb0 &
1828 htole64(XHCI_TRB_0_DIR_IN_MASK))
1829 dword |= XHCI_TRB_3_TRT_IN;
1831 dword |= XHCI_TRB_3_TRT_OUT;
1834 td->td_trb[0].dwTrb3 = htole32(dword);
1836 xhci_dump_trb(&td->td_trb[x]);
1844 /* fill out buffer pointers */
1847 memset(&buf_res, 0, sizeof(buf_res));
1849 usbd_get_page(temp->pc, temp->offset +
1850 buf_offset, &buf_res);
1852 /* get length to end of page */
1853 if (buf_res.length > average)
1854 buf_res.length = average;
1856 /* check for maximum length */
1857 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1858 buf_res.length = XHCI_TD_PAGE_SIZE;
1860 npkt_off += buf_res.length;
1864 npkt = howmany(len_old - npkt_off,
1865 temp->max_packet_size);
1872 /* fill out TRB's */
1873 td->td_trb[x].qwTrb0 =
1874 htole64((uint64_t)buf_res.physaddr);
1877 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1878 XHCI_TRB_2_TDSZ_SET(npkt) |
1879 XHCI_TRB_2_IRQ_SET(0);
1881 td->td_trb[x].dwTrb2 = htole32(dword);
1883 switch (temp->trb_type) {
1884 case XHCI_TRB_TYPE_ISOCH:
1885 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1886 XHCI_TRB_3_TBC_SET(temp->tbc) |
1887 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1888 if (td != td_first) {
1889 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1890 } else if (temp->do_isoc_sync != 0) {
1891 temp->do_isoc_sync = 0;
1892 /* wait until "isoc_frame" */
1893 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1894 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1896 /* start data transfer at next interval */
1897 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1898 XHCI_TRB_3_ISO_SIA_BIT;
1900 if (temp->direction == UE_DIR_IN)
1901 dword |= XHCI_TRB_3_ISP_BIT;
1903 case XHCI_TRB_TYPE_DATA_STAGE:
1904 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1905 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1906 if (temp->direction == UE_DIR_IN)
1907 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1909 * Section 3.2.9 in the XHCI
1910 * specification about control
1911 * transfers says that we should use a
1912 * normal-TRB if there are more TRBs
1913 * extending the data-stage
1914 * TRB. Update the "trb_type".
1916 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1918 case XHCI_TRB_TYPE_STATUS_STAGE:
1919 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1920 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1921 if (temp->direction == UE_DIR_IN)
1922 dword |= XHCI_TRB_3_DIR_IN;
1924 default: /* XHCI_TRB_TYPE_NORMAL */
1925 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1926 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1927 if (temp->direction == UE_DIR_IN)
1928 dword |= XHCI_TRB_3_ISP_BIT;
1931 td->td_trb[x].dwTrb3 = htole32(dword);
1933 average -= buf_res.length;
1934 buf_offset += buf_res.length;
1936 xhci_dump_trb(&td->td_trb[x]);
1940 } while (average != 0);
1942 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1944 /* store number of data TRB's */
1948 DPRINTF("NTRB=%u\n", x);
1950 /* fill out link TRB */
1952 if (td_next != NULL) {
1953 /* link the current TD with the next one */
1954 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1955 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1957 /* this field will get updated later */
1958 DPRINTF("NOLINK\n");
1961 dword = XHCI_TRB_2_IRQ_SET(0);
1963 td->td_trb[x].dwTrb2 = htole32(dword);
1965 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1966 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1968 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1969 * frame only receives a single short packet event
1970 * by setting the CHAIN bit in the LINK field. In
1971 * addition some XHCI controllers have problems
1972 * sending a ZLP unless the CHAIN-BIT is set in
1975 XHCI_TRB_3_CHAIN_BIT;
1977 td->td_trb[x].dwTrb3 = htole32(dword);
1979 td->alt_next = td_alt_next;
1981 xhci_dump_trb(&td->td_trb[x]);
1983 usb_pc_cpu_flush(td->page_cache);
1989 /* set up alt next pointer, if any */
1990 if (temp->last_frame) {
1993 /* we use this field internally */
1994 td_alt_next = td_next;
1998 temp->shortpkt = shortpkt_old;
1999 temp->len = len_old;
2004 * Remove cycle bit from the first TRB if we are
2007 if (temp->step_td != 0) {
2008 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
2009 usb_pc_cpu_flush(td_first->page_cache);
2012 /* clear TD SIZE to zero, hence this is the last TRB */
2013 /* remove chain bit because this is the last data TRB in the chain */
2014 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(31));
2015 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2016 /* remove CHAIN-BIT from last LINK TRB */
2017 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2019 usb_pc_cpu_flush(td->page_cache);
2022 temp->td_next = td_next;
2026 xhci_setup_generic_chain(struct usb_xfer *xfer)
2028 struct xhci_std_temp temp;
2034 temp.do_isoc_sync = 0;
2038 temp.average = xfer->max_hc_frame_size;
2039 temp.max_packet_size = xfer->max_packet_size;
2040 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2042 temp.last_frame = 0;
2044 temp.multishort = xfer->flags_int.isochronous_xfr ||
2045 xfer->flags_int.control_xfr ||
2046 xfer->flags_int.short_frames_ok;
2048 /* toggle the DMA set we are using */
2049 xfer->flags_int.curr_dma_set ^= 1;
2051 /* get next DMA set */
2052 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2057 xfer->td_transfer_first = td;
2058 xfer->td_transfer_cache = td;
2060 if (xfer->flags_int.isochronous_xfr) {
2063 /* compute multiplier for ISOCHRONOUS transfers */
2064 mult = xfer->endpoint->ecomp ?
2065 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2067 /* check for USB 2.0 multiplier */
2069 mult = (xfer->endpoint->edesc->
2070 wMaxPacketSize[1] >> 3) & 3;
2078 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2080 DPRINTF("MFINDEX=0x%08x\n", x);
2082 switch (usbd_get_speed(xfer->xroot->udev)) {
2083 case USB_SPEED_FULL:
2085 temp.isoc_delta = 8; /* 1ms */
2086 x += temp.isoc_delta - 1;
2087 x &= ~(temp.isoc_delta - 1);
2090 shift = usbd_xfer_get_fps_shift(xfer);
2091 temp.isoc_delta = 1U << shift;
2092 x += temp.isoc_delta - 1;
2093 x &= ~(temp.isoc_delta - 1);
2094 /* simple frame load balancing */
2095 x += xfer->endpoint->usb_uframe;
2099 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2101 if ((xfer->endpoint->is_synced == 0) ||
2102 (y < (xfer->nframes << shift)) ||
2103 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2105 * If there is data underflow or the pipe
2106 * queue is empty we schedule the transfer a
2107 * few frames ahead of the current frame
2108 * position. Else two isochronous transfers
2111 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2112 xfer->endpoint->is_synced = 1;
2113 temp.do_isoc_sync = 1;
2115 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2118 /* compute isochronous completion time */
2120 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2122 xfer->isoc_time_complete =
2123 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2124 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2127 temp.isoc_frame = xfer->endpoint->isoc_next;
2128 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2130 xfer->endpoint->isoc_next += xfer->nframes << shift;
2132 } else if (xfer->flags_int.control_xfr) {
2134 /* check if we should prepend a setup message */
2136 if (xfer->flags_int.control_hdr) {
2138 temp.len = xfer->frlengths[0];
2139 temp.pc = xfer->frbuffers + 0;
2140 temp.shortpkt = temp.len ? 1 : 0;
2141 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2144 /* check for last frame */
2145 if (xfer->nframes == 1) {
2146 /* no STATUS stage yet, SETUP is last */
2147 if (xfer->flags_int.control_act)
2148 temp.last_frame = 1;
2151 xhci_setup_generic_chain_sub(&temp);
2155 temp.isoc_delta = 0;
2156 temp.isoc_frame = 0;
2157 temp.trb_type = xfer->flags_int.control_did_data ?
2158 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2162 temp.isoc_delta = 0;
2163 temp.isoc_frame = 0;
2164 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2167 if (x != xfer->nframes) {
2168 /* set up page_cache pointer */
2169 temp.pc = xfer->frbuffers + x;
2170 /* set endpoint direction */
2171 temp.direction = UE_GET_DIR(xfer->endpointno);
2174 while (x != xfer->nframes) {
2176 /* DATA0 / DATA1 message */
2178 temp.len = xfer->frlengths[x];
2179 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2180 x != 0 && temp.multishort == 0);
2184 if (x == xfer->nframes) {
2185 if (xfer->flags_int.control_xfr) {
2186 /* no STATUS stage yet, DATA is last */
2187 if (xfer->flags_int.control_act)
2188 temp.last_frame = 1;
2190 temp.last_frame = 1;
2193 if (temp.len == 0) {
2195 /* make sure that we send an USB packet */
2200 temp.tlbpc = mult - 1;
2202 } else if (xfer->flags_int.isochronous_xfr) {
2207 * Isochronous transfers don't have short
2208 * packet termination:
2213 /* isochronous transfers have a transfer limit */
2215 if (temp.len > xfer->max_frame_size)
2216 temp.len = xfer->max_frame_size;
2218 /* compute TD packet count */
2219 tdpc = howmany(temp.len, xfer->max_packet_size);
2221 temp.tbc = howmany(tdpc, mult) - 1;
2222 temp.tlbpc = (tdpc % mult);
2224 if (temp.tlbpc == 0)
2225 temp.tlbpc = mult - 1;
2230 /* regular data transfer */
2232 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2235 xhci_setup_generic_chain_sub(&temp);
2237 if (xfer->flags_int.isochronous_xfr) {
2238 temp.offset += xfer->frlengths[x - 1];
2239 temp.isoc_frame += temp.isoc_delta;
2241 /* get next Page Cache pointer */
2242 temp.pc = xfer->frbuffers + x;
2246 /* check if we should append a status stage */
2248 if (xfer->flags_int.control_xfr &&
2249 !xfer->flags_int.control_act) {
2252 * Send a DATA1 message and invert the current
2253 * endpoint direction.
2255 if (xhcictlstep || temp.sc->sc_ctlstep) {
2257 * Some XHCI controllers will not delay the
2258 * status stage until the next SOF. Force this
2259 * behaviour to avoid failed control
2262 temp.step_td = (xfer->nframes != 0);
2266 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2270 temp.last_frame = 1;
2271 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2273 xhci_setup_generic_chain_sub(&temp);
2278 /* must have at least one frame! */
2280 xfer->td_transfer_last = td;
2282 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2286 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2288 struct usb_page_search buf_res;
2289 struct xhci_dev_ctx_addr *pdctxa;
2291 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2293 pdctxa = buf_res.buffer;
2295 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2297 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2299 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2303 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2305 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2306 struct usb_page_search buf_inp;
2307 struct xhci_input_dev_ctx *pinp;
2312 index = udev->controller_slot_id;
2314 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2316 pinp = buf_inp.buffer;
2319 mask &= XHCI_INCTX_NON_CTRL_MASK;
2320 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2321 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2324 * Some hardware requires that we drop the endpoint
2325 * context before adding it again:
2327 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2328 mask & XHCI_INCTX_NON_CTRL_MASK);
2330 /* Add new endpoint context */
2331 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2333 /* find most significant set bit */
2334 for (x = 31; x != 1; x--) {
2335 if (mask & (1 << x))
2342 /* figure out the maximum number of contexts */
2343 if (x > sc->sc_hw.devs[index].context_num)
2344 sc->sc_hw.devs[index].context_num = x;
2346 x = sc->sc_hw.devs[index].context_num;
2348 /* update number of contexts */
2349 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2350 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2351 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2352 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2354 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2359 xhci_configure_endpoint(struct usb_device *udev,
2360 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2361 uint16_t interval, uint8_t max_packet_count,
2362 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2363 uint16_t max_frame_size, uint8_t ep_mode)
2365 struct usb_page_search buf_inp;
2366 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2367 struct xhci_input_dev_ctx *pinp;
2368 uint64_t ring_addr = pepext->physaddr;
2374 index = udev->controller_slot_id;
2376 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2378 pinp = buf_inp.buffer;
2380 epno = edesc->bEndpointAddress;
2381 type = edesc->bmAttributes & UE_XFERTYPE;
2383 if (type == UE_CONTROL)
2386 epno = XHCI_EPNO2EPID(epno);
2389 return (USB_ERR_NO_PIPE); /* invalid */
2391 if (max_packet_count == 0)
2392 return (USB_ERR_BAD_BUFSIZE);
2397 return (USB_ERR_BAD_BUFSIZE);
2399 /* store endpoint mode */
2400 pepext->trb_ep_mode = ep_mode;
2401 /* store bMaxPacketSize for control endpoints */
2402 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2403 usb_pc_cpu_flush(pepext->page_cache);
2405 if (ep_mode == USB_EP_MODE_STREAMS) {
2406 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2407 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2408 XHCI_EPCTX_0_LSA_SET(1);
2410 ring_addr += sizeof(struct xhci_trb) *
2411 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2413 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2414 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2415 XHCI_EPCTX_0_LSA_SET(0);
2417 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2420 switch (udev->speed) {
2421 case USB_SPEED_FULL:
2434 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2436 case UE_ISOCHRONOUS:
2437 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2439 switch (udev->speed) {
2440 case USB_SPEED_SUPER:
2443 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2444 max_packet_count /= mult;
2454 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2457 XHCI_EPCTX_1_HID_SET(0) |
2458 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2459 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2462 * Always enable the "three strikes and you are gone" feature
2463 * except for ISOCHRONOUS endpoints. This is suggested by
2464 * section 4.3.3 in the XHCI specification about device slot
2467 if (type != UE_ISOCHRONOUS)
2468 temp |= XHCI_EPCTX_1_CERR_SET(3);
2472 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2474 case UE_ISOCHRONOUS:
2475 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2478 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2481 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2485 /* check for IN direction */
2487 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2489 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2490 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2492 switch (edesc->bmAttributes & UE_XFERTYPE) {
2494 case UE_ISOCHRONOUS:
2495 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2496 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2500 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2503 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2507 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2510 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2512 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2514 return (0); /* success */
2518 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2520 struct xhci_endpoint_ext *pepext;
2521 struct usb_endpoint_ss_comp_descriptor *ecomp;
2524 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2525 xfer->endpoint->edesc);
2527 ecomp = xfer->endpoint->ecomp;
2529 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2532 /* halt any transfers */
2533 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2535 /* compute start of TRB ring for stream "x" */
2536 temp = pepext->physaddr +
2537 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2538 XHCI_SCTX_0_SCT_SEC_TR_RING;
2540 /* make tree structure */
2541 pepext->trb[(XHCI_MAX_TRANSFERS *
2542 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2544 /* reserved fields */
2545 pepext->trb[(XHCI_MAX_TRANSFERS *
2546 XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2547 pepext->trb[(XHCI_MAX_TRANSFERS *
2548 XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2550 usb_pc_cpu_flush(pepext->page_cache);
2552 return (xhci_configure_endpoint(xfer->xroot->udev,
2553 xfer->endpoint->edesc, pepext,
2554 xfer->interval, xfer->max_packet_count,
2555 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2556 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2557 xfer->max_frame_size, xfer->endpoint->ep_mode));
2561 xhci_configure_device(struct usb_device *udev)
2563 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2564 struct usb_page_search buf_inp;
2565 struct usb_page_cache *pcinp;
2566 struct xhci_input_dev_ctx *pinp;
2567 struct usb_device *hubdev;
2575 index = udev->controller_slot_id;
2577 DPRINTF("index=%u\n", index);
2579 pcinp = &sc->sc_hw.devs[index].input_pc;
2581 usbd_get_page(pcinp, 0, &buf_inp);
2583 pinp = buf_inp.buffer;
2588 /* figure out route string and root HUB port number */
2590 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2592 if (hubdev->parent_hub == NULL)
2595 depth = hubdev->parent_hub->depth;
2598 * NOTE: HS/FS/LS devices and the SS root HUB can have
2599 * more than 15 ports
2602 rh_port = hubdev->port_no;
2611 route |= rh_port << (4 * (depth - 1));
2614 DPRINTF("Route=0x%08x\n", route);
2616 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2617 XHCI_SCTX_0_CTX_NUM_SET(
2618 sc->sc_hw.devs[index].context_num + 1);
2620 switch (udev->speed) {
2622 temp |= XHCI_SCTX_0_SPEED_SET(2);
2623 if (udev->parent_hs_hub != NULL &&
2624 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2626 DPRINTF("Device inherits MTT\n");
2627 temp |= XHCI_SCTX_0_MTT_SET(1);
2630 case USB_SPEED_HIGH:
2631 temp |= XHCI_SCTX_0_SPEED_SET(3);
2632 if (sc->sc_hw.devs[index].nports != 0 &&
2633 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2634 DPRINTF("HUB supports MTT\n");
2635 temp |= XHCI_SCTX_0_MTT_SET(1);
2638 case USB_SPEED_FULL:
2639 temp |= XHCI_SCTX_0_SPEED_SET(1);
2640 if (udev->parent_hs_hub != NULL &&
2641 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2643 DPRINTF("Device inherits MTT\n");
2644 temp |= XHCI_SCTX_0_MTT_SET(1);
2648 temp |= XHCI_SCTX_0_SPEED_SET(4);
2652 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2653 (udev->speed == USB_SPEED_SUPER ||
2654 udev->speed == USB_SPEED_HIGH);
2657 temp |= XHCI_SCTX_0_HUB_SET(1);
2659 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2661 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2664 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2665 sc->sc_hw.devs[index].nports);
2668 switch (udev->speed) {
2669 case USB_SPEED_SUPER:
2670 switch (sc->sc_hw.devs[index].state) {
2671 case XHCI_ST_ADDRESSED:
2672 case XHCI_ST_CONFIGURED:
2673 /* enable power save */
2674 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2677 /* disable power save */
2685 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2687 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2690 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2691 sc->sc_hw.devs[index].tt);
2694 hubdev = udev->parent_hs_hub;
2696 /* check if we should activate the transaction translator */
2697 switch (udev->speed) {
2698 case USB_SPEED_FULL:
2700 if (hubdev != NULL) {
2701 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2702 hubdev->controller_slot_id);
2703 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2711 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2714 * These fields should be initialized to zero, according to
2715 * XHCI section 6.2.2 - slot context:
2717 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2718 XHCI_SCTX_3_SLOT_STATE_SET(0);
2720 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2723 xhci_dump_device(sc, &pinp->ctx_slot);
2725 usb_pc_cpu_flush(pcinp);
2727 return (0); /* success */
2731 xhci_alloc_device_ext(struct usb_device *udev)
2733 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2734 struct usb_page_search buf_dev;
2735 struct usb_page_search buf_ep;
2736 struct xhci_trb *trb;
2737 struct usb_page_cache *pc;
2738 struct usb_page *pg;
2743 index = udev->controller_slot_id;
2745 pc = &sc->sc_hw.devs[index].device_pc;
2746 pg = &sc->sc_hw.devs[index].device_pg;
2748 /* need to initialize the page cache */
2749 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2751 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2752 (2 * sizeof(struct xhci_dev_ctx)) :
2753 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2756 usbd_get_page(pc, 0, &buf_dev);
2758 pc = &sc->sc_hw.devs[index].input_pc;
2759 pg = &sc->sc_hw.devs[index].input_pg;
2761 /* need to initialize the page cache */
2762 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2764 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2765 (2 * sizeof(struct xhci_input_dev_ctx)) :
2766 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2770 /* initialize all endpoint LINK TRBs */
2772 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2774 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2775 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2777 /* need to initialize the page cache */
2778 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2780 if (usb_pc_alloc_mem(pc, pg,
2781 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2785 /* lookup endpoint TRB ring */
2786 usbd_get_page(pc, 0, &buf_ep);
2788 /* get TRB pointer */
2789 trb = buf_ep.buffer;
2790 trb += XHCI_MAX_TRANSFERS - 1;
2792 /* get TRB start address */
2793 addr = buf_ep.physaddr;
2795 /* create LINK TRB */
2796 trb->qwTrb0 = htole64(addr);
2797 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2798 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2799 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2801 usb_pc_cpu_flush(pc);
2804 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2809 xhci_free_device_ext(udev);
2811 return (USB_ERR_NOMEM);
2815 xhci_free_device_ext(struct usb_device *udev)
2817 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2821 index = udev->controller_slot_id;
2822 xhci_set_slot_pointer(sc, index, 0);
2824 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2825 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2826 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2827 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2830 static struct xhci_endpoint_ext *
2831 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2833 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2834 struct xhci_endpoint_ext *pepext;
2835 struct usb_page_cache *pc;
2836 struct usb_page_search buf_ep;
2840 epno = edesc->bEndpointAddress;
2841 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2844 epno = XHCI_EPNO2EPID(epno);
2846 index = udev->controller_slot_id;
2848 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2850 usbd_get_page(pc, 0, &buf_ep);
2852 pepext = &sc->sc_hw.devs[index].endp[epno];
2853 pepext->page_cache = pc;
2854 pepext->trb = buf_ep.buffer;
2855 pepext->physaddr = buf_ep.physaddr;
2861 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2863 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2867 epno = xfer->endpointno;
2868 if (xfer->flags_int.control_xfr)
2871 epno = XHCI_EPNO2EPID(epno);
2872 index = xfer->xroot->udev->controller_slot_id;
2874 if (xfer->xroot->udev->flags.self_suspended == 0) {
2875 XWRITE4(sc, door, XHCI_DOORBELL(index),
2876 epno | XHCI_DB_SID_SET(xfer->stream_id));
2881 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2883 struct xhci_endpoint_ext *pepext;
2885 if (xfer->flags_int.bandwidth_reclaimed) {
2886 xfer->flags_int.bandwidth_reclaimed = 0;
2888 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2889 xfer->endpoint->edesc);
2891 pepext->trb_used[xfer->stream_id]--;
2893 pepext->xfer[xfer->qh_pos] = NULL;
2895 if (error && pepext->trb_running != 0) {
2896 pepext->trb_halted = 1;
2897 pepext->trb_running = 0;
2903 xhci_transfer_insert(struct usb_xfer *xfer)
2905 struct xhci_td *td_first;
2906 struct xhci_td *td_last;
2907 struct xhci_trb *trb_link;
2908 struct xhci_endpoint_ext *pepext;
2917 id = xfer->stream_id;
2919 /* check if already inserted */
2920 if (xfer->flags_int.bandwidth_reclaimed) {
2921 DPRINTFN(8, "Already in schedule\n");
2925 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2926 xfer->endpoint->edesc);
2928 td_first = xfer->td_transfer_first;
2929 td_last = xfer->td_transfer_last;
2930 addr = pepext->physaddr;
2932 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2935 /* single buffered */
2939 /* multi buffered */
2940 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2944 if (pepext->trb_used[id] >= trb_limit) {
2945 DPRINTFN(8, "Too many TDs queued.\n");
2946 return (USB_ERR_NOMEM);
2949 /* check if bMaxPacketSize changed */
2950 if (xfer->flags_int.control_xfr != 0 &&
2951 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2953 DPRINTFN(8, "Reconfigure control endpoint\n");
2955 /* force driver to reconfigure endpoint */
2956 pepext->trb_halted = 1;
2957 pepext->trb_running = 0;
2960 /* check for stopped condition, after putting transfer on interrupt queue */
2961 if (pepext->trb_running == 0) {
2962 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2964 DPRINTFN(8, "Not running\n");
2966 /* start configuration */
2967 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2968 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2972 pepext->trb_used[id]++;
2974 /* get current TRB index */
2975 i = pepext->trb_index[id];
2977 /* get next TRB index */
2980 /* the last entry of the ring is a hardcoded link TRB */
2981 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2984 /* store next TRB index, before stream ID offset is added */
2985 pepext->trb_index[id] = inext;
2987 /* offset for stream */
2988 i += id * XHCI_MAX_TRANSFERS;
2989 inext += id * XHCI_MAX_TRANSFERS;
2991 /* compute terminating return address */
2992 addr += (inext * sizeof(struct xhci_trb));
2994 /* compute link TRB pointer */
2995 trb_link = td_last->td_trb + td_last->ntrb;
2997 /* update next pointer of last link TRB */
2998 trb_link->qwTrb0 = htole64(addr);
2999 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3000 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
3001 XHCI_TRB_3_CYCLE_BIT |
3002 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3005 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
3007 usb_pc_cpu_flush(td_last->page_cache);
3009 /* write ahead chain end marker */
3011 pepext->trb[inext].qwTrb0 = 0;
3012 pepext->trb[inext].dwTrb2 = 0;
3013 pepext->trb[inext].dwTrb3 = 0;
3015 /* update next pointer of link TRB */
3017 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
3018 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3021 xhci_dump_trb(&pepext->trb[i]);
3023 usb_pc_cpu_flush(pepext->page_cache);
3025 /* toggle cycle bit which activates the transfer chain */
3027 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
3028 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3030 usb_pc_cpu_flush(pepext->page_cache);
3032 DPRINTF("qh_pos = %u\n", i);
3034 pepext->xfer[i] = xfer;
3038 xfer->flags_int.bandwidth_reclaimed = 1;
3040 xhci_endpoint_doorbell(xfer);
3046 xhci_root_intr(struct xhci_softc *sc)
3050 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3052 /* clear any old interrupt data */
3053 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3055 for (i = 1; i <= sc->sc_noport; i++) {
3056 /* pick out CHANGE bits from the status register */
3057 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3058 XHCI_PS_CSC | XHCI_PS_PEC |
3059 XHCI_PS_OCC | XHCI_PS_WRC |
3060 XHCI_PS_PRC | XHCI_PS_PLC |
3062 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3063 DPRINTF("port %d changed\n", i);
3066 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3067 sizeof(sc->sc_hub_idata));
3070 /*------------------------------------------------------------------------*
3071 * xhci_device_done - XHCI done handler
3073 * NOTE: This function can be called two times in a row on
3074 * the same USB transfer. From close and from interrupt.
3075 *------------------------------------------------------------------------*/
3077 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3079 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3080 xfer, xfer->endpoint, error);
3082 /* remove transfer from HW queue */
3083 xhci_transfer_remove(xfer, error);
3085 /* dequeue transfer and start next transfer */
3086 usbd_transfer_done(xfer, error);
3089 /*------------------------------------------------------------------------*
3090 * XHCI data transfer support (generic type)
3091 *------------------------------------------------------------------------*/
3093 xhci_device_generic_open(struct usb_xfer *xfer)
3095 if (xfer->flags_int.isochronous_xfr) {
3096 switch (xfer->xroot->udev->speed) {
3097 case USB_SPEED_FULL:
3100 usb_hs_bandwidth_alloc(xfer);
3107 xhci_device_generic_close(struct usb_xfer *xfer)
3111 xhci_device_done(xfer, USB_ERR_CANCELLED);
3113 if (xfer->flags_int.isochronous_xfr) {
3114 switch (xfer->xroot->udev->speed) {
3115 case USB_SPEED_FULL:
3118 usb_hs_bandwidth_free(xfer);
3125 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3126 usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3128 struct usb_xfer *xfer;
3130 /* check if there is a current transfer */
3131 xfer = ep->endpoint_q[stream_id].curr;
3136 * Check if the current transfer is started and then pickup
3137 * the next one, if any. Else wait for next start event due to
3138 * block on failure feature.
3140 if (!xfer->flags_int.bandwidth_reclaimed)
3143 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3146 * In case of enter we have to consider that the
3147 * transfer is queued by the USB core after the enter
3156 /* try to multi buffer */
3157 xhci_transfer_insert(xfer);
3161 xhci_device_generic_enter(struct usb_xfer *xfer)
3165 /* set up TD's and QH */
3166 xhci_setup_generic_chain(xfer);
3168 xhci_device_generic_multi_enter(xfer->endpoint,
3169 xfer->stream_id, xfer);
3173 xhci_device_generic_start(struct usb_xfer *xfer)
3177 /* try to insert xfer on HW queue */
3178 xhci_transfer_insert(xfer);
3180 /* try to multi buffer */
3181 xhci_device_generic_multi_enter(xfer->endpoint,
3182 xfer->stream_id, NULL);
3184 /* add transfer last on interrupt queue */
3185 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3187 /* start timeout, if any */
3188 if (xfer->timeout != 0)
3189 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3192 static const struct usb_pipe_methods xhci_device_generic_methods =
3194 .open = xhci_device_generic_open,
3195 .close = xhci_device_generic_close,
3196 .enter = xhci_device_generic_enter,
3197 .start = xhci_device_generic_start,
3200 /*------------------------------------------------------------------------*
3201 * xhci root HUB support
3202 *------------------------------------------------------------------------*
3203 * Simulate a hardware HUB by handling all the necessary requests.
3204 *------------------------------------------------------------------------*/
3206 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3209 struct usb_device_descriptor xhci_devd =
3211 .bLength = sizeof(xhci_devd),
3212 .bDescriptorType = UDESC_DEVICE, /* type */
3213 HSETW(.bcdUSB, 0x0300), /* USB version */
3214 .bDeviceClass = UDCLASS_HUB, /* class */
3215 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3216 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3217 .bMaxPacketSize = 9, /* max packet size */
3218 HSETW(.idVendor, 0x0000), /* vendor */
3219 HSETW(.idProduct, 0x0000), /* product */
3220 HSETW(.bcdDevice, 0x0100), /* device version */
3224 .bNumConfigurations = 1, /* # of configurations */
3228 struct xhci_bos_desc xhci_bosd = {
3230 .bLength = sizeof(xhci_bosd.bosd),
3231 .bDescriptorType = UDESC_BOS,
3232 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3233 .bNumDeviceCaps = 3,
3236 .bLength = sizeof(xhci_bosd.usb2extd),
3237 .bDescriptorType = 1,
3238 .bDevCapabilityType = 2,
3239 .bmAttributes[0] = 2,
3242 .bLength = sizeof(xhci_bosd.usbdcd),
3243 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3244 .bDevCapabilityType = 3,
3245 .bmAttributes = 0, /* XXX */
3246 HSETW(.wSpeedsSupported, 0x000C),
3247 .bFunctionalitySupport = 8,
3248 .bU1DevExitLat = 255, /* dummy - not used */
3249 .wU2DevExitLat = { 0x00, 0x08 },
3252 .bLength = sizeof(xhci_bosd.cidd),
3253 .bDescriptorType = 1,
3254 .bDevCapabilityType = 4,
3256 .bContainerID = 0, /* XXX */
3261 struct xhci_config_desc xhci_confd = {
3263 .bLength = sizeof(xhci_confd.confd),
3264 .bDescriptorType = UDESC_CONFIG,
3265 .wTotalLength[0] = sizeof(xhci_confd),
3267 .bConfigurationValue = 1,
3268 .iConfiguration = 0,
3269 .bmAttributes = UC_SELF_POWERED,
3270 .bMaxPower = 0 /* max power */
3273 .bLength = sizeof(xhci_confd.ifcd),
3274 .bDescriptorType = UDESC_INTERFACE,
3276 .bInterfaceClass = UICLASS_HUB,
3277 .bInterfaceSubClass = UISUBCLASS_HUB,
3278 .bInterfaceProtocol = 0,
3281 .bLength = sizeof(xhci_confd.endpd),
3282 .bDescriptorType = UDESC_ENDPOINT,
3283 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3284 .bmAttributes = UE_INTERRUPT,
3285 .wMaxPacketSize[0] = 2, /* max 15 ports */
3289 .bLength = sizeof(xhci_confd.endpcd),
3290 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3297 struct usb_hub_ss_descriptor xhci_hubd = {
3298 .bLength = sizeof(xhci_hubd),
3299 .bDescriptorType = UDESC_SS_HUB,
3303 xhci_roothub_exec(struct usb_device *udev,
3304 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3306 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3307 const char *str_ptr;
3318 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3321 ptr = (const void *)&sc->sc_hub_desc;
3325 value = UGETW(req->wValue);
3326 index = UGETW(req->wIndex);
3328 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3329 "wValue=0x%04x wIndex=0x%04x\n",
3330 req->bmRequestType, req->bRequest,
3331 UGETW(req->wLength), value, index);
3333 #define C(x,y) ((x) | ((y) << 8))
3334 switch (C(req->bRequest, req->bmRequestType)) {
3335 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3336 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3337 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3339 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3340 * for the integrated root hub.
3343 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3345 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3347 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3348 switch (value >> 8) {
3350 if ((value & 0xff) != 0) {
3351 err = USB_ERR_IOERROR;
3354 len = sizeof(xhci_devd);
3355 ptr = (const void *)&xhci_devd;
3359 if ((value & 0xff) != 0) {
3360 err = USB_ERR_IOERROR;
3363 len = sizeof(xhci_bosd);
3364 ptr = (const void *)&xhci_bosd;
3368 if ((value & 0xff) != 0) {
3369 err = USB_ERR_IOERROR;
3372 len = sizeof(xhci_confd);
3373 ptr = (const void *)&xhci_confd;
3377 switch (value & 0xff) {
3378 case 0: /* Language table */
3382 case 1: /* Vendor */
3383 str_ptr = sc->sc_vendor;
3386 case 2: /* Product */
3387 str_ptr = "XHCI root HUB";
3395 len = usb_make_str_desc(
3396 sc->sc_hub_desc.temp,
3397 sizeof(sc->sc_hub_desc.temp),
3402 err = USB_ERR_IOERROR;
3406 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3408 sc->sc_hub_desc.temp[0] = 0;
3410 case C(UR_GET_STATUS, UT_READ_DEVICE):
3412 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3414 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3415 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3417 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3419 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3420 if (value >= XHCI_MAX_DEVICES) {
3421 err = USB_ERR_IOERROR;
3425 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3426 if (value != 0 && value != 1) {
3427 err = USB_ERR_IOERROR;
3430 sc->sc_conf = value;
3432 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3434 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3435 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3436 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3437 err = USB_ERR_IOERROR;
3439 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3441 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3444 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3446 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3447 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3450 (index > sc->sc_noport)) {
3451 err = USB_ERR_IOERROR;
3454 port = XHCI_PORTSC(index);
3456 v = XREAD4(sc, oper, port);
3457 i = XHCI_PS_PLS_GET(v);
3458 v &= ~XHCI_PS_CLEAR;
3461 case UHF_C_BH_PORT_RESET:
3462 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3464 case UHF_C_PORT_CONFIG_ERROR:
3465 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3467 case UHF_C_PORT_SUSPEND:
3468 case UHF_C_PORT_LINK_STATE:
3469 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3471 case UHF_C_PORT_CONNECTION:
3472 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3474 case UHF_C_PORT_ENABLE:
3475 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3477 case UHF_C_PORT_OVER_CURRENT:
3478 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3480 case UHF_C_PORT_RESET:
3481 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3483 case UHF_PORT_ENABLE:
3484 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3486 case UHF_PORT_POWER:
3487 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3489 case UHF_PORT_INDICATOR:
3490 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3492 case UHF_PORT_SUSPEND:
3496 XWRITE4(sc, oper, port, v |
3497 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3500 /* wait 20ms for resume sequence to complete */
3501 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3504 XWRITE4(sc, oper, port, v |
3505 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3508 err = USB_ERR_IOERROR;
3513 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3514 if ((value & 0xff) != 0) {
3515 err = USB_ERR_IOERROR;
3519 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3521 sc->sc_hub_desc.hubd = xhci_hubd;
3523 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3525 if (XHCI_HCS0_PPC(v))
3526 i = UHD_PWR_INDIVIDUAL;
3530 if (XHCI_HCS0_PIND(v))
3533 i |= UHD_OC_INDIVIDUAL;
3535 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3537 /* see XHCI section 5.4.9: */
3538 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3540 for (j = 1; j <= sc->sc_noport; j++) {
3542 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3543 if (v & XHCI_PS_DR) {
3544 sc->sc_hub_desc.hubd.
3545 DeviceRemovable[j / 8] |= 1U << (j % 8);
3548 len = sc->sc_hub_desc.hubd.bLength;
3551 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3553 memset(sc->sc_hub_desc.temp, 0, 16);
3556 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3557 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3560 (index > sc->sc_noport)) {
3561 err = USB_ERR_IOERROR;
3565 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3567 DPRINTFN(9, "port status=0x%08x\n", v);
3569 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3571 switch (XHCI_PS_SPEED_GET(v)) {
3573 i |= UPS_HIGH_SPEED;
3582 i |= UPS_OTHER_SPEED;
3586 if (v & XHCI_PS_CCS)
3587 i |= UPS_CURRENT_CONNECT_STATUS;
3588 if (v & XHCI_PS_PED)
3589 i |= UPS_PORT_ENABLED;
3590 if (v & XHCI_PS_OCA)
3591 i |= UPS_OVERCURRENT_INDICATOR;
3594 if (v & XHCI_PS_PP) {
3596 * The USB 3.0 RH is using the
3597 * USB 2.0's power bit
3599 i |= UPS_PORT_POWER;
3601 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3604 if (v & XHCI_PS_CSC)
3605 i |= UPS_C_CONNECT_STATUS;
3606 if (v & XHCI_PS_PEC)
3607 i |= UPS_C_PORT_ENABLED;
3608 if (v & XHCI_PS_OCC)
3609 i |= UPS_C_OVERCURRENT_INDICATOR;
3610 if (v & XHCI_PS_WRC)
3611 i |= UPS_C_BH_PORT_RESET;
3612 if (v & XHCI_PS_PRC)
3613 i |= UPS_C_PORT_RESET;
3614 if (v & XHCI_PS_PLC)
3615 i |= UPS_C_PORT_LINK_STATE;
3616 if (v & XHCI_PS_CEC)
3617 i |= UPS_C_PORT_CONFIG_ERROR;
3619 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3620 len = sizeof(sc->sc_hub_desc.ps);
3623 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3624 err = USB_ERR_IOERROR;
3627 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3630 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3636 (index > sc->sc_noport)) {
3637 err = USB_ERR_IOERROR;
3641 port = XHCI_PORTSC(index);
3642 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3645 case UHF_PORT_U1_TIMEOUT:
3646 if (XHCI_PS_SPEED_GET(v) != 4) {
3647 err = USB_ERR_IOERROR;
3650 port = XHCI_PORTPMSC(index);
3651 v = XREAD4(sc, oper, port);
3652 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3653 v |= XHCI_PM3_U1TO_SET(i);
3654 XWRITE4(sc, oper, port, v);
3656 case UHF_PORT_U2_TIMEOUT:
3657 if (XHCI_PS_SPEED_GET(v) != 4) {
3658 err = USB_ERR_IOERROR;
3661 port = XHCI_PORTPMSC(index);
3662 v = XREAD4(sc, oper, port);
3663 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3664 v |= XHCI_PM3_U2TO_SET(i);
3665 XWRITE4(sc, oper, port, v);
3667 case UHF_BH_PORT_RESET:
3668 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3670 case UHF_PORT_LINK_STATE:
3671 XWRITE4(sc, oper, port, v |
3672 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3673 /* 4ms settle time */
3674 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3676 case UHF_PORT_ENABLE:
3677 DPRINTFN(3, "set port enable %d\n", index);
3679 case UHF_PORT_SUSPEND:
3680 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3681 j = XHCI_PS_SPEED_GET(v);
3682 if ((j < 1) || (j > 3)) {
3683 /* non-supported speed */
3684 err = USB_ERR_IOERROR;
3687 XWRITE4(sc, oper, port, v |
3688 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3690 case UHF_PORT_RESET:
3691 DPRINTFN(6, "reset port %d\n", index);
3692 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3694 case UHF_PORT_POWER:
3695 DPRINTFN(3, "set port power %d\n", index);
3696 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3699 DPRINTFN(3, "set port test %d\n", index);
3701 case UHF_PORT_INDICATOR:
3702 DPRINTFN(3, "set port indicator %d\n", index);
3704 v &= ~XHCI_PS_PIC_SET(3);
3705 v |= XHCI_PS_PIC_SET(1);
3707 XWRITE4(sc, oper, port, v);
3710 err = USB_ERR_IOERROR;
3715 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3716 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3717 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3718 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3721 err = USB_ERR_IOERROR;
3731 xhci_xfer_setup(struct usb_setup_params *parm)
3733 struct usb_page_search page_info;
3734 struct usb_page_cache *pc;
3735 struct usb_xfer *xfer;
3740 xfer = parm->curr_xfer;
3743 * The proof for the "ntd" formula is illustrated like this:
3745 * +------------------------------------+
3749 * | | xxx | x | frm 0 |
3751 * | | xxx | xx | frm 1 |
3754 * +------------------------------------+
3756 * "xxx" means a completely full USB transfer descriptor
3758 * "x" and "xx" means a short USB packet
3760 * For the remainder of an USB transfer modulo
3761 * "max_data_length" we need two USB transfer descriptors.
3762 * One to transfer the remaining data and one to finalise with
3763 * a zero length packet in case the "force_short_xfer" flag is
3764 * set. We only need two USB transfer descriptors in the case
3765 * where the transfer length of the first one is a factor of
3766 * "max_frame_size". The rest of the needed USB transfer
3767 * descriptors is given by the buffer size divided by the
3768 * maximum data payload.
3770 parm->hc_max_packet_size = 0x400;
3771 parm->hc_max_packet_count = 16 * 3;
3772 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3774 xfer->flags_int.bdma_enable = 1;
3776 usbd_transfer_setup_sub(parm);
3778 if (xfer->flags_int.isochronous_xfr) {
3779 ntd = ((1 * xfer->nframes)
3780 + (xfer->max_data_length / xfer->max_hc_frame_size));
3781 } else if (xfer->flags_int.control_xfr) {
3782 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3783 + (xfer->max_data_length / xfer->max_hc_frame_size));
3785 ntd = ((2 * xfer->nframes)
3786 + (xfer->max_data_length / xfer->max_hc_frame_size));
3795 * Allocate queue heads and transfer descriptors
3799 if (usbd_transfer_setup_sub_malloc(
3800 parm, &pc, sizeof(struct xhci_td),
3801 XHCI_TD_ALIGN, ntd)) {
3802 parm->err = USB_ERR_NOMEM;
3806 for (n = 0; n != ntd; n++) {
3809 usbd_get_page(pc + n, 0, &page_info);
3811 td = page_info.buffer;
3814 td->td_self = page_info.physaddr;
3815 td->obj_next = last_obj;
3816 td->page_cache = pc + n;
3820 usb_pc_cpu_flush(pc + n);
3823 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3825 if (!xfer->flags_int.curr_dma_set) {
3826 xfer->flags_int.curr_dma_set = 1;
3832 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3834 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3835 struct usb_page_search buf_inp;
3836 struct usb_device *udev;
3837 struct xhci_endpoint_ext *pepext;
3838 struct usb_endpoint_descriptor *edesc;
3839 struct usb_page_cache *pcinp;
3841 usb_stream_t stream_id;
3846 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3847 xfer->endpoint->edesc);
3849 udev = xfer->xroot->udev;
3850 index = udev->controller_slot_id;
3852 pcinp = &sc->sc_hw.devs[index].input_pc;
3854 usbd_get_page(pcinp, 0, &buf_inp);
3856 edesc = xfer->endpoint->edesc;
3858 epno = edesc->bEndpointAddress;
3859 stream_id = xfer->stream_id;
3861 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3864 epno = XHCI_EPNO2EPID(epno);
3867 return (USB_ERR_NO_PIPE); /* invalid */
3871 /* configure endpoint */
3873 err = xhci_configure_endpoint_by_xfer(xfer);
3876 XHCI_CMD_UNLOCK(sc);
3881 * Get the endpoint into the stopped state according to the
3882 * endpoint context state diagram in the XHCI specification:
3885 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3888 DPRINTF("Could not stop endpoint %u\n", epno);
3890 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3893 DPRINTF("Could not reset endpoint %u\n", epno);
3895 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3896 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3897 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3898 stream_id, epno, index);
3901 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3904 * Get the endpoint into the running state according to the
3905 * endpoint context state diagram in the XHCI specification:
3908 mask = (1U << epno);
3909 xhci_configure_mask(udev, mask | 1U, 0);
3911 if (!(sc->sc_hw.devs[index].ep_configured & mask)) {
3912 sc->sc_hw.devs[index].ep_configured |= mask;
3913 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3915 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3919 DPRINTF("Could not configure "
3920 "endpoint %u at slot %u.\n", epno, index);
3922 XHCI_CMD_UNLOCK(sc);
3928 xhci_xfer_unsetup(struct usb_xfer *xfer)
3934 xhci_start_dma_delay(struct usb_xfer *xfer)
3936 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3938 /* put transfer on interrupt queue (again) */
3939 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3941 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3942 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3946 xhci_configure_msg(struct usb_proc_msg *pm)
3948 struct xhci_softc *sc;
3949 struct xhci_endpoint_ext *pepext;
3950 struct usb_xfer *xfer;
3952 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3955 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3957 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3958 xfer->endpoint->edesc);
3960 if ((pepext->trb_halted != 0) ||
3961 (pepext->trb_running == 0)) {
3965 /* clear halted and running */
3966 pepext->trb_halted = 0;
3967 pepext->trb_running = 0;
3969 /* nuke remaining buffered transfers */
3971 for (i = 0; i != (XHCI_MAX_TRANSFERS *
3972 XHCI_MAX_STREAMS); i++) {
3974 * NOTE: We need to use the timeout
3975 * error code here else existing
3976 * isochronous clients can get
3979 if (pepext->xfer[i] != NULL) {
3980 xhci_device_done(pepext->xfer[i],
3986 * NOTE: The USB transfer cannot vanish in
3990 USB_BUS_UNLOCK(&sc->sc_bus);
3992 xhci_configure_reset_endpoint(xfer);
3994 USB_BUS_LOCK(&sc->sc_bus);
3996 /* check if halted is still cleared */
3997 if (pepext->trb_halted == 0) {
3998 pepext->trb_running = 1;
3999 memset(pepext->trb_index, 0,
4000 sizeof(pepext->trb_index));
4005 if (xfer->flags_int.did_dma_delay) {
4007 /* remove transfer from interrupt queue (again) */
4008 usbd_transfer_dequeue(xfer);
4010 /* we are finally done */
4011 usb_dma_delay_done_cb(xfer);
4013 /* queue changed - restart */
4018 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
4020 /* try to insert xfer on HW queue */
4021 xhci_transfer_insert(xfer);
4023 /* try to multi buffer */
4024 xhci_device_generic_multi_enter(xfer->endpoint,
4025 xfer->stream_id, NULL);
4030 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4031 struct usb_endpoint *ep)
4033 struct xhci_endpoint_ext *pepext;
4035 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4036 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4038 if (udev->parent_hub == NULL) {
4039 /* root HUB has special endpoint handling */
4043 ep->methods = &xhci_device_generic_methods;
4045 pepext = xhci_get_endpoint_ext(udev, edesc);
4047 USB_BUS_LOCK(udev->bus);
4048 pepext->trb_halted = 1;
4049 pepext->trb_running = 0;
4050 USB_BUS_UNLOCK(udev->bus);
4054 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4060 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4062 struct xhci_endpoint_ext *pepext;
4066 if (udev->flags.usb_mode != USB_MODE_HOST) {
4070 if (udev->parent_hub == NULL) {
4071 /* root HUB has special endpoint handling */
4075 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4077 USB_BUS_LOCK(udev->bus);
4078 pepext->trb_halted = 1;
4079 pepext->trb_running = 0;
4080 USB_BUS_UNLOCK(udev->bus);
4084 xhci_device_init(struct usb_device *udev)
4086 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4090 /* no init for root HUB */
4091 if (udev->parent_hub == NULL)
4096 /* set invalid default */
4098 udev->controller_slot_id = sc->sc_noslot + 1;
4100 /* try to get a new slot ID from the XHCI */
4102 err = xhci_cmd_enable_slot(sc, &temp);
4105 XHCI_CMD_UNLOCK(sc);
4109 if (temp > sc->sc_noslot) {
4110 XHCI_CMD_UNLOCK(sc);
4111 return (USB_ERR_BAD_ADDRESS);
4114 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4115 DPRINTF("slot %u already allocated.\n", temp);
4116 XHCI_CMD_UNLOCK(sc);
4117 return (USB_ERR_BAD_ADDRESS);
4120 /* store slot ID for later reference */
4122 udev->controller_slot_id = temp;
4124 /* reset data structure */
4126 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4128 /* set mark slot allocated */
4130 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4132 err = xhci_alloc_device_ext(udev);
4134 XHCI_CMD_UNLOCK(sc);
4136 /* get device into default state */
4139 err = xhci_set_address(udev, NULL, 0);
4145 xhci_device_uninit(struct usb_device *udev)
4147 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4150 /* no init for root HUB */
4151 if (udev->parent_hub == NULL)
4156 index = udev->controller_slot_id;
4158 if (index <= sc->sc_noslot) {
4159 xhci_cmd_disable_slot(sc, index);
4160 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4162 /* free device extension */
4163 xhci_free_device_ext(udev);
4166 XHCI_CMD_UNLOCK(sc);
4170 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4173 * Wait until the hardware has finished any possible use of
4174 * the transfer descriptor(s)
4176 *pus = 2048; /* microseconds */
4180 xhci_device_resume(struct usb_device *udev)
4182 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4189 /* check for root HUB */
4190 if (udev->parent_hub == NULL)
4193 index = udev->controller_slot_id;
4197 /* blindly resume all endpoints */
4199 USB_BUS_LOCK(udev->bus);
4201 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4202 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4203 XWRITE4(sc, door, XHCI_DOORBELL(index),
4204 n | XHCI_DB_SID_SET(p));
4208 USB_BUS_UNLOCK(udev->bus);
4210 XHCI_CMD_UNLOCK(sc);
4214 xhci_device_suspend(struct usb_device *udev)
4216 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4223 /* check for root HUB */
4224 if (udev->parent_hub == NULL)
4227 index = udev->controller_slot_id;
4231 /* blindly suspend all endpoints */
4233 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4234 err = xhci_cmd_stop_ep(sc, 1, n, index);
4236 DPRINTF("Failed to suspend endpoint "
4237 "%u on slot %u (ignored).\n", n, index);
4241 XHCI_CMD_UNLOCK(sc);
4245 xhci_set_hw_power(struct usb_bus *bus)
4251 xhci_device_state_change(struct usb_device *udev)
4253 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4254 struct usb_page_search buf_inp;
4258 /* check for root HUB */
4259 if (udev->parent_hub == NULL)
4262 index = udev->controller_slot_id;
4266 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4267 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4268 &sc->sc_hw.devs[index].tt);
4270 sc->sc_hw.devs[index].nports = 0;
4275 switch (usb_get_device_state(udev)) {
4276 case USB_STATE_POWERED:
4277 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4280 /* set default state */
4281 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4282 sc->sc_hw.devs[index].ep_configured = 3U;
4284 /* reset number of contexts */
4285 sc->sc_hw.devs[index].context_num = 0;
4287 err = xhci_cmd_reset_dev(sc, index);
4290 DPRINTF("Device reset failed "
4291 "for slot %u.\n", index);
4295 case USB_STATE_ADDRESSED:
4296 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4299 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4300 sc->sc_hw.devs[index].ep_configured = 3U;
4302 /* set configure mask to slot only */
4303 xhci_configure_mask(udev, 1, 0);
4305 /* deconfigure all endpoints, except EP0 */
4306 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4309 DPRINTF("Failed to deconfigure "
4310 "slot %u.\n", index);
4314 case USB_STATE_CONFIGURED:
4315 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) {
4316 /* deconfigure all endpoints, except EP0 */
4317 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4320 DPRINTF("Failed to deconfigure "
4321 "slot %u.\n", index);
4325 /* set configured state */
4326 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4327 sc->sc_hw.devs[index].ep_configured = 3U;
4329 /* reset number of contexts */
4330 sc->sc_hw.devs[index].context_num = 0;
4332 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4334 xhci_configure_mask(udev, 3, 0);
4336 err = xhci_configure_device(udev);
4338 DPRINTF("Could not configure device "
4339 "at slot %u.\n", index);
4342 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4344 DPRINTF("Could not evaluate device "
4345 "context at slot %u.\n", index);
4352 XHCI_CMD_UNLOCK(sc);
4356 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4360 case USB_EP_MODE_DEFAULT:
4362 case USB_EP_MODE_STREAMS:
4363 if (xhcistreams == 0 ||
4364 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4365 udev->speed != USB_SPEED_SUPER)
4366 return (USB_ERR_INVAL);
4369 return (USB_ERR_INVAL);
4373 static const struct usb_bus_methods xhci_bus_methods = {
4374 .endpoint_init = xhci_ep_init,
4375 .endpoint_uninit = xhci_ep_uninit,
4376 .xfer_setup = xhci_xfer_setup,
4377 .xfer_unsetup = xhci_xfer_unsetup,
4378 .get_dma_delay = xhci_get_dma_delay,
4379 .device_init = xhci_device_init,
4380 .device_uninit = xhci_device_uninit,
4381 .device_resume = xhci_device_resume,
4382 .device_suspend = xhci_device_suspend,
4383 .set_hw_power = xhci_set_hw_power,
4384 .roothub_exec = xhci_roothub_exec,
4385 .xfer_poll = xhci_do_poll,
4386 .start_dma_delay = xhci_start_dma_delay,
4387 .set_address = xhci_set_address,
4388 .clear_stall = xhci_ep_clear_stall,
4389 .device_state_change = xhci_device_state_change,
4390 .set_hw_power_sleep = xhci_set_hw_power_sleep,
4391 .set_endpoint_mode = xhci_set_endpoint_mode,