3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
32 * The XHCI 1.0 spec can be found at
33 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
34 * and the USB 3.0 spec at
35 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
39 * A few words about the design implementation: This driver emulates
40 * the concept about TDs which is found in EHCI specification. This
41 * way we achieve that the USB controller drivers look similar to
42 * eachother which makes it easier to understand the code.
45 #ifdef USB_GLOBAL_INCLUDE_FILE
46 #include USB_GLOBAL_INCLUDE_FILE
48 #include <sys/stdint.h>
49 #include <sys/stddef.h>
50 #include <sys/param.h>
51 #include <sys/queue.h>
52 #include <sys/types.h>
53 #include <sys/systm.h>
54 #include <sys/kernel.h>
56 #include <sys/module.h>
58 #include <sys/mutex.h>
59 #include <sys/condvar.h>
60 #include <sys/sysctl.h>
62 #include <sys/unistd.h>
63 #include <sys/callout.h>
64 #include <sys/malloc.h>
67 #include <dev/usb/usb.h>
68 #include <dev/usb/usbdi.h>
70 #define USB_DEBUG_VAR xhcidebug
72 #include <dev/usb/usb_core.h>
73 #include <dev/usb/usb_debug.h>
74 #include <dev/usb/usb_busdma.h>
75 #include <dev/usb/usb_process.h>
76 #include <dev/usb/usb_transfer.h>
77 #include <dev/usb/usb_device.h>
78 #include <dev/usb/usb_hub.h>
79 #include <dev/usb/usb_util.h>
81 #include <dev/usb/usb_controller.h>
82 #include <dev/usb/usb_bus.h>
83 #endif /* USB_GLOBAL_INCLUDE_FILE */
85 #include <dev/usb/controller/xhci.h>
86 #include <dev/usb/controller/xhcireg.h>
88 #define XHCI_BUS2SC(bus) \
89 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
90 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
92 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
94 static int xhcistreams;
95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN,
96 &xhcistreams, 0, "Set to enable streams mode support");
100 static int xhciroute;
101 static int xhcipolling;
102 static int xhcidma32;
103 static int xhcictlstep;
105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN,
106 &xhcidebug, 0, "Debug level");
107 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN,
108 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
109 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN,
110 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
111 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
112 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
113 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
114 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
118 #define xhcictlstep 0
121 #define XHCI_INTR_ENDPT 1
123 struct xhci_std_temp {
124 struct xhci_softc *sc;
125 struct usb_page_cache *pc;
127 struct xhci_td *td_next;
130 uint32_t max_packet_size;
142 uint8_t do_isoc_sync;
145 static void xhci_do_poll(struct usb_bus *);
146 static void xhci_device_done(struct usb_xfer *, usb_error_t);
147 static void xhci_root_intr(struct xhci_softc *);
148 static void xhci_free_device_ext(struct usb_device *);
149 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
150 struct usb_endpoint_descriptor *);
151 static usb_proc_callback_t xhci_configure_msg;
152 static usb_error_t xhci_configure_device(struct usb_device *);
153 static usb_error_t xhci_configure_endpoint(struct usb_device *,
154 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
155 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
157 static usb_error_t xhci_configure_mask(struct usb_device *,
159 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
161 static void xhci_endpoint_doorbell(struct usb_xfer *);
162 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
163 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
164 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
166 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
169 static const struct usb_bus_methods xhci_bus_methods;
173 xhci_dump_trb(struct xhci_trb *trb)
175 DPRINTFN(5, "trb = %p\n", trb);
176 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
177 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
178 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
182 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
184 DPRINTFN(5, "pep = %p\n", pep);
185 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
186 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
187 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
188 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
189 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
190 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
191 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
195 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
197 DPRINTFN(5, "psl = %p\n", psl);
198 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
199 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
200 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
201 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
206 xhci_use_polling(void)
209 return (xhcipolling != 0);
216 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
218 struct xhci_softc *sc = XHCI_BUS2SC(bus);
221 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
222 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
224 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
225 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
227 for (i = 0; i != sc->sc_noscratch; i++) {
228 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
229 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
234 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
236 if (sc->sc_ctx_is_64_byte) {
238 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
239 /* all contexts are initially 32-bytes */
240 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
241 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
247 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
249 if (sc->sc_ctx_is_64_byte) {
251 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
252 /* all contexts are initially 32-bytes */
253 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
254 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
256 return (le32toh(*ptr));
260 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
262 if (sc->sc_ctx_is_64_byte) {
264 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
265 /* all contexts are initially 32-bytes */
266 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
267 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
274 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
276 if (sc->sc_ctx_is_64_byte) {
278 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
279 /* all contexts are initially 32-bytes */
280 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
281 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
283 return (le64toh(*ptr));
288 xhci_reset_command_queue_locked(struct xhci_softc *sc)
290 struct usb_page_search buf_res;
291 struct xhci_hw_root *phwr;
297 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
298 if (temp & XHCI_CRCR_LO_CRR) {
299 DPRINTF("Command ring running\n");
300 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
303 * Try to abort the last command as per section
304 * 4.6.1.2 "Aborting a Command" of the XHCI
308 /* stop and cancel */
309 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
310 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
312 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
313 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
316 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
318 /* check if command ring is still running */
319 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
320 if (temp & XHCI_CRCR_LO_CRR) {
321 DPRINTF("Comand ring still running\n");
322 return (USB_ERR_IOERROR);
326 /* reset command ring */
327 sc->sc_command_ccs = 1;
328 sc->sc_command_idx = 0;
330 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
332 /* set up command ring control base address */
333 addr = buf_res.physaddr;
334 phwr = buf_res.buffer;
335 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
337 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
339 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
340 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
342 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
344 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
345 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
351 xhci_start_controller(struct xhci_softc *sc)
353 struct usb_page_search buf_res;
354 struct xhci_hw_root *phwr;
355 struct xhci_dev_ctx_addr *pdctxa;
363 sc->sc_event_ccs = 1;
364 sc->sc_event_idx = 0;
365 sc->sc_command_ccs = 1;
366 sc->sc_command_idx = 0;
368 err = xhci_reset_controller(sc);
372 /* set up number of device slots */
373 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
374 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
376 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
378 temp = XREAD4(sc, oper, XHCI_USBSTS);
380 /* clear interrupts */
381 XWRITE4(sc, oper, XHCI_USBSTS, temp);
382 /* disable all device notifications */
383 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
385 /* set up device context base address */
386 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
387 pdctxa = buf_res.buffer;
388 memset(pdctxa, 0, sizeof(*pdctxa));
390 addr = buf_res.physaddr;
391 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
393 /* slot 0 points to the table of scratchpad pointers */
394 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
396 for (i = 0; i != sc->sc_noscratch; i++) {
397 struct usb_page_search buf_scp;
398 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
399 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
402 addr = buf_res.physaddr;
404 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
405 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
406 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
407 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
409 /* set up event table size */
410 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
411 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
413 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
415 /* set up interrupt rate */
416 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
418 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
420 phwr = buf_res.buffer;
421 addr = buf_res.physaddr;
422 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
424 /* reset hardware root structure */
425 memset(phwr, 0, sizeof(*phwr));
427 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
428 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
430 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
432 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
433 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
435 addr = buf_res.physaddr;
437 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
439 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
440 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
442 /* set up interrupter registers */
443 temp = XREAD4(sc, runt, XHCI_IMAN(0));
444 temp |= XHCI_IMAN_INTR_ENA;
445 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
447 /* set up command ring control base address */
448 addr = buf_res.physaddr;
449 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
451 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
453 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
454 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
456 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
458 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
461 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
462 XHCI_CMD_INTE | XHCI_CMD_HSEE);
464 for (i = 0; i != 100; i++) {
465 usb_pause_mtx(NULL, hz / 100);
466 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
471 XWRITE4(sc, oper, XHCI_USBCMD, 0);
472 device_printf(sc->sc_bus.parent, "Run timeout.\n");
473 return (USB_ERR_IOERROR);
476 /* catch any lost interrupts */
477 xhci_do_poll(&sc->sc_bus);
479 if (sc->sc_port_route != NULL) {
480 /* Route all ports to the XHCI by default */
481 sc->sc_port_route(sc->sc_bus.parent,
482 ~xhciroute, xhciroute);
488 xhci_halt_controller(struct xhci_softc *sc)
496 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
497 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
498 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
500 /* Halt controller */
501 XWRITE4(sc, oper, XHCI_USBCMD, 0);
503 for (i = 0; i != 100; i++) {
504 usb_pause_mtx(NULL, hz / 100);
505 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
511 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
512 return (USB_ERR_IOERROR);
518 xhci_reset_controller(struct xhci_softc *sc)
525 /* Reset controller */
526 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
528 for (i = 0; i != 100; i++) {
529 usb_pause_mtx(NULL, hz / 100);
530 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
531 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
537 device_printf(sc->sc_bus.parent, "Controller "
539 return (USB_ERR_IOERROR);
545 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
551 /* initialize some bus fields */
552 sc->sc_bus.parent = self;
554 /* set the bus revision */
555 sc->sc_bus.usbrev = USB_REV_3_0;
557 /* set up the bus struct */
558 sc->sc_bus.methods = &xhci_bus_methods;
560 /* set up devices array */
561 sc->sc_bus.devices = sc->sc_devices;
562 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
564 /* set default cycle state in case of early interrupts */
565 sc->sc_event_ccs = 1;
566 sc->sc_command_ccs = 1;
568 /* set up bus space offsets */
570 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
571 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
572 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
574 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
575 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
576 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
578 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
580 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
581 device_printf(sc->sc_bus.parent, "Controller does "
582 "not support 4K page size.\n");
586 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
588 DPRINTF("HCS0 = 0x%08x\n", temp);
590 /* set up context size */
591 if (XHCI_HCS0_CSZ(temp)) {
592 sc->sc_ctx_is_64_byte = 1;
594 sc->sc_ctx_is_64_byte = 0;
598 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
599 xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
601 device_printf(self, "%d bytes context size, %d-bit DMA\n",
602 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
604 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
606 /* get number of device slots */
607 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
609 if (sc->sc_noport == 0) {
610 device_printf(sc->sc_bus.parent, "Invalid number "
611 "of ports: %u\n", sc->sc_noport);
615 sc->sc_noport = sc->sc_noport;
616 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
618 DPRINTF("Max slots: %u\n", sc->sc_noslot);
620 if (sc->sc_noslot > XHCI_MAX_DEVICES)
621 sc->sc_noslot = XHCI_MAX_DEVICES;
623 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
625 DPRINTF("HCS2=0x%08x\n", temp);
627 /* get number of scratchpads */
628 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
630 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
631 device_printf(sc->sc_bus.parent, "XHCI request "
632 "too many scratchpads\n");
636 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
638 /* get event table size */
639 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
640 if (sc->sc_erst_max > XHCI_MAX_RSEG)
641 sc->sc_erst_max = XHCI_MAX_RSEG;
643 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
645 /* get maximum exit latency */
646 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
647 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
649 /* Check if we should use the default IMOD value. */
650 if (sc->sc_imod_default == 0)
651 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
653 /* get all DMA memory */
654 if (usb_bus_mem_alloc_all(&sc->sc_bus,
655 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
659 /* set up command queue mutex and condition varible */
660 cv_init(&sc->sc_cmd_cv, "CMDQ");
661 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
663 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
664 sc->sc_config_msg[0].bus = &sc->sc_bus;
665 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
666 sc->sc_config_msg[1].bus = &sc->sc_bus;
672 xhci_uninit(struct xhci_softc *sc)
675 * NOTE: At this point the control transfer process is gone
676 * and "xhci_configure_msg" is no longer called. Consequently
677 * waiting for the configuration messages to complete is not
680 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
682 cv_destroy(&sc->sc_cmd_cv);
683 sx_destroy(&sc->sc_cmd_sx);
687 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
689 struct xhci_softc *sc = XHCI_BUS2SC(bus);
692 case USB_HW_POWER_SUSPEND:
693 DPRINTF("Stopping the XHCI\n");
694 xhci_halt_controller(sc);
695 xhci_reset_controller(sc);
697 case USB_HW_POWER_SHUTDOWN:
698 DPRINTF("Stopping the XHCI\n");
699 xhci_halt_controller(sc);
700 xhci_reset_controller(sc);
702 case USB_HW_POWER_RESUME:
703 DPRINTF("Starting the XHCI\n");
704 xhci_start_controller(sc);
712 xhci_generic_done_sub(struct usb_xfer *xfer)
715 struct xhci_td *td_alt_next;
719 td = xfer->td_transfer_cache;
720 td_alt_next = td->alt_next;
722 if (xfer->aframes != xfer->nframes)
723 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
727 usb_pc_cpu_invalidate(td->page_cache);
732 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
733 xfer, (unsigned int)xfer->aframes,
734 (unsigned int)xfer->nframes,
735 (unsigned int)len, (unsigned int)td->len,
736 (unsigned int)status);
739 * Verify the status length and
740 * add the length to "frlengths[]":
743 /* should not happen */
744 DPRINTF("Invalid status length, "
745 "0x%04x/0x%04x bytes\n", len, td->len);
746 status = XHCI_TRB_ERROR_LENGTH;
747 } else if (xfer->aframes != xfer->nframes) {
748 xfer->frlengths[xfer->aframes] += td->len - len;
750 /* Check for last transfer */
751 if (((void *)td) == xfer->td_transfer_last) {
755 /* Check for transfer error */
756 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
757 status != XHCI_TRB_ERROR_SUCCESS) {
758 /* the transfer is finished */
762 /* Check for short transfer */
764 if (xfer->flags_int.short_frames_ok ||
765 xfer->flags_int.isochronous_xfr ||
766 xfer->flags_int.control_xfr) {
767 /* follow alt next */
770 /* the transfer is finished */
777 if (td->alt_next != td_alt_next) {
778 /* this USB frame is complete */
783 /* update transfer cache */
785 xfer->td_transfer_cache = td;
787 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
788 (status != XHCI_TRB_ERROR_SHORT_PKT &&
789 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
790 USB_ERR_NORMAL_COMPLETION);
794 xhci_generic_done(struct usb_xfer *xfer)
798 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
799 xfer, xfer->endpoint);
803 xfer->td_transfer_cache = xfer->td_transfer_first;
805 if (xfer->flags_int.control_xfr) {
807 if (xfer->flags_int.control_hdr)
808 err = xhci_generic_done_sub(xfer);
812 if (xfer->td_transfer_cache == NULL)
816 while (xfer->aframes != xfer->nframes) {
818 err = xhci_generic_done_sub(xfer);
821 if (xfer->td_transfer_cache == NULL)
825 if (xfer->flags_int.control_xfr &&
826 !xfer->flags_int.control_act)
827 err = xhci_generic_done_sub(xfer);
829 /* transfer is complete */
830 xhci_device_done(xfer, err);
834 xhci_activate_transfer(struct usb_xfer *xfer)
838 td = xfer->td_transfer_cache;
840 usb_pc_cpu_invalidate(td->page_cache);
842 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
844 /* activate the transfer */
846 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
847 usb_pc_cpu_flush(td->page_cache);
849 xhci_endpoint_doorbell(xfer);
854 xhci_skip_transfer(struct usb_xfer *xfer)
857 struct xhci_td *td_last;
859 td = xfer->td_transfer_cache;
860 td_last = xfer->td_transfer_last;
864 usb_pc_cpu_invalidate(td->page_cache);
866 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
868 usb_pc_cpu_invalidate(td_last->page_cache);
870 /* copy LINK TRB to current waiting location */
872 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
873 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
874 usb_pc_cpu_flush(td->page_cache);
876 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
877 usb_pc_cpu_flush(td->page_cache);
879 xhci_endpoint_doorbell(xfer);
883 /*------------------------------------------------------------------------*
884 * xhci_check_transfer
885 *------------------------------------------------------------------------*/
887 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
889 struct xhci_endpoint_ext *pepext;
902 td_event = le64toh(trb->qwTrb0);
903 temp = le32toh(trb->dwTrb2);
905 remainder = XHCI_TRB_2_REM_GET(temp);
906 status = XHCI_TRB_2_ERROR_GET(temp);
907 stream_id = XHCI_TRB_2_STREAM_GET(temp);
909 temp = le32toh(trb->dwTrb3);
910 epno = XHCI_TRB_3_EP_GET(temp);
911 index = XHCI_TRB_3_SLOT_GET(temp);
913 /* check if error means halted */
914 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
915 status != XHCI_TRB_ERROR_SUCCESS);
917 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
918 index, epno, stream_id, remainder, status);
920 if (index > sc->sc_noslot) {
921 DPRINTF("Invalid slot.\n");
925 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
926 DPRINTF("Invalid endpoint.\n");
930 pepext = &sc->sc_hw.devs[index].endp[epno];
932 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
934 DPRINTF("stream_id=0\n");
935 } else if (stream_id >= XHCI_MAX_STREAMS) {
936 DPRINTF("Invalid stream ID.\n");
940 /* try to find the USB transfer that generated the event */
941 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
942 struct usb_xfer *xfer;
945 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
949 td = xfer->td_transfer_cache;
951 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
953 (long long)td->td_self,
954 (long long)td->td_self + sizeof(td->td_trb));
957 * NOTE: Some XHCI implementations might not trigger
958 * an event on the last LINK TRB so we need to
959 * consider both the last and second last event
960 * address as conditions for a successful transfer.
962 * NOTE: We assume that the XHCI will only trigger one
963 * event per chain of TRBs.
966 offset = td_event - td->td_self;
969 offset < (int64_t)sizeof(td->td_trb)) {
971 usb_pc_cpu_invalidate(td->page_cache);
973 /* compute rest of remainder, if any */
974 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
975 temp = le32toh(td->td_trb[i].dwTrb2);
976 remainder += XHCI_TRB_2_BYTES_GET(temp);
979 DPRINTFN(5, "New remainder: %u\n", remainder);
981 /* clear isochronous transfer errors */
982 if (xfer->flags_int.isochronous_xfr) {
985 status = XHCI_TRB_ERROR_SUCCESS;
990 /* "td->remainder" is verified later */
991 td->remainder = remainder;
994 usb_pc_cpu_flush(td->page_cache);
997 * 1) Last transfer descriptor makes the
1000 if (((void *)td) == xfer->td_transfer_last) {
1001 DPRINTF("TD is last\n");
1002 xhci_generic_done(xfer);
1007 * 2) Any kind of error makes the transfer
1011 DPRINTF("TD has I/O error\n");
1012 xhci_generic_done(xfer);
1017 * 3) If there is no alternate next transfer,
1018 * a short packet also makes the transfer done
1020 if (td->remainder > 0) {
1021 if (td->alt_next == NULL) {
1023 "short TD has no alternate next\n");
1024 xhci_generic_done(xfer);
1027 DPRINTF("TD has short pkt\n");
1028 if (xfer->flags_int.short_frames_ok ||
1029 xfer->flags_int.isochronous_xfr ||
1030 xfer->flags_int.control_xfr) {
1031 /* follow the alt next */
1032 xfer->td_transfer_cache = td->alt_next;
1033 xhci_activate_transfer(xfer);
1036 xhci_skip_transfer(xfer);
1037 xhci_generic_done(xfer);
1042 * 4) Transfer complete - go to next TD
1044 DPRINTF("Following next TD\n");
1045 xfer->td_transfer_cache = td->obj_next;
1046 xhci_activate_transfer(xfer);
1047 break; /* there should only be one match */
1053 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1055 if (sc->sc_cmd_addr == trb->qwTrb0) {
1056 DPRINTF("Received command event\n");
1057 sc->sc_cmd_result[0] = trb->dwTrb2;
1058 sc->sc_cmd_result[1] = trb->dwTrb3;
1059 cv_signal(&sc->sc_cmd_cv);
1060 return (1); /* command match */
1066 xhci_interrupt_poll(struct xhci_softc *sc)
1068 struct usb_page_search buf_res;
1069 struct xhci_hw_root *phwr;
1079 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1081 phwr = buf_res.buffer;
1083 /* Receive any events */
1085 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1087 i = sc->sc_event_idx;
1088 j = sc->sc_event_ccs;
1093 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1095 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1100 event = XHCI_TRB_3_TYPE_GET(temp);
1102 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1103 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1104 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1105 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1108 case XHCI_TRB_EVENT_TRANSFER:
1109 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1111 case XHCI_TRB_EVENT_CMD_COMPLETE:
1112 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1115 DPRINTF("Unhandled event = %u\n", event);
1121 if (i == XHCI_MAX_EVENTS) {
1125 /* check for timeout */
1131 sc->sc_event_idx = i;
1132 sc->sc_event_ccs = j;
1135 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1136 * latched. That means to activate the register we need to
1137 * write both the low and high double word of the 64-bit
1141 addr = buf_res.physaddr;
1142 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1144 /* try to clear busy bit */
1145 addr |= XHCI_ERDP_LO_BUSY;
1147 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1148 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1154 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1155 uint16_t timeout_ms)
1157 struct usb_page_search buf_res;
1158 struct xhci_hw_root *phwr;
1163 uint8_t timeout = 0;
1166 XHCI_CMD_ASSERT_LOCKED(sc);
1168 /* get hardware root structure */
1170 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1172 phwr = buf_res.buffer;
1176 USB_BUS_LOCK(&sc->sc_bus);
1178 i = sc->sc_command_idx;
1179 j = sc->sc_command_ccs;
1181 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1182 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1183 (long long)le64toh(trb->qwTrb0),
1184 (long)le32toh(trb->dwTrb2),
1185 (long)le32toh(trb->dwTrb3));
1187 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1188 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1190 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1195 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1197 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1199 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1201 phwr->hwr_commands[i].dwTrb3 = temp;
1203 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1205 addr = buf_res.physaddr;
1206 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1208 sc->sc_cmd_addr = htole64(addr);
1212 if (i == (XHCI_MAX_COMMANDS - 1)) {
1215 temp = htole32(XHCI_TRB_3_TC_BIT |
1216 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1217 XHCI_TRB_3_CYCLE_BIT);
1219 temp = htole32(XHCI_TRB_3_TC_BIT |
1220 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1223 phwr->hwr_commands[i].dwTrb3 = temp;
1225 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1231 sc->sc_command_idx = i;
1232 sc->sc_command_ccs = j;
1234 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1236 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1237 USB_MS_TO_TICKS(timeout_ms));
1240 * In some error cases event interrupts are not generated.
1241 * Poll one time to see if the command has completed.
1243 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1244 DPRINTF("Command was completed when polling\n");
1248 DPRINTF("Command timeout!\n");
1250 * After some weeks of continuous operation, it has
1251 * been observed that the ASMedia Technology, ASM1042
1252 * SuperSpeed USB Host Controller can suddenly stop
1253 * accepting commands via the command queue. Try to
1254 * first reset the command queue. If that fails do a
1255 * host controller reset.
1258 xhci_reset_command_queue_locked(sc) == 0) {
1259 temp = le32toh(trb->dwTrb3);
1262 * Avoid infinite XHCI reset loops if the set
1263 * address command fails to respond due to a
1264 * non-enumerating device:
1266 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1267 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1268 DPRINTF("Set address timeout\n");
1274 DPRINTF("Controller reset!\n");
1275 usb_bus_reset_async_locked(&sc->sc_bus);
1277 err = USB_ERR_TIMEOUT;
1281 temp = le32toh(sc->sc_cmd_result[0]);
1282 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1283 err = USB_ERR_IOERROR;
1285 trb->dwTrb2 = sc->sc_cmd_result[0];
1286 trb->dwTrb3 = sc->sc_cmd_result[1];
1289 USB_BUS_UNLOCK(&sc->sc_bus);
1296 xhci_cmd_nop(struct xhci_softc *sc)
1298 struct xhci_trb trb;
1305 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1307 trb.dwTrb3 = htole32(temp);
1309 return (xhci_do_command(sc, &trb, 100 /* ms */));
1314 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1316 struct xhci_trb trb;
1324 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1326 err = xhci_do_command(sc, &trb, 100 /* ms */);
1330 temp = le32toh(trb.dwTrb3);
1332 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1339 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1341 struct xhci_trb trb;
1348 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1349 XHCI_TRB_3_SLOT_SET(slot_id);
1351 trb.dwTrb3 = htole32(temp);
1353 return (xhci_do_command(sc, &trb, 100 /* ms */));
1357 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1358 uint8_t bsr, uint8_t slot_id)
1360 struct xhci_trb trb;
1365 trb.qwTrb0 = htole64(input_ctx);
1367 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1368 XHCI_TRB_3_SLOT_SET(slot_id);
1371 temp |= XHCI_TRB_3_BSR_BIT;
1373 trb.dwTrb3 = htole32(temp);
1375 return (xhci_do_command(sc, &trb, 500 /* ms */));
1379 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1381 struct usb_page_search buf_inp;
1382 struct usb_page_search buf_dev;
1383 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1384 struct xhci_hw_dev *hdev;
1385 struct xhci_dev_ctx *pdev;
1386 struct xhci_endpoint_ext *pepext;
1392 /* the root HUB case is not handled here */
1393 if (udev->parent_hub == NULL)
1394 return (USB_ERR_INVAL);
1396 index = udev->controller_slot_id;
1398 hdev = &sc->sc_hw.devs[index];
1405 switch (hdev->state) {
1406 case XHCI_ST_DEFAULT:
1407 case XHCI_ST_ENABLED:
1409 hdev->state = XHCI_ST_ENABLED;
1411 /* set configure mask to slot and EP0 */
1412 xhci_configure_mask(udev, 3, 0);
1414 /* configure input slot context structure */
1415 err = xhci_configure_device(udev);
1418 DPRINTF("Could not configure device\n");
1422 /* configure input endpoint context structure */
1423 switch (udev->speed) {
1425 case USB_SPEED_FULL:
1428 case USB_SPEED_HIGH:
1436 pepext = xhci_get_endpoint_ext(udev,
1437 &udev->ctrl_ep_desc);
1439 /* ensure the control endpoint is setup again */
1440 USB_BUS_LOCK(udev->bus);
1441 pepext->trb_halted = 1;
1442 pepext->trb_running = 0;
1443 USB_BUS_UNLOCK(udev->bus);
1445 err = xhci_configure_endpoint(udev,
1446 &udev->ctrl_ep_desc, pepext,
1447 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1450 DPRINTF("Could not configure default endpoint\n");
1454 /* execute set address command */
1455 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1457 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1458 (address == 0), index);
1461 temp = le32toh(sc->sc_cmd_result[0]);
1462 if (address == 0 && sc->sc_port_route != NULL &&
1463 XHCI_TRB_2_ERROR_GET(temp) ==
1464 XHCI_TRB_ERROR_PARAMETER) {
1465 /* LynxPoint XHCI - ports are not switchable */
1466 /* Un-route all ports from the XHCI */
1467 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1469 DPRINTF("Could not set address "
1470 "for slot %u.\n", index);
1475 /* update device address to new value */
1477 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1478 pdev = buf_dev.buffer;
1479 usb_pc_cpu_invalidate(&hdev->device_pc);
1481 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1482 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1484 /* update device state to new value */
1487 hdev->state = XHCI_ST_ADDRESSED;
1489 hdev->state = XHCI_ST_DEFAULT;
1493 DPRINTF("Wrong state for set address.\n");
1494 err = USB_ERR_IOERROR;
1497 XHCI_CMD_UNLOCK(sc);
1506 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1507 uint8_t deconfigure, uint8_t slot_id)
1509 struct xhci_trb trb;
1514 trb.qwTrb0 = htole64(input_ctx);
1516 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1517 XHCI_TRB_3_SLOT_SET(slot_id);
1520 temp |= XHCI_TRB_3_DCEP_BIT;
1522 trb.dwTrb3 = htole32(temp);
1524 return (xhci_do_command(sc, &trb, 100 /* ms */));
1528 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1531 struct xhci_trb trb;
1536 trb.qwTrb0 = htole64(input_ctx);
1538 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1539 XHCI_TRB_3_SLOT_SET(slot_id);
1540 trb.dwTrb3 = htole32(temp);
1542 return (xhci_do_command(sc, &trb, 100 /* ms */));
1546 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1547 uint8_t ep_id, uint8_t slot_id)
1549 struct xhci_trb trb;
1556 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1557 XHCI_TRB_3_SLOT_SET(slot_id) |
1558 XHCI_TRB_3_EP_SET(ep_id);
1561 temp |= XHCI_TRB_3_PRSV_BIT;
1563 trb.dwTrb3 = htole32(temp);
1565 return (xhci_do_command(sc, &trb, 100 /* ms */));
1569 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1570 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1572 struct xhci_trb trb;
1577 trb.qwTrb0 = htole64(dequeue_ptr);
1579 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1580 trb.dwTrb2 = htole32(temp);
1582 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1583 XHCI_TRB_3_SLOT_SET(slot_id) |
1584 XHCI_TRB_3_EP_SET(ep_id);
1585 trb.dwTrb3 = htole32(temp);
1587 return (xhci_do_command(sc, &trb, 100 /* ms */));
1591 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1592 uint8_t ep_id, uint8_t slot_id)
1594 struct xhci_trb trb;
1601 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1602 XHCI_TRB_3_SLOT_SET(slot_id) |
1603 XHCI_TRB_3_EP_SET(ep_id);
1606 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1608 trb.dwTrb3 = htole32(temp);
1610 return (xhci_do_command(sc, &trb, 100 /* ms */));
1614 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1616 struct xhci_trb trb;
1623 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1624 XHCI_TRB_3_SLOT_SET(slot_id);
1626 trb.dwTrb3 = htole32(temp);
1628 return (xhci_do_command(sc, &trb, 100 /* ms */));
1631 /*------------------------------------------------------------------------*
1632 * xhci_interrupt - XHCI interrupt handler
1633 *------------------------------------------------------------------------*/
1635 xhci_interrupt(struct xhci_softc *sc)
1640 USB_BUS_LOCK(&sc->sc_bus);
1642 status = XREAD4(sc, oper, XHCI_USBSTS);
1644 /* acknowledge interrupts, if any */
1646 XWRITE4(sc, oper, XHCI_USBSTS, status);
1647 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1650 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1652 /* force clearing of pending interrupts */
1653 if (temp & XHCI_IMAN_INTR_PEND)
1654 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1656 /* check for event(s) */
1657 xhci_interrupt_poll(sc);
1659 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1660 XHCI_STS_HSE | XHCI_STS_HCE)) {
1662 if (status & XHCI_STS_PCD) {
1666 if (status & XHCI_STS_HCH) {
1667 printf("%s: host controller halted\n",
1671 if (status & XHCI_STS_HSE) {
1672 printf("%s: host system error\n",
1676 if (status & XHCI_STS_HCE) {
1677 printf("%s: host controller error\n",
1681 USB_BUS_UNLOCK(&sc->sc_bus);
1684 /*------------------------------------------------------------------------*
1685 * xhci_timeout - XHCI timeout handler
1686 *------------------------------------------------------------------------*/
1688 xhci_timeout(void *arg)
1690 struct usb_xfer *xfer = arg;
1692 DPRINTF("xfer=%p\n", xfer);
1694 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1696 /* transfer is transferred */
1697 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1701 xhci_do_poll(struct usb_bus *bus)
1703 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1705 USB_BUS_LOCK(&sc->sc_bus);
1706 xhci_interrupt_poll(sc);
1707 USB_BUS_UNLOCK(&sc->sc_bus);
1711 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1713 struct usb_page_search buf_res;
1715 struct xhci_td *td_next;
1716 struct xhci_td *td_alt_next;
1717 struct xhci_td *td_first;
1718 uint32_t buf_offset;
1723 uint8_t shortpkt_old;
1729 shortpkt_old = temp->shortpkt;
1730 len_old = temp->len;
1737 td_next = td_first = temp->td_next;
1741 if (temp->len == 0) {
1746 /* send a Zero Length Packet, ZLP, last */
1753 average = temp->average;
1755 if (temp->len < average) {
1756 if (temp->len % temp->max_packet_size) {
1759 average = temp->len;
1763 if (td_next == NULL)
1764 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1769 td_next = td->obj_next;
1771 /* check if we are pre-computing */
1775 /* update remaining length */
1777 temp->len -= average;
1781 /* fill out current TD */
1787 /* update remaining length */
1789 temp->len -= average;
1791 /* reset TRB index */
1795 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1796 /* immediate data */
1801 td->td_trb[0].qwTrb0 = 0;
1803 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1804 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1807 dword = XHCI_TRB_2_BYTES_SET(8) |
1808 XHCI_TRB_2_TDSZ_SET(0) |
1809 XHCI_TRB_2_IRQ_SET(0);
1811 td->td_trb[0].dwTrb2 = htole32(dword);
1813 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1814 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1817 if (td->td_trb[0].qwTrb0 &
1818 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1819 if (td->td_trb[0].qwTrb0 &
1820 htole64(XHCI_TRB_0_DIR_IN_MASK))
1821 dword |= XHCI_TRB_3_TRT_IN;
1823 dword |= XHCI_TRB_3_TRT_OUT;
1826 td->td_trb[0].dwTrb3 = htole32(dword);
1828 xhci_dump_trb(&td->td_trb[x]);
1836 /* fill out buffer pointers */
1839 memset(&buf_res, 0, sizeof(buf_res));
1841 usbd_get_page(temp->pc, temp->offset +
1842 buf_offset, &buf_res);
1844 /* get length to end of page */
1845 if (buf_res.length > average)
1846 buf_res.length = average;
1848 /* check for maximum length */
1849 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1850 buf_res.length = XHCI_TD_PAGE_SIZE;
1852 npkt_off += buf_res.length;
1856 npkt = howmany(len_old - npkt_off,
1857 temp->max_packet_size);
1864 /* fill out TRB's */
1865 td->td_trb[x].qwTrb0 =
1866 htole64((uint64_t)buf_res.physaddr);
1869 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1870 XHCI_TRB_2_TDSZ_SET(npkt) |
1871 XHCI_TRB_2_IRQ_SET(0);
1873 td->td_trb[x].dwTrb2 = htole32(dword);
1875 switch (temp->trb_type) {
1876 case XHCI_TRB_TYPE_ISOCH:
1877 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1878 XHCI_TRB_3_TBC_SET(temp->tbc) |
1879 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1880 if (td != td_first) {
1881 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1882 } else if (temp->do_isoc_sync != 0) {
1883 temp->do_isoc_sync = 0;
1884 /* wait until "isoc_frame" */
1885 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1886 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1888 /* start data transfer at next interval */
1889 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1890 XHCI_TRB_3_ISO_SIA_BIT;
1892 if (temp->direction == UE_DIR_IN)
1893 dword |= XHCI_TRB_3_ISP_BIT;
1895 case XHCI_TRB_TYPE_DATA_STAGE:
1896 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1897 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1898 if (temp->direction == UE_DIR_IN)
1899 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1901 * Section 3.2.9 in the XHCI
1902 * specification about control
1903 * transfers says that we should use a
1904 * normal-TRB if there are more TRBs
1905 * extending the data-stage
1906 * TRB. Update the "trb_type".
1908 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1910 case XHCI_TRB_TYPE_STATUS_STAGE:
1911 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1912 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1913 if (temp->direction == UE_DIR_IN)
1914 dword |= XHCI_TRB_3_DIR_IN;
1916 default: /* XHCI_TRB_TYPE_NORMAL */
1917 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1918 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1919 if (temp->direction == UE_DIR_IN)
1920 dword |= XHCI_TRB_3_ISP_BIT;
1923 td->td_trb[x].dwTrb3 = htole32(dword);
1925 average -= buf_res.length;
1926 buf_offset += buf_res.length;
1928 xhci_dump_trb(&td->td_trb[x]);
1932 } while (average != 0);
1934 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1936 /* store number of data TRB's */
1940 DPRINTF("NTRB=%u\n", x);
1942 /* fill out link TRB */
1944 if (td_next != NULL) {
1945 /* link the current TD with the next one */
1946 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1947 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1949 /* this field will get updated later */
1950 DPRINTF("NOLINK\n");
1953 dword = XHCI_TRB_2_IRQ_SET(0);
1955 td->td_trb[x].dwTrb2 = htole32(dword);
1957 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1958 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1960 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1961 * frame only receives a single short packet event
1962 * by setting the CHAIN bit in the LINK field. In
1963 * addition some XHCI controllers have problems
1964 * sending a ZLP unless the CHAIN-BIT is set in
1967 XHCI_TRB_3_CHAIN_BIT;
1969 td->td_trb[x].dwTrb3 = htole32(dword);
1971 td->alt_next = td_alt_next;
1973 xhci_dump_trb(&td->td_trb[x]);
1975 usb_pc_cpu_flush(td->page_cache);
1981 /* set up alt next pointer, if any */
1982 if (temp->last_frame) {
1985 /* we use this field internally */
1986 td_alt_next = td_next;
1990 temp->shortpkt = shortpkt_old;
1991 temp->len = len_old;
1996 * Remove cycle bit from the first TRB if we are
1999 if (temp->step_td != 0) {
2000 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
2001 usb_pc_cpu_flush(td_first->page_cache);
2004 /* clear TD SIZE to zero, hence this is the last TRB */
2005 /* remove chain bit because this is the last data TRB in the chain */
2006 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
2007 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2008 /* remove CHAIN-BIT from last LINK TRB */
2009 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2011 usb_pc_cpu_flush(td->page_cache);
2014 temp->td_next = td_next;
2018 xhci_setup_generic_chain(struct usb_xfer *xfer)
2020 struct xhci_std_temp temp;
2026 temp.do_isoc_sync = 0;
2030 temp.average = xfer->max_hc_frame_size;
2031 temp.max_packet_size = xfer->max_packet_size;
2032 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2034 temp.last_frame = 0;
2036 temp.multishort = xfer->flags_int.isochronous_xfr ||
2037 xfer->flags_int.control_xfr ||
2038 xfer->flags_int.short_frames_ok;
2040 /* toggle the DMA set we are using */
2041 xfer->flags_int.curr_dma_set ^= 1;
2043 /* get next DMA set */
2044 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2049 xfer->td_transfer_first = td;
2050 xfer->td_transfer_cache = td;
2052 if (xfer->flags_int.isochronous_xfr) {
2055 /* compute multiplier for ISOCHRONOUS transfers */
2056 mult = xfer->endpoint->ecomp ?
2057 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2059 /* check for USB 2.0 multiplier */
2061 mult = (xfer->endpoint->edesc->
2062 wMaxPacketSize[1] >> 3) & 3;
2070 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2072 DPRINTF("MFINDEX=0x%08x\n", x);
2074 switch (usbd_get_speed(xfer->xroot->udev)) {
2075 case USB_SPEED_FULL:
2077 temp.isoc_delta = 8; /* 1ms */
2078 x += temp.isoc_delta - 1;
2079 x &= ~(temp.isoc_delta - 1);
2082 shift = usbd_xfer_get_fps_shift(xfer);
2083 temp.isoc_delta = 1U << shift;
2084 x += temp.isoc_delta - 1;
2085 x &= ~(temp.isoc_delta - 1);
2086 /* simple frame load balancing */
2087 x += xfer->endpoint->usb_uframe;
2091 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2093 if ((xfer->endpoint->is_synced == 0) ||
2094 (y < (xfer->nframes << shift)) ||
2095 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2097 * If there is data underflow or the pipe
2098 * queue is empty we schedule the transfer a
2099 * few frames ahead of the current frame
2100 * position. Else two isochronous transfers
2103 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2104 xfer->endpoint->is_synced = 1;
2105 temp.do_isoc_sync = 1;
2107 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2110 /* compute isochronous completion time */
2112 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2114 xfer->isoc_time_complete =
2115 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2116 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2119 temp.isoc_frame = xfer->endpoint->isoc_next;
2120 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2122 xfer->endpoint->isoc_next += xfer->nframes << shift;
2124 } else if (xfer->flags_int.control_xfr) {
2126 /* check if we should prepend a setup message */
2128 if (xfer->flags_int.control_hdr) {
2130 temp.len = xfer->frlengths[0];
2131 temp.pc = xfer->frbuffers + 0;
2132 temp.shortpkt = temp.len ? 1 : 0;
2133 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2136 /* check for last frame */
2137 if (xfer->nframes == 1) {
2138 /* no STATUS stage yet, SETUP is last */
2139 if (xfer->flags_int.control_act)
2140 temp.last_frame = 1;
2143 xhci_setup_generic_chain_sub(&temp);
2147 temp.isoc_delta = 0;
2148 temp.isoc_frame = 0;
2149 temp.trb_type = xfer->flags_int.control_did_data ?
2150 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2154 temp.isoc_delta = 0;
2155 temp.isoc_frame = 0;
2156 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2159 if (x != xfer->nframes) {
2160 /* set up page_cache pointer */
2161 temp.pc = xfer->frbuffers + x;
2162 /* set endpoint direction */
2163 temp.direction = UE_GET_DIR(xfer->endpointno);
2166 while (x != xfer->nframes) {
2168 /* DATA0 / DATA1 message */
2170 temp.len = xfer->frlengths[x];
2171 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2172 x != 0 && temp.multishort == 0);
2176 if (x == xfer->nframes) {
2177 if (xfer->flags_int.control_xfr) {
2178 /* no STATUS stage yet, DATA is last */
2179 if (xfer->flags_int.control_act)
2180 temp.last_frame = 1;
2182 temp.last_frame = 1;
2185 if (temp.len == 0) {
2187 /* make sure that we send an USB packet */
2192 temp.tlbpc = mult - 1;
2194 } else if (xfer->flags_int.isochronous_xfr) {
2199 * Isochronous transfers don't have short
2200 * packet termination:
2205 /* isochronous transfers have a transfer limit */
2207 if (temp.len > xfer->max_frame_size)
2208 temp.len = xfer->max_frame_size;
2210 /* compute TD packet count */
2211 tdpc = howmany(temp.len, xfer->max_packet_size);
2213 temp.tbc = howmany(tdpc, mult) - 1;
2214 temp.tlbpc = (tdpc % mult);
2216 if (temp.tlbpc == 0)
2217 temp.tlbpc = mult - 1;
2222 /* regular data transfer */
2224 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2227 xhci_setup_generic_chain_sub(&temp);
2229 if (xfer->flags_int.isochronous_xfr) {
2230 temp.offset += xfer->frlengths[x - 1];
2231 temp.isoc_frame += temp.isoc_delta;
2233 /* get next Page Cache pointer */
2234 temp.pc = xfer->frbuffers + x;
2238 /* check if we should append a status stage */
2240 if (xfer->flags_int.control_xfr &&
2241 !xfer->flags_int.control_act) {
2244 * Send a DATA1 message and invert the current
2245 * endpoint direction.
2247 if (xhcictlstep || temp.sc->sc_ctlstep) {
2249 * Some XHCI controllers will not delay the
2250 * status stage until the next SOF. Force this
2251 * behaviour to avoid failed control
2254 temp.step_td = (xfer->nframes != 0);
2258 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2262 temp.last_frame = 1;
2263 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2265 xhci_setup_generic_chain_sub(&temp);
2270 /* must have at least one frame! */
2272 xfer->td_transfer_last = td;
2274 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2278 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2280 struct usb_page_search buf_res;
2281 struct xhci_dev_ctx_addr *pdctxa;
2283 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2285 pdctxa = buf_res.buffer;
2287 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2289 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2291 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2295 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2297 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2298 struct usb_page_search buf_inp;
2299 struct xhci_input_dev_ctx *pinp;
2304 index = udev->controller_slot_id;
2306 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2308 pinp = buf_inp.buffer;
2311 mask &= XHCI_INCTX_NON_CTRL_MASK;
2312 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2313 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2316 * Some hardware requires that we drop the endpoint
2317 * context before adding it again:
2319 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2320 mask & XHCI_INCTX_NON_CTRL_MASK);
2322 /* Add new endpoint context */
2323 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2325 /* find most significant set bit */
2326 for (x = 31; x != 1; x--) {
2327 if (mask & (1 << x))
2334 /* figure out the maximum number of contexts */
2335 if (x > sc->sc_hw.devs[index].context_num)
2336 sc->sc_hw.devs[index].context_num = x;
2338 x = sc->sc_hw.devs[index].context_num;
2340 /* update number of contexts */
2341 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2342 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2343 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2344 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2346 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2351 xhci_configure_endpoint(struct usb_device *udev,
2352 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2353 uint16_t interval, uint8_t max_packet_count,
2354 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2355 uint16_t max_frame_size, uint8_t ep_mode)
2357 struct usb_page_search buf_inp;
2358 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2359 struct xhci_input_dev_ctx *pinp;
2360 uint64_t ring_addr = pepext->physaddr;
2366 index = udev->controller_slot_id;
2368 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2370 pinp = buf_inp.buffer;
2372 epno = edesc->bEndpointAddress;
2373 type = edesc->bmAttributes & UE_XFERTYPE;
2375 if (type == UE_CONTROL)
2378 epno = XHCI_EPNO2EPID(epno);
2381 return (USB_ERR_NO_PIPE); /* invalid */
2383 if (max_packet_count == 0)
2384 return (USB_ERR_BAD_BUFSIZE);
2389 return (USB_ERR_BAD_BUFSIZE);
2391 /* store endpoint mode */
2392 pepext->trb_ep_mode = ep_mode;
2393 /* store bMaxPacketSize for control endpoints */
2394 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2395 usb_pc_cpu_flush(pepext->page_cache);
2397 if (ep_mode == USB_EP_MODE_STREAMS) {
2398 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2399 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2400 XHCI_EPCTX_0_LSA_SET(1);
2402 ring_addr += sizeof(struct xhci_trb) *
2403 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2405 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2406 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2407 XHCI_EPCTX_0_LSA_SET(0);
2409 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2412 switch (udev->speed) {
2413 case USB_SPEED_FULL:
2426 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2428 case UE_ISOCHRONOUS:
2429 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2431 switch (udev->speed) {
2432 case USB_SPEED_SUPER:
2435 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2436 max_packet_count /= mult;
2446 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2449 XHCI_EPCTX_1_HID_SET(0) |
2450 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2451 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2454 * Always enable the "three strikes and you are gone" feature
2455 * except for ISOCHRONOUS endpoints. This is suggested by
2456 * section 4.3.3 in the XHCI specification about device slot
2459 if (type != UE_ISOCHRONOUS)
2460 temp |= XHCI_EPCTX_1_CERR_SET(3);
2464 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2466 case UE_ISOCHRONOUS:
2467 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2470 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2473 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2477 /* check for IN direction */
2479 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2481 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2482 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2484 switch (edesc->bmAttributes & UE_XFERTYPE) {
2486 case UE_ISOCHRONOUS:
2487 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2488 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2492 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2495 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2499 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2502 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2504 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2506 return (0); /* success */
2510 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2512 struct xhci_endpoint_ext *pepext;
2513 struct usb_endpoint_ss_comp_descriptor *ecomp;
2516 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2517 xfer->endpoint->edesc);
2519 ecomp = xfer->endpoint->ecomp;
2521 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2524 /* halt any transfers */
2525 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2527 /* compute start of TRB ring for stream "x" */
2528 temp = pepext->physaddr +
2529 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2530 XHCI_SCTX_0_SCT_SEC_TR_RING;
2532 /* make tree structure */
2533 pepext->trb[(XHCI_MAX_TRANSFERS *
2534 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2536 /* reserved fields */
2537 pepext->trb[(XHCI_MAX_TRANSFERS *
2538 XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2539 pepext->trb[(XHCI_MAX_TRANSFERS *
2540 XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2542 usb_pc_cpu_flush(pepext->page_cache);
2544 return (xhci_configure_endpoint(xfer->xroot->udev,
2545 xfer->endpoint->edesc, pepext,
2546 xfer->interval, xfer->max_packet_count,
2547 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2548 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2549 xfer->max_frame_size, xfer->endpoint->ep_mode));
2553 xhci_configure_device(struct usb_device *udev)
2555 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2556 struct usb_page_search buf_inp;
2557 struct usb_page_cache *pcinp;
2558 struct xhci_input_dev_ctx *pinp;
2559 struct usb_device *hubdev;
2567 index = udev->controller_slot_id;
2569 DPRINTF("index=%u\n", index);
2571 pcinp = &sc->sc_hw.devs[index].input_pc;
2573 usbd_get_page(pcinp, 0, &buf_inp);
2575 pinp = buf_inp.buffer;
2580 /* figure out route string and root HUB port number */
2582 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2584 if (hubdev->parent_hub == NULL)
2587 depth = hubdev->parent_hub->depth;
2590 * NOTE: HS/FS/LS devices and the SS root HUB can have
2591 * more than 15 ports
2594 rh_port = hubdev->port_no;
2603 route |= rh_port << (4 * (depth - 1));
2606 DPRINTF("Route=0x%08x\n", route);
2608 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2609 XHCI_SCTX_0_CTX_NUM_SET(
2610 sc->sc_hw.devs[index].context_num + 1);
2612 switch (udev->speed) {
2614 temp |= XHCI_SCTX_0_SPEED_SET(2);
2615 if (udev->parent_hs_hub != NULL &&
2616 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2618 DPRINTF("Device inherits MTT\n");
2619 temp |= XHCI_SCTX_0_MTT_SET(1);
2622 case USB_SPEED_HIGH:
2623 temp |= XHCI_SCTX_0_SPEED_SET(3);
2624 if (sc->sc_hw.devs[index].nports != 0 &&
2625 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2626 DPRINTF("HUB supports MTT\n");
2627 temp |= XHCI_SCTX_0_MTT_SET(1);
2630 case USB_SPEED_FULL:
2631 temp |= XHCI_SCTX_0_SPEED_SET(1);
2632 if (udev->parent_hs_hub != NULL &&
2633 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2635 DPRINTF("Device inherits MTT\n");
2636 temp |= XHCI_SCTX_0_MTT_SET(1);
2640 temp |= XHCI_SCTX_0_SPEED_SET(4);
2644 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2645 (udev->speed == USB_SPEED_SUPER ||
2646 udev->speed == USB_SPEED_HIGH);
2649 temp |= XHCI_SCTX_0_HUB_SET(1);
2651 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2653 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2656 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2657 sc->sc_hw.devs[index].nports);
2660 switch (udev->speed) {
2661 case USB_SPEED_SUPER:
2662 switch (sc->sc_hw.devs[index].state) {
2663 case XHCI_ST_ADDRESSED:
2664 case XHCI_ST_CONFIGURED:
2665 /* enable power save */
2666 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2669 /* disable power save */
2677 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2679 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2682 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2683 sc->sc_hw.devs[index].tt);
2686 hubdev = udev->parent_hs_hub;
2688 /* check if we should activate the transaction translator */
2689 switch (udev->speed) {
2690 case USB_SPEED_FULL:
2692 if (hubdev != NULL) {
2693 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2694 hubdev->controller_slot_id);
2695 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2703 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2706 * These fields should be initialized to zero, according to
2707 * XHCI section 6.2.2 - slot context:
2709 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2710 XHCI_SCTX_3_SLOT_STATE_SET(0);
2712 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2715 xhci_dump_device(sc, &pinp->ctx_slot);
2717 usb_pc_cpu_flush(pcinp);
2719 return (0); /* success */
2723 xhci_alloc_device_ext(struct usb_device *udev)
2725 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2726 struct usb_page_search buf_dev;
2727 struct usb_page_search buf_ep;
2728 struct xhci_trb *trb;
2729 struct usb_page_cache *pc;
2730 struct usb_page *pg;
2735 index = udev->controller_slot_id;
2737 pc = &sc->sc_hw.devs[index].device_pc;
2738 pg = &sc->sc_hw.devs[index].device_pg;
2740 /* need to initialize the page cache */
2741 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2743 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2744 (2 * sizeof(struct xhci_dev_ctx)) :
2745 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2748 usbd_get_page(pc, 0, &buf_dev);
2750 pc = &sc->sc_hw.devs[index].input_pc;
2751 pg = &sc->sc_hw.devs[index].input_pg;
2753 /* need to initialize the page cache */
2754 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2756 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2757 (2 * sizeof(struct xhci_input_dev_ctx)) :
2758 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2762 /* initialize all endpoint LINK TRBs */
2764 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2766 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2767 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2769 /* need to initialize the page cache */
2770 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2772 if (usb_pc_alloc_mem(pc, pg,
2773 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2777 /* lookup endpoint TRB ring */
2778 usbd_get_page(pc, 0, &buf_ep);
2780 /* get TRB pointer */
2781 trb = buf_ep.buffer;
2782 trb += XHCI_MAX_TRANSFERS - 1;
2784 /* get TRB start address */
2785 addr = buf_ep.physaddr;
2787 /* create LINK TRB */
2788 trb->qwTrb0 = htole64(addr);
2789 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2790 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2791 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2793 usb_pc_cpu_flush(pc);
2796 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2801 xhci_free_device_ext(udev);
2803 return (USB_ERR_NOMEM);
2807 xhci_free_device_ext(struct usb_device *udev)
2809 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2813 index = udev->controller_slot_id;
2814 xhci_set_slot_pointer(sc, index, 0);
2816 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2817 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2818 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2819 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2822 static struct xhci_endpoint_ext *
2823 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2825 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2826 struct xhci_endpoint_ext *pepext;
2827 struct usb_page_cache *pc;
2828 struct usb_page_search buf_ep;
2832 epno = edesc->bEndpointAddress;
2833 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2836 epno = XHCI_EPNO2EPID(epno);
2838 index = udev->controller_slot_id;
2840 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2842 usbd_get_page(pc, 0, &buf_ep);
2844 pepext = &sc->sc_hw.devs[index].endp[epno];
2845 pepext->page_cache = pc;
2846 pepext->trb = buf_ep.buffer;
2847 pepext->physaddr = buf_ep.physaddr;
2853 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2855 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2859 epno = xfer->endpointno;
2860 if (xfer->flags_int.control_xfr)
2863 epno = XHCI_EPNO2EPID(epno);
2864 index = xfer->xroot->udev->controller_slot_id;
2866 if (xfer->xroot->udev->flags.self_suspended == 0) {
2867 XWRITE4(sc, door, XHCI_DOORBELL(index),
2868 epno | XHCI_DB_SID_SET(xfer->stream_id));
2873 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2875 struct xhci_endpoint_ext *pepext;
2877 if (xfer->flags_int.bandwidth_reclaimed) {
2878 xfer->flags_int.bandwidth_reclaimed = 0;
2880 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2881 xfer->endpoint->edesc);
2883 pepext->trb_used[xfer->stream_id]--;
2885 pepext->xfer[xfer->qh_pos] = NULL;
2887 if (error && pepext->trb_running != 0) {
2888 pepext->trb_halted = 1;
2889 pepext->trb_running = 0;
2895 xhci_transfer_insert(struct usb_xfer *xfer)
2897 struct xhci_td *td_first;
2898 struct xhci_td *td_last;
2899 struct xhci_trb *trb_link;
2900 struct xhci_endpoint_ext *pepext;
2909 id = xfer->stream_id;
2911 /* check if already inserted */
2912 if (xfer->flags_int.bandwidth_reclaimed) {
2913 DPRINTFN(8, "Already in schedule\n");
2917 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2918 xfer->endpoint->edesc);
2920 td_first = xfer->td_transfer_first;
2921 td_last = xfer->td_transfer_last;
2922 addr = pepext->physaddr;
2924 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2927 /* single buffered */
2931 /* multi buffered */
2932 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2936 if (pepext->trb_used[id] >= trb_limit) {
2937 DPRINTFN(8, "Too many TDs queued.\n");
2938 return (USB_ERR_NOMEM);
2941 /* check if bMaxPacketSize changed */
2942 if (xfer->flags_int.control_xfr != 0 &&
2943 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2945 DPRINTFN(8, "Reconfigure control endpoint\n");
2947 /* force driver to reconfigure endpoint */
2948 pepext->trb_halted = 1;
2949 pepext->trb_running = 0;
2952 /* check for stopped condition, after putting transfer on interrupt queue */
2953 if (pepext->trb_running == 0) {
2954 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2956 DPRINTFN(8, "Not running\n");
2958 /* start configuration */
2959 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2960 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2964 pepext->trb_used[id]++;
2966 /* get current TRB index */
2967 i = pepext->trb_index[id];
2969 /* get next TRB index */
2972 /* the last entry of the ring is a hardcoded link TRB */
2973 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2976 /* store next TRB index, before stream ID offset is added */
2977 pepext->trb_index[id] = inext;
2979 /* offset for stream */
2980 i += id * XHCI_MAX_TRANSFERS;
2981 inext += id * XHCI_MAX_TRANSFERS;
2983 /* compute terminating return address */
2984 addr += (inext * sizeof(struct xhci_trb));
2986 /* compute link TRB pointer */
2987 trb_link = td_last->td_trb + td_last->ntrb;
2989 /* update next pointer of last link TRB */
2990 trb_link->qwTrb0 = htole64(addr);
2991 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2992 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2993 XHCI_TRB_3_CYCLE_BIT |
2994 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2997 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2999 usb_pc_cpu_flush(td_last->page_cache);
3001 /* write ahead chain end marker */
3003 pepext->trb[inext].qwTrb0 = 0;
3004 pepext->trb[inext].dwTrb2 = 0;
3005 pepext->trb[inext].dwTrb3 = 0;
3007 /* update next pointer of link TRB */
3009 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
3010 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3013 xhci_dump_trb(&pepext->trb[i]);
3015 usb_pc_cpu_flush(pepext->page_cache);
3017 /* toggle cycle bit which activates the transfer chain */
3019 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
3020 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3022 usb_pc_cpu_flush(pepext->page_cache);
3024 DPRINTF("qh_pos = %u\n", i);
3026 pepext->xfer[i] = xfer;
3030 xfer->flags_int.bandwidth_reclaimed = 1;
3032 xhci_endpoint_doorbell(xfer);
3038 xhci_root_intr(struct xhci_softc *sc)
3042 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3044 /* clear any old interrupt data */
3045 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3047 for (i = 1; i <= sc->sc_noport; i++) {
3048 /* pick out CHANGE bits from the status register */
3049 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3050 XHCI_PS_CSC | XHCI_PS_PEC |
3051 XHCI_PS_OCC | XHCI_PS_WRC |
3052 XHCI_PS_PRC | XHCI_PS_PLC |
3054 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3055 DPRINTF("port %d changed\n", i);
3058 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3059 sizeof(sc->sc_hub_idata));
3062 /*------------------------------------------------------------------------*
3063 * xhci_device_done - XHCI done handler
3065 * NOTE: This function can be called two times in a row on
3066 * the same USB transfer. From close and from interrupt.
3067 *------------------------------------------------------------------------*/
3069 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3071 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3072 xfer, xfer->endpoint, error);
3074 /* remove transfer from HW queue */
3075 xhci_transfer_remove(xfer, error);
3077 /* dequeue transfer and start next transfer */
3078 usbd_transfer_done(xfer, error);
3081 /*------------------------------------------------------------------------*
3082 * XHCI data transfer support (generic type)
3083 *------------------------------------------------------------------------*/
3085 xhci_device_generic_open(struct usb_xfer *xfer)
3087 if (xfer->flags_int.isochronous_xfr) {
3088 switch (xfer->xroot->udev->speed) {
3089 case USB_SPEED_FULL:
3092 usb_hs_bandwidth_alloc(xfer);
3099 xhci_device_generic_close(struct usb_xfer *xfer)
3103 xhci_device_done(xfer, USB_ERR_CANCELLED);
3105 if (xfer->flags_int.isochronous_xfr) {
3106 switch (xfer->xroot->udev->speed) {
3107 case USB_SPEED_FULL:
3110 usb_hs_bandwidth_free(xfer);
3117 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3118 usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3120 struct usb_xfer *xfer;
3122 /* check if there is a current transfer */
3123 xfer = ep->endpoint_q[stream_id].curr;
3128 * Check if the current transfer is started and then pickup
3129 * the next one, if any. Else wait for next start event due to
3130 * block on failure feature.
3132 if (!xfer->flags_int.bandwidth_reclaimed)
3135 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3138 * In case of enter we have to consider that the
3139 * transfer is queued by the USB core after the enter
3148 /* try to multi buffer */
3149 xhci_transfer_insert(xfer);
3153 xhci_device_generic_enter(struct usb_xfer *xfer)
3157 /* set up TD's and QH */
3158 xhci_setup_generic_chain(xfer);
3160 xhci_device_generic_multi_enter(xfer->endpoint,
3161 xfer->stream_id, xfer);
3165 xhci_device_generic_start(struct usb_xfer *xfer)
3169 /* try to insert xfer on HW queue */
3170 xhci_transfer_insert(xfer);
3172 /* try to multi buffer */
3173 xhci_device_generic_multi_enter(xfer->endpoint,
3174 xfer->stream_id, NULL);
3176 /* add transfer last on interrupt queue */
3177 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3179 /* start timeout, if any */
3180 if (xfer->timeout != 0)
3181 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3184 static const struct usb_pipe_methods xhci_device_generic_methods =
3186 .open = xhci_device_generic_open,
3187 .close = xhci_device_generic_close,
3188 .enter = xhci_device_generic_enter,
3189 .start = xhci_device_generic_start,
3192 /*------------------------------------------------------------------------*
3193 * xhci root HUB support
3194 *------------------------------------------------------------------------*
3195 * Simulate a hardware HUB by handling all the necessary requests.
3196 *------------------------------------------------------------------------*/
3198 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3201 struct usb_device_descriptor xhci_devd =
3203 .bLength = sizeof(xhci_devd),
3204 .bDescriptorType = UDESC_DEVICE, /* type */
3205 HSETW(.bcdUSB, 0x0300), /* USB version */
3206 .bDeviceClass = UDCLASS_HUB, /* class */
3207 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3208 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3209 .bMaxPacketSize = 9, /* max packet size */
3210 HSETW(.idVendor, 0x0000), /* vendor */
3211 HSETW(.idProduct, 0x0000), /* product */
3212 HSETW(.bcdDevice, 0x0100), /* device version */
3216 .bNumConfigurations = 1, /* # of configurations */
3220 struct xhci_bos_desc xhci_bosd = {
3222 .bLength = sizeof(xhci_bosd.bosd),
3223 .bDescriptorType = UDESC_BOS,
3224 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3225 .bNumDeviceCaps = 3,
3228 .bLength = sizeof(xhci_bosd.usb2extd),
3229 .bDescriptorType = 1,
3230 .bDevCapabilityType = 2,
3231 .bmAttributes[0] = 2,
3234 .bLength = sizeof(xhci_bosd.usbdcd),
3235 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3236 .bDevCapabilityType = 3,
3237 .bmAttributes = 0, /* XXX */
3238 HSETW(.wSpeedsSupported, 0x000C),
3239 .bFunctionalitySupport = 8,
3240 .bU1DevExitLat = 255, /* dummy - not used */
3241 .wU2DevExitLat = { 0x00, 0x08 },
3244 .bLength = sizeof(xhci_bosd.cidd),
3245 .bDescriptorType = 1,
3246 .bDevCapabilityType = 4,
3248 .bContainerID = 0, /* XXX */
3253 struct xhci_config_desc xhci_confd = {
3255 .bLength = sizeof(xhci_confd.confd),
3256 .bDescriptorType = UDESC_CONFIG,
3257 .wTotalLength[0] = sizeof(xhci_confd),
3259 .bConfigurationValue = 1,
3260 .iConfiguration = 0,
3261 .bmAttributes = UC_SELF_POWERED,
3262 .bMaxPower = 0 /* max power */
3265 .bLength = sizeof(xhci_confd.ifcd),
3266 .bDescriptorType = UDESC_INTERFACE,
3268 .bInterfaceClass = UICLASS_HUB,
3269 .bInterfaceSubClass = UISUBCLASS_HUB,
3270 .bInterfaceProtocol = 0,
3273 .bLength = sizeof(xhci_confd.endpd),
3274 .bDescriptorType = UDESC_ENDPOINT,
3275 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3276 .bmAttributes = UE_INTERRUPT,
3277 .wMaxPacketSize[0] = 2, /* max 15 ports */
3281 .bLength = sizeof(xhci_confd.endpcd),
3282 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3289 struct usb_hub_ss_descriptor xhci_hubd = {
3290 .bLength = sizeof(xhci_hubd),
3291 .bDescriptorType = UDESC_SS_HUB,
3295 xhci_roothub_exec(struct usb_device *udev,
3296 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3298 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3299 const char *str_ptr;
3310 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3313 ptr = (const void *)&sc->sc_hub_desc;
3317 value = UGETW(req->wValue);
3318 index = UGETW(req->wIndex);
3320 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3321 "wValue=0x%04x wIndex=0x%04x\n",
3322 req->bmRequestType, req->bRequest,
3323 UGETW(req->wLength), value, index);
3325 #define C(x,y) ((x) | ((y) << 8))
3326 switch (C(req->bRequest, req->bmRequestType)) {
3327 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3328 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3329 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3331 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3332 * for the integrated root hub.
3335 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3337 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3339 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3340 switch (value >> 8) {
3342 if ((value & 0xff) != 0) {
3343 err = USB_ERR_IOERROR;
3346 len = sizeof(xhci_devd);
3347 ptr = (const void *)&xhci_devd;
3351 if ((value & 0xff) != 0) {
3352 err = USB_ERR_IOERROR;
3355 len = sizeof(xhci_bosd);
3356 ptr = (const void *)&xhci_bosd;
3360 if ((value & 0xff) != 0) {
3361 err = USB_ERR_IOERROR;
3364 len = sizeof(xhci_confd);
3365 ptr = (const void *)&xhci_confd;
3369 switch (value & 0xff) {
3370 case 0: /* Language table */
3374 case 1: /* Vendor */
3375 str_ptr = sc->sc_vendor;
3378 case 2: /* Product */
3379 str_ptr = "XHCI root HUB";
3387 len = usb_make_str_desc(
3388 sc->sc_hub_desc.temp,
3389 sizeof(sc->sc_hub_desc.temp),
3394 err = USB_ERR_IOERROR;
3398 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3400 sc->sc_hub_desc.temp[0] = 0;
3402 case C(UR_GET_STATUS, UT_READ_DEVICE):
3404 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3406 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3407 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3409 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3411 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3412 if (value >= XHCI_MAX_DEVICES) {
3413 err = USB_ERR_IOERROR;
3417 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3418 if (value != 0 && value != 1) {
3419 err = USB_ERR_IOERROR;
3422 sc->sc_conf = value;
3424 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3426 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3427 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3428 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3429 err = USB_ERR_IOERROR;
3431 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3433 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3436 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3438 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3439 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3442 (index > sc->sc_noport)) {
3443 err = USB_ERR_IOERROR;
3446 port = XHCI_PORTSC(index);
3448 v = XREAD4(sc, oper, port);
3449 i = XHCI_PS_PLS_GET(v);
3450 v &= ~XHCI_PS_CLEAR;
3453 case UHF_C_BH_PORT_RESET:
3454 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3456 case UHF_C_PORT_CONFIG_ERROR:
3457 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3459 case UHF_C_PORT_SUSPEND:
3460 case UHF_C_PORT_LINK_STATE:
3461 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3463 case UHF_C_PORT_CONNECTION:
3464 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3466 case UHF_C_PORT_ENABLE:
3467 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3469 case UHF_C_PORT_OVER_CURRENT:
3470 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3472 case UHF_C_PORT_RESET:
3473 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3475 case UHF_PORT_ENABLE:
3476 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3478 case UHF_PORT_POWER:
3479 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3481 case UHF_PORT_INDICATOR:
3482 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3484 case UHF_PORT_SUSPEND:
3488 XWRITE4(sc, oper, port, v |
3489 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3492 /* wait 20ms for resume sequence to complete */
3493 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3496 XWRITE4(sc, oper, port, v |
3497 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3500 err = USB_ERR_IOERROR;
3505 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3506 if ((value & 0xff) != 0) {
3507 err = USB_ERR_IOERROR;
3511 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3513 sc->sc_hub_desc.hubd = xhci_hubd;
3515 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3517 if (XHCI_HCS0_PPC(v))
3518 i = UHD_PWR_INDIVIDUAL;
3522 if (XHCI_HCS0_PIND(v))
3525 i |= UHD_OC_INDIVIDUAL;
3527 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3529 /* see XHCI section 5.4.9: */
3530 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3532 for (j = 1; j <= sc->sc_noport; j++) {
3534 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3535 if (v & XHCI_PS_DR) {
3536 sc->sc_hub_desc.hubd.
3537 DeviceRemovable[j / 8] |= 1U << (j % 8);
3540 len = sc->sc_hub_desc.hubd.bLength;
3543 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3545 memset(sc->sc_hub_desc.temp, 0, 16);
3548 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3549 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3552 (index > sc->sc_noport)) {
3553 err = USB_ERR_IOERROR;
3557 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3559 DPRINTFN(9, "port status=0x%08x\n", v);
3561 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3563 switch (XHCI_PS_SPEED_GET(v)) {
3565 i |= UPS_HIGH_SPEED;
3574 i |= UPS_OTHER_SPEED;
3578 if (v & XHCI_PS_CCS)
3579 i |= UPS_CURRENT_CONNECT_STATUS;
3580 if (v & XHCI_PS_PED)
3581 i |= UPS_PORT_ENABLED;
3582 if (v & XHCI_PS_OCA)
3583 i |= UPS_OVERCURRENT_INDICATOR;
3586 if (v & XHCI_PS_PP) {
3588 * The USB 3.0 RH is using the
3589 * USB 2.0's power bit
3591 i |= UPS_PORT_POWER;
3593 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3596 if (v & XHCI_PS_CSC)
3597 i |= UPS_C_CONNECT_STATUS;
3598 if (v & XHCI_PS_PEC)
3599 i |= UPS_C_PORT_ENABLED;
3600 if (v & XHCI_PS_OCC)
3601 i |= UPS_C_OVERCURRENT_INDICATOR;
3602 if (v & XHCI_PS_WRC)
3603 i |= UPS_C_BH_PORT_RESET;
3604 if (v & XHCI_PS_PRC)
3605 i |= UPS_C_PORT_RESET;
3606 if (v & XHCI_PS_PLC)
3607 i |= UPS_C_PORT_LINK_STATE;
3608 if (v & XHCI_PS_CEC)
3609 i |= UPS_C_PORT_CONFIG_ERROR;
3611 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3612 len = sizeof(sc->sc_hub_desc.ps);
3615 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3616 err = USB_ERR_IOERROR;
3619 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3622 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3628 (index > sc->sc_noport)) {
3629 err = USB_ERR_IOERROR;
3633 port = XHCI_PORTSC(index);
3634 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3637 case UHF_PORT_U1_TIMEOUT:
3638 if (XHCI_PS_SPEED_GET(v) != 4) {
3639 err = USB_ERR_IOERROR;
3642 port = XHCI_PORTPMSC(index);
3643 v = XREAD4(sc, oper, port);
3644 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3645 v |= XHCI_PM3_U1TO_SET(i);
3646 XWRITE4(sc, oper, port, v);
3648 case UHF_PORT_U2_TIMEOUT:
3649 if (XHCI_PS_SPEED_GET(v) != 4) {
3650 err = USB_ERR_IOERROR;
3653 port = XHCI_PORTPMSC(index);
3654 v = XREAD4(sc, oper, port);
3655 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3656 v |= XHCI_PM3_U2TO_SET(i);
3657 XWRITE4(sc, oper, port, v);
3659 case UHF_BH_PORT_RESET:
3660 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3662 case UHF_PORT_LINK_STATE:
3663 XWRITE4(sc, oper, port, v |
3664 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3665 /* 4ms settle time */
3666 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3668 case UHF_PORT_ENABLE:
3669 DPRINTFN(3, "set port enable %d\n", index);
3671 case UHF_PORT_SUSPEND:
3672 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3673 j = XHCI_PS_SPEED_GET(v);
3674 if ((j < 1) || (j > 3)) {
3675 /* non-supported speed */
3676 err = USB_ERR_IOERROR;
3679 XWRITE4(sc, oper, port, v |
3680 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3682 case UHF_PORT_RESET:
3683 DPRINTFN(6, "reset port %d\n", index);
3684 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3686 case UHF_PORT_POWER:
3687 DPRINTFN(3, "set port power %d\n", index);
3688 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3691 DPRINTFN(3, "set port test %d\n", index);
3693 case UHF_PORT_INDICATOR:
3694 DPRINTFN(3, "set port indicator %d\n", index);
3696 v &= ~XHCI_PS_PIC_SET(3);
3697 v |= XHCI_PS_PIC_SET(1);
3699 XWRITE4(sc, oper, port, v);
3702 err = USB_ERR_IOERROR;
3707 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3708 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3709 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3710 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3713 err = USB_ERR_IOERROR;
3723 xhci_xfer_setup(struct usb_setup_params *parm)
3725 struct usb_page_search page_info;
3726 struct usb_page_cache *pc;
3727 struct usb_xfer *xfer;
3732 xfer = parm->curr_xfer;
3735 * The proof for the "ntd" formula is illustrated like this:
3737 * +------------------------------------+
3741 * | | xxx | x | frm 0 |
3743 * | | xxx | xx | frm 1 |
3746 * +------------------------------------+
3748 * "xxx" means a completely full USB transfer descriptor
3750 * "x" and "xx" means a short USB packet
3752 * For the remainder of an USB transfer modulo
3753 * "max_data_length" we need two USB transfer descriptors.
3754 * One to transfer the remaining data and one to finalise with
3755 * a zero length packet in case the "force_short_xfer" flag is
3756 * set. We only need two USB transfer descriptors in the case
3757 * where the transfer length of the first one is a factor of
3758 * "max_frame_size". The rest of the needed USB transfer
3759 * descriptors is given by the buffer size divided by the
3760 * maximum data payload.
3762 parm->hc_max_packet_size = 0x400;
3763 parm->hc_max_packet_count = 16 * 3;
3764 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3766 xfer->flags_int.bdma_enable = 1;
3768 usbd_transfer_setup_sub(parm);
3770 if (xfer->flags_int.isochronous_xfr) {
3771 ntd = ((1 * xfer->nframes)
3772 + (xfer->max_data_length / xfer->max_hc_frame_size));
3773 } else if (xfer->flags_int.control_xfr) {
3774 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3775 + (xfer->max_data_length / xfer->max_hc_frame_size));
3777 ntd = ((2 * xfer->nframes)
3778 + (xfer->max_data_length / xfer->max_hc_frame_size));
3787 * Allocate queue heads and transfer descriptors
3791 if (usbd_transfer_setup_sub_malloc(
3792 parm, &pc, sizeof(struct xhci_td),
3793 XHCI_TD_ALIGN, ntd)) {
3794 parm->err = USB_ERR_NOMEM;
3798 for (n = 0; n != ntd; n++) {
3801 usbd_get_page(pc + n, 0, &page_info);
3803 td = page_info.buffer;
3806 td->td_self = page_info.physaddr;
3807 td->obj_next = last_obj;
3808 td->page_cache = pc + n;
3812 usb_pc_cpu_flush(pc + n);
3815 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3817 if (!xfer->flags_int.curr_dma_set) {
3818 xfer->flags_int.curr_dma_set = 1;
3824 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3826 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3827 struct usb_page_search buf_inp;
3828 struct usb_device *udev;
3829 struct xhci_endpoint_ext *pepext;
3830 struct usb_endpoint_descriptor *edesc;
3831 struct usb_page_cache *pcinp;
3833 usb_stream_t stream_id;
3837 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3838 xfer->endpoint->edesc);
3840 udev = xfer->xroot->udev;
3841 index = udev->controller_slot_id;
3843 pcinp = &sc->sc_hw.devs[index].input_pc;
3845 usbd_get_page(pcinp, 0, &buf_inp);
3847 edesc = xfer->endpoint->edesc;
3849 epno = edesc->bEndpointAddress;
3850 stream_id = xfer->stream_id;
3852 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3855 epno = XHCI_EPNO2EPID(epno);
3858 return (USB_ERR_NO_PIPE); /* invalid */
3862 /* configure endpoint */
3864 err = xhci_configure_endpoint_by_xfer(xfer);
3867 XHCI_CMD_UNLOCK(sc);
3872 * Get the endpoint into the stopped state according to the
3873 * endpoint context state diagram in the XHCI specification:
3876 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3879 DPRINTF("Could not stop endpoint %u\n", epno);
3881 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3884 DPRINTF("Could not reset endpoint %u\n", epno);
3886 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3887 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3888 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3889 stream_id, epno, index);
3892 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3895 * Get the endpoint into the running state according to the
3896 * endpoint context state diagram in the XHCI specification:
3899 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3902 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3904 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3907 DPRINTF("Could not configure endpoint %u\n", epno);
3909 XHCI_CMD_UNLOCK(sc);
3915 xhci_xfer_unsetup(struct usb_xfer *xfer)
3921 xhci_start_dma_delay(struct usb_xfer *xfer)
3923 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3925 /* put transfer on interrupt queue (again) */
3926 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3928 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3929 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3933 xhci_configure_msg(struct usb_proc_msg *pm)
3935 struct xhci_softc *sc;
3936 struct xhci_endpoint_ext *pepext;
3937 struct usb_xfer *xfer;
3939 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3942 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3944 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3945 xfer->endpoint->edesc);
3947 if ((pepext->trb_halted != 0) ||
3948 (pepext->trb_running == 0)) {
3952 /* clear halted and running */
3953 pepext->trb_halted = 0;
3954 pepext->trb_running = 0;
3956 /* nuke remaining buffered transfers */
3958 for (i = 0; i != (XHCI_MAX_TRANSFERS *
3959 XHCI_MAX_STREAMS); i++) {
3961 * NOTE: We need to use the timeout
3962 * error code here else existing
3963 * isochronous clients can get
3966 if (pepext->xfer[i] != NULL) {
3967 xhci_device_done(pepext->xfer[i],
3973 * NOTE: The USB transfer cannot vanish in
3977 USB_BUS_UNLOCK(&sc->sc_bus);
3979 xhci_configure_reset_endpoint(xfer);
3981 USB_BUS_LOCK(&sc->sc_bus);
3983 /* check if halted is still cleared */
3984 if (pepext->trb_halted == 0) {
3985 pepext->trb_running = 1;
3986 memset(pepext->trb_index, 0,
3987 sizeof(pepext->trb_index));
3992 if (xfer->flags_int.did_dma_delay) {
3994 /* remove transfer from interrupt queue (again) */
3995 usbd_transfer_dequeue(xfer);
3997 /* we are finally done */
3998 usb_dma_delay_done_cb(xfer);
4000 /* queue changed - restart */
4005 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
4007 /* try to insert xfer on HW queue */
4008 xhci_transfer_insert(xfer);
4010 /* try to multi buffer */
4011 xhci_device_generic_multi_enter(xfer->endpoint,
4012 xfer->stream_id, NULL);
4017 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4018 struct usb_endpoint *ep)
4020 struct xhci_endpoint_ext *pepext;
4022 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4023 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4025 if (udev->parent_hub == NULL) {
4026 /* root HUB has special endpoint handling */
4030 ep->methods = &xhci_device_generic_methods;
4032 pepext = xhci_get_endpoint_ext(udev, edesc);
4034 USB_BUS_LOCK(udev->bus);
4035 pepext->trb_halted = 1;
4036 pepext->trb_running = 0;
4037 USB_BUS_UNLOCK(udev->bus);
4041 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4047 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4049 struct xhci_endpoint_ext *pepext;
4053 if (udev->flags.usb_mode != USB_MODE_HOST) {
4057 if (udev->parent_hub == NULL) {
4058 /* root HUB has special endpoint handling */
4062 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4064 USB_BUS_LOCK(udev->bus);
4065 pepext->trb_halted = 1;
4066 pepext->trb_running = 0;
4067 USB_BUS_UNLOCK(udev->bus);
4071 xhci_device_init(struct usb_device *udev)
4073 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4077 /* no init for root HUB */
4078 if (udev->parent_hub == NULL)
4083 /* set invalid default */
4085 udev->controller_slot_id = sc->sc_noslot + 1;
4087 /* try to get a new slot ID from the XHCI */
4089 err = xhci_cmd_enable_slot(sc, &temp);
4092 XHCI_CMD_UNLOCK(sc);
4096 if (temp > sc->sc_noslot) {
4097 XHCI_CMD_UNLOCK(sc);
4098 return (USB_ERR_BAD_ADDRESS);
4101 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4102 DPRINTF("slot %u already allocated.\n", temp);
4103 XHCI_CMD_UNLOCK(sc);
4104 return (USB_ERR_BAD_ADDRESS);
4107 /* store slot ID for later reference */
4109 udev->controller_slot_id = temp;
4111 /* reset data structure */
4113 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4115 /* set mark slot allocated */
4117 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4119 err = xhci_alloc_device_ext(udev);
4121 XHCI_CMD_UNLOCK(sc);
4123 /* get device into default state */
4126 err = xhci_set_address(udev, NULL, 0);
4132 xhci_device_uninit(struct usb_device *udev)
4134 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4137 /* no init for root HUB */
4138 if (udev->parent_hub == NULL)
4143 index = udev->controller_slot_id;
4145 if (index <= sc->sc_noslot) {
4146 xhci_cmd_disable_slot(sc, index);
4147 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4149 /* free device extension */
4150 xhci_free_device_ext(udev);
4153 XHCI_CMD_UNLOCK(sc);
4157 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4160 * Wait until the hardware has finished any possible use of
4161 * the transfer descriptor(s)
4163 *pus = 2048; /* microseconds */
4167 xhci_device_resume(struct usb_device *udev)
4169 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4176 /* check for root HUB */
4177 if (udev->parent_hub == NULL)
4180 index = udev->controller_slot_id;
4184 /* blindly resume all endpoints */
4186 USB_BUS_LOCK(udev->bus);
4188 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4189 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4190 XWRITE4(sc, door, XHCI_DOORBELL(index),
4191 n | XHCI_DB_SID_SET(p));
4195 USB_BUS_UNLOCK(udev->bus);
4197 XHCI_CMD_UNLOCK(sc);
4201 xhci_device_suspend(struct usb_device *udev)
4203 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4210 /* check for root HUB */
4211 if (udev->parent_hub == NULL)
4214 index = udev->controller_slot_id;
4218 /* blindly suspend all endpoints */
4220 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4221 err = xhci_cmd_stop_ep(sc, 1, n, index);
4223 DPRINTF("Failed to suspend endpoint "
4224 "%u on slot %u (ignored).\n", n, index);
4228 XHCI_CMD_UNLOCK(sc);
4232 xhci_set_hw_power(struct usb_bus *bus)
4238 xhci_device_state_change(struct usb_device *udev)
4240 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4241 struct usb_page_search buf_inp;
4245 /* check for root HUB */
4246 if (udev->parent_hub == NULL)
4249 index = udev->controller_slot_id;
4253 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4254 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4255 &sc->sc_hw.devs[index].tt);
4257 sc->sc_hw.devs[index].nports = 0;
4262 switch (usb_get_device_state(udev)) {
4263 case USB_STATE_POWERED:
4264 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4267 /* set default state */
4268 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4270 /* reset number of contexts */
4271 sc->sc_hw.devs[index].context_num = 0;
4273 err = xhci_cmd_reset_dev(sc, index);
4276 DPRINTF("Device reset failed "
4277 "for slot %u.\n", index);
4281 case USB_STATE_ADDRESSED:
4282 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4285 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4287 /* set configure mask to slot only */
4288 xhci_configure_mask(udev, 1, 0);
4290 /* deconfigure all endpoints, except EP0 */
4291 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4294 DPRINTF("Failed to deconfigure "
4295 "slot %u.\n", index);
4299 case USB_STATE_CONFIGURED:
4300 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4303 /* set configured state */
4304 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4306 /* reset number of contexts */
4307 sc->sc_hw.devs[index].context_num = 0;
4309 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4311 xhci_configure_mask(udev, 3, 0);
4313 err = xhci_configure_device(udev);
4315 DPRINTF("Could not configure device "
4316 "at slot %u.\n", index);
4319 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4321 DPRINTF("Could not evaluate device "
4322 "context at slot %u.\n", index);
4329 XHCI_CMD_UNLOCK(sc);
4333 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4337 case USB_EP_MODE_DEFAULT:
4339 case USB_EP_MODE_STREAMS:
4340 if (xhcistreams == 0 ||
4341 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4342 udev->speed != USB_SPEED_SUPER)
4343 return (USB_ERR_INVAL);
4346 return (USB_ERR_INVAL);
4350 static const struct usb_bus_methods xhci_bus_methods = {
4351 .endpoint_init = xhci_ep_init,
4352 .endpoint_uninit = xhci_ep_uninit,
4353 .xfer_setup = xhci_xfer_setup,
4354 .xfer_unsetup = xhci_xfer_unsetup,
4355 .get_dma_delay = xhci_get_dma_delay,
4356 .device_init = xhci_device_init,
4357 .device_uninit = xhci_device_uninit,
4358 .device_resume = xhci_device_resume,
4359 .device_suspend = xhci_device_suspend,
4360 .set_hw_power = xhci_set_hw_power,
4361 .roothub_exec = xhci_roothub_exec,
4362 .xfer_poll = xhci_do_poll,
4363 .start_dma_delay = xhci_start_dma_delay,
4364 .set_address = xhci_set_address,
4365 .clear_stall = xhci_ep_clear_stall,
4366 .device_state_change = xhci_device_state_change,
4367 .set_hw_power_sleep = xhci_set_hw_power_sleep,
4368 .set_endpoint_mode = xhci_set_endpoint_mode,