4 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
6 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128)
34 #define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */
35 #define XHCI_MAX_SCRATCHPADS 256 /* theoretical max is 1023 */
36 #define XHCI_MAX_EVENTS (16 * 13)
37 #define XHCI_MAX_COMMANDS (16 * 1)
38 #define XHCI_MAX_RSEG 1
39 #define XHCI_MAX_TRANSFERS 4
40 #if USB_MAX_EP_STREAMS == 8
41 #define XHCI_MAX_STREAMS 8
42 #define XHCI_MAX_STREAMS_LOG 3
43 #elif USB_MAX_EP_STREAMS == 1
44 #define XHCI_MAX_STREAMS 1
45 #define XHCI_MAX_STREAMS_LOG 0
47 #error "The USB_MAX_EP_STREAMS value is not supported."
49 #define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */
50 #define XHCI_DEV_CTX_ALIGN 64 /* bytes */
51 #define XHCI_INPUT_CTX_ALIGN 64 /* bytes */
52 #define XHCI_SLOT_CTX_ALIGN 32 /* bytes */
53 #define XHCI_ENDP_CTX_ALIGN 32 /* bytes */
54 #define XHCI_STREAM_CTX_ALIGN 16 /* bytes */
55 #define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */
56 #define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */
57 #define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */
58 #define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */
59 #define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE
60 #define XHCI_TRB_ALIGN 16 /* bytes */
61 #define XHCI_TD_ALIGN 64 /* bytes */
62 #define XHCI_PAGE_SIZE 4096 /* bytes */
64 struct xhci_dev_ctx_addr {
65 volatile uint64_t qwBaaDevCtxAddr[USB_MAX_DEVICES + 1];
67 volatile uint64_t dummy;
68 } __aligned(64) padding;
69 volatile uint64_t qwSpBufPtr[XHCI_MAX_SCRATCHPADS];
72 #define XHCI_EPNO2EPID(x) \
73 ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR)))
75 struct xhci_slot_ctx {
76 volatile uint32_t dwSctx0;
77 #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF)
78 #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF)
79 #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20)
80 #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF)
81 #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25)
82 #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1)
83 #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26)
84 #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1)
85 #define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27)
86 #define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F)
87 volatile uint32_t dwSctx1;
88 #define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF)
89 #define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF)
90 #define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16)
91 #define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF)
92 #define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24)
93 #define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF)
94 volatile uint32_t dwSctx2;
95 #define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF)
96 #define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF)
97 #define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8)
98 #define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF)
99 #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16)
100 #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3)
101 #define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22)
102 #define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF)
103 volatile uint32_t dwSctx3;
104 #define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF)
105 #define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF)
106 #define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27)
107 #define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F)
108 volatile uint32_t dwSctx4;
109 volatile uint32_t dwSctx5;
110 volatile uint32_t dwSctx6;
111 volatile uint32_t dwSctx7;
114 struct xhci_endp_ctx {
115 volatile uint32_t dwEpCtx0;
116 #define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7)
117 #define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7)
118 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8)
119 #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3)
120 #define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10)
121 #define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F)
122 #define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15)
123 #define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1)
124 #define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16)
125 #define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF)
126 volatile uint32_t dwEpCtx1;
127 #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1)
128 #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3)
129 #define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3)
130 #define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7)
131 #define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7)
132 #define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1)
133 #define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8)
134 #define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF)
135 #define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16)
136 #define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF)
137 volatile uint64_t qwEpCtx2;
138 #define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1)
139 #define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1)
140 #define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
141 volatile uint32_t dwEpCtx4;
142 #define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF)
143 #define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF)
144 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16)
145 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF)
146 volatile uint32_t dwEpCtx5;
147 volatile uint32_t dwEpCtx6;
148 volatile uint32_t dwEpCtx7;
151 struct xhci_input_ctx {
152 #define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU
153 volatile uint32_t dwInCtx0;
154 #define XHCI_INCTX_0_DROP_MASK(n) (1U << (n))
155 volatile uint32_t dwInCtx1;
156 #define XHCI_INCTX_1_ADD_MASK(n) (1U << (n))
157 volatile uint32_t dwInCtx2;
158 volatile uint32_t dwInCtx3;
159 volatile uint32_t dwInCtx4;
160 volatile uint32_t dwInCtx5;
161 volatile uint32_t dwInCtx6;
162 volatile uint32_t dwInCtx7;
165 struct xhci_input_dev_ctx {
166 struct xhci_input_ctx ctx_input;
167 struct xhci_slot_ctx ctx_slot;
168 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1];
171 struct xhci_dev_ctx {
172 struct xhci_slot_ctx ctx_slot;
173 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1];
174 } __aligned(XHCI_DEV_CTX_ALIGN);
176 struct xhci_stream_ctx {
177 volatile uint64_t qwSctx0;
178 #define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1)
179 #define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1)
180 #define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1)
181 #define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7)
182 #define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0
183 #define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1
184 #define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2
185 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3
186 #define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4
187 #define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5
188 #define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6
189 #define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7
190 #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U
191 volatile uint32_t dwSctx2;
192 volatile uint32_t dwSctx3;
196 volatile uint64_t qwTrb0;
197 #define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0)
198 #define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48)
199 volatile uint32_t dwTrb2;
200 #define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF)
201 #define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24)
202 #define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F)
203 #define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17)
204 #define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF)
205 #define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF)
206 #define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF)
207 #define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF)
208 #define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF)
209 #define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22)
210 #define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF)
211 #define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16)
213 volatile uint32_t dwTrb3;
214 #define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F)
215 #define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10)
216 #define XHCI_TRB_3_CYCLE_BIT (1U << 0)
217 #define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */
218 #define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */
219 #define XHCI_TRB_3_ISP_BIT (1U << 2)
220 #define XHCI_TRB_3_NSNOOP_BIT (1U << 3)
221 #define XHCI_TRB_3_CHAIN_BIT (1U << 4)
222 #define XHCI_TRB_3_IOC_BIT (1U << 5)
223 #define XHCI_TRB_3_IDT_BIT (1U << 6)
224 #define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3)
225 #define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7)
226 #define XHCI_TRB_3_BEI_BIT (1U << 9)
227 #define XHCI_TRB_3_DCEP_BIT (1U << 9)
228 #define XHCI_TRB_3_PRSV_BIT (1U << 9)
229 #define XHCI_TRB_3_BSR_BIT (1U << 9)
230 #define XHCI_TRB_3_TRT_MASK (3U << 16)
231 #define XHCI_TRB_3_TRT_NONE (0U << 16)
232 #define XHCI_TRB_3_TRT_OUT (2U << 16)
233 #define XHCI_TRB_3_TRT_IN (3U << 16)
234 #define XHCI_TRB_3_DIR_IN (1U << 16)
235 #define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF)
236 #define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16)
237 #define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F)
238 #define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16)
239 #define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF)
240 #define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20)
241 #define XHCI_TRB_3_ISO_SIA_BIT (1U << 31)
242 #define XHCI_TRB_3_SUSP_EP_BIT (1U << 23)
243 #define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF)
244 #define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24)
247 #define XHCI_TRB_TYPE_RESERVED 0x00
248 #define XHCI_TRB_TYPE_NORMAL 0x01
249 #define XHCI_TRB_TYPE_SETUP_STAGE 0x02
250 #define XHCI_TRB_TYPE_DATA_STAGE 0x03
251 #define XHCI_TRB_TYPE_STATUS_STAGE 0x04
252 #define XHCI_TRB_TYPE_ISOCH 0x05
253 #define XHCI_TRB_TYPE_LINK 0x06
254 #define XHCI_TRB_TYPE_EVENT_DATA 0x07
255 #define XHCI_TRB_TYPE_NOOP 0x08
256 #define XHCI_TRB_TYPE_ENABLE_SLOT 0x09
257 #define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A
258 #define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B
259 #define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C
260 #define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D
261 #define XHCI_TRB_TYPE_RESET_EP 0x0E
262 #define XHCI_TRB_TYPE_STOP_EP 0x0F
263 #define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10
264 #define XHCI_TRB_TYPE_RESET_DEVICE 0x11
265 #define XHCI_TRB_TYPE_FORCE_EVENT 0x12
266 #define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13
267 #define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14
268 #define XHCI_TRB_TYPE_GET_PORT_BW 0x15
269 #define XHCI_TRB_TYPE_FORCE_HEADER 0x16
270 #define XHCI_TRB_TYPE_NOOP_CMD 0x17
273 #define XHCI_TRB_EVENT_TRANSFER 0x20
274 #define XHCI_TRB_EVENT_CMD_COMPLETE 0x21
275 #define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22
276 #define XHCI_TRB_EVENT_BW_REQUEST 0x23
277 #define XHCI_TRB_EVENT_DOORBELL 0x24
278 #define XHCI_TRB_EVENT_HOST_CTRL 0x25
279 #define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26
280 #define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27
283 #define XHCI_TRB_ERROR_INVALID 0x00
284 #define XHCI_TRB_ERROR_SUCCESS 0x01
285 #define XHCI_TRB_ERROR_DATA_BUF 0x02
286 #define XHCI_TRB_ERROR_BABBLE 0x03
287 #define XHCI_TRB_ERROR_XACT 0x04
288 #define XHCI_TRB_ERROR_TRB 0x05
289 #define XHCI_TRB_ERROR_STALL 0x06
290 #define XHCI_TRB_ERROR_RESOURCE 0x07
291 #define XHCI_TRB_ERROR_BANDWIDTH 0x08
292 #define XHCI_TRB_ERROR_NO_SLOTS 0x09
293 #define XHCI_TRB_ERROR_STREAM_TYPE 0x0A
294 #define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B
295 #define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C
296 #define XHCI_TRB_ERROR_SHORT_PKT 0x0D
297 #define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E
298 #define XHCI_TRB_ERROR_RING_OVERRUN 0x0F
299 #define XHCI_TRB_ERROR_VF_RING_FULL 0x10
300 #define XHCI_TRB_ERROR_PARAMETER 0x11
301 #define XHCI_TRB_ERROR_BW_OVERRUN 0x12
302 #define XHCI_TRB_ERROR_CONTEXT_STATE 0x13
303 #define XHCI_TRB_ERROR_NO_PING_RESP 0x14
304 #define XHCI_TRB_ERROR_EV_RING_FULL 0x15
305 #define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16
306 #define XHCI_TRB_ERROR_MISSED_SERVICE 0x17
307 #define XHCI_TRB_ERROR_CMD_RING_STOP 0x18
308 #define XHCI_TRB_ERROR_CMD_ABORTED 0x19
309 #define XHCI_TRB_ERROR_STOPPED 0x1A
310 #define XHCI_TRB_ERROR_LENGTH 0x1B
311 #define XHCI_TRB_ERROR_BAD_MELAT 0x1D
312 #define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F
313 #define XHCI_TRB_ERROR_EVENT_LOST 0x20
314 #define XHCI_TRB_ERROR_UNDEFINED 0x21
315 #define XHCI_TRB_ERROR_INVALID_SID 0x22
316 #define XHCI_TRB_ERROR_SEC_BW 0x23
317 #define XHCI_TRB_ERROR_SPLIT_XACT 0x24
320 struct xhci_dev_endpoint_trbs {
321 struct xhci_trb trb[(XHCI_MAX_STREAMS *
322 XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS];
325 #if (USB_PAGE_SIZE < 4096)
326 #error "The XHCI driver needs a pagesize above or equal to 4K"
329 /* Define the maximum payload which we will handle in a single TRB */
330 #define XHCI_TD_PAYLOAD_MAX 65536 /* bytes */
332 /* Define the maximum payload of a single scatter-gather list element */
333 #define XHCI_TD_PAGE_SIZE \
334 ((USB_PAGE_SIZE < XHCI_TD_PAYLOAD_MAX) ? USB_PAGE_SIZE : XHCI_TD_PAYLOAD_MAX)
336 /* Define the maximum length of the scatter-gather list */
337 #define XHCI_TD_PAGE_NBUF \
338 (((XHCI_TD_PAYLOAD_MAX + XHCI_TD_PAGE_SIZE - 1) / XHCI_TD_PAGE_SIZE) + 1)
341 /* one LINK TRB has been added to the TRB array */
342 struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF + 1];
345 * Extra information needed:
348 struct xhci_td *next;
349 struct xhci_td *alt_next;
350 struct xhci_td *obj_next;
351 struct usb_page_cache *page_cache;
356 } __aligned(XHCI_TRB_ALIGN);
358 struct xhci_command {
360 TAILQ_ENTRY(xhci_command) entry;
363 struct xhci_event_ring_seg {
364 volatile uint64_t qwEvrsTablePtr;
365 volatile uint32_t dwEvrsTableSize;
366 volatile uint32_t dwEvrsReserved;
369 struct xhci_hw_root {
370 struct xhci_event_ring_seg hwr_ring_seg[XHCI_MAX_RSEG];
372 volatile uint64_t dummy;
373 } __aligned(64) padding;
374 struct xhci_trb hwr_events[XHCI_MAX_EVENTS];
375 struct xhci_trb hwr_commands[XHCI_MAX_COMMANDS];
378 struct xhci_endpoint_ext {
379 struct xhci_trb *trb;
380 struct usb_xfer *xfer[XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS];
381 struct usb_page_cache *page_cache;
383 uint8_t trb_used[XHCI_MAX_STREAMS];
384 uint8_t trb_index[XHCI_MAX_STREAMS];
401 struct usb_page_cache device_pc;
402 struct usb_page_cache input_pc;
403 struct usb_page_cache endpoint_pc[XHCI_MAX_ENDPOINTS];
405 struct usb_page device_pg;
406 struct usb_page input_pg;
407 struct usb_page endpoint_pg[XHCI_MAX_ENDPOINTS];
409 struct xhci_endpoint_ext endp[XHCI_MAX_ENDPOINTS];
417 struct xhci_hw_softc {
418 struct usb_page_cache root_pc;
419 struct usb_page_cache ctx_pc;
420 struct usb_page_cache scratch_pc[XHCI_MAX_SCRATCHPADS];
422 struct usb_page root_pg;
423 struct usb_page ctx_pg;
424 struct usb_page scratch_pg[XHCI_MAX_SCRATCHPADS];
426 struct xhci_hw_dev devs[XHCI_MAX_DEVICES + 1];
429 struct xhci_config_desc {
430 struct usb_config_descriptor confd;
431 struct usb_interface_descriptor ifcd;
432 struct usb_endpoint_descriptor endpd;
433 struct usb_endpoint_ss_comp_descriptor endpcd;
436 struct xhci_bos_desc {
437 struct usb_bos_descriptor bosd;
438 struct usb_devcap_usb2ext_descriptor usb2extd;
439 struct usb_devcap_ss_descriptor usbdcd;
440 struct usb_devcap_container_id_descriptor cidd;
443 union xhci_hub_desc {
444 struct usb_status stat;
445 struct usb_port_status ps;
446 struct usb_hub_ss_descriptor hubd;
450 typedef int (xhci_port_route_t)(device_t, uint32_t, uint32_t);
453 struct xhci_hw_softc sc_hw;
455 struct usb_bus sc_bus;
456 /* configure message */
457 struct usb_bus_msg sc_config_msg[2];
459 struct usb_callout sc_callout;
461 xhci_port_route_t *sc_port_route;
463 union xhci_hub_desc sc_hub_desc;
468 struct usb_device *sc_devices[XHCI_MAX_DEVICES];
469 struct resource *sc_io_res;
470 struct resource *sc_irq_res;
471 struct resource *sc_msix_res;
474 bus_size_t sc_io_size;
475 bus_space_tag_t sc_io_tag;
476 bus_space_handle_t sc_io_hdl;
477 /* last pending command address */
478 uint64_t sc_cmd_addr;
479 /* result of command */
480 uint32_t sc_cmd_result[2];
481 /* copy of cmd register */
483 /* worst case exit latency */
484 uint32_t sc_exit_lat_max;
486 /* offset to operational registers */
487 uint32_t sc_oper_off;
488 /* offset to capability registers */
489 uint32_t sc_capa_off;
490 /* offset to runtime registers */
491 uint32_t sc_runt_off;
492 /* offset to doorbell registers */
493 uint32_t sc_door_off;
496 uint16_t sc_erst_max;
497 uint16_t sc_event_idx;
498 uint16_t sc_command_idx;
499 uint16_t sc_imod_default;
501 /* number of scratch pages */
502 uint16_t sc_noscratch;
504 uint8_t sc_event_ccs;
505 uint8_t sc_command_ccs;
506 /* number of XHCI device slots */
508 /* number of ports on root HUB */
510 /* root HUB device configuration */
512 /* step status stage of all control transfers */
514 /* root HUB port event bitmap, max 256 ports */
515 uint8_t sc_hub_idata[32];
517 /* size of context */
518 uint8_t sc_ctx_is_64_byte;
520 /* vendor string for root HUB */
524 #define XHCI_CMD_LOCK(sc) sx_xlock(&(sc)->sc_cmd_sx)
525 #define XHCI_CMD_UNLOCK(sc) sx_xunlock(&(sc)->sc_cmd_sx)
526 #define XHCI_CMD_ASSERT_LOCKED(sc) sx_assert(&(sc)->sc_cmd_sx, SA_LOCKED)
530 uint8_t xhci_use_polling(void);
531 usb_error_t xhci_halt_controller(struct xhci_softc *);
532 usb_error_t xhci_reset_controller(struct xhci_softc *);
533 usb_error_t xhci_init(struct xhci_softc *, device_t, uint8_t);
534 usb_error_t xhci_start_controller(struct xhci_softc *);
535 void xhci_interrupt(struct xhci_softc *);
536 void xhci_uninit(struct xhci_softc *);
538 #endif /* _XHCI_H_ */