2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet
37 * chip. The Pegasus uses a total of four USB endpoints: the control
38 * endpoint (0), a bulk read endpoint for receiving packets (1),
39 * a bulk write endpoint for sending packets (2) and an interrupt
40 * endpoint for passing RX and TX status (3). Endpoint 0 is used
41 * to read and write the ethernet module's registers. All registers
44 * Packet transfer is done in 64 byte chunks. The last chunk in a
45 * transfer is denoted by having a length less that 64 bytes. For
46 * the RX case, the data includes an optional RX status word.
49 #define AUE_VENDORID_ADMTEK 0x07A6
50 #define AUE_DEVICEID_PEGASUS 0x0986
52 #define AUE_VENDORID_BILLIONTON 0x08DD
53 #define AUE_DEVICEID_USB100 0x0986
55 #define AUE_VENDORID_MELCO 0x0411
56 #define AUE_DEVICEID_LUATX 0x0001
59 #define AUE_UR_READREG 0xF0
60 #define AUE_UR_WRITEREG 0xF1
63 * Note that while the ADMtek technically has four
64 * endpoints, the control endpoint (endpoint 0) is
65 * regarded as special by the USB code and drivers
66 * don't have direct access to it. (We access it
67 * using usbd_do_request() when reading/writing
68 * registers.) Consequently, our endpoint indexes
69 * don't match those in the ADMtek Pegasus manual:
70 * we consider the RX data endpoint to be index 0
71 * and work up from there.
73 #define AUE_ENDPT_RX 0x0
74 #define AUE_ENDPT_TX 0x1
75 #define AUE_ENDPT_INTR 0x2
76 #define AUE_ENDPT_MAX 0x3
78 #define AUE_INTR_PKTLEN 0x8
91 #define AUE_MAR AUE_MAR0
98 #define AUE_PAR AUE_PAR0
99 #define AUE_PAUSE0 0x18
100 #define AUE_PAUSE1 0x19
101 #define AUE_PAUSE AUE_PAUSE0
102 #define AUE_RX_FLOWCTL_CNT 0x1A
103 #define AUE_RX_FLOWCTL_FIFO 0x1B
104 #define AUE_EE_REG 0x20
105 #define AUE_EE_DATA0 0x21
106 #define AUE_EE_DATA1 0x22
107 #define AUE_EE_DATA AUE_EE_DATA0
108 #define AUE_EE_CTL 0x23
109 #define AUE_PHY_ADDR 0x25
110 #define AUE_PHY_DATA0 0x26
111 #define AUE_PHY_DATA1 0x27
112 #define AUE_PHY_DATA AUE_PHY_DATA0
113 #define AUE_PHY_CTL 0x28
114 #define AUE_USB_STS 0x2A
115 #define AUE_TXSTAT0 0x2B
116 #define AUE_TXSTAT1 0x2C
117 #define AUE_TXSTAT AUE_TXSTAT0
118 #define AUE_RXSTAT 0x2D
119 #define AUE_PKTLOST0 0x2E
120 #define AUE_PKTLOST1 0x2F
121 #define AUE_PKTLOST AUE_PKTLOST0
123 #define AUE_GPIO0 0x7E
124 #define AUE_GPIO1 0x7F
126 #define AUE_CTL0_INCLUDE_RXCRC 0x01
127 #define AUE_CTL0_ALLMULTI 0x02
128 #define AUE_CTL0_STOP_BACKOFF 0x04
129 #define AUE_CTL0_RXSTAT_APPEND 0x08
130 #define AUE_CTL0_WAKEON_ENB 0x10
131 #define AUE_CTL0_RXPAUSE_ENB 0x20
132 #define AUE_CTL0_RX_ENB 0x40
133 #define AUE_CTL0_TX_ENB 0x80
135 #define AUE_CTL1_HOMELAN 0x04
136 #define AUE_CTL1_RESETMAC 0x08
137 #define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */
138 #define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */
139 #define AUE_CTL1_DELAYHOME 0x40
141 #define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */
142 #define AUE_CTL2_RX_BADFRAMES 0x02
143 #define AUE_CTL2_RX_PROMISC 0x04
144 #define AUE_CTL2_LOOPBACK 0x08
145 #define AUE_CTL2_EEPROMWR_ENB 0x10
146 #define AUE_CTL2_EEPROM_LOAD 0x20
148 #define AUE_EECTL_WRITE 0x01
149 #define AUE_EECTL_READ 0x02
150 #define AUE_EECTL_DONE 0x04
152 #define AUE_PHYCTL_PHYREG 0x1F
153 #define AUE_PHYCTL_WRITE 0x20
154 #define AUE_PHYCTL_READ 0x40
155 #define AUE_PHYCTL_DONE 0x80
157 #define AUE_USBSTS_SUSPEND 0x01
158 #define AUE_USBSTS_RESUME 0x02
160 #define AUE_TXSTAT0_JABTIMO 0x04
161 #define AUE_TXSTAT0_CARLOSS 0x08
162 #define AUE_TXSTAT0_NOCARRIER 0x10
163 #define AUE_TXSTAT0_LATECOLL 0x20
164 #define AUE_TXSTAT0_EXCESSCOLL 0x40
165 #define AUE_TXSTAT0_UNDERRUN 0x80
167 #define AUE_TXSTAT1_PKTCNT 0x0F
168 #define AUE_TXSTAT1_FIFO_EMPTY 0x40
169 #define AUE_TXSTAT1_FIFO_FULL 0x80
171 #define AUE_RXSTAT_OVERRUN 0x01
172 #define AUE_RXSTAT_PAUSE 0x02
174 #define AUE_GPIO_IN0 0x01
175 #define AUE_GPIO_OUT0 0x02
176 #define AUE_GPIO_SEL0 0x04
177 #define AUE_GPIO_IN1 0x08
178 #define AUE_GPIO_OUT1 0x10
179 #define AUE_GPIO_SEL1 0x20
182 u_int8_t aue_txstat0;
183 u_int8_t aue_txstat1;
185 u_int8_t aue_rxlostpkt0;
186 u_int8_t aue_rxlostpkt1;
187 u_int8_t aue_wakeupstat;
192 u_int16_t aue_pktlen;
196 #define AUE_RXSTAT_MCAST 0x01
197 #define AUE_RXSTAT_GIANT 0x02
198 #define AUE_RXSTAT_RUNT 0x04
199 #define AUE_RXSTAT_CRCERR 0x08
200 #define AUE_RXSTAT_DRIBBLE 0x10
201 #define AUE_RXSTAT_MASK 0x1E
209 #define AUE_TX_LIST_CNT 1
210 #define AUE_RX_LIST_CNT 1
215 struct aue_softc *aue_sc;
216 usbd_xfer_handle aue_xfer;
218 struct mbuf *aue_mbuf;
224 struct aue_chain aue_tx_chain[AUE_TX_LIST_CNT];
225 struct aue_chain aue_rx_chain[AUE_RX_LIST_CNT];
226 struct aue_intrpkt *aue_ibuf;
233 #define AUE_INC(x, y) (x) = (x + 1) % y
236 struct arpcom arpcom;
238 usbd_device_handle aue_udev;
239 usbd_interface_handle aue_iface;
240 int aue_ed[AUE_ENDPT_MAX];
241 usbd_pipe_handle aue_ep[AUE_ENDPT_MAX];
245 struct aue_cdata aue_cdata;
246 struct callout_handle aue_stat_ch;
249 #define AUE_TIMEOUT 1000
250 #define ETHER_ALIGN 2
251 #define AUE_BUFSZ 1536
252 #define AUE_CUTOFF 1088
253 #define AUE_MIN_FRAMELEN 60