2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
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11 * notice, this list of conditions and the following disclaimer.
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13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
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19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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32 * THE POSSIBILITY OF SUCH DAMAGE.
38 * Register definitions for ADMtek Pegasus AN986 USB to Ethernet
39 * chip. The Pegasus uses a total of four USB endpoints: the control
40 * endpoint (0), a bulk read endpoint for receiving packets (1),
41 * a bulk write endpoint for sending packets (2) and an interrupt
42 * endpoint for passing RX and TX status (3). Endpoint 0 is used
43 * to read and write the ethernet module's registers. All registers
46 * Packet transfer is done in 64 byte chunks. The last chunk in a
47 * transfer is denoted by having a length less that 64 bytes. For
48 * the RX case, the data includes an optional RX status word.
51 #define AUE_UR_READREG 0xF0
52 #define AUE_UR_WRITEREG 0xF1
54 #define AUE_CONFIG_INDEX 0 /* config number 1 */
55 #define AUE_IFACE_IDX 0
58 * Note that while the ADMtek technically has four endpoints, the control
59 * endpoint (endpoint 0) is regarded as special by the USB code and drivers
60 * don't have direct access to it (we access it using usbd_do_request()
61 * when reading/writing registers. Consequently, our endpoint indexes
62 * don't match those in the ADMtek Pegasus manual: we consider the RX data
63 * endpoint to be index 0 and work up from there.
72 #define AUE_INTR_PKTLEN 0x8
85 #define AUE_MAR AUE_MAR0
92 #define AUE_PAR AUE_PAR0
93 #define AUE_PAUSE0 0x18
94 #define AUE_PAUSE1 0x19
95 #define AUE_PAUSE AUE_PAUSE0
96 #define AUE_RX_FLOWCTL_CNT 0x1A
97 #define AUE_RX_FLOWCTL_FIFO 0x1B
98 #define AUE_REG_1D 0x1D
99 #define AUE_EE_REG 0x20
100 #define AUE_EE_DATA0 0x21
101 #define AUE_EE_DATA1 0x22
102 #define AUE_EE_DATA AUE_EE_DATA0
103 #define AUE_EE_CTL 0x23
104 #define AUE_PHY_ADDR 0x25
105 #define AUE_PHY_DATA0 0x26
106 #define AUE_PHY_DATA1 0x27
107 #define AUE_PHY_DATA AUE_PHY_DATA0
108 #define AUE_PHY_CTL 0x28
109 #define AUE_USB_STS 0x2A
110 #define AUE_TXSTAT0 0x2B
111 #define AUE_TXSTAT1 0x2C
112 #define AUE_TXSTAT AUE_TXSTAT0
113 #define AUE_RXSTAT 0x2D
114 #define AUE_PKTLOST0 0x2E
115 #define AUE_PKTLOST1 0x2F
116 #define AUE_PKTLOST AUE_PKTLOST0
118 #define AUE_REG_7B 0x7B
119 #define AUE_GPIO0 0x7E
120 #define AUE_GPIO1 0x7F
121 #define AUE_REG_81 0x81
123 #define AUE_CTL0_INCLUDE_RXCRC 0x01
124 #define AUE_CTL0_ALLMULTI 0x02
125 #define AUE_CTL0_STOP_BACKOFF 0x04
126 #define AUE_CTL0_RXSTAT_APPEND 0x08
127 #define AUE_CTL0_WAKEON_ENB 0x10
128 #define AUE_CTL0_RXPAUSE_ENB 0x20
129 #define AUE_CTL0_RX_ENB 0x40
130 #define AUE_CTL0_TX_ENB 0x80
132 #define AUE_CTL1_HOMELAN 0x04
133 #define AUE_CTL1_RESETMAC 0x08
134 #define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */
135 #define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */
136 #define AUE_CTL1_DELAYHOME 0x40
138 #define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */
139 #define AUE_CTL2_RX_BADFRAMES 0x02
140 #define AUE_CTL2_RX_PROMISC 0x04
141 #define AUE_CTL2_LOOPBACK 0x08
142 #define AUE_CTL2_EEPROMWR_ENB 0x10
143 #define AUE_CTL2_EEPROM_LOAD 0x20
145 #define AUE_EECTL_WRITE 0x01
146 #define AUE_EECTL_READ 0x02
147 #define AUE_EECTL_DONE 0x04
149 #define AUE_PHYCTL_PHYREG 0x1F
150 #define AUE_PHYCTL_WRITE 0x20
151 #define AUE_PHYCTL_READ 0x40
152 #define AUE_PHYCTL_DONE 0x80
154 #define AUE_USBSTS_SUSPEND 0x01
155 #define AUE_USBSTS_RESUME 0x02
157 #define AUE_TXSTAT0_JABTIMO 0x04
158 #define AUE_TXSTAT0_CARLOSS 0x08
159 #define AUE_TXSTAT0_NOCARRIER 0x10
160 #define AUE_TXSTAT0_LATECOLL 0x20
161 #define AUE_TXSTAT0_EXCESSCOLL 0x40
162 #define AUE_TXSTAT0_UNDERRUN 0x80
164 #define AUE_TXSTAT1_PKTCNT 0x0F
165 #define AUE_TXSTAT1_FIFO_EMPTY 0x40
166 #define AUE_TXSTAT1_FIFO_FULL 0x80
168 #define AUE_RXSTAT_OVERRUN 0x01
169 #define AUE_RXSTAT_PAUSE 0x02
171 #define AUE_GPIO_IN0 0x01
172 #define AUE_GPIO_OUT0 0x02
173 #define AUE_GPIO_SEL0 0x04
174 #define AUE_GPIO_IN1 0x08
175 #define AUE_GPIO_OUT1 0x10
176 #define AUE_GPIO_SEL1 0x20
178 #define AUE_TIMEOUT 100 /* 10*ms */
179 #define AUE_MIN_FRAMELEN 60
181 #define AUE_RXSTAT_MCAST 0x01
182 #define AUE_RXSTAT_GIANT 0x02
183 #define AUE_RXSTAT_RUNT 0x04
184 #define AUE_RXSTAT_CRCERR 0x08
185 #define AUE_RXSTAT_DRIBBLE 0x10
186 #define AUE_RXSTAT_MASK 0x1E
188 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue)
194 uint8_t aue_rxlostpkt0;
195 uint8_t aue_rxlostpkt1;
196 uint8_t aue_wakeupstat;
207 struct usb_ether sc_ue;
209 struct usb_xfer *sc_xfer[AUE_N_TRANSFER];
212 #define AUE_FLAG_LSYS 0x0001 /* use Linksys reset */
213 #define AUE_FLAG_PNA 0x0002 /* has Home PNA */
214 #define AUE_FLAG_PII 0x0004 /* Pegasus II chip */
215 #define AUE_FLAG_LINK 0x0008 /* wait for link to come up */
216 #define AUE_FLAG_VER_2 0x0200 /* chip is version 2 */
217 #define AUE_FLAG_DUAL_PHY 0x0400 /* chip has two transcivers */
220 #define AUE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
221 #define AUE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
222 #define AUE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)