2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998, 1999, 2000-2003
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
40 * Used in the LinkSys USB200M and various other adapters.
42 * Manuals available from:
43 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
44 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
45 * controller) to find the definitions for the RX control register.
46 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
48 * Written by Bill Paul <wpaul@windriver.com>
54 * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
55 * It uses an external PHY (reference designs use a RealTek chip),
56 * and has a 64-bit multicast hash filter. There is some information
57 * missing from the manual which one needs to know in order to make
60 * - You must set bit 7 in the RX control register, otherwise the
61 * chip won't receive any packets.
62 * - You must initialize all 3 IPG registers, or you won't be able
63 * to send any packets.
65 * Note that this device appears to only support loading the station
66 * address via autload from the EEPROM (i.e. there's no way to manually
69 * (Adam Weinberger wanted me to name this driver if_gir.c.)
73 * Ax88178 and Ax88772 support backported from the OpenBSD driver.
74 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
77 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
78 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
81 #include <sys/param.h>
82 #include <sys/systm.h>
84 #include <sys/condvar.h>
85 #include <sys/endian.h>
86 #include <sys/kernel.h>
88 #include <sys/malloc.h>
90 #include <sys/module.h>
91 #include <sys/mutex.h>
92 #include <sys/socket.h>
93 #include <sys/sockio.h>
94 #include <sys/sysctl.h>
98 #include <net/if_var.h>
99 #include <net/ethernet.h>
100 #include <net/if_types.h>
101 #include <net/if_media.h>
102 #include <net/if_vlan_var.h>
104 #include <dev/mii/mii.h>
105 #include <dev/mii/miivar.h>
107 #include <dev/usb/usb.h>
108 #include <dev/usb/usbdi.h>
109 #include <dev/usb/usbdi_util.h>
112 #define USB_DEBUG_VAR axe_debug
113 #include <dev/usb/usb_debug.h>
114 #include <dev/usb/usb_process.h>
116 #include <dev/usb/net/usb_ethernet.h>
117 #include <dev/usb/net/if_axereg.h>
119 #include "miibus_if.h"
122 * AXE_178_MAX_FRAME_BURST
123 * max frame burst size for Ax88178 and Ax88772
128 * use the largest your system can handle without USB stalling.
130 * NB: 88772 parts appear to generate lots of input errors with
131 * a 2K rx buffer and 8K is only slightly faster than 4K on an
132 * EHCI port on a T42 so change at your own risk.
134 #define AXE_178_MAX_FRAME_BURST 1
136 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
139 static int axe_debug = 0;
141 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
143 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0,
148 * Various supported device vendors/products.
150 static const STRUCT_USB_HOST_ID axe_devs[] = {
151 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
152 AXE_DEV(ABOCOM, UF200, 0),
153 AXE_DEV(ACERCM, EP1427X2, 0),
154 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
155 AXE_DEV(ASIX, AX88172, 0),
156 AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
157 AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
158 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
159 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B),
160 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B),
161 AXE_DEV(ATEN, UC210T, 0),
162 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
163 AXE_DEV(BILLIONTON, USB2AR, 0),
164 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A),
165 AXE_DEV(COREGA, FETHER_USB2_TX, 0),
166 AXE_DEV(DLINK, DUBE100, 0),
167 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
168 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B),
169 AXE_DEV(GOODWAY, GWUSB2E, 0),
170 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
171 AXE_DEV(JVC, MP_PRX1, 0),
172 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B),
173 AXE_DEV(LINKSYS2, USB200M, 0),
174 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
175 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
176 AXE_DEV(MELCO, LUAU2KTX, 0),
177 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
178 AXE_DEV(NETGEAR, FA120, 0),
179 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
180 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
181 AXE_DEV(SITECOM, LN029, 0),
182 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
183 AXE_DEV(SITECOMEU, LN031, AXE_FLAG_178),
184 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
188 static device_probe_t axe_probe;
189 static device_attach_t axe_attach;
190 static device_detach_t axe_detach;
192 static usb_callback_t axe_bulk_read_callback;
193 static usb_callback_t axe_bulk_write_callback;
195 static miibus_readreg_t axe_miibus_readreg;
196 static miibus_writereg_t axe_miibus_writereg;
197 static miibus_statchg_t axe_miibus_statchg;
199 static uether_fn_t axe_attach_post;
200 static uether_fn_t axe_init;
201 static uether_fn_t axe_stop;
202 static uether_fn_t axe_start;
203 static uether_fn_t axe_tick;
204 static uether_fn_t axe_setmulti;
205 static uether_fn_t axe_setpromisc;
207 static int axe_attach_post_sub(struct usb_ether *);
208 static int axe_ifmedia_upd(struct ifnet *);
209 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
210 static int axe_cmd(struct axe_softc *, int, int, int, void *);
211 static void axe_ax88178_init(struct axe_softc *);
212 static void axe_ax88772_init(struct axe_softc *);
213 static void axe_ax88772_phywake(struct axe_softc *);
214 static void axe_ax88772a_init(struct axe_softc *);
215 static void axe_ax88772b_init(struct axe_softc *);
216 static int axe_get_phyno(struct axe_softc *, int);
217 static int axe_ioctl(struct ifnet *, u_long, caddr_t);
218 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
219 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *,
220 unsigned int offset, unsigned int, struct axe_csum_hdr *);
221 static void axe_csum_cfg(struct usb_ether *);
223 static const struct usb_config axe_config[AXE_N_TRANSFER] = {
226 .endpoint = UE_ADDR_ANY,
227 .direction = UE_DIR_OUT,
229 .bufsize = 16 * MCLBYTES,
230 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
231 .callback = axe_bulk_write_callback,
232 .timeout = 10000, /* 10 seconds */
237 .endpoint = UE_ADDR_ANY,
238 .direction = UE_DIR_IN,
239 .bufsize = 16384, /* bytes */
240 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
241 .callback = axe_bulk_read_callback,
242 .timeout = 0, /* no timeout */
246 static const struct ax88772b_mfb ax88772b_mfb_table[] = {
247 { 0x8000, 0x8001, 2048 },
248 { 0x8100, 0x8147, 4096},
249 { 0x8200, 0x81EB, 6144},
250 { 0x8300, 0x83D7, 8192},
251 { 0x8400, 0x851E, 16384},
252 { 0x8500, 0x8666, 20480},
253 { 0x8600, 0x87AE, 24576},
254 { 0x8700, 0x8A3D, 32768}
257 static device_method_t axe_methods[] = {
258 /* Device interface */
259 DEVMETHOD(device_probe, axe_probe),
260 DEVMETHOD(device_attach, axe_attach),
261 DEVMETHOD(device_detach, axe_detach),
264 DEVMETHOD(miibus_readreg, axe_miibus_readreg),
265 DEVMETHOD(miibus_writereg, axe_miibus_writereg),
266 DEVMETHOD(miibus_statchg, axe_miibus_statchg),
271 static driver_t axe_driver = {
273 .methods = axe_methods,
274 .size = sizeof(struct axe_softc),
277 static devclass_t axe_devclass;
279 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0);
280 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0);
281 MODULE_DEPEND(axe, uether, 1, 1, 1);
282 MODULE_DEPEND(axe, usb, 1, 1, 1);
283 MODULE_DEPEND(axe, ether, 1, 1, 1);
284 MODULE_DEPEND(axe, miibus, 1, 1, 1);
285 MODULE_VERSION(axe, 1);
286 USB_PNP_HOST_INFO(axe_devs);
288 static const struct usb_ether_methods axe_ue_methods = {
289 .ue_attach_post = axe_attach_post,
290 .ue_attach_post_sub = axe_attach_post_sub,
291 .ue_start = axe_start,
295 .ue_setmulti = axe_setmulti,
296 .ue_setpromisc = axe_setpromisc,
297 .ue_mii_upd = axe_ifmedia_upd,
298 .ue_mii_sts = axe_ifmedia_sts,
302 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
304 struct usb_device_request req;
307 AXE_LOCK_ASSERT(sc, MA_OWNED);
309 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
310 UT_WRITE_VENDOR_DEVICE :
311 UT_READ_VENDOR_DEVICE);
312 req.bRequest = AXE_CMD_CMD(cmd);
313 USETW(req.wValue, val);
314 USETW(req.wIndex, index);
315 USETW(req.wLength, AXE_CMD_LEN(cmd));
317 err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
323 axe_miibus_readreg(device_t dev, int phy, int reg)
325 struct axe_softc *sc = device_get_softc(dev);
329 locked = mtx_owned(&sc->sc_mtx);
333 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
334 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
335 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
338 if (AXE_IS_772(sc) && reg == MII_BMSR) {
340 * BMSR of AX88772 indicates that it supports extended
341 * capability but the extended status register is
342 * revered for embedded ethernet PHY. So clear the
343 * extended capability bit of BMSR.
354 axe_miibus_writereg(device_t dev, int phy, int reg, int val)
356 struct axe_softc *sc = device_get_softc(dev);
360 locked = mtx_owned(&sc->sc_mtx);
364 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
365 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
366 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
374 axe_miibus_statchg(device_t dev)
376 struct axe_softc *sc = device_get_softc(dev);
377 struct mii_data *mii = GET_MII(sc);
382 locked = mtx_owned(&sc->sc_mtx);
386 ifp = uether_getifp(&sc->sc_ue);
387 if (mii == NULL || ifp == NULL ||
388 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
391 sc->sc_flags &= ~AXE_FLAG_LINK;
392 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
393 (IFM_ACTIVE | IFM_AVALID)) {
394 switch (IFM_SUBTYPE(mii->mii_media_active)) {
397 sc->sc_flags |= AXE_FLAG_LINK;
400 if ((sc->sc_flags & AXE_FLAG_178) == 0)
402 sc->sc_flags |= AXE_FLAG_LINK;
409 /* Lost link, do nothing. */
410 if ((sc->sc_flags & AXE_FLAG_LINK) == 0)
414 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
415 val |= AXE_MEDIA_FULL_DUPLEX;
416 if (AXE_IS_178_FAMILY(sc)) {
417 if ((IFM_OPTIONS(mii->mii_media_active) &
418 IFM_ETH_TXPAUSE) != 0)
419 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN;
420 if ((IFM_OPTIONS(mii->mii_media_active) &
421 IFM_ETH_RXPAUSE) != 0)
422 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN;
425 if (AXE_IS_178_FAMILY(sc)) {
426 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
427 if ((sc->sc_flags & AXE_FLAG_178) != 0)
428 val |= AXE_178_MEDIA_ENCK;
429 switch (IFM_SUBTYPE(mii->mii_media_active)) {
431 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
434 val |= AXE_178_MEDIA_100TX;
437 /* doesn't need to be handled */
441 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
443 device_printf(dev, "media change failed, error %d\n", err);
453 axe_ifmedia_upd(struct ifnet *ifp)
455 struct axe_softc *sc = ifp->if_softc;
456 struct mii_data *mii = GET_MII(sc);
457 struct mii_softc *miisc;
460 AXE_LOCK_ASSERT(sc, MA_OWNED);
462 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
464 error = mii_mediachg(mii);
469 * Report current media status.
472 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
474 struct axe_softc *sc = ifp->if_softc;
475 struct mii_data *mii = GET_MII(sc);
479 ifmr->ifm_active = mii->mii_media_active;
480 ifmr->ifm_status = mii->mii_media_status;
485 axe_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
487 uint8_t *hashtbl = arg;
490 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
491 hashtbl[h / 8] |= 1 << (h % 8);
497 axe_setmulti(struct usb_ether *ue)
499 struct axe_softc *sc = uether_getsc(ue);
500 struct ifnet *ifp = uether_getifp(ue);
502 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
504 AXE_LOCK_ASSERT(sc, MA_OWNED);
506 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
507 rxmode = le16toh(rxmode);
509 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
510 rxmode |= AXE_RXCMD_ALLMULTI;
511 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
514 rxmode &= ~AXE_RXCMD_ALLMULTI;
516 if_foreach_llmaddr(ifp, axe_hash_maddr, &hashtbl);
518 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
519 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
523 axe_get_phyno(struct axe_softc *sc, int sel)
527 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
528 case PHY_TYPE_100_HOME:
530 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
532 case PHY_TYPE_SPECIAL:
536 case PHY_TYPE_NON_SUP:
546 #define AXE_GPIO_WRITE(x, y) do { \
547 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \
548 uether_pause(ue, (y)); \
552 axe_ax88178_init(struct axe_softc *sc)
554 struct usb_ether *ue;
555 int gpio0, ledmode, phymode;
556 uint16_t eeprom, val;
559 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
561 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
562 eeprom = le16toh(eeprom);
563 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
565 /* if EEPROM is invalid we have to use to GPIO0 */
566 if (eeprom == 0xffff) {
567 phymode = AXE_PHY_MODE_MARVELL;
571 phymode = eeprom & 0x7f;
572 gpio0 = (eeprom & 0x80) ? 0 : 1;
573 ledmode = eeprom >> 8;
577 device_printf(sc->sc_ue.ue_dev,
578 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
580 /* Program GPIOs depending on PHY hardware. */
582 case AXE_PHY_MODE_MARVELL:
584 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
586 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
588 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
589 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
592 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
593 AXE_GPIO1_EN, hz / 3);
595 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
596 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
599 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
600 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
601 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
602 AXE_GPIO2_EN, hz / 4);
603 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
604 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
608 case AXE_PHY_MODE_CICADA:
609 case AXE_PHY_MODE_CICADA_V2:
610 case AXE_PHY_MODE_CICADA_V2_ASIX:
612 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
613 AXE_GPIO0_EN, hz / 32);
615 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
616 AXE_GPIO1_EN, hz / 32);
618 case AXE_PHY_MODE_AGERE:
619 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
620 AXE_GPIO1_EN, hz / 32);
621 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
622 AXE_GPIO2_EN, hz / 32);
623 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
624 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
625 AXE_GPIO2_EN, hz / 32);
627 case AXE_PHY_MODE_REALTEK_8211CL:
628 case AXE_PHY_MODE_REALTEK_8211BN:
629 case AXE_PHY_MODE_REALTEK_8251CL:
630 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
631 AXE_GPIO1 | AXE_GPIO1_EN;
632 AXE_GPIO_WRITE(val, hz / 32);
633 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
634 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
635 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
636 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
637 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
639 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
641 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
643 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
645 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
650 /* Unknown PHY model or no need to program GPIOs. */
655 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
656 uether_pause(ue, hz / 4);
658 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
659 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
660 uether_pause(ue, hz / 4);
661 /* Enable MII/GMII/RGMII interface to work with external PHY. */
662 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
663 uether_pause(ue, hz / 4);
665 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
669 axe_ax88772_init(struct axe_softc *sc)
671 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
672 uether_pause(&sc->sc_ue, hz / 16);
674 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
675 /* ask for the embedded PHY */
676 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
677 uether_pause(&sc->sc_ue, hz / 64);
679 /* power down and reset state, pin reset state */
680 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
681 AXE_SW_RESET_CLEAR, NULL);
682 uether_pause(&sc->sc_ue, hz / 16);
684 /* power down/reset state, pin operating state */
685 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
686 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
687 uether_pause(&sc->sc_ue, hz / 4);
689 /* power up, reset */
690 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
692 /* power up, operating */
693 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
694 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
696 /* ask for external PHY */
697 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
698 uether_pause(&sc->sc_ue, hz / 64);
700 /* power down internal PHY */
701 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
702 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
705 uether_pause(&sc->sc_ue, hz / 4);
706 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
710 axe_ax88772_phywake(struct axe_softc *sc)
712 struct usb_ether *ue;
715 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
716 /* Manually select internal(embedded) PHY - MAC mode. */
717 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
718 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
720 uether_pause(&sc->sc_ue, hz / 32);
723 * Manually select external PHY - MAC mode.
724 * Reverse MII/RMII is for AX88772A PHY mode.
726 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
727 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
728 uether_pause(&sc->sc_ue, hz / 32);
730 /* Take PHY out of power down. */
731 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
732 AXE_SW_RESET_IPRL, NULL);
733 uether_pause(&sc->sc_ue, hz / 4);
734 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
735 uether_pause(&sc->sc_ue, hz);
736 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
737 uether_pause(&sc->sc_ue, hz / 32);
738 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
739 uether_pause(&sc->sc_ue, hz / 32);
743 axe_ax88772a_init(struct axe_softc *sc)
745 struct usb_ether *ue;
749 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
750 axe_ax88772_phywake(sc);
752 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
756 axe_ax88772b_init(struct axe_softc *sc)
758 struct usb_ether *ue;
765 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
767 * Save PHY power saving configuration(high byte) and
768 * clear EEPROM checksum value(low byte).
770 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
771 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
774 * Auto-loaded default station address from internal ROM is
775 * 00:00:00:00:00:00 such that an explicit access to EEPROM
776 * is required to get real station address.
778 eaddr = ue->ue_eaddr;
779 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
780 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i,
782 eeprom = le16toh(eeprom);
783 *eaddr++ = (uint8_t)(eeprom & 0xFF);
784 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
787 axe_ax88772_phywake(sc);
789 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
792 #undef AXE_GPIO_WRITE
795 axe_reset(struct axe_softc *sc)
797 struct usb_config_descriptor *cd;
800 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
802 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
803 cd->bConfigurationValue);
805 DPRINTF("reset failed (ignored)\n");
807 /* Wait a little while for the chip to get its brains in order. */
808 uether_pause(&sc->sc_ue, hz / 100);
810 /* Reinitialize controller to achieve full reset. */
811 if (sc->sc_flags & AXE_FLAG_178)
812 axe_ax88178_init(sc);
813 else if (sc->sc_flags & AXE_FLAG_772)
814 axe_ax88772_init(sc);
815 else if (sc->sc_flags & AXE_FLAG_772A)
816 axe_ax88772a_init(sc);
817 else if (sc->sc_flags & AXE_FLAG_772B)
818 axe_ax88772b_init(sc);
822 axe_attach_post(struct usb_ether *ue)
824 struct axe_softc *sc = uether_getsc(ue);
827 * Load PHY indexes first. Needed by axe_xxx_init().
829 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
831 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
832 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
833 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
834 if (sc->sc_phyno == -1)
835 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
836 if (sc->sc_phyno == -1) {
837 device_printf(sc->sc_ue.ue_dev,
838 "no valid PHY address found, assuming PHY address 0\n");
842 /* Initialize controller and get station address. */
843 if (sc->sc_flags & AXE_FLAG_178) {
844 axe_ax88178_init(sc);
845 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
846 } else if (sc->sc_flags & AXE_FLAG_772) {
847 axe_ax88772_init(sc);
848 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
849 } else if (sc->sc_flags & AXE_FLAG_772A) {
850 axe_ax88772a_init(sc);
851 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
852 } else if (sc->sc_flags & AXE_FLAG_772B) {
853 axe_ax88772b_init(sc);
855 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
860 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
861 /* Set IPG values. */
862 sc->sc_ipgs[0] = 0x15;
863 sc->sc_ipgs[1] = 0x16;
864 sc->sc_ipgs[2] = 0x1A;
866 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
870 axe_attach_post_sub(struct usb_ether *ue)
872 struct axe_softc *sc;
877 sc = uether_getsc(ue);
879 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
880 ifp->if_start = uether_start;
881 ifp->if_ioctl = axe_ioctl;
882 ifp->if_init = uether_init;
883 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
884 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
885 IFQ_SET_READY(&ifp->if_snd);
887 if (AXE_IS_178_FAMILY(sc))
888 ifp->if_capabilities |= IFCAP_VLAN_MTU;
889 if (sc->sc_flags & AXE_FLAG_772B) {
890 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM;
891 ifp->if_hwassist = AXE_CSUM_FEATURES;
893 * Checksum offloading of AX88772B also works with VLAN
894 * tagged frames but there is no way to take advantage
895 * of the feature because vlan(4) assumes
896 * IFCAP_VLAN_HWTAGGING is prerequisite condition to
897 * support checksum offloading with VLAN. VLAN hardware
898 * tagging support of AX88772B is very limited so it's
899 * not possible to announce IFCAP_VLAN_HWTAGGING.
902 ifp->if_capenable = ifp->if_capabilities;
903 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178))
904 adv_pause = MIIF_DOPAUSE;
908 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
909 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
910 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause);
917 * Probe for a AX88172 chip.
920 axe_probe(device_t dev)
922 struct usb_attach_arg *uaa = device_get_ivars(dev);
924 if (uaa->usb_mode != USB_MODE_HOST)
926 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
928 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
931 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
935 * Attach the interface. Allocate softc structures, do ifmedia
936 * setup and ethernet/BPF attach.
939 axe_attach(device_t dev)
941 struct usb_attach_arg *uaa = device_get_ivars(dev);
942 struct axe_softc *sc = device_get_softc(dev);
943 struct usb_ether *ue = &sc->sc_ue;
947 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
949 device_set_usb_desc(dev);
951 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
953 iface_index = AXE_IFACE_IDX;
954 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
955 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
957 device_printf(dev, "allocating USB transfers failed\n");
963 ue->ue_udev = uaa->device;
964 ue->ue_mtx = &sc->sc_mtx;
965 ue->ue_methods = &axe_ue_methods;
967 error = uether_ifattach(ue);
969 device_printf(dev, "could not attach interface\n");
972 return (0); /* success */
976 return (ENXIO); /* failure */
980 axe_detach(device_t dev)
982 struct axe_softc *sc = device_get_softc(dev);
983 struct usb_ether *ue = &sc->sc_ue;
985 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
987 mtx_destroy(&sc->sc_mtx);
992 #if (AXE_BULK_BUF_SIZE >= 0x10000)
993 #error "Please update axe_bulk_read_callback()!"
997 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
999 struct axe_softc *sc = usbd_xfer_softc(xfer);
1000 struct usb_ether *ue = &sc->sc_ue;
1001 struct usb_page_cache *pc;
1004 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
1006 switch (USB_GET_STATE(xfer)) {
1007 case USB_ST_TRANSFERRED:
1008 pc = usbd_xfer_get_frame(xfer, 0);
1009 axe_rx_frame(ue, pc, actlen);
1014 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
1015 usbd_transfer_submit(xfer);
1019 default: /* Error */
1020 DPRINTF("bulk read error, %s\n", usbd_errstr(error));
1022 if (error != USB_ERR_CANCELLED) {
1023 /* try to clear stall first */
1024 usbd_xfer_set_stall(xfer);
1032 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
1034 struct axe_softc *sc;
1035 struct axe_sframe_hdr hdr;
1036 struct axe_csum_hdr csum_hdr;
1037 int error, len, pos;
1039 sc = uether_getsc(ue);
1043 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) {
1044 while (pos < actlen) {
1045 if ((int)(pos + sizeof(hdr)) > actlen) {
1046 /* too little data */
1050 usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
1052 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) {
1058 len = le16toh(hdr.len);
1059 if (pos + len > actlen) {
1060 /* invalid length */
1064 axe_rxeof(ue, pc, pos, len, NULL);
1065 pos += len + (len % 2);
1067 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) {
1068 while (pos < actlen) {
1069 if ((int)(pos + sizeof(csum_hdr)) > actlen) {
1070 /* too little data */
1074 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr));
1076 csum_hdr.len = le16toh(csum_hdr.len);
1077 csum_hdr.ilen = le16toh(csum_hdr.ilen);
1078 csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
1079 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^
1080 AXE_CSUM_RXBYTES(csum_hdr.ilen)) !=
1087 * Get total transferred frame length including
1088 * checksum header. The length should be multiple
1091 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len);
1092 len = (len + 3) & ~3;
1093 if (pos + len > actlen) {
1094 /* invalid length */
1098 axe_rxeof(ue, pc, pos + sizeof(csum_hdr),
1099 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr);
1103 axe_rxeof(ue, pc, 0, actlen, NULL);
1106 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1);
1111 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset,
1112 unsigned int len, struct axe_csum_hdr *csum_hdr)
1114 struct ifnet *ifp = ue->ue_ifp;
1117 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
1118 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1122 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1124 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1127 m->m_len = m->m_pkthdr.len = MCLBYTES;
1128 m_adj(m, ETHER_ALIGN);
1130 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1132 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1133 m->m_pkthdr.rcvif = ifp;
1134 m->m_pkthdr.len = m->m_len = len;
1136 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) {
1137 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR |
1138 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) {
1139 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1141 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1142 AXE_CSUM_HDR_L4_TYPE_TCP ||
1143 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1144 AXE_CSUM_HDR_L4_TYPE_UDP) {
1145 m->m_pkthdr.csum_flags |=
1146 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1147 m->m_pkthdr.csum_data = 0xffff;
1152 (void)mbufq_enqueue(&ue->ue_rxq, m);
1156 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
1157 #error "Please update axe_bulk_write_callback()!"
1161 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
1163 struct axe_softc *sc = usbd_xfer_softc(xfer);
1164 struct axe_sframe_hdr hdr;
1165 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
1166 struct usb_page_cache *pc;
1170 switch (USB_GET_STATE(xfer)) {
1171 case USB_ST_TRANSFERRED:
1172 DPRINTFN(11, "transfer complete\n");
1173 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1177 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
1178 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
1180 * Don't send anything if there is no link or
1181 * controller is busy.
1186 for (nframes = 0; nframes < 16 &&
1187 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
1188 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1191 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
1194 pc = usbd_xfer_get_frame(xfer, nframes);
1195 if (AXE_IS_178_FAMILY(sc)) {
1196 hdr.len = htole16(m->m_pkthdr.len);
1197 hdr.ilen = ~hdr.len;
1199 * If upper stack computed checksum, driver
1200 * should tell controller not to insert
1201 * computed checksum for checksum offloading
1202 * enabled controller.
1204 if (ifp->if_capabilities & IFCAP_TXCSUM) {
1205 if ((m->m_pkthdr.csum_flags &
1206 AXE_CSUM_FEATURES) != 0)
1208 AXE_TX_CSUM_PSEUDO_HDR);
1213 usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
1215 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1216 pos += m->m_pkthdr.len;
1217 if ((pos % 512) == 0) {
1220 usbd_copy_in(pc, pos, &hdr,
1225 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1226 pos += m->m_pkthdr.len;
1231 * Update TX packet counter here. This is not
1232 * correct way but it seems that there is no way
1233 * to know how many packets are sent at the end
1234 * of transfer because controller combines
1235 * multiple writes into single one if there is
1236 * room in TX buffer of controller.
1238 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1241 * if there's a BPF listener, bounce a copy
1242 * of this frame to him:
1248 /* Set frame length. */
1249 usbd_xfer_set_frame_len(xfer, nframes, pos);
1252 usbd_xfer_set_frames(xfer, nframes);
1253 usbd_transfer_submit(xfer);
1254 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1258 default: /* Error */
1259 DPRINTFN(11, "transfer error, %s\n",
1260 usbd_errstr(error));
1262 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1263 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1265 if (error != USB_ERR_CANCELLED) {
1266 /* try to clear stall first */
1267 usbd_xfer_set_stall(xfer);
1275 axe_tick(struct usb_ether *ue)
1277 struct axe_softc *sc = uether_getsc(ue);
1278 struct mii_data *mii = GET_MII(sc);
1280 AXE_LOCK_ASSERT(sc, MA_OWNED);
1283 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1284 axe_miibus_statchg(ue->ue_dev);
1285 if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1291 axe_start(struct usb_ether *ue)
1293 struct axe_softc *sc = uether_getsc(ue);
1296 * start the USB transfers, if not already started:
1298 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1299 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1303 axe_csum_cfg(struct usb_ether *ue)
1305 struct axe_softc *sc;
1307 uint16_t csum1, csum2;
1309 sc = uether_getsc(ue);
1310 AXE_LOCK_ASSERT(sc, MA_OWNED);
1312 if ((sc->sc_flags & AXE_FLAG_772B) != 0) {
1313 ifp = uether_getifp(ue);
1316 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1317 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP |
1319 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL);
1322 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1323 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE |
1324 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP |
1326 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL);
1331 axe_init(struct usb_ether *ue)
1333 struct axe_softc *sc = uether_getsc(ue);
1334 struct ifnet *ifp = uether_getifp(ue);
1337 AXE_LOCK_ASSERT(sc, MA_OWNED);
1339 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1342 /* Cancel pending I/O */
1347 /* Set MAC address and transmitter IPG values. */
1348 if (AXE_IS_178_FAMILY(sc)) {
1349 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1350 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1351 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1353 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1354 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1355 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1356 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1359 if (AXE_IS_178_FAMILY(sc)) {
1360 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME);
1361 if ((sc->sc_flags & AXE_FLAG_772B) != 0 &&
1362 (ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1363 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK;
1364 sc->sc_flags |= AXE_FLAG_CSUM_FRAME;
1366 sc->sc_lenmask = AXE_HDR_LEN_MASK;
1367 sc->sc_flags |= AXE_FLAG_STD_FRAME;
1371 /* Configure TX/RX checksum offloading. */
1374 if (sc->sc_flags & AXE_FLAG_772B) {
1375 /* AX88772B uses different maximum frame burst configuration. */
1376 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1377 ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1378 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1381 /* Enable receiver, set RX mode. */
1382 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1383 if (AXE_IS_178_FAMILY(sc)) {
1384 if (sc->sc_flags & AXE_FLAG_772B) {
1386 * Select RX header format type 1. Aligning IP
1387 * header on 4 byte boundary is not needed when
1388 * checksum offloading feature is not used
1389 * because we always copy the received frame in
1390 * RX handler. When RX checksum offloading is
1391 * active, aligning IP header is required to
1392 * reflect actual frame length including RX
1395 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1396 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1397 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN;
1400 * Default Rx buffer size is too small to get
1401 * maximum performance.
1403 rxmode |= AXE_178_RXCMD_MFB_16384;
1406 rxmode |= AXE_172_RXCMD_UNICAST;
1409 /* If we want promiscuous mode, set the allframes bit. */
1410 if (ifp->if_flags & IFF_PROMISC)
1411 rxmode |= AXE_RXCMD_PROMISC;
1413 if (ifp->if_flags & IFF_BROADCAST)
1414 rxmode |= AXE_RXCMD_BROADCAST;
1416 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1418 /* Load the multicast filter. */
1421 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1423 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1424 /* Switch to selected media. */
1425 axe_ifmedia_upd(ifp);
1429 axe_setpromisc(struct usb_ether *ue)
1431 struct axe_softc *sc = uether_getsc(ue);
1432 struct ifnet *ifp = uether_getifp(ue);
1435 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1437 rxmode = le16toh(rxmode);
1439 if (ifp->if_flags & IFF_PROMISC) {
1440 rxmode |= AXE_RXCMD_PROMISC;
1442 rxmode &= ~AXE_RXCMD_PROMISC;
1445 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1451 axe_stop(struct usb_ether *ue)
1453 struct axe_softc *sc = uether_getsc(ue);
1454 struct ifnet *ifp = uether_getifp(ue);
1456 AXE_LOCK_ASSERT(sc, MA_OWNED);
1458 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1459 sc->sc_flags &= ~AXE_FLAG_LINK;
1462 * stop all the transfers, if not already stopped:
1464 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1465 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1469 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1471 struct usb_ether *ue = ifp->if_softc;
1472 struct axe_softc *sc;
1474 int error, mask, reinit;
1476 sc = uether_getsc(ue);
1477 ifr = (struct ifreq *)data;
1480 if (cmd == SIOCSIFCAP) {
1482 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1483 if ((mask & IFCAP_TXCSUM) != 0 &&
1484 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1485 ifp->if_capenable ^= IFCAP_TXCSUM;
1486 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1487 ifp->if_hwassist |= AXE_CSUM_FEATURES;
1489 ifp->if_hwassist &= ~AXE_CSUM_FEATURES;
1492 if ((mask & IFCAP_RXCSUM) != 0 &&
1493 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1494 ifp->if_capenable ^= IFCAP_RXCSUM;
1497 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
1498 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1505 error = uether_ioctl(ifp, cmd, data);