2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013-2014 Kevin Lo
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver.
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/condvar.h>
40 #include <sys/endian.h>
41 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
45 #include <sys/socket.h>
46 #include <sys/sysctl.h>
47 #include <sys/unistd.h>
50 #include <net/if_var.h>
51 #include <net/if_media.h>
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
56 #include <dev/usb/usb.h>
57 #include <dev/usb/usbdi.h>
58 #include <dev/usb/usbdi_util.h>
61 #define USB_DEBUG_VAR axge_debug
62 #include <dev/usb/usb_debug.h>
63 #include <dev/usb/usb_process.h>
65 #include <dev/usb/net/usb_ethernet.h>
66 #include <dev/usb/net/if_axgereg.h>
68 #include "miibus_if.h"
71 * Various supported device vendors/products.
74 static const STRUCT_USB_HOST_ID axge_devs[] = {
75 #define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
76 AXGE_DEV(ASIX, AX88178A),
77 AXGE_DEV(ASIX, AX88179),
78 AXGE_DEV(DLINK, DUB1312),
79 AXGE_DEV(LENOVO, GIGALAN),
80 AXGE_DEV(SITECOMEU, LN032),
90 } __packed axge_bulk_size[] = {
91 { 7, 0x4f, 0x00, 0x12, 0xff },
92 { 7, 0x20, 0x03, 0x16, 0xff },
93 { 7, 0xae, 0x07, 0x18, 0xff },
94 { 7, 0xcc, 0x4c, 0x18, 0x08 }
99 static device_probe_t axge_probe;
100 static device_attach_t axge_attach;
101 static device_detach_t axge_detach;
103 static usb_callback_t axge_bulk_read_callback;
104 static usb_callback_t axge_bulk_write_callback;
106 static miibus_readreg_t axge_miibus_readreg;
107 static miibus_writereg_t axge_miibus_writereg;
108 static miibus_statchg_t axge_miibus_statchg;
110 static uether_fn_t axge_attach_post;
111 static uether_fn_t axge_init;
112 static uether_fn_t axge_stop;
113 static uether_fn_t axge_start;
114 static uether_fn_t axge_tick;
115 static uether_fn_t axge_rxfilter;
117 static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t,
118 uint16_t, void *, int);
119 static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t,
120 uint16_t, void *, int);
121 static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t);
122 static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t,
124 static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t,
126 static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t,
128 static void axge_chip_init(struct axge_softc *);
129 static void axge_reset(struct axge_softc *);
131 static int axge_attach_post_sub(struct usb_ether *);
132 static int axge_ifmedia_upd(struct ifnet *);
133 static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
134 static int axge_ioctl(struct ifnet *, u_long, caddr_t);
135 static void axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
136 static void axge_rxeof(struct usb_ether *, struct usb_page_cache *,
137 unsigned int, unsigned int, uint32_t);
138 static void axge_csum_cfg(struct usb_ether *);
140 #define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
143 static int axge_debug = 0;
145 static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW, 0, "USB axge");
146 SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RWTUN, &axge_debug, 0,
150 static const struct usb_config axge_config[AXGE_N_TRANSFER] = {
151 [AXGE_BULK_DT_WR] = {
153 .endpoint = UE_ADDR_ANY,
154 .direction = UE_DIR_OUT,
155 .frames = AXGE_N_FRAMES,
156 .bufsize = AXGE_N_FRAMES * MCLBYTES,
157 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
158 .callback = axge_bulk_write_callback,
159 .timeout = 10000, /* 10 seconds */
161 [AXGE_BULK_DT_RD] = {
163 .endpoint = UE_ADDR_ANY,
164 .direction = UE_DIR_IN,
166 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
167 .callback = axge_bulk_read_callback,
168 .timeout = 0, /* no timeout */
172 static device_method_t axge_methods[] = {
173 /* Device interface. */
174 DEVMETHOD(device_probe, axge_probe),
175 DEVMETHOD(device_attach, axge_attach),
176 DEVMETHOD(device_detach, axge_detach),
179 DEVMETHOD(miibus_readreg, axge_miibus_readreg),
180 DEVMETHOD(miibus_writereg, axge_miibus_writereg),
181 DEVMETHOD(miibus_statchg, axge_miibus_statchg),
186 static driver_t axge_driver = {
188 .methods = axge_methods,
189 .size = sizeof(struct axge_softc),
192 static devclass_t axge_devclass;
194 DRIVER_MODULE(axge, uhub, axge_driver, axge_devclass, NULL, NULL);
195 DRIVER_MODULE(miibus, axge, miibus_driver, miibus_devclass, NULL, NULL);
196 MODULE_DEPEND(axge, uether, 1, 1, 1);
197 MODULE_DEPEND(axge, usb, 1, 1, 1);
198 MODULE_DEPEND(axge, ether, 1, 1, 1);
199 MODULE_DEPEND(axge, miibus, 1, 1, 1);
200 MODULE_VERSION(axge, 1);
201 USB_PNP_HOST_INFO(axge_devs);
203 static const struct usb_ether_methods axge_ue_methods = {
204 .ue_attach_post = axge_attach_post,
205 .ue_attach_post_sub = axge_attach_post_sub,
206 .ue_start = axge_start,
207 .ue_init = axge_init,
208 .ue_stop = axge_stop,
209 .ue_tick = axge_tick,
210 .ue_setmulti = axge_rxfilter,
211 .ue_setpromisc = axge_rxfilter,
212 .ue_mii_upd = axge_ifmedia_upd,
213 .ue_mii_sts = axge_ifmedia_sts,
217 axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
218 uint16_t val, void *buf, int len)
220 struct usb_device_request req;
222 AXGE_LOCK_ASSERT(sc, MA_OWNED);
224 req.bmRequestType = UT_READ_VENDOR_DEVICE;
226 USETW(req.wValue, val);
227 USETW(req.wIndex, index);
228 USETW(req.wLength, len);
230 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
234 axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
235 uint16_t val, void *buf, int len)
237 struct usb_device_request req;
239 AXGE_LOCK_ASSERT(sc, MA_OWNED);
241 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
243 USETW(req.wValue, val);
244 USETW(req.wIndex, index);
245 USETW(req.wLength, len);
247 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) {
253 axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg)
257 axge_read_mem(sc, cmd, 1, reg, &val, 1);
262 axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
267 axge_read_mem(sc, cmd, index, reg, &val, 2);
272 axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val)
274 axge_write_mem(sc, cmd, 1, reg, &val, 1);
278 axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
279 uint16_t reg, uint16_t val)
284 axge_write_mem(sc, cmd, index, reg, &temp, 2);
288 axge_miibus_readreg(device_t dev, int phy, int reg)
290 struct axge_softc *sc;
294 sc = device_get_softc(dev);
295 locked = mtx_owned(&sc->sc_mtx);
299 val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy);
308 axge_miibus_writereg(device_t dev, int phy, int reg, int val)
310 struct axge_softc *sc;
313 sc = device_get_softc(dev);
314 locked = mtx_owned(&sc->sc_mtx);
318 axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val);
327 axge_miibus_statchg(device_t dev)
329 struct axge_softc *sc;
330 struct mii_data *mii;
332 uint8_t link_status, tmp[5];
336 sc = device_get_softc(dev);
338 locked = mtx_owned(&sc->sc_mtx);
342 ifp = uether_getifp(&sc->sc_ue);
343 if (mii == NULL || ifp == NULL ||
344 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
347 sc->sc_flags &= ~AXGE_FLAG_LINK;
348 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
349 (IFM_ACTIVE | IFM_AVALID)) {
350 switch (IFM_SUBTYPE(mii->mii_media_active)) {
354 sc->sc_flags |= AXGE_FLAG_LINK;
361 /* Lost link, do nothing. */
362 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0)
365 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR);
368 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
370 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
372 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
376 switch (IFM_SUBTYPE(mii->mii_media_active)) {
378 val |= MSR_GM | MSR_EN_125MHZ;
379 if (link_status & PLSR_USB_SS)
380 memcpy(tmp, &axge_bulk_size[0], 5);
381 else if (link_status & PLSR_USB_HS)
382 memcpy(tmp, &axge_bulk_size[1], 5);
384 memcpy(tmp, &axge_bulk_size[3], 5);
388 if (link_status & (PLSR_USB_SS | PLSR_USB_HS))
389 memcpy(tmp, &axge_bulk_size[2], 5);
391 memcpy(tmp, &axge_bulk_size[3], 5);
394 memcpy(tmp, &axge_bulk_size[3], 5);
397 /* Rx bulk configuration. */
398 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5);
399 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);
406 axge_chip_init(struct axge_softc *sc)
408 /* Power up ethernet PHY. */
409 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0);
410 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL);
411 uether_pause(&sc->sc_ue, hz / 4);
412 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT,
413 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS);
414 uether_pause(&sc->sc_ue, hz / 10);
418 axge_reset(struct axge_softc *sc)
420 struct usb_config_descriptor *cd;
423 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
425 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
426 cd->bConfigurationValue);
428 DPRINTF("reset failed (ignored)\n");
430 /* Wait a little while for the chip to get its brains in order. */
431 uether_pause(&sc->sc_ue, hz / 100);
433 /* Reinitialize controller to achieve full reset. */
438 axge_attach_post(struct usb_ether *ue)
440 struct axge_softc *sc;
442 sc = uether_getsc(ue);
444 /* Initialize controller and get station address. */
446 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
447 ue->ue_eaddr, ETHER_ADDR_LEN);
451 axge_attach_post_sub(struct usb_ether *ue)
453 struct axge_softc *sc;
457 sc = uether_getsc(ue);
459 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
460 ifp->if_start = uether_start;
461 ifp->if_ioctl = axge_ioctl;
462 ifp->if_init = uether_init;
463 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
464 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
465 IFQ_SET_READY(&ifp->if_snd);
467 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM;
468 ifp->if_hwassist = AXGE_CSUM_FEATURES;
469 ifp->if_capenable = ifp->if_capabilities;
472 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
473 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
474 BMSR_DEFCAPMASK, AXGE_PHY_ADDR, MII_OFFSET_ANY, MIIF_DOPAUSE);
484 axge_ifmedia_upd(struct ifnet *ifp)
486 struct axge_softc *sc;
487 struct mii_data *mii;
488 struct mii_softc *miisc;
493 AXGE_LOCK_ASSERT(sc, MA_OWNED);
495 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
497 error = mii_mediachg(mii);
503 * Report current media status.
506 axge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
508 struct axge_softc *sc;
509 struct mii_data *mii;
515 ifmr->ifm_active = mii->mii_media_active;
516 ifmr->ifm_status = mii->mii_media_status;
521 * Probe for a AX88179 chip.
524 axge_probe(device_t dev)
526 struct usb_attach_arg *uaa;
528 uaa = device_get_ivars(dev);
529 if (uaa->usb_mode != USB_MODE_HOST)
531 if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX)
533 if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX)
536 return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa));
540 * Attach the interface. Allocate softc structures, do ifmedia
541 * setup and ethernet/BPF attach.
544 axge_attach(device_t dev)
546 struct usb_attach_arg *uaa;
547 struct axge_softc *sc;
548 struct usb_ether *ue;
552 uaa = device_get_ivars(dev);
553 sc = device_get_softc(dev);
556 device_set_usb_desc(dev);
557 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
559 iface_index = AXGE_IFACE_IDX;
560 error = usbd_transfer_setup(uaa->device, &iface_index,
561 sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_mtx);
563 device_printf(dev, "allocating USB transfers failed\n");
564 mtx_destroy(&sc->sc_mtx);
570 ue->ue_udev = uaa->device;
571 ue->ue_mtx = &sc->sc_mtx;
572 ue->ue_methods = &axge_ue_methods;
574 error = uether_ifattach(ue);
576 device_printf(dev, "could not attach interface\n");
579 return (0); /* success */
583 return (ENXIO); /* failure */
587 axge_detach(device_t dev)
589 struct axge_softc *sc;
590 struct usb_ether *ue;
593 sc = device_get_softc(dev);
595 if (device_is_attached(dev)) {
597 /* wait for any post attach or other command to complete */
598 usb_proc_drain(&ue->ue_tq);
603 * ether_ifdetach(9) should be called first.
606 /* Force bulk-in to return a zero-length USB packet. */
607 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR);
608 val |= EPPRCR_BZ | EPPRCR_IPRL;
609 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, val);
611 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 0);
613 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, 0);
616 usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER);
618 mtx_destroy(&sc->sc_mtx);
624 axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
626 struct axge_softc *sc;
627 struct usb_ether *ue;
628 struct usb_page_cache *pc;
631 sc = usbd_xfer_softc(xfer);
633 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
635 switch (USB_GET_STATE(xfer)) {
636 case USB_ST_TRANSFERRED:
637 pc = usbd_xfer_get_frame(xfer, 0);
638 axge_rx_frame(ue, pc, actlen);
643 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
644 usbd_transfer_submit(xfer);
649 if (error != USB_ERR_CANCELLED) {
650 usbd_xfer_set_stall(xfer);
658 axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
660 struct axge_softc *sc;
662 struct usb_page_cache *pc;
664 struct axge_frame_txhdr txhdr;
667 sc = usbd_xfer_softc(xfer);
668 ifp = uether_getifp(&sc->sc_ue);
670 switch (USB_GET_STATE(xfer)) {
671 case USB_ST_TRANSFERRED:
672 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
676 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 ||
677 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
679 * Don't send anything if there is no link or
680 * controller is busy.
685 for (nframes = 0; nframes < AXGE_N_FRAMES &&
686 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
687 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
690 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
692 pc = usbd_xfer_get_frame(xfer, nframes);
694 txhdr.len = htole32(AXGE_TXBYTES(m->m_pkthdr.len));
695 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0 &&
696 (m->m_pkthdr.csum_flags & AXGE_CSUM_FEATURES) == 0)
697 txhdr.len |= htole32(AXGE_CSUM_DISABLE);
700 usbd_copy_in(pc, pos, &txhdr, sizeof(txhdr));
701 pos += sizeof(txhdr);
702 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
703 pos += m->m_pkthdr.len;
706 * if there's a BPF listener, bounce a copy
707 * of this frame to him:
713 /* Set frame length. */
714 usbd_xfer_set_frame_len(xfer, nframes, pos);
719 * Update TX packet counter here. This is not
720 * correct way but it seems that there is no way
721 * to know how many packets are sent at the end
722 * of transfer because controller combines
723 * multiple writes into single one if there is
724 * room in TX buffer of controller.
726 if_inc_counter(ifp, IFCOUNTER_OPACKETS, nframes);
727 usbd_xfer_set_frames(xfer, nframes);
728 usbd_transfer_submit(xfer);
729 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
734 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
735 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
737 if (error != USB_ERR_CANCELLED) {
738 usbd_xfer_set_stall(xfer);
747 axge_tick(struct usb_ether *ue)
749 struct axge_softc *sc;
750 struct mii_data *mii;
752 sc = uether_getsc(ue);
754 AXGE_LOCK_ASSERT(sc, MA_OWNED);
760 axge_rxfilter(struct usb_ether *ue)
762 struct axge_softc *sc;
764 struct ifmultiaddr *ifma;
767 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
769 sc = uether_getsc(ue);
770 ifp = uether_getifp(ue);
772 AXGE_LOCK_ASSERT(sc, MA_OWNED);
775 * Configure RX settings.
776 * Don't set RCR_IPE(IP header alignment on 32bit boundary) to disable
777 * inserting extra padding bytes. This wastes ethernet to USB host
778 * bandwidth as well as complicating RX handling logic. Current USB
779 * framework requires copying RX frames to mbufs so there is no need
780 * to worry about alignment.
782 rxmode = RCR_DROP_CRCERR | RCR_START;
783 if (ifp->if_flags & IFF_BROADCAST)
784 rxmode |= RCR_ACPT_BCAST;
785 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
786 if (ifp->if_flags & IFF_PROMISC)
787 rxmode |= RCR_PROMISC;
788 rxmode |= RCR_ACPT_ALL_MCAST;
789 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
793 rxmode |= RCR_ACPT_MCAST;
795 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
796 if (ifma->ifma_addr->sa_family != AF_LINK)
798 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
799 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
800 hashtbl[h / 8] |= 1 << (h % 8);
802 if_maddr_runlock(ifp);
804 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8);
805 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
809 axge_start(struct usb_ether *ue)
811 struct axge_softc *sc;
813 sc = uether_getsc(ue);
815 * Start the USB transfers, if not already started.
817 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]);
818 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]);
822 axge_init(struct usb_ether *ue)
824 struct axge_softc *sc;
827 sc = uether_getsc(ue);
828 ifp = uether_getifp(ue);
829 AXGE_LOCK_ASSERT(sc, MA_OWNED);
831 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
835 * Cancel pending I/O and free all RX/TX buffers.
841 /* Set MAC address. */
842 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
843 IF_LLADDR(ifp), ETHER_ADDR_LEN);
845 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34);
846 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52);
848 /* Configure TX/RX checksum offloading. */
851 /* Configure RX filters. */
856 * Controller supports wakeup on link change detection,
857 * magic packet and wakeup frame recpetion. But it seems
858 * there is no framework for USB ethernet suspend/wakeup.
859 * Disable all wakeup functions.
861 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 0);
862 (void)axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR);
864 /* Configure default medium type. */
865 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, MSR_GM | MSR_FD |
866 MSR_RFC | MSR_TFC | MSR_RE);
868 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]);
870 ifp->if_drv_flags |= IFF_DRV_RUNNING;
871 /* Switch to selected media. */
872 axge_ifmedia_upd(ifp);
876 axge_stop(struct usb_ether *ue)
878 struct axge_softc *sc;
882 sc = uether_getsc(ue);
883 ifp = uether_getifp(ue);
885 AXGE_LOCK_ASSERT(sc, MA_OWNED);
887 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR);
889 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);
892 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
893 sc->sc_flags &= ~AXGE_FLAG_LINK;
896 * Stop all the transfers, if not already stopped:
898 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]);
899 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]);
903 axge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
905 struct usb_ether *ue;
906 struct axge_softc *sc;
908 int error, mask, reinit;
911 sc = uether_getsc(ue);
912 ifr = (struct ifreq *)data;
915 if (cmd == SIOCSIFCAP) {
917 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
918 if ((mask & IFCAP_TXCSUM) != 0 &&
919 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
920 ifp->if_capenable ^= IFCAP_TXCSUM;
921 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
922 ifp->if_hwassist |= AXGE_CSUM_FEATURES;
924 ifp->if_hwassist &= ~AXGE_CSUM_FEATURES;
927 if ((mask & IFCAP_RXCSUM) != 0 &&
928 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
929 ifp->if_capenable ^= IFCAP_RXCSUM;
932 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
933 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
940 error = uether_ioctl(ifp, cmd, data);
946 axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
948 struct axge_frame_rxhdr pkt_hdr;
951 uint32_t pkt_cnt, pkt_end;
955 /* verify we have enough data */
956 if (actlen < (int)sizeof(rxhdr))
961 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr));
962 rxhdr = le32toh(rxhdr);
964 pkt_cnt = rxhdr & 0xFFFF;
965 hdr_off = pkt_end = (rxhdr >> 16) & 0xFFFF;
968 * <----------------------- actlen ------------------------>
969 * [frame #0]...[frame #N][pkt_hdr #0]...[pkt_hdr #N][rxhdr]
970 * Each RX frame would be aligned on 8 bytes boundary. If
971 * RCR_IPE bit is set in AXGE_RCR register, there would be 2
972 * padding bytes and 6 dummy bytes(as the padding also should
973 * be aligned on 8 bytes boundary) for each RX frame to align
974 * IP header on 32bits boundary. Driver don't set RCR_IPE bit
975 * of AXGE_RCR register, so there should be no padding bytes
976 * which simplifies RX logic a lot.
979 /* verify the header offset */
980 if ((int)(hdr_off + sizeof(pkt_hdr)) > actlen) {
981 DPRINTF("End of packet headers\n");
984 usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr));
985 pkt_hdr.status = le32toh(pkt_hdr.status);
986 pktlen = AXGE_RXBYTES(pkt_hdr.status);
987 if (pos + pktlen > pkt_end) {
988 DPRINTF("Data position reached end\n");
992 if (AXGE_RX_ERR(pkt_hdr.status) != 0) {
993 DPRINTF("Dropped a packet\n");
994 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1);
996 axge_rxeof(ue, pc, pos, pktlen, pkt_hdr.status);
997 pos += (pktlen + 7) & ~7;
998 hdr_off += sizeof(pkt_hdr);
1003 axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset,
1004 unsigned int len, uint32_t status)
1010 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
1011 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1015 if (len > MHLEN - ETHER_ALIGN)
1016 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1018 m = m_gethdr(M_NOWAIT, MT_DATA);
1020 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1023 m->m_pkthdr.rcvif = ifp;
1024 m->m_len = m->m_pkthdr.len = len;
1025 m->m_data += ETHER_ALIGN;
1027 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1029 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1030 if ((status & AXGE_RX_L3_CSUM_ERR) == 0 &&
1031 (status & AXGE_RX_L3_TYPE_MASK) == AXGE_RX_L3_TYPE_IPV4)
1032 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1034 if ((status & AXGE_RX_L4_CSUM_ERR) == 0 &&
1035 ((status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_UDP ||
1036 (status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_TCP)) {
1037 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1039 m->m_pkthdr.csum_data = 0xffff;
1042 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1044 _IF_ENQUEUE(&ue->ue_rxq, m);
1048 axge_csum_cfg(struct usb_ether *ue)
1050 struct axge_softc *sc;
1054 sc = uether_getsc(ue);
1055 AXGE_LOCK_ASSERT(sc, MA_OWNED);
1056 ifp = uether_getifp(ue);
1059 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1060 csum |= CTCR_IP | CTCR_TCP | CTCR_UDP;
1061 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum);
1064 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1065 csum |= CRCR_IP | CRCR_TCP | CRCR_UDP;
1066 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum);