2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013-2014 Kevin Lo
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver.
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/condvar.h>
40 #include <sys/endian.h>
41 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/mutex.h>
45 #include <sys/socket.h>
46 #include <sys/sysctl.h>
47 #include <sys/unistd.h>
50 #include <net/if_var.h>
51 #include <net/if_media.h>
53 #include <dev/mii/mii.h>
54 #include <dev/mii/miivar.h>
56 #include <dev/usb/usb.h>
57 #include <dev/usb/usbdi.h>
58 #include <dev/usb/usbdi_util.h>
61 #define USB_DEBUG_VAR axge_debug
62 #include <dev/usb/usb_debug.h>
63 #include <dev/usb/usb_process.h>
65 #include <dev/usb/net/usb_ethernet.h>
66 #include <dev/usb/net/if_axgereg.h>
68 #include "miibus_if.h"
71 * Various supported device vendors/products.
74 static const STRUCT_USB_HOST_ID axge_devs[] = {
75 #define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
76 AXGE_DEV(ASIX, AX88178A),
77 AXGE_DEV(ASIX, AX88179),
78 AXGE_DEV(BELKIN, B2B128),
79 AXGE_DEV(DLINK, DUB1312),
80 AXGE_DEV(LENOVO, GIGALAN),
81 AXGE_DEV(SITECOMEU, LN032),
91 } __packed axge_bulk_size[] = {
92 { 7, 0x4f, 0x00, 0x12, 0xff },
93 { 7, 0x20, 0x03, 0x16, 0xff },
94 { 7, 0xae, 0x07, 0x18, 0xff },
95 { 7, 0xcc, 0x4c, 0x18, 0x08 }
100 static device_probe_t axge_probe;
101 static device_attach_t axge_attach;
102 static device_detach_t axge_detach;
104 static usb_callback_t axge_bulk_read_callback;
105 static usb_callback_t axge_bulk_write_callback;
107 static miibus_readreg_t axge_miibus_readreg;
108 static miibus_writereg_t axge_miibus_writereg;
109 static miibus_statchg_t axge_miibus_statchg;
111 static uether_fn_t axge_attach_post;
112 static uether_fn_t axge_init;
113 static uether_fn_t axge_stop;
114 static uether_fn_t axge_start;
115 static uether_fn_t axge_tick;
116 static uether_fn_t axge_rxfilter;
118 static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t,
119 uint16_t, void *, int);
120 static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t,
121 uint16_t, void *, int);
122 static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t);
123 static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t,
125 static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t,
127 static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t,
129 static void axge_chip_init(struct axge_softc *);
130 static void axge_reset(struct axge_softc *);
132 static int axge_attach_post_sub(struct usb_ether *);
133 static int axge_ifmedia_upd(struct ifnet *);
134 static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
135 static int axge_ioctl(struct ifnet *, u_long, caddr_t);
136 static void axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
137 static void axge_rxeof(struct usb_ether *, struct usb_page_cache *,
138 unsigned int, unsigned int, uint32_t);
139 static void axge_csum_cfg(struct usb_ether *);
141 #define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
144 static int axge_debug = 0;
146 static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
148 SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RWTUN, &axge_debug, 0,
152 static const struct usb_config axge_config[AXGE_N_TRANSFER] = {
153 [AXGE_BULK_DT_WR] = {
155 .endpoint = UE_ADDR_ANY,
156 .direction = UE_DIR_OUT,
157 .frames = AXGE_N_FRAMES,
158 .bufsize = AXGE_N_FRAMES * MCLBYTES,
159 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
160 .callback = axge_bulk_write_callback,
161 .timeout = 10000, /* 10 seconds */
163 [AXGE_BULK_DT_RD] = {
165 .endpoint = UE_ADDR_ANY,
166 .direction = UE_DIR_IN,
168 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
169 .callback = axge_bulk_read_callback,
170 .timeout = 0, /* no timeout */
174 static device_method_t axge_methods[] = {
175 /* Device interface. */
176 DEVMETHOD(device_probe, axge_probe),
177 DEVMETHOD(device_attach, axge_attach),
178 DEVMETHOD(device_detach, axge_detach),
181 DEVMETHOD(miibus_readreg, axge_miibus_readreg),
182 DEVMETHOD(miibus_writereg, axge_miibus_writereg),
183 DEVMETHOD(miibus_statchg, axge_miibus_statchg),
188 static driver_t axge_driver = {
190 .methods = axge_methods,
191 .size = sizeof(struct axge_softc),
194 static devclass_t axge_devclass;
196 DRIVER_MODULE(axge, uhub, axge_driver, axge_devclass, NULL, NULL);
197 DRIVER_MODULE(miibus, axge, miibus_driver, miibus_devclass, NULL, NULL);
198 MODULE_DEPEND(axge, uether, 1, 1, 1);
199 MODULE_DEPEND(axge, usb, 1, 1, 1);
200 MODULE_DEPEND(axge, ether, 1, 1, 1);
201 MODULE_DEPEND(axge, miibus, 1, 1, 1);
202 MODULE_VERSION(axge, 1);
203 USB_PNP_HOST_INFO(axge_devs);
205 static const struct usb_ether_methods axge_ue_methods = {
206 .ue_attach_post = axge_attach_post,
207 .ue_attach_post_sub = axge_attach_post_sub,
208 .ue_start = axge_start,
209 .ue_init = axge_init,
210 .ue_stop = axge_stop,
211 .ue_tick = axge_tick,
212 .ue_setmulti = axge_rxfilter,
213 .ue_setpromisc = axge_rxfilter,
214 .ue_mii_upd = axge_ifmedia_upd,
215 .ue_mii_sts = axge_ifmedia_sts,
219 axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
220 uint16_t val, void *buf, int len)
222 struct usb_device_request req;
224 AXGE_LOCK_ASSERT(sc, MA_OWNED);
226 req.bmRequestType = UT_READ_VENDOR_DEVICE;
228 USETW(req.wValue, val);
229 USETW(req.wIndex, index);
230 USETW(req.wLength, len);
232 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
236 axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
237 uint16_t val, void *buf, int len)
239 struct usb_device_request req;
241 AXGE_LOCK_ASSERT(sc, MA_OWNED);
243 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
245 USETW(req.wValue, val);
246 USETW(req.wIndex, index);
247 USETW(req.wLength, len);
249 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) {
255 axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg)
259 axge_read_mem(sc, cmd, 1, reg, &val, 1);
264 axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
269 axge_read_mem(sc, cmd, index, reg, &val, 2);
274 axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val)
276 axge_write_mem(sc, cmd, 1, reg, &val, 1);
280 axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
281 uint16_t reg, uint16_t val)
286 axge_write_mem(sc, cmd, index, reg, &temp, 2);
290 axge_miibus_readreg(device_t dev, int phy, int reg)
292 struct axge_softc *sc;
296 sc = device_get_softc(dev);
297 locked = mtx_owned(&sc->sc_mtx);
301 val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy);
310 axge_miibus_writereg(device_t dev, int phy, int reg, int val)
312 struct axge_softc *sc;
315 sc = device_get_softc(dev);
316 locked = mtx_owned(&sc->sc_mtx);
320 axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val);
329 axge_miibus_statchg(device_t dev)
331 struct axge_softc *sc;
332 struct mii_data *mii;
334 uint8_t link_status, tmp[5];
338 sc = device_get_softc(dev);
340 locked = mtx_owned(&sc->sc_mtx);
344 ifp = uether_getifp(&sc->sc_ue);
345 if (mii == NULL || ifp == NULL ||
346 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
349 sc->sc_flags &= ~AXGE_FLAG_LINK;
350 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
351 (IFM_ACTIVE | IFM_AVALID)) {
352 switch (IFM_SUBTYPE(mii->mii_media_active)) {
356 sc->sc_flags |= AXGE_FLAG_LINK;
363 /* Lost link, do nothing. */
364 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0)
367 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR);
370 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
372 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
374 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
378 switch (IFM_SUBTYPE(mii->mii_media_active)) {
380 val |= MSR_GM | MSR_EN_125MHZ;
381 if (link_status & PLSR_USB_SS)
382 memcpy(tmp, &axge_bulk_size[0], 5);
383 else if (link_status & PLSR_USB_HS)
384 memcpy(tmp, &axge_bulk_size[1], 5);
386 memcpy(tmp, &axge_bulk_size[3], 5);
390 if (link_status & (PLSR_USB_SS | PLSR_USB_HS))
391 memcpy(tmp, &axge_bulk_size[2], 5);
393 memcpy(tmp, &axge_bulk_size[3], 5);
396 memcpy(tmp, &axge_bulk_size[3], 5);
399 /* Rx bulk configuration. */
400 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5);
401 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);
408 axge_chip_init(struct axge_softc *sc)
410 /* Power up ethernet PHY. */
411 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0);
412 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL);
413 uether_pause(&sc->sc_ue, hz / 4);
414 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT,
415 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS);
416 uether_pause(&sc->sc_ue, hz / 10);
420 axge_reset(struct axge_softc *sc)
422 struct usb_config_descriptor *cd;
425 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
427 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
428 cd->bConfigurationValue);
430 DPRINTF("reset failed (ignored)\n");
432 /* Wait a little while for the chip to get its brains in order. */
433 uether_pause(&sc->sc_ue, hz / 100);
435 /* Reinitialize controller to achieve full reset. */
440 axge_attach_post(struct usb_ether *ue)
442 struct axge_softc *sc;
444 sc = uether_getsc(ue);
446 /* Initialize controller and get station address. */
448 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
449 ue->ue_eaddr, ETHER_ADDR_LEN);
453 axge_attach_post_sub(struct usb_ether *ue)
455 struct axge_softc *sc;
459 sc = uether_getsc(ue);
461 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
462 ifp->if_start = uether_start;
463 ifp->if_ioctl = axge_ioctl;
464 ifp->if_init = uether_init;
465 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
466 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
467 IFQ_SET_READY(&ifp->if_snd);
469 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM;
470 ifp->if_hwassist = AXGE_CSUM_FEATURES;
471 ifp->if_capenable = ifp->if_capabilities;
474 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
475 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
476 BMSR_DEFCAPMASK, AXGE_PHY_ADDR, MII_OFFSET_ANY, MIIF_DOPAUSE);
486 axge_ifmedia_upd(struct ifnet *ifp)
488 struct axge_softc *sc;
489 struct mii_data *mii;
490 struct mii_softc *miisc;
495 AXGE_LOCK_ASSERT(sc, MA_OWNED);
497 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
499 error = mii_mediachg(mii);
505 * Report current media status.
508 axge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
510 struct axge_softc *sc;
511 struct mii_data *mii;
517 ifmr->ifm_active = mii->mii_media_active;
518 ifmr->ifm_status = mii->mii_media_status;
523 * Probe for a AX88179 chip.
526 axge_probe(device_t dev)
528 struct usb_attach_arg *uaa;
530 uaa = device_get_ivars(dev);
531 if (uaa->usb_mode != USB_MODE_HOST)
533 if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX)
535 if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX)
538 return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa));
542 * Attach the interface. Allocate softc structures, do ifmedia
543 * setup and ethernet/BPF attach.
546 axge_attach(device_t dev)
548 struct usb_attach_arg *uaa;
549 struct axge_softc *sc;
550 struct usb_ether *ue;
554 uaa = device_get_ivars(dev);
555 sc = device_get_softc(dev);
558 device_set_usb_desc(dev);
559 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
561 iface_index = AXGE_IFACE_IDX;
562 error = usbd_transfer_setup(uaa->device, &iface_index,
563 sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_mtx);
565 device_printf(dev, "allocating USB transfers failed\n");
566 mtx_destroy(&sc->sc_mtx);
572 ue->ue_udev = uaa->device;
573 ue->ue_mtx = &sc->sc_mtx;
574 ue->ue_methods = &axge_ue_methods;
576 error = uether_ifattach(ue);
578 device_printf(dev, "could not attach interface\n");
581 return (0); /* success */
585 return (ENXIO); /* failure */
589 axge_detach(device_t dev)
591 struct axge_softc *sc;
592 struct usb_ether *ue;
595 sc = device_get_softc(dev);
597 if (device_is_attached(dev)) {
598 /* wait for any post attach or other command to complete */
599 usb_proc_drain(&ue->ue_tq);
604 * ether_ifdetach(9) should be called first.
607 /* Force bulk-in to return a zero-length USB packet. */
608 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR);
609 val |= EPPRCR_BZ | EPPRCR_IPRL;
610 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, val);
612 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 0);
614 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, 0);
617 usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER);
619 mtx_destroy(&sc->sc_mtx);
625 axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
627 struct axge_softc *sc;
628 struct usb_ether *ue;
629 struct usb_page_cache *pc;
632 sc = usbd_xfer_softc(xfer);
634 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
636 switch (USB_GET_STATE(xfer)) {
637 case USB_ST_TRANSFERRED:
638 pc = usbd_xfer_get_frame(xfer, 0);
639 axge_rx_frame(ue, pc, actlen);
644 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
645 usbd_transfer_submit(xfer);
650 if (error != USB_ERR_CANCELLED) {
651 usbd_xfer_set_stall(xfer);
659 axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
661 struct axge_softc *sc;
663 struct usb_page_cache *pc;
665 struct axge_frame_txhdr txhdr;
668 sc = usbd_xfer_softc(xfer);
669 ifp = uether_getifp(&sc->sc_ue);
671 switch (USB_GET_STATE(xfer)) {
672 case USB_ST_TRANSFERRED:
673 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
677 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 ||
678 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
680 * Don't send anything if there is no link or
681 * controller is busy.
686 for (nframes = 0; nframes < AXGE_N_FRAMES &&
687 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
688 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
691 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
693 pc = usbd_xfer_get_frame(xfer, nframes);
695 txhdr.len = htole32(AXGE_TXBYTES(m->m_pkthdr.len));
696 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0 &&
697 (m->m_pkthdr.csum_flags & AXGE_CSUM_FEATURES) == 0)
698 txhdr.len |= htole32(AXGE_CSUM_DISABLE);
701 usbd_copy_in(pc, pos, &txhdr, sizeof(txhdr));
702 pos += sizeof(txhdr);
703 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
704 pos += m->m_pkthdr.len;
707 * if there's a BPF listener, bounce a copy
708 * of this frame to him:
714 /* Set frame length. */
715 usbd_xfer_set_frame_len(xfer, nframes, pos);
720 * Update TX packet counter here. This is not
721 * correct way but it seems that there is no way
722 * to know how many packets are sent at the end
723 * of transfer because controller combines
724 * multiple writes into single one if there is
725 * room in TX buffer of controller.
727 if_inc_counter(ifp, IFCOUNTER_OPACKETS, nframes);
728 usbd_xfer_set_frames(xfer, nframes);
729 usbd_transfer_submit(xfer);
730 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
735 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
736 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
738 if (error != USB_ERR_CANCELLED) {
739 usbd_xfer_set_stall(xfer);
747 axge_tick(struct usb_ether *ue)
749 struct axge_softc *sc;
750 struct mii_data *mii;
752 sc = uether_getsc(ue);
754 AXGE_LOCK_ASSERT(sc, MA_OWNED);
760 axge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
762 uint8_t *hashtbl = arg;
765 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
766 hashtbl[h / 8] |= 1 << (h % 8);
772 axge_rxfilter(struct usb_ether *ue)
774 struct axge_softc *sc;
777 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
779 sc = uether_getsc(ue);
780 ifp = uether_getifp(ue);
781 AXGE_LOCK_ASSERT(sc, MA_OWNED);
784 * Configure RX settings.
785 * Don't set RCR_IPE(IP header alignment on 32bit boundary) to disable
786 * inserting extra padding bytes. This wastes ethernet to USB host
787 * bandwidth as well as complicating RX handling logic. Current USB
788 * framework requires copying RX frames to mbufs so there is no need
789 * to worry about alignment.
791 rxmode = RCR_DROP_CRCERR | RCR_START;
792 if (ifp->if_flags & IFF_BROADCAST)
793 rxmode |= RCR_ACPT_BCAST;
794 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
795 if (ifp->if_flags & IFF_PROMISC)
796 rxmode |= RCR_PROMISC;
797 rxmode |= RCR_ACPT_ALL_MCAST;
798 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
802 rxmode |= RCR_ACPT_MCAST;
803 if_foreach_llmaddr(ifp, axge_hash_maddr, &hashtbl);
805 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8);
806 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
810 axge_start(struct usb_ether *ue)
812 struct axge_softc *sc;
814 sc = uether_getsc(ue);
816 * Start the USB transfers, if not already started.
818 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]);
819 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]);
823 axge_init(struct usb_ether *ue)
825 struct axge_softc *sc;
828 sc = uether_getsc(ue);
829 ifp = uether_getifp(ue);
830 AXGE_LOCK_ASSERT(sc, MA_OWNED);
832 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
836 * Cancel pending I/O and free all RX/TX buffers.
842 /* Set MAC address. */
843 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
844 IF_LLADDR(ifp), ETHER_ADDR_LEN);
846 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34);
847 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52);
849 /* Configure TX/RX checksum offloading. */
852 /* Configure RX filters. */
857 * Controller supports wakeup on link change detection,
858 * magic packet and wakeup frame recpetion. But it seems
859 * there is no framework for USB ethernet suspend/wakeup.
860 * Disable all wakeup functions.
862 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 0);
863 (void)axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR);
865 /* Configure default medium type. */
866 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, MSR_GM | MSR_FD |
867 MSR_RFC | MSR_TFC | MSR_RE);
869 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]);
871 ifp->if_drv_flags |= IFF_DRV_RUNNING;
872 /* Switch to selected media. */
873 axge_ifmedia_upd(ifp);
877 axge_stop(struct usb_ether *ue)
879 struct axge_softc *sc;
883 sc = uether_getsc(ue);
884 ifp = uether_getifp(ue);
886 AXGE_LOCK_ASSERT(sc, MA_OWNED);
888 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR);
890 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);
893 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
894 sc->sc_flags &= ~AXGE_FLAG_LINK;
897 * Stop all the transfers, if not already stopped:
899 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]);
900 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]);
904 axge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
906 struct usb_ether *ue;
907 struct axge_softc *sc;
909 int error, mask, reinit;
912 sc = uether_getsc(ue);
913 ifr = (struct ifreq *)data;
916 if (cmd == SIOCSIFCAP) {
918 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
919 if ((mask & IFCAP_TXCSUM) != 0 &&
920 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
921 ifp->if_capenable ^= IFCAP_TXCSUM;
922 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
923 ifp->if_hwassist |= AXGE_CSUM_FEATURES;
925 ifp->if_hwassist &= ~AXGE_CSUM_FEATURES;
928 if ((mask & IFCAP_RXCSUM) != 0 &&
929 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
930 ifp->if_capenable ^= IFCAP_RXCSUM;
933 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
934 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
941 error = uether_ioctl(ifp, cmd, data);
947 axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
949 struct axge_frame_rxhdr pkt_hdr;
952 uint32_t pkt_cnt, pkt_end;
956 /* verify we have enough data */
957 if (actlen < (int)sizeof(rxhdr))
962 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr));
963 rxhdr = le32toh(rxhdr);
965 pkt_cnt = rxhdr & 0xFFFF;
966 hdr_off = pkt_end = (rxhdr >> 16) & 0xFFFF;
969 * <----------------------- actlen ------------------------>
970 * [frame #0]...[frame #N][pkt_hdr #0]...[pkt_hdr #N][rxhdr]
971 * Each RX frame would be aligned on 8 bytes boundary. If
972 * RCR_IPE bit is set in AXGE_RCR register, there would be 2
973 * padding bytes and 6 dummy bytes(as the padding also should
974 * be aligned on 8 bytes boundary) for each RX frame to align
975 * IP header on 32bits boundary. Driver don't set RCR_IPE bit
976 * of AXGE_RCR register, so there should be no padding bytes
977 * which simplifies RX logic a lot.
980 /* verify the header offset */
981 if ((int)(hdr_off + sizeof(pkt_hdr)) > actlen) {
982 DPRINTF("End of packet headers\n");
985 usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr));
986 pkt_hdr.status = le32toh(pkt_hdr.status);
987 pktlen = AXGE_RXBYTES(pkt_hdr.status);
988 if (pos + pktlen > pkt_end) {
989 DPRINTF("Data position reached end\n");
993 if (AXGE_RX_ERR(pkt_hdr.status) != 0) {
994 DPRINTF("Dropped a packet\n");
995 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1);
997 axge_rxeof(ue, pc, pos, pktlen, pkt_hdr.status);
998 pos += (pktlen + 7) & ~7;
999 hdr_off += sizeof(pkt_hdr);
1004 axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset,
1005 unsigned int len, uint32_t status)
1011 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
1012 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1016 if (len > MHLEN - ETHER_ALIGN)
1017 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1019 m = m_gethdr(M_NOWAIT, MT_DATA);
1021 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1024 m->m_pkthdr.rcvif = ifp;
1025 m->m_len = m->m_pkthdr.len = len;
1026 m->m_data += ETHER_ALIGN;
1028 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1030 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1031 if ((status & AXGE_RX_L3_CSUM_ERR) == 0 &&
1032 (status & AXGE_RX_L3_TYPE_MASK) == AXGE_RX_L3_TYPE_IPV4)
1033 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1035 if ((status & AXGE_RX_L4_CSUM_ERR) == 0 &&
1036 ((status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_UDP ||
1037 (status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_TCP)) {
1038 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1040 m->m_pkthdr.csum_data = 0xffff;
1043 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1045 (void)mbufq_enqueue(&ue->ue_rxq, m);
1049 axge_csum_cfg(struct usb_ether *ue)
1051 struct axge_softc *sc;
1055 sc = uether_getsc(ue);
1056 AXGE_LOCK_ASSERT(sc, MA_OWNED);
1057 ifp = uether_getifp(ue);
1060 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1061 csum |= CTCR_IP | CTCR_TCP | CTCR_UDP;
1062 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum);
1065 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1066 csum |= CRCR_IP | CRCR_TCP | CRCR_UDP;
1067 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum);