2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/condvar.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/socket.h>
39 #include <sys/sysctl.h>
40 #include <sys/unistd.h>
43 #include <net/if_var.h>
45 #include <dev/usb/usb.h>
46 #include <dev/usb/usbdi.h>
47 #include <dev/usb/usbdi_util.h>
50 #define USB_DEBUG_VAR ure_debug
51 #include <dev/usb/usb_debug.h>
52 #include <dev/usb/usb_process.h>
54 #include <dev/usb/net/usb_ethernet.h>
55 #include <dev/usb/net/if_urereg.h>
58 static int ure_debug = 0;
60 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure");
61 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
66 * Various supported device vendors/products.
68 static const STRUCT_USB_HOST_ID ure_devs[] = {
69 #define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
70 URE_DEV(LENOVO, RTL8153, 0),
71 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
72 URE_DEV(REALTEK, RTL8153, 0),
73 URE_DEV(TPLINK, RTL8153, 0),
77 static device_probe_t ure_probe;
78 static device_attach_t ure_attach;
79 static device_detach_t ure_detach;
81 static usb_callback_t ure_bulk_read_callback;
82 static usb_callback_t ure_bulk_write_callback;
84 static miibus_readreg_t ure_miibus_readreg;
85 static miibus_writereg_t ure_miibus_writereg;
86 static miibus_statchg_t ure_miibus_statchg;
88 static uether_fn_t ure_attach_post;
89 static uether_fn_t ure_init;
90 static uether_fn_t ure_stop;
91 static uether_fn_t ure_start;
92 static uether_fn_t ure_tick;
93 static uether_fn_t ure_rxfilter;
95 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
97 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
99 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
101 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t);
102 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
103 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
104 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
105 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
106 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
107 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
108 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
110 static void ure_read_chipver(struct ure_softc *);
111 static int ure_attach_post_sub(struct usb_ether *);
112 static void ure_reset(struct ure_softc *);
113 static int ure_ifmedia_upd(struct ifnet *);
114 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *);
115 static int ure_ioctl(struct ifnet *, u_long, caddr_t);
116 static void ure_rtl8152_init(struct ure_softc *);
117 static void ure_rtl8153_init(struct ure_softc *);
118 static void ure_disable_teredo(struct ure_softc *);
119 static void ure_init_fifo(struct ure_softc *);
121 static const struct usb_config ure_config[URE_N_TRANSFER] = {
124 .endpoint = UE_ADDR_ANY,
125 .direction = UE_DIR_OUT,
127 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
128 .callback = ure_bulk_write_callback,
129 .timeout = 10000, /* 10 seconds */
133 .endpoint = UE_ADDR_ANY,
134 .direction = UE_DIR_IN,
136 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
137 .callback = ure_bulk_read_callback,
138 .timeout = 0, /* no timeout */
142 static device_method_t ure_methods[] = {
143 /* Device interface. */
144 DEVMETHOD(device_probe, ure_probe),
145 DEVMETHOD(device_attach, ure_attach),
146 DEVMETHOD(device_detach, ure_detach),
149 DEVMETHOD(miibus_readreg, ure_miibus_readreg),
150 DEVMETHOD(miibus_writereg, ure_miibus_writereg),
151 DEVMETHOD(miibus_statchg, ure_miibus_statchg),
156 static driver_t ure_driver = {
158 .methods = ure_methods,
159 .size = sizeof(struct ure_softc),
162 static devclass_t ure_devclass;
164 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL);
165 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL);
166 MODULE_DEPEND(ure, uether, 1, 1, 1);
167 MODULE_DEPEND(ure, usb, 1, 1, 1);
168 MODULE_DEPEND(ure, ether, 1, 1, 1);
169 MODULE_DEPEND(ure, miibus, 1, 1, 1);
170 MODULE_VERSION(ure, 1);
172 static const struct usb_ether_methods ure_ue_methods = {
173 .ue_attach_post = ure_attach_post,
174 .ue_attach_post_sub = ure_attach_post_sub,
175 .ue_start = ure_start,
179 .ue_setmulti = ure_rxfilter,
180 .ue_setpromisc = ure_rxfilter,
181 .ue_mii_upd = ure_ifmedia_upd,
182 .ue_mii_sts = ure_ifmedia_sts,
186 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
189 struct usb_device_request req;
191 URE_LOCK_ASSERT(sc, MA_OWNED);
193 if (rw == URE_CTL_WRITE)
194 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
196 req.bmRequestType = UT_READ_VENDOR_DEVICE;
197 req.bRequest = UR_SET_ADDRESS;
198 USETW(req.wValue, val);
199 USETW(req.wIndex, index);
200 USETW(req.wLength, len);
202 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
206 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
210 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
214 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
218 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
222 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
228 shift = (reg & 3) << 3;
231 ure_read_mem(sc, reg, index, &temp, 4);
239 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
245 shift = (reg & 2) << 3;
248 ure_read_mem(sc, reg, index, &temp, 4);
252 return (val & 0xffff);
256 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
260 ure_read_mem(sc, reg, index, &temp, 4);
261 return (UGETDW(temp));
265 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
271 byen = URE_BYTE_EN_BYTE;
277 val <<= (shift << 3);
282 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
286 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
292 byen = URE_BYTE_EN_WORD;
298 val <<= (shift << 3);
303 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
307 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
312 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
316 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
320 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
321 reg = (addr & 0x0fff) | 0xb000;
323 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
327 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
331 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
332 reg = (addr & 0x0fff) | 0xb000;
334 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
338 ure_miibus_readreg(device_t dev, int phy, int reg)
340 struct ure_softc *sc;
344 sc = device_get_softc(dev);
345 locked = mtx_owned(&sc->sc_mtx);
349 /* Let the rgephy driver read the URE_GMEDIASTAT register. */
350 if (reg == URE_GMEDIASTAT) {
353 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
356 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
364 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
366 struct ure_softc *sc;
369 sc = device_get_softc(dev);
370 if (sc->sc_phyno != phy)
373 locked = mtx_owned(&sc->sc_mtx);
377 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
385 ure_miibus_statchg(device_t dev)
387 struct ure_softc *sc;
388 struct mii_data *mii;
392 sc = device_get_softc(dev);
394 locked = mtx_owned(&sc->sc_mtx);
398 ifp = uether_getifp(&sc->sc_ue);
399 if (mii == NULL || ifp == NULL ||
400 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
403 sc->sc_flags &= ~URE_FLAG_LINK;
404 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
405 (IFM_ACTIVE | IFM_AVALID)) {
406 switch (IFM_SUBTYPE(mii->mii_media_active)) {
409 sc->sc_flags |= URE_FLAG_LINK;
412 if ((sc->sc_flags & URE_FLAG_8152) != 0)
414 sc->sc_flags |= URE_FLAG_LINK;
421 /* Lost link, do nothing. */
422 if ((sc->sc_flags & URE_FLAG_LINK) == 0)
430 * Probe for a RTL8152/RTL8153 chip.
433 ure_probe(device_t dev)
435 struct usb_attach_arg *uaa;
437 uaa = device_get_ivars(dev);
438 if (uaa->usb_mode != USB_MODE_HOST)
440 if (uaa->info.bConfigIndex != URE_CONFIG_IDX)
442 if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
445 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
449 * Attach the interface. Allocate softc structures, do ifmedia
450 * setup and ethernet/BPF attach.
453 ure_attach(device_t dev)
455 struct usb_attach_arg *uaa = device_get_ivars(dev);
456 struct ure_softc *sc = device_get_softc(dev);
457 struct usb_ether *ue = &sc->sc_ue;
461 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
462 device_set_usb_desc(dev);
463 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
465 iface_index = URE_IFACE_IDX;
466 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
467 ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx);
469 device_printf(dev, "allocating USB transfers failed\n");
475 ue->ue_udev = uaa->device;
476 ue->ue_mtx = &sc->sc_mtx;
477 ue->ue_methods = &ure_ue_methods;
479 error = uether_ifattach(ue);
481 device_printf(dev, "could not attach interface\n");
484 return (0); /* success */
488 return (ENXIO); /* failure */
492 ure_detach(device_t dev)
494 struct ure_softc *sc = device_get_softc(dev);
495 struct usb_ether *ue = &sc->sc_ue;
497 usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER);
499 mtx_destroy(&sc->sc_mtx);
505 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
507 struct ure_softc *sc = usbd_xfer_softc(xfer);
508 struct usb_ether *ue = &sc->sc_ue;
509 struct ifnet *ifp = uether_getifp(ue);
510 struct usb_page_cache *pc;
511 struct ure_rxpkt pkt;
514 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
516 switch (USB_GET_STATE(xfer)) {
517 case USB_ST_TRANSFERRED:
518 if (actlen < (int)(sizeof(pkt))) {
519 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
522 pc = usbd_xfer_get_frame(xfer, 0);
523 usbd_copy_out(pc, 0, &pkt, sizeof(pkt));
524 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
525 len -= ETHER_CRC_LEN;
526 if (actlen < (int)(len + sizeof(pkt))) {
527 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
531 uether_rxbuf(ue, pc, sizeof(pkt), len);
535 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
536 usbd_transfer_submit(xfer);
541 DPRINTF("bulk read error, %s\n",
544 if (error != USB_ERR_CANCELLED) {
545 /* try to clear stall first */
546 usbd_xfer_set_stall(xfer);
554 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
556 struct ure_softc *sc = usbd_xfer_softc(xfer);
557 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
558 struct usb_page_cache *pc;
560 struct ure_txpkt txpkt;
563 switch (USB_GET_STATE(xfer)) {
564 case USB_ST_TRANSFERRED:
565 DPRINTFN(11, "transfer complete\n");
566 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
570 if ((sc->sc_flags & URE_FLAG_LINK) == 0 ||
571 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
573 * don't send anything if there is no link !
577 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
581 len = m->m_pkthdr.len;
582 pc = usbd_xfer_get_frame(xfer, 0);
583 memset(&txpkt, 0, sizeof(txpkt));
584 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
585 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
586 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
587 pos += sizeof(txpkt);
588 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
589 pos += m->m_pkthdr.len;
591 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
594 * If there's a BPF listener, bounce a copy
595 * of this frame to him.
601 /* Set frame length. */
602 usbd_xfer_set_frame_len(xfer, 0, pos);
604 usbd_transfer_submit(xfer);
605 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
608 DPRINTFN(11, "transfer error, %s\n",
611 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
612 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
614 if (error != USB_ERR_CANCELLED) {
615 /* try to clear stall first */
616 usbd_xfer_set_stall(xfer);
624 ure_read_chipver(struct ure_softc *sc)
628 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
631 sc->sc_chip |= URE_CHIP_VER_4C00;
634 sc->sc_chip |= URE_CHIP_VER_4C10;
637 sc->sc_chip |= URE_CHIP_VER_5C00;
640 sc->sc_chip |= URE_CHIP_VER_5C10;
643 sc->sc_chip |= URE_CHIP_VER_5C20;
646 sc->sc_chip |= URE_CHIP_VER_5C30;
649 device_printf(sc->sc_ue.ue_dev,
650 "unknown version 0x%04x\n", ver);
656 ure_attach_post(struct usb_ether *ue)
658 struct ure_softc *sc = uether_getsc(ue);
662 /* Determine the chip version. */
663 ure_read_chipver(sc);
665 /* Initialize controller and get station address. */
666 if (sc->sc_flags & URE_FLAG_8152)
667 ure_rtl8152_init(sc);
669 ure_rtl8153_init(sc);
671 if (sc->sc_chip & URE_CHIP_VER_4C00)
672 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
675 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
680 ure_attach_post_sub(struct usb_ether *ue)
682 struct ure_softc *sc;
686 sc = uether_getsc(ue);
688 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
689 ifp->if_start = uether_start;
690 ifp->if_ioctl = ure_ioctl;
691 ifp->if_init = uether_init;
692 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
693 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
694 IFQ_SET_READY(&ifp->if_snd);
697 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
698 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
699 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
706 ure_init(struct usb_ether *ue)
708 struct ure_softc *sc = uether_getsc(ue);
709 struct ifnet *ifp = uether_getifp(ue);
711 URE_LOCK_ASSERT(sc, MA_OWNED);
713 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
716 /* Cancel pending I/O. */
721 /* Set MAC address. */
722 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
725 /* Reset the packet filter. */
726 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
727 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) &
728 ~URE_FMC_FCR_MCU_EN);
729 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
730 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) |
733 /* Enable transmit and receive. */
734 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA,
735 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE |
738 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
739 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) &
742 /* Configure RX filters. */
745 usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]);
747 /* Indicate we are up and running. */
748 ifp->if_drv_flags |= IFF_DRV_RUNNING;
750 /* Switch to selected media. */
751 ure_ifmedia_upd(ifp);
755 ure_tick(struct usb_ether *ue)
757 struct ure_softc *sc = uether_getsc(ue);
758 struct mii_data *mii = GET_MII(sc);
760 URE_LOCK_ASSERT(sc, MA_OWNED);
763 if ((sc->sc_flags & URE_FLAG_LINK) == 0
764 && mii->mii_media_status & IFM_ACTIVE &&
765 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
766 sc->sc_flags |= URE_FLAG_LINK;
772 * Program the 64-bit multicast hash filter.
775 ure_rxfilter(struct usb_ether *ue)
777 struct ure_softc *sc = uether_getsc(ue);
778 struct ifnet *ifp = uether_getifp(ue);
779 struct ifmultiaddr *ifma;
781 uint32_t hashes[2] = { 0, 0 };
783 URE_LOCK_ASSERT(sc, MA_OWNED);
785 rxmode = URE_RCR_APM;
786 if (ifp->if_flags & IFF_BROADCAST)
787 rxmode |= URE_RCR_AB;
788 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
789 if (ifp->if_flags & IFF_PROMISC)
790 rxmode |= URE_RCR_AAP;
791 rxmode |= URE_RCR_AM;
792 hashes[0] = hashes[1] = 0xffffffff;
796 rxmode |= URE_RCR_AM;
798 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
799 if (ifma->ifma_addr->sa_family != AF_LINK)
801 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
802 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
804 hashes[0] |= (1 << h);
806 hashes[1] |= (1 << (h - 32));
808 if_maddr_runlock(ifp);
810 h = bswap32(hashes[0]);
811 hashes[0] = bswap32(hashes[1]);
813 rxmode |= URE_RCR_AM;
816 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
817 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
818 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
822 ure_start(struct usb_ether *ue)
824 struct ure_softc *sc = uether_getsc(ue);
827 * start the USB transfers, if not already started:
829 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]);
830 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]);
834 ure_reset(struct ure_softc *sc)
838 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
840 for (i = 0; i < URE_TIMEOUT; i++) {
841 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
844 uether_pause(&sc->sc_ue, hz / 100);
846 if (i == URE_TIMEOUT)
847 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
854 ure_ifmedia_upd(struct ifnet *ifp)
856 struct ure_softc *sc = ifp->if_softc;
857 struct mii_data *mii = GET_MII(sc);
858 struct mii_softc *miisc;
861 URE_LOCK_ASSERT(sc, MA_OWNED);
863 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
865 error = mii_mediachg(mii);
870 * Report current media status.
873 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
875 struct ure_softc *sc;
876 struct mii_data *mii;
883 ifmr->ifm_active = mii->mii_media_active;
884 ifmr->ifm_status = mii->mii_media_status;
889 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
891 struct usb_ether *ue = ifp->if_softc;
892 struct ure_softc *sc;
894 int error, mask, reinit;
896 sc = uether_getsc(ue);
897 ifr = (struct ifreq *)data;
900 if (cmd == SIOCSIFCAP) {
902 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
903 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
904 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
911 error = uether_ioctl(ifp, cmd, data);
917 ure_rtl8152_init(struct ure_softc *sc)
922 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
924 uether_pause(&sc->sc_ue, hz / 50);
926 if (sc->sc_chip & URE_CHIP_VER_4C00) {
927 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
928 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
932 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB,
933 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) &
935 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB,
936 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) &
937 ~URE_RESUME_INDICATE);
939 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
940 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
941 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
942 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
943 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
944 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
945 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
946 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
947 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
948 URE_SPDWN_LINKCHG_MSK);
950 /* Disable Rx aggregation. */
951 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
952 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
956 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
958 uether_pause(&sc->sc_ue, hz / 50);
962 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
963 URE_TX_AGG_MAX_THRESHOLD);
964 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
965 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
966 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
970 ure_rtl8153_init(struct ure_softc *sc)
977 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
978 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
979 uether_pause(&sc->sc_ue, hz / 50);
981 memset(u1u2, 0x00, sizeof(u1u2));
982 ure_write_mem(sc, URE_USB_TOLERANCE,
983 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
985 for (i = 0; i < URE_TIMEOUT; i++) {
986 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
989 uether_pause(&sc->sc_ue, hz / 100);
991 if (i == URE_TIMEOUT)
992 device_printf(sc->sc_ue.ue_dev,
993 "timeout waiting for chip autoload\n");
995 for (i = 0; i < URE_TIMEOUT; i++) {
996 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
998 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
1000 uether_pause(&sc->sc_ue, hz / 100);
1002 if (i == URE_TIMEOUT)
1003 device_printf(sc->sc_ue.ue_dev,
1004 "timeout waiting for phy to stabilize\n");
1006 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,
1007 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) &
1010 if (sc->sc_chip & URE_CHIP_VER_5C10) {
1011 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1012 val &= ~URE_PWD_DN_SCALE_MASK;
1013 val |= URE_PWD_DN_SCALE(96);
1014 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
1016 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB,
1017 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) |
1018 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1019 } else if (sc->sc_chip & URE_CHIP_VER_5C20) {
1020 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA,
1021 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) &
1024 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1025 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
1026 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
1028 val &= ~URE_DYNAMIC_BURST;
1030 val |= URE_DYNAMIC_BURST;
1031 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
1034 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB,
1035 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) |
1038 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB,
1039 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) &
1042 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
1043 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
1044 ~URE_LED_MODE_MASK);
1046 if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
1047 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
1048 val = URE_LPM_TIMER_500MS;
1050 val = URE_LPM_TIMER_500US;
1051 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1052 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
1054 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1055 val &= ~URE_SEN_VAL_MASK;
1056 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1057 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
1059 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1061 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,
1062 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) &
1063 ~(URE_PWR_EN | URE_PHASE2_EN));
1064 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB,
1065 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) &
1068 memset(u1u2, 0xff, sizeof(u1u2));
1069 ure_write_mem(sc, URE_USB_TOLERANCE,
1070 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1072 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
1073 URE_ALDPS_SPDWN_RATIO);
1074 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1075 URE_EEE_SPDWN_RATIO);
1076 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1077 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
1078 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
1079 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
1080 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
1081 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
1084 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1085 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1086 val |= URE_U2P3_ENABLE;
1088 val &= ~URE_U2P3_ENABLE;
1089 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1091 memset(u1u2, 0x00, sizeof(u1u2));
1092 ure_write_mem(sc, URE_USB_TOLERANCE,
1093 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1095 /* Disable ALDPS. */
1096 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1097 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
1098 uether_pause(&sc->sc_ue, hz / 50);
1102 /* Disable Rx aggregation. */
1103 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
1104 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
1105 URE_RX_AGG_DISABLE);
1107 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1108 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1109 val |= URE_U2P3_ENABLE;
1111 val &= ~URE_U2P3_ENABLE;
1112 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1114 memset(u1u2, 0xff, sizeof(u1u2));
1115 ure_write_mem(sc, URE_USB_TOLERANCE,
1116 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1120 ure_stop(struct usb_ether *ue)
1122 struct ure_softc *sc = uether_getsc(ue);
1123 struct ifnet *ifp = uether_getifp(ue);
1125 URE_LOCK_ASSERT(sc, MA_OWNED);
1127 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1128 sc->sc_flags &= ~URE_FLAG_LINK;
1131 * stop all the transfers, if not already stopped:
1133 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]);
1134 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]);
1138 ure_disable_teredo(struct ure_softc *sc)
1141 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
1142 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) &
1143 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
1144 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA,
1146 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
1147 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
1151 ure_init_fifo(struct ure_softc *sc)
1153 uint32_t rx_fifo1, rx_fifo2;
1156 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
1157 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) |
1160 ure_disable_teredo(sc);
1162 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA,
1163 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) &
1166 if (!(sc->sc_flags & URE_FLAG_8152)) {
1167 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1168 URE_CHIP_VER_5C20)) {
1169 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
1170 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1172 if (sc->sc_chip & URE_CHIP_VER_5C00) {
1173 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
1174 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
1175 ~URE_CTAP_SHORT_EN);
1177 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1178 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1180 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
1181 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
1183 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1184 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1186 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE);
1187 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13);
1188 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
1189 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
1190 URE_PFM_PWM_SWITCH);
1192 /* Enable LPF corner auto tune. */
1193 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG);
1194 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f);
1196 /* Adjust 10M amplitude. */
1197 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1);
1198 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af);
1199 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2);
1200 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208);
1205 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
1207 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA,
1208 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1211 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1212 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) &
1214 for (i = 0; i < URE_TIMEOUT; i++) {
1215 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1216 URE_LINK_LIST_READY)
1218 uether_pause(&sc->sc_ue, hz / 100);
1220 if (i == URE_TIMEOUT)
1221 device_printf(sc->sc_ue.ue_dev,
1222 "timeout waiting for OOB control\n");
1223 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1224 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) |
1226 for (i = 0; i < URE_TIMEOUT; i++) {
1227 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1228 URE_LINK_LIST_READY)
1230 uether_pause(&sc->sc_ue, hz / 100);
1232 if (i == URE_TIMEOUT)
1233 device_printf(sc->sc_ue.ue_dev,
1234 "timeout waiting for OOB control\n");
1236 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA,
1237 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) &
1239 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,
1240 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) |
1241 URE_TCR0_AUTO_FIFO);
1243 /* Configure Rx FIFO threshold. */
1244 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
1245 URE_RXFIFO_THR1_NORMAL);
1246 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
1247 rx_fifo1 = URE_RXFIFO_THR2_FULL;
1248 rx_fifo2 = URE_RXFIFO_THR3_FULL;
1250 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
1251 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
1253 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
1254 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
1256 /* Configure Tx FIFO threshold. */
1257 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
1258 URE_TXFIFO_THR_NORMAL);