2 * Copyright (c) 2015 Kevin Lo <kevlo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/condvar.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/socket.h>
39 #include <sys/sysctl.h>
40 #include <sys/unistd.h>
43 #include <net/if_var.h>
45 #include <dev/usb/usb.h>
46 #include <dev/usb/usbdi.h>
47 #include <dev/usb/usbdi_util.h>
50 #define USB_DEBUG_VAR ure_debug
51 #include <dev/usb/usb_debug.h>
52 #include <dev/usb/usb_process.h>
54 #include <dev/usb/net/usb_ethernet.h>
55 #include <dev/usb/net/if_urereg.h>
58 static int ure_debug = 0;
60 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure");
61 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
66 * Various supported device vendors/products.
68 static const STRUCT_USB_HOST_ID ure_devs[] = {
69 #define URE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
70 URE_DEV(REALTEK, RTL8152),
74 static device_probe_t ure_probe;
75 static device_attach_t ure_attach;
76 static device_detach_t ure_detach;
78 static usb_callback_t ure_bulk_read_callback;
79 static usb_callback_t ure_bulk_write_callback;
81 static miibus_readreg_t ure_miibus_readreg;
82 static miibus_writereg_t ure_miibus_writereg;
83 static miibus_statchg_t ure_miibus_statchg;
85 static uether_fn_t ure_attach_post;
86 static uether_fn_t ure_init;
87 static uether_fn_t ure_stop;
88 static uether_fn_t ure_start;
89 static uether_fn_t ure_tick;
90 static uether_fn_t ure_setmulti;
91 static uether_fn_t ure_setpromisc;
93 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
95 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
97 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
99 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t);
100 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
101 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
102 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
103 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
104 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
105 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
106 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
108 static void ure_read_chipver(struct ure_softc *);
109 static int ure_attach_post_sub(struct usb_ether *);
110 static void ure_reset(struct ure_softc *);
111 static int ure_ifmedia_upd(struct ifnet *);
112 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *);
113 static int ure_ioctl(struct ifnet *, u_long, caddr_t);
114 static void ure_rtl8152_init(struct ure_softc *);
115 static void ure_disable_teredo(struct ure_softc *);
116 static void ure_init_fifo(struct ure_softc *);
118 static const struct usb_config ure_config[URE_N_TRANSFER] = {
121 .endpoint = UE_ADDR_ANY,
122 .direction = UE_DIR_OUT,
124 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
125 .callback = ure_bulk_write_callback,
126 .timeout = 10000, /* 10 seconds */
130 .endpoint = UE_ADDR_ANY,
131 .direction = UE_DIR_IN,
133 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
134 .callback = ure_bulk_read_callback,
135 .timeout = 0, /* no timeout */
139 static device_method_t ure_methods[] = {
140 /* Device interface. */
141 DEVMETHOD(device_probe, ure_probe),
142 DEVMETHOD(device_attach, ure_attach),
143 DEVMETHOD(device_detach, ure_detach),
146 DEVMETHOD(miibus_readreg, ure_miibus_readreg),
147 DEVMETHOD(miibus_writereg, ure_miibus_writereg),
148 DEVMETHOD(miibus_statchg, ure_miibus_statchg),
153 static driver_t ure_driver = {
155 .methods = ure_methods,
156 .size = sizeof(struct ure_softc),
159 static devclass_t ure_devclass;
161 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL);
162 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL);
163 MODULE_DEPEND(ure, uether, 1, 1, 1);
164 MODULE_DEPEND(ure, usb, 1, 1, 1);
165 MODULE_DEPEND(ure, ether, 1, 1, 1);
166 MODULE_DEPEND(ure, miibus, 1, 1, 1);
167 MODULE_VERSION(ure, 1);
169 static const struct usb_ether_methods ure_ue_methods = {
170 .ue_attach_post = ure_attach_post,
171 .ue_attach_post_sub = ure_attach_post_sub,
172 .ue_start = ure_start,
176 .ue_setmulti = ure_setmulti,
177 .ue_setpromisc = ure_setpromisc,
178 .ue_mii_upd = ure_ifmedia_upd,
179 .ue_mii_sts = ure_ifmedia_sts,
183 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
186 struct usb_device_request req;
188 URE_LOCK_ASSERT(sc, MA_OWNED);
190 if (rw == URE_CTL_WRITE)
191 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
193 req.bmRequestType = UT_READ_VENDOR_DEVICE;
194 req.bRequest = UR_SET_ADDRESS;
195 USETW(req.wValue, val);
196 USETW(req.wIndex, index);
197 USETW(req.wLength, len);
199 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
203 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
207 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
211 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
215 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
219 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
225 shift = (reg & 3) << 3;
228 ure_read_mem(sc, reg, index, &temp, 4);
236 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
242 shift = (reg & 2) << 3;
245 ure_read_mem(sc, reg, index, &temp, 4);
249 return (val & 0xffff);
253 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
257 ure_read_mem(sc, reg, index, &temp, 4);
258 return (UGETDW(temp));
262 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
268 byen = URE_BYTE_EN_BYTE;
274 val <<= (shift << 3);
279 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
283 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
289 byen = URE_BYTE_EN_WORD;
295 val <<= (shift << 3);
300 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
304 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
309 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
313 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
317 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
318 reg = (addr & 0x0fff) | 0xb000;
320 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
324 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
328 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
329 reg = (addr & 0x0fff) | 0xb000;
331 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
335 ure_miibus_readreg(device_t dev, int phy, int reg)
337 struct ure_softc *sc;
341 sc = device_get_softc(dev);
342 locked = mtx_owned(&sc->sc_mtx);
346 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
354 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
356 struct ure_softc *sc;
359 sc = device_get_softc(dev);
360 if (sc->sc_phyno != phy)
363 locked = mtx_owned(&sc->sc_mtx);
367 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
375 ure_miibus_statchg(device_t dev)
377 struct ure_softc *sc;
378 struct mii_data *mii;
382 sc = device_get_softc(dev);
384 locked = mtx_owned(&sc->sc_mtx);
388 ifp = uether_getifp(&sc->sc_ue);
389 if (mii == NULL || ifp == NULL ||
390 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
393 sc->sc_flags &= ~URE_FLAG_LINK;
394 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
395 (IFM_ACTIVE | IFM_AVALID)) {
396 switch (IFM_SUBTYPE(mii->mii_media_active)) {
399 sc->sc_flags |= URE_FLAG_LINK;
406 /* Lost link, do nothing. */
407 if ((sc->sc_flags & URE_FLAG_LINK) == 0)
415 * Probe for a RTL8152 chip.
418 ure_probe(device_t dev)
420 struct usb_attach_arg *uaa;
422 uaa = device_get_ivars(dev);
423 if (uaa->usb_mode != USB_MODE_HOST)
425 if (uaa->info.bConfigIndex != URE_CONFIG_IDX)
427 if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
430 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
434 * Attach the interface. Allocate softc structures, do ifmedia
435 * setup and ethernet/BPF attach.
438 ure_attach(device_t dev)
440 struct usb_attach_arg *uaa = device_get_ivars(dev);
441 struct ure_softc *sc = device_get_softc(dev);
442 struct usb_ether *ue = &sc->sc_ue;
446 device_set_usb_desc(dev);
447 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
449 iface_index = URE_IFACE_IDX;
450 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
451 ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx);
453 device_printf(dev, "allocating USB transfers failed\n");
459 ue->ue_udev = uaa->device;
460 ue->ue_mtx = &sc->sc_mtx;
461 ue->ue_methods = &ure_ue_methods;
463 error = uether_ifattach(ue);
465 device_printf(dev, "could not attach interface\n");
468 return (0); /* success */
472 return (ENXIO); /* failure */
476 ure_detach(device_t dev)
478 struct ure_softc *sc = device_get_softc(dev);
479 struct usb_ether *ue = &sc->sc_ue;
481 usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER);
483 mtx_destroy(&sc->sc_mtx);
489 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
491 struct ure_softc *sc = usbd_xfer_softc(xfer);
492 struct usb_ether *ue = &sc->sc_ue;
493 struct ifnet *ifp = uether_getifp(ue);
494 struct usb_page_cache *pc;
495 struct ure_rxpkt pkt;
498 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
500 switch (USB_GET_STATE(xfer)) {
501 case USB_ST_TRANSFERRED:
502 if (actlen < (int)(sizeof(pkt))) {
503 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
506 pc = usbd_xfer_get_frame(xfer, 0);
507 usbd_copy_out(pc, 0, &pkt, sizeof(pkt));
508 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
509 len -= ETHER_CRC_LEN;
510 if (actlen < (int)(len + sizeof(pkt))) {
511 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
515 uether_rxbuf(ue, pc, sizeof(pkt), len);
519 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
520 usbd_transfer_submit(xfer);
525 DPRINTF("bulk read error, %s\n",
528 if (error != USB_ERR_CANCELLED) {
529 /* try to clear stall first */
530 usbd_xfer_set_stall(xfer);
538 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
540 struct ure_softc *sc = usbd_xfer_softc(xfer);
541 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
542 struct usb_page_cache *pc;
544 struct ure_txpkt txpkt;
547 switch (USB_GET_STATE(xfer)) {
548 case USB_ST_TRANSFERRED:
549 DPRINTFN(11, "transfer complete\n");
550 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
554 if ((sc->sc_flags & URE_FLAG_LINK) == 0 ||
555 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
557 * don't send anything if there is no link !
561 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
565 len = m->m_pkthdr.len;
566 pc = usbd_xfer_get_frame(xfer, 0);
567 memset(&txpkt, 0, sizeof(txpkt));
568 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
569 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
570 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
571 pos += sizeof(txpkt);
572 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
573 pos += m->m_pkthdr.len;
575 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
578 * If there's a BPF listener, bounce a copy
579 * of this frame to him.
585 /* Set frame length. */
586 usbd_xfer_set_frame_len(xfer, 0, pos);
588 usbd_transfer_submit(xfer);
589 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
592 DPRINTFN(11, "transfer error, %s\n",
595 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
596 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
598 if (error != USB_ERR_CANCELLED) {
599 /* try to clear stall first */
600 usbd_xfer_set_stall(xfer);
608 ure_read_chipver(struct ure_softc *sc)
612 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
615 sc->sc_chip |= URE_CHIP_VER_4C00;
618 sc->sc_chip |= URE_CHIP_VER_4C10;
621 device_printf(sc->sc_ue.ue_dev,
622 "unknown version 0x%04x\n", ver);
628 ure_attach_post(struct usb_ether *ue)
630 struct ure_softc *sc = uether_getsc(ue);
634 /* Determine the chip version. */
635 ure_read_chipver(sc);
637 /* Initialize controller and get station address. */
638 ure_rtl8152_init(sc);
640 if (sc->sc_chip & URE_CHIP_VER_4C00)
641 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
644 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
649 ure_attach_post_sub(struct usb_ether *ue)
651 struct ure_softc *sc;
655 sc = uether_getsc(ue);
657 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
658 ifp->if_start = uether_start;
659 ifp->if_ioctl = ure_ioctl;
660 ifp->if_init = uether_init;
661 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
662 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
663 IFQ_SET_READY(&ifp->if_snd);
666 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
667 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
668 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
675 ure_init(struct usb_ether *ue)
677 struct ure_softc *sc = uether_getsc(ue);
678 struct ifnet *ifp = uether_getifp(ue);
681 URE_LOCK_ASSERT(sc, MA_OWNED);
683 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
686 /* Cancel pending I/O. */
691 /* Set MAC address. */
692 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
695 /* Reset the packet filter. */
696 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
697 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) &
698 ~URE_FMC_FCR_MCU_EN);
699 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
700 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) |
703 /* Enable transmit and receive. */
704 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA,
705 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE |
708 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
709 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) &
713 rxmode = URE_RCR_APM;
715 /* If we want promiscuous mode, set the allframes bit. */
716 if (ifp->if_flags & IFF_PROMISC)
717 rxmode |= URE_RCR_AAP;
719 if (ifp->if_flags & IFF_BROADCAST)
720 rxmode |= URE_RCR_AB;
722 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
724 /* Load the multicast filter. */
727 usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]);
729 /* Indicate we are up and running. */
730 ifp->if_drv_flags |= IFF_DRV_RUNNING;
732 /* Switch to selected media. */
733 ure_ifmedia_upd(ifp);
737 ure_tick(struct usb_ether *ue)
739 struct ure_softc *sc = uether_getsc(ue);
740 struct mii_data *mii = GET_MII(sc);
742 URE_LOCK_ASSERT(sc, MA_OWNED);
745 if ((sc->sc_flags & URE_FLAG_LINK) == 0
746 && mii->mii_media_status & IFM_ACTIVE &&
747 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
748 sc->sc_flags |= URE_FLAG_LINK;
754 ure_setpromisc(struct usb_ether *ue)
756 struct ure_softc *sc = uether_getsc(ue);
757 struct ifnet *ifp = uether_getifp(ue);
760 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA);
762 if (ifp->if_flags & IFF_PROMISC)
763 rxmode |= URE_RCR_AAP;
765 rxmode &= ~URE_RCR_AAP;
767 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
773 * Program the 64-bit multicast hash filter.
776 ure_setmulti(struct usb_ether *ue)
778 struct ure_softc *sc = uether_getsc(ue);
779 struct ifnet *ifp = uether_getifp(ue);
780 struct ifmultiaddr *ifma;
782 uint32_t hashes[2] = { 0, 0 };
784 URE_LOCK_ASSERT(sc, MA_OWNED);
786 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA);
787 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
788 if (ifp->if_flags & IFF_PROMISC)
789 rxmode |= URE_RCR_AAP;
790 rxmode |= URE_RCR_AM;
791 hashes[0] = hashes[1] = 0xffffffff;
796 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
797 if (ifma->ifma_addr->sa_family != AF_LINK)
799 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
800 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
802 hashes[0] |= (1 << h);
804 hashes[1] |= (1 << (h - 32));
806 if_maddr_runlock(ifp);
808 h = bswap32(hashes[0]);
809 hashes[0] = bswap32(hashes[1]);
811 rxmode |= URE_RCR_AM;
814 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
815 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
816 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
820 ure_start(struct usb_ether *ue)
822 struct ure_softc *sc = uether_getsc(ue);
825 * start the USB transfers, if not already started:
827 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]);
828 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]);
832 ure_reset(struct ure_softc *sc)
836 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
838 for (i = 0; i < URE_TIMEOUT; i++) {
839 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
842 uether_pause(&sc->sc_ue, hz / 100);
844 if (i == URE_TIMEOUT)
845 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
852 ure_ifmedia_upd(struct ifnet *ifp)
854 struct ure_softc *sc = ifp->if_softc;
855 struct mii_data *mii = GET_MII(sc);
856 struct mii_softc *miisc;
859 URE_LOCK_ASSERT(sc, MA_OWNED);
861 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
863 error = mii_mediachg(mii);
868 * Report current media status.
871 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
873 struct ure_softc *sc;
874 struct mii_data *mii;
881 ifmr->ifm_active = mii->mii_media_active;
882 ifmr->ifm_status = mii->mii_media_status;
887 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
889 struct usb_ether *ue = ifp->if_softc;
890 struct ure_softc *sc;
892 int error, mask, reinit;
894 sc = uether_getsc(ue);
895 ifr = (struct ifreq *)data;
898 if (cmd == SIOCSIFCAP) {
900 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
901 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
902 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
909 error = uether_ioctl(ifp, cmd, data);
915 ure_rtl8152_init(struct ure_softc *sc)
920 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
922 uether_pause(&sc->sc_ue, hz / 50);
924 if (sc->sc_chip & URE_CHIP_VER_4C00) {
925 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
926 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
930 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB,
931 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) &
933 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB,
934 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) &
935 ~URE_RESUME_INDICATE);
937 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
938 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
939 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
940 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
941 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
942 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
943 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
944 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
945 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
946 URE_SPDWN_LINKCHG_MSK);
948 /* Disable Rx aggregation. */
949 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
950 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
954 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
956 uether_pause(&sc->sc_ue, hz / 50);
960 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
961 URE_TX_AGG_MAX_THRESHOLD);
962 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
963 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
964 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
968 ure_stop(struct usb_ether *ue)
970 struct ure_softc *sc = uether_getsc(ue);
971 struct ifnet *ifp = uether_getifp(ue);
973 URE_LOCK_ASSERT(sc, MA_OWNED);
975 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
976 sc->sc_flags &= ~URE_FLAG_LINK;
979 * stop all the transfers, if not already stopped:
981 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]);
982 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]);
986 ure_disable_teredo(struct ure_softc *sc)
989 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
990 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) &
991 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
992 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA,
994 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
995 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
999 ure_init_fifo(struct ure_softc *sc)
1001 uint32_t rx_fifo1, rx_fifo2;
1004 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
1005 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) |
1008 ure_disable_teredo(sc);
1010 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA,
1011 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) &
1016 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
1018 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA,
1019 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1022 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1023 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) &
1025 for (i = 0; i < URE_TIMEOUT; i++) {
1026 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1027 URE_LINK_LIST_READY)
1029 uether_pause(&sc->sc_ue, hz / 100);
1031 if (i == URE_TIMEOUT)
1032 device_printf(sc->sc_ue.ue_dev,
1033 "timeout waiting for OOB control\n");
1034 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1035 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) |
1037 for (i = 0; i < URE_TIMEOUT; i++) {
1038 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1039 URE_LINK_LIST_READY)
1041 uether_pause(&sc->sc_ue, hz / 100);
1043 if (i == URE_TIMEOUT)
1044 device_printf(sc->sc_ue.ue_dev,
1045 "timeout waiting for OOB control\n");
1047 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA,
1048 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) &
1050 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,
1051 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) |
1052 URE_TCR0_AUTO_FIFO);
1054 /* Configure Rx FIFO threshold. */
1055 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
1056 URE_RXFIFO_THR1_NORMAL);
1057 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
1058 rx_fifo1 = URE_RXFIFO_THR2_FULL;
1059 rx_fifo2 = URE_RXFIFO_THR3_FULL;
1061 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
1062 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
1064 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
1065 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
1067 /* Configure Tx FIFO threshold. */
1068 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
1069 URE_TXFIFO_THR_NORMAL);