2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/condvar.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/socket.h>
39 #include <sys/sysctl.h>
40 #include <sys/unistd.h>
43 #include <net/if_var.h>
44 #include <net/if_media.h>
46 #include <dev/mii/mii.h>
47 #include <dev/mii/miivar.h>
49 #include <dev/usb/usb.h>
50 #include <dev/usb/usbdi.h>
51 #include <dev/usb/usbdi_util.h>
54 #define USB_DEBUG_VAR ure_debug
55 #include <dev/usb/usb_debug.h>
56 #include <dev/usb/usb_process.h>
58 #include <dev/usb/net/usb_ethernet.h>
59 #include <dev/usb/net/if_urereg.h>
61 #include "miibus_if.h"
64 static int ure_debug = 0;
66 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
68 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
73 * Various supported device vendors/products.
75 static const STRUCT_USB_HOST_ID ure_devs[] = {
76 #define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
77 URE_DEV(LENOVO, RTL8153, 0),
78 URE_DEV(LENOVO, TBT3LAN, 0),
79 URE_DEV(LENOVO, ONELINK, 0),
80 URE_DEV(LENOVO, USBCLAN, 0),
81 URE_DEV(NVIDIA, RTL8153, 0),
82 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
83 URE_DEV(REALTEK, RTL8153, 0),
84 URE_DEV(TPLINK, RTL8153, 0),
88 static device_probe_t ure_probe;
89 static device_attach_t ure_attach;
90 static device_detach_t ure_detach;
92 static usb_callback_t ure_bulk_read_callback;
93 static usb_callback_t ure_bulk_write_callback;
95 static miibus_readreg_t ure_miibus_readreg;
96 static miibus_writereg_t ure_miibus_writereg;
97 static miibus_statchg_t ure_miibus_statchg;
99 static uether_fn_t ure_attach_post;
100 static uether_fn_t ure_init;
101 static uether_fn_t ure_stop;
102 static uether_fn_t ure_start;
103 static uether_fn_t ure_tick;
104 static uether_fn_t ure_rxfilter;
106 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
108 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
110 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
112 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t);
113 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
114 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
115 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
116 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
117 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
118 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
119 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
121 static void ure_read_chipver(struct ure_softc *);
122 static int ure_attach_post_sub(struct usb_ether *);
123 static void ure_reset(struct ure_softc *);
124 static int ure_ifmedia_upd(struct ifnet *);
125 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *);
126 static int ure_ioctl(struct ifnet *, u_long, caddr_t);
127 static void ure_rtl8152_init(struct ure_softc *);
128 static void ure_rtl8153_init(struct ure_softc *);
129 static void ure_disable_teredo(struct ure_softc *);
130 static void ure_init_fifo(struct ure_softc *);
132 static const struct usb_config ure_config[URE_N_TRANSFER] = {
135 .endpoint = UE_ADDR_ANY,
136 .direction = UE_DIR_OUT,
138 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
139 .callback = ure_bulk_write_callback,
140 .timeout = 10000, /* 10 seconds */
144 .endpoint = UE_ADDR_ANY,
145 .direction = UE_DIR_IN,
147 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
148 .callback = ure_bulk_read_callback,
149 .timeout = 0, /* no timeout */
153 static device_method_t ure_methods[] = {
154 /* Device interface. */
155 DEVMETHOD(device_probe, ure_probe),
156 DEVMETHOD(device_attach, ure_attach),
157 DEVMETHOD(device_detach, ure_detach),
160 DEVMETHOD(miibus_readreg, ure_miibus_readreg),
161 DEVMETHOD(miibus_writereg, ure_miibus_writereg),
162 DEVMETHOD(miibus_statchg, ure_miibus_statchg),
167 static driver_t ure_driver = {
169 .methods = ure_methods,
170 .size = sizeof(struct ure_softc),
173 static devclass_t ure_devclass;
175 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL);
176 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL);
177 MODULE_DEPEND(ure, uether, 1, 1, 1);
178 MODULE_DEPEND(ure, usb, 1, 1, 1);
179 MODULE_DEPEND(ure, ether, 1, 1, 1);
180 MODULE_DEPEND(ure, miibus, 1, 1, 1);
181 MODULE_VERSION(ure, 1);
182 USB_PNP_HOST_INFO(ure_devs);
184 static const struct usb_ether_methods ure_ue_methods = {
185 .ue_attach_post = ure_attach_post,
186 .ue_attach_post_sub = ure_attach_post_sub,
187 .ue_start = ure_start,
191 .ue_setmulti = ure_rxfilter,
192 .ue_setpromisc = ure_rxfilter,
193 .ue_mii_upd = ure_ifmedia_upd,
194 .ue_mii_sts = ure_ifmedia_sts,
198 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
201 struct usb_device_request req;
203 URE_LOCK_ASSERT(sc, MA_OWNED);
205 if (rw == URE_CTL_WRITE)
206 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
208 req.bmRequestType = UT_READ_VENDOR_DEVICE;
209 req.bRequest = UR_SET_ADDRESS;
210 USETW(req.wValue, val);
211 USETW(req.wIndex, index);
212 USETW(req.wLength, len);
214 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
218 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
222 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
226 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
230 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
234 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
240 shift = (reg & 3) << 3;
243 ure_read_mem(sc, reg, index, &temp, 4);
251 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
257 shift = (reg & 2) << 3;
260 ure_read_mem(sc, reg, index, &temp, 4);
264 return (val & 0xffff);
268 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
272 ure_read_mem(sc, reg, index, &temp, 4);
273 return (UGETDW(temp));
277 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
283 byen = URE_BYTE_EN_BYTE;
289 val <<= (shift << 3);
294 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
298 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
304 byen = URE_BYTE_EN_WORD;
310 val <<= (shift << 3);
315 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
319 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
324 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
328 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
332 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
333 reg = (addr & 0x0fff) | 0xb000;
335 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
339 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
343 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
344 reg = (addr & 0x0fff) | 0xb000;
346 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
350 ure_miibus_readreg(device_t dev, int phy, int reg)
352 struct ure_softc *sc;
356 sc = device_get_softc(dev);
357 locked = mtx_owned(&sc->sc_mtx);
361 /* Let the rgephy driver read the URE_GMEDIASTAT register. */
362 if (reg == URE_GMEDIASTAT) {
365 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
368 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
376 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
378 struct ure_softc *sc;
381 sc = device_get_softc(dev);
382 if (sc->sc_phyno != phy)
385 locked = mtx_owned(&sc->sc_mtx);
389 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
397 ure_miibus_statchg(device_t dev)
399 struct ure_softc *sc;
400 struct mii_data *mii;
404 sc = device_get_softc(dev);
406 locked = mtx_owned(&sc->sc_mtx);
410 ifp = uether_getifp(&sc->sc_ue);
411 if (mii == NULL || ifp == NULL ||
412 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
415 sc->sc_flags &= ~URE_FLAG_LINK;
416 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
417 (IFM_ACTIVE | IFM_AVALID)) {
418 switch (IFM_SUBTYPE(mii->mii_media_active)) {
421 sc->sc_flags |= URE_FLAG_LINK;
424 if ((sc->sc_flags & URE_FLAG_8152) != 0)
426 sc->sc_flags |= URE_FLAG_LINK;
433 /* Lost link, do nothing. */
434 if ((sc->sc_flags & URE_FLAG_LINK) == 0)
442 * Probe for a RTL8152/RTL8153 chip.
445 ure_probe(device_t dev)
447 struct usb_attach_arg *uaa;
449 uaa = device_get_ivars(dev);
450 if (uaa->usb_mode != USB_MODE_HOST)
452 if (uaa->info.bConfigIndex != URE_CONFIG_IDX)
454 if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
457 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
461 * Attach the interface. Allocate softc structures, do ifmedia
462 * setup and ethernet/BPF attach.
465 ure_attach(device_t dev)
467 struct usb_attach_arg *uaa = device_get_ivars(dev);
468 struct ure_softc *sc = device_get_softc(dev);
469 struct usb_ether *ue = &sc->sc_ue;
473 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
474 device_set_usb_desc(dev);
475 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
477 iface_index = URE_IFACE_IDX;
478 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
479 ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx);
481 device_printf(dev, "allocating USB transfers failed\n");
487 ue->ue_udev = uaa->device;
488 ue->ue_mtx = &sc->sc_mtx;
489 ue->ue_methods = &ure_ue_methods;
491 error = uether_ifattach(ue);
493 device_printf(dev, "could not attach interface\n");
496 return (0); /* success */
500 return (ENXIO); /* failure */
504 ure_detach(device_t dev)
506 struct ure_softc *sc = device_get_softc(dev);
507 struct usb_ether *ue = &sc->sc_ue;
509 usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER);
511 mtx_destroy(&sc->sc_mtx);
517 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
519 struct ure_softc *sc = usbd_xfer_softc(xfer);
520 struct usb_ether *ue = &sc->sc_ue;
521 struct ifnet *ifp = uether_getifp(ue);
522 struct usb_page_cache *pc;
523 struct ure_rxpkt pkt;
526 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
528 switch (USB_GET_STATE(xfer)) {
529 case USB_ST_TRANSFERRED:
530 if (actlen < (int)(sizeof(pkt))) {
531 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
534 pc = usbd_xfer_get_frame(xfer, 0);
535 usbd_copy_out(pc, 0, &pkt, sizeof(pkt));
536 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
537 len -= ETHER_CRC_LEN;
538 if (actlen < (int)(len + sizeof(pkt))) {
539 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
543 uether_rxbuf(ue, pc, sizeof(pkt), len);
547 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
548 usbd_transfer_submit(xfer);
553 DPRINTF("bulk read error, %s\n",
556 if (error != USB_ERR_CANCELLED) {
557 /* try to clear stall first */
558 usbd_xfer_set_stall(xfer);
566 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
568 struct ure_softc *sc = usbd_xfer_softc(xfer);
569 struct ifnet *ifp = uether_getifp(&sc->sc_ue);
570 struct usb_page_cache *pc;
572 struct ure_txpkt txpkt;
575 switch (USB_GET_STATE(xfer)) {
576 case USB_ST_TRANSFERRED:
577 DPRINTFN(11, "transfer complete\n");
578 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
582 if ((sc->sc_flags & URE_FLAG_LINK) == 0 ||
583 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
585 * don't send anything if there is no link !
589 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
593 len = m->m_pkthdr.len;
594 pc = usbd_xfer_get_frame(xfer, 0);
595 memset(&txpkt, 0, sizeof(txpkt));
596 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
597 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
598 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
599 pos += sizeof(txpkt);
600 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
601 pos += m->m_pkthdr.len;
603 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
606 * If there's a BPF listener, bounce a copy
607 * of this frame to him.
613 /* Set frame length. */
614 usbd_xfer_set_frame_len(xfer, 0, pos);
616 usbd_transfer_submit(xfer);
617 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
620 DPRINTFN(11, "transfer error, %s\n",
623 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
624 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
626 if (error != USB_ERR_CANCELLED) {
627 /* try to clear stall first */
628 usbd_xfer_set_stall(xfer);
636 ure_read_chipver(struct ure_softc *sc)
640 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
643 sc->sc_chip |= URE_CHIP_VER_4C00;
646 sc->sc_chip |= URE_CHIP_VER_4C10;
649 sc->sc_chip |= URE_CHIP_VER_5C00;
652 sc->sc_chip |= URE_CHIP_VER_5C10;
655 sc->sc_chip |= URE_CHIP_VER_5C20;
658 sc->sc_chip |= URE_CHIP_VER_5C30;
661 device_printf(sc->sc_ue.ue_dev,
662 "unknown version 0x%04x\n", ver);
668 ure_attach_post(struct usb_ether *ue)
670 struct ure_softc *sc = uether_getsc(ue);
674 /* Determine the chip version. */
675 ure_read_chipver(sc);
677 /* Initialize controller and get station address. */
678 if (sc->sc_flags & URE_FLAG_8152)
679 ure_rtl8152_init(sc);
681 ure_rtl8153_init(sc);
683 if ((sc->sc_chip & URE_CHIP_VER_4C00) ||
684 (sc->sc_chip & URE_CHIP_VER_4C10))
685 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
688 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
691 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) {
692 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n");
693 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0);
694 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */
695 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */
700 ure_attach_post_sub(struct usb_ether *ue)
702 struct ure_softc *sc;
706 sc = uether_getsc(ue);
708 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
709 ifp->if_start = uether_start;
710 ifp->if_ioctl = ure_ioctl;
711 ifp->if_init = uether_init;
712 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
713 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
714 IFQ_SET_READY(&ifp->if_snd);
717 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
718 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
719 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
726 ure_init(struct usb_ether *ue)
728 struct ure_softc *sc = uether_getsc(ue);
729 struct ifnet *ifp = uether_getifp(ue);
731 URE_LOCK_ASSERT(sc, MA_OWNED);
733 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
736 /* Cancel pending I/O. */
741 /* Set MAC address. */
742 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
743 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
745 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
747 /* Reset the packet filter. */
748 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
749 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) &
750 ~URE_FMC_FCR_MCU_EN);
751 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
752 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) |
755 /* Enable transmit and receive. */
756 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA,
757 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE |
760 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
761 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) &
764 /* Configure RX filters. */
767 usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]);
769 /* Indicate we are up and running. */
770 ifp->if_drv_flags |= IFF_DRV_RUNNING;
772 /* Switch to selected media. */
773 ure_ifmedia_upd(ifp);
777 ure_tick(struct usb_ether *ue)
779 struct ure_softc *sc = uether_getsc(ue);
780 struct mii_data *mii = GET_MII(sc);
782 URE_LOCK_ASSERT(sc, MA_OWNED);
785 if ((sc->sc_flags & URE_FLAG_LINK) == 0
786 && mii->mii_media_status & IFM_ACTIVE &&
787 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
788 sc->sc_flags |= URE_FLAG_LINK;
794 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
796 uint32_t h, *hashes = arg;
798 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
800 hashes[0] |= (1 << h);
802 hashes[1] |= (1 << (h - 32));
807 * Program the 64-bit multicast hash filter.
810 ure_rxfilter(struct usb_ether *ue)
812 struct ure_softc *sc = uether_getsc(ue);
813 struct ifnet *ifp = uether_getifp(ue);
815 uint32_t h, hashes[2] = { 0, 0 };
817 URE_LOCK_ASSERT(sc, MA_OWNED);
819 rxmode = URE_RCR_APM;
820 if (ifp->if_flags & IFF_BROADCAST)
821 rxmode |= URE_RCR_AB;
822 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
823 if (ifp->if_flags & IFF_PROMISC)
824 rxmode |= URE_RCR_AAP;
825 rxmode |= URE_RCR_AM;
826 hashes[0] = hashes[1] = 0xffffffff;
830 rxmode |= URE_RCR_AM;
831 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes);
833 h = bswap32(hashes[0]);
834 hashes[0] = bswap32(hashes[1]);
836 rxmode |= URE_RCR_AM;
839 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
840 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
841 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
845 ure_start(struct usb_ether *ue)
847 struct ure_softc *sc = uether_getsc(ue);
850 * start the USB transfers, if not already started:
852 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]);
853 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]);
857 ure_reset(struct ure_softc *sc)
861 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
863 for (i = 0; i < URE_TIMEOUT; i++) {
864 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
867 uether_pause(&sc->sc_ue, hz / 100);
869 if (i == URE_TIMEOUT)
870 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
877 ure_ifmedia_upd(struct ifnet *ifp)
879 struct ure_softc *sc = ifp->if_softc;
880 struct mii_data *mii = GET_MII(sc);
881 struct mii_softc *miisc;
884 URE_LOCK_ASSERT(sc, MA_OWNED);
886 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
888 error = mii_mediachg(mii);
893 * Report current media status.
896 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
898 struct ure_softc *sc;
899 struct mii_data *mii;
906 ifmr->ifm_active = mii->mii_media_active;
907 ifmr->ifm_status = mii->mii_media_status;
912 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
914 struct usb_ether *ue = ifp->if_softc;
915 struct ure_softc *sc;
917 int error, mask, reinit;
919 sc = uether_getsc(ue);
920 ifr = (struct ifreq *)data;
923 if (cmd == SIOCSIFCAP) {
925 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
926 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
927 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
934 error = uether_ioctl(ifp, cmd, data);
940 ure_rtl8152_init(struct ure_softc *sc)
945 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
947 uether_pause(&sc->sc_ue, hz / 50);
949 if (sc->sc_chip & URE_CHIP_VER_4C00) {
950 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
951 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
955 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB,
956 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) &
958 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB,
959 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) &
960 ~URE_RESUME_INDICATE);
962 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
963 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
964 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
965 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
966 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
967 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
968 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
969 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
970 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
971 URE_SPDWN_LINKCHG_MSK);
973 /* Disable Rx aggregation. */
974 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
975 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
979 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
981 uether_pause(&sc->sc_ue, hz / 50);
985 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
986 URE_TX_AGG_MAX_THRESHOLD);
987 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
988 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
989 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
993 ure_rtl8153_init(struct ure_softc *sc)
1000 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1001 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
1002 uether_pause(&sc->sc_ue, hz / 50);
1004 memset(u1u2, 0x00, sizeof(u1u2));
1005 ure_write_mem(sc, URE_USB_TOLERANCE,
1006 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1008 for (i = 0; i < URE_TIMEOUT; i++) {
1009 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1012 uether_pause(&sc->sc_ue, hz / 100);
1014 if (i == URE_TIMEOUT)
1015 device_printf(sc->sc_ue.ue_dev,
1016 "timeout waiting for chip autoload\n");
1018 for (i = 0; i < URE_TIMEOUT; i++) {
1019 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
1021 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
1023 uether_pause(&sc->sc_ue, hz / 100);
1025 if (i == URE_TIMEOUT)
1026 device_printf(sc->sc_ue.ue_dev,
1027 "timeout waiting for phy to stabilize\n");
1029 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,
1030 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) &
1033 if (sc->sc_chip & URE_CHIP_VER_5C10) {
1034 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1035 val &= ~URE_PWD_DN_SCALE_MASK;
1036 val |= URE_PWD_DN_SCALE(96);
1037 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
1039 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB,
1040 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) |
1041 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1042 } else if (sc->sc_chip & URE_CHIP_VER_5C20) {
1043 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA,
1044 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) &
1047 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1048 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
1049 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
1051 val &= ~URE_DYNAMIC_BURST;
1053 val |= URE_DYNAMIC_BURST;
1054 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
1057 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB,
1058 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) |
1061 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB,
1062 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) &
1065 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
1066 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
1067 ~URE_LED_MODE_MASK);
1069 if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
1070 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
1071 val = URE_LPM_TIMER_500MS;
1073 val = URE_LPM_TIMER_500US;
1074 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1075 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
1077 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1078 val &= ~URE_SEN_VAL_MASK;
1079 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1080 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
1082 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1084 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,
1085 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) &
1086 ~(URE_PWR_EN | URE_PHASE2_EN));
1087 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB,
1088 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) &
1091 memset(u1u2, 0xff, sizeof(u1u2));
1092 ure_write_mem(sc, URE_USB_TOLERANCE,
1093 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1095 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
1096 URE_ALDPS_SPDWN_RATIO);
1097 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1098 URE_EEE_SPDWN_RATIO);
1099 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1100 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
1101 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
1102 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
1103 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
1104 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
1107 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1108 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1109 val |= URE_U2P3_ENABLE;
1111 val &= ~URE_U2P3_ENABLE;
1112 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1114 memset(u1u2, 0x00, sizeof(u1u2));
1115 ure_write_mem(sc, URE_USB_TOLERANCE,
1116 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1118 /* Disable ALDPS. */
1119 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1120 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
1121 uether_pause(&sc->sc_ue, hz / 50);
1125 /* Disable Rx aggregation. */
1126 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
1127 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
1128 URE_RX_AGG_DISABLE);
1130 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1131 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1132 val |= URE_U2P3_ENABLE;
1134 val &= ~URE_U2P3_ENABLE;
1135 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1137 memset(u1u2, 0xff, sizeof(u1u2));
1138 ure_write_mem(sc, URE_USB_TOLERANCE,
1139 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1143 ure_stop(struct usb_ether *ue)
1145 struct ure_softc *sc = uether_getsc(ue);
1146 struct ifnet *ifp = uether_getifp(ue);
1148 URE_LOCK_ASSERT(sc, MA_OWNED);
1150 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1151 sc->sc_flags &= ~URE_FLAG_LINK;
1154 * stop all the transfers, if not already stopped:
1156 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]);
1157 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]);
1161 ure_disable_teredo(struct ure_softc *sc)
1164 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
1165 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) &
1166 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
1167 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA,
1169 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
1170 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
1174 ure_init_fifo(struct ure_softc *sc)
1176 uint32_t rx_fifo1, rx_fifo2;
1179 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
1180 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) |
1183 ure_disable_teredo(sc);
1185 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA,
1186 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) &
1189 if (!(sc->sc_flags & URE_FLAG_8152)) {
1190 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1191 URE_CHIP_VER_5C20)) {
1192 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
1193 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1195 if (sc->sc_chip & URE_CHIP_VER_5C00) {
1196 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
1197 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
1198 ~URE_CTAP_SHORT_EN);
1200 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1201 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1203 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
1204 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
1206 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1207 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1209 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE);
1210 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13);
1211 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
1212 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
1213 URE_PFM_PWM_SWITCH);
1215 /* Enable LPF corner auto tune. */
1216 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG);
1217 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f);
1219 /* Adjust 10M amplitude. */
1220 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1);
1221 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af);
1222 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2);
1223 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208);
1228 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
1230 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA,
1231 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1234 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1235 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) &
1237 for (i = 0; i < URE_TIMEOUT; i++) {
1238 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1239 URE_LINK_LIST_READY)
1241 uether_pause(&sc->sc_ue, hz / 100);
1243 if (i == URE_TIMEOUT)
1244 device_printf(sc->sc_ue.ue_dev,
1245 "timeout waiting for OOB control\n");
1246 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1247 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) |
1249 for (i = 0; i < URE_TIMEOUT; i++) {
1250 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1251 URE_LINK_LIST_READY)
1253 uether_pause(&sc->sc_ue, hz / 100);
1255 if (i == URE_TIMEOUT)
1256 device_printf(sc->sc_ue.ue_dev,
1257 "timeout waiting for OOB control\n");
1259 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA,
1260 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) &
1262 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,
1263 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) |
1264 URE_TCR0_AUTO_FIFO);
1266 /* Configure Rx FIFO threshold. */
1267 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
1268 URE_RXFIFO_THR1_NORMAL);
1269 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
1270 rx_fifo1 = URE_RXFIFO_THR2_FULL;
1271 rx_fifo2 = URE_RXFIFO_THR3_FULL;
1273 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
1274 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
1276 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
1277 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
1279 /* Configure Tx FIFO threshold. */
1280 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
1281 URE_TXFIFO_THR_NORMAL);