sys/dev/usb/net/if_ure.c

   1 /*-
   2  * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/condvar.h>
  34 #include <sys/kernel.h>
  35 #include <sys/lock.h>
  36 #include <sys/module.h>
  37 #include <sys/mutex.h>
  38 #include <sys/socket.h>
  39 #include <sys/sysctl.h>
  40 #include <sys/unistd.h>
  41
  42 #include <net/if.h>
  43 #include <net/if_var.h>
  44
  45 #include <dev/usb/usb.h>
  46 #include <dev/usb/usbdi.h>
  47 #include <dev/usb/usbdi_util.h>
  48 #include "usbdevs.h"
  49
  50 #define USB_DEBUG_VAR   ure_debug
  51 #include <dev/usb/usb_debug.h>
  52 #include <dev/usb/usb_process.h>
  53
  54 #include <dev/usb/net/usb_ethernet.h>
  55 #include <dev/usb/net/if_urereg.h>
  56
  57 #ifdef USB_DEBUG
  58 static int ure_debug = 0;
  59
  60 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure");
  61 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
  62     "Debug level");
  63 #endif
  64
  65 /*
  66  * Various supported device vendors/products.
  67  */
  68 static const STRUCT_USB_HOST_ID ure_devs[] = {
  69 #define URE_DEV(v,p,i)  { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
  70         URE_DEV(LENOVO, RTL8153, 0),
  71         URE_DEV(NVIDIA, RTL8153, 0),
  72         URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
  73         URE_DEV(REALTEK, RTL8153, 0),
  74         URE_DEV(TPLINK, RTL8153, 0),
  75 #undef URE_DEV
  76 };
  77
  78 static device_probe_t ure_probe;
  79 static device_attach_t ure_attach;
  80 static device_detach_t ure_detach;
  81
  82 static usb_callback_t ure_bulk_read_callback;
  83 static usb_callback_t ure_bulk_write_callback;
  84
  85 static miibus_readreg_t ure_miibus_readreg;
  86 static miibus_writereg_t ure_miibus_writereg;
  87 static miibus_statchg_t ure_miibus_statchg;
  88
  89 static uether_fn_t ure_attach_post;
  90 static uether_fn_t ure_init;
  91 static uether_fn_t ure_stop;
  92 static uether_fn_t ure_start;
  93 static uether_fn_t ure_tick;
  94 static uether_fn_t ure_rxfilter;
  95
  96 static int      ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
  97                     void *, int);
  98 static int      ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
  99                     int);
 100 static int      ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
 101                     int);
 102 static uint8_t  ure_read_1(struct ure_softc *, uint16_t, uint16_t);
 103 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
 104 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
 105 static int      ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
 106 static int      ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
 107 static int      ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
 108 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
 109 static void     ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
 110
 111 static void     ure_read_chipver(struct ure_softc *);
 112 static int      ure_attach_post_sub(struct usb_ether *);
 113 static void     ure_reset(struct ure_softc *);
 114 static int      ure_ifmedia_upd(struct ifnet *);
 115 static void     ure_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 116 static int      ure_ioctl(struct ifnet *, u_long, caddr_t);
 117 static void     ure_rtl8152_init(struct ure_softc *);
 118 static void     ure_rtl8153_init(struct ure_softc *);
 119 static void     ure_disable_teredo(struct ure_softc *);
 120 static void     ure_init_fifo(struct ure_softc *);
 121
 122 static const struct usb_config ure_config[URE_N_TRANSFER] = {
 123         [URE_BULK_DT_WR] = {
 124                 .type = UE_BULK,
 125                 .endpoint = UE_ADDR_ANY,
 126                 .direction = UE_DIR_OUT,
 127                 .bufsize = MCLBYTES,
 128                 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
 129                 .callback = ure_bulk_write_callback,
 130                 .timeout = 10000,       /* 10 seconds */
 131         },
 132         [URE_BULK_DT_RD] = {
 133                 .type = UE_BULK,
 134                 .endpoint = UE_ADDR_ANY,
 135                 .direction = UE_DIR_IN,
 136                 .bufsize = 16384,
 137                 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
 138                 .callback = ure_bulk_read_callback,
 139                 .timeout = 0,   /* no timeout */
 140         },
 141 };
 142
 143 static device_method_t ure_methods[] = {
 144         /* Device interface. */
 145         DEVMETHOD(device_probe, ure_probe),
 146         DEVMETHOD(device_attach, ure_attach),
 147         DEVMETHOD(device_detach, ure_detach),
 148
 149         /* MII interface. */
 150         DEVMETHOD(miibus_readreg, ure_miibus_readreg),
 151         DEVMETHOD(miibus_writereg, ure_miibus_writereg),
 152         DEVMETHOD(miibus_statchg, ure_miibus_statchg),
 153
 154         DEVMETHOD_END
 155 };
 156
 157 static driver_t ure_driver = {
 158         .name = "ure",
 159         .methods = ure_methods,
 160         .size = sizeof(struct ure_softc),
 161 };
 162
 163 static devclass_t ure_devclass;
 164
 165 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL);
 166 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL);
 167 MODULE_DEPEND(ure, uether, 1, 1, 1);
 168 MODULE_DEPEND(ure, usb, 1, 1, 1);
 169 MODULE_DEPEND(ure, ether, 1, 1, 1);
 170 MODULE_DEPEND(ure, miibus, 1, 1, 1);
 171 MODULE_VERSION(ure, 1);
 172
 173 static const struct usb_ether_methods ure_ue_methods = {
 174         .ue_attach_post = ure_attach_post,
 175         .ue_attach_post_sub = ure_attach_post_sub,
 176         .ue_start = ure_start,
 177         .ue_init = ure_init,
 178         .ue_stop = ure_stop,
 179         .ue_tick = ure_tick,
 180         .ue_setmulti = ure_rxfilter,
 181         .ue_setpromisc = ure_rxfilter,
 182         .ue_mii_upd = ure_ifmedia_upd,
 183         .ue_mii_sts = ure_ifmedia_sts,
 184 };
 185
 186 static int
 187 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
 188     void *buf, int len)
 189 {
 190         struct usb_device_request req;
 191
 192         URE_LOCK_ASSERT(sc, MA_OWNED);
 193
 194         if (rw == URE_CTL_WRITE)
 195                 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
 196         else
 197                 req.bmRequestType = UT_READ_VENDOR_DEVICE;
 198         req.bRequest = UR_SET_ADDRESS;
 199         USETW(req.wValue, val);
 200         USETW(req.wIndex, index);
 201         USETW(req.wLength, len);
 202
 203         return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
 204 }
 205
 206 static int
 207 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
 208     void *buf, int len)
 209 {
 210
 211         return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
 212 }
 213
 214 static int
 215 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
 216     void *buf, int len)
 217 {
 218
 219         return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
 220 }
 221
 222 static uint8_t
 223 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
 224 {
 225         uint32_t val;
 226         uint8_t temp[4];
 227         uint8_t shift;
 228
 229         shift = (reg & 3) << 3;
 230         reg &= ~3;
 231
 232         ure_read_mem(sc, reg, index, &temp, 4);
 233         val = UGETDW(temp);
 234         val >>= shift;
 235
 236         return (val & 0xff);
 237 }
 238
 239 static uint16_t
 240 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
 241 {
 242         uint32_t val;
 243         uint8_t temp[4];
 244         uint8_t shift;
 245
 246         shift = (reg & 2) << 3;
 247         reg &= ~3;
 248
 249         ure_read_mem(sc, reg, index, &temp, 4);
 250         val = UGETDW(temp);
 251         val >>= shift;
 252
 253         return (val & 0xffff);
 254 }
 255
 256 static uint32_t
 257 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
 258 {
 259         uint8_t temp[4];
 260
 261         ure_read_mem(sc, reg, index, &temp, 4);
 262         return (UGETDW(temp));
 263 }
 264
 265 static int
 266 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
 267 {
 268         uint16_t byen;
 269         uint8_t temp[4];
 270         uint8_t shift;
 271
 272         byen = URE_BYTE_EN_BYTE;
 273         shift = reg & 3;
 274         val &= 0xff;
 275
 276         if (reg & 3) {
 277                 byen <<= shift;
 278                 val <<= (shift << 3);
 279                 reg &= ~3;
 280         }
 281
 282         USETDW(temp, val);
 283         return (ure_write_mem(sc, reg, index | byen, &temp, 4));
 284 }
 285
 286 static int
 287 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
 288 {
 289         uint16_t byen;
 290         uint8_t temp[4];
 291         uint8_t shift;
 292
 293         byen = URE_BYTE_EN_WORD;
 294         shift = reg & 2;
 295         val &= 0xffff;
 296
 297         if (reg & 2) {
 298                 byen <<= shift;
 299                 val <<= (shift << 3);
 300                 reg &= ~3;
 301         }
 302
 303         USETDW(temp, val);
 304         return (ure_write_mem(sc, reg, index | byen, &temp, 4));
 305 }
 306
 307 static int
 308 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
 309 {
 310         uint8_t temp[4];
 311
 312         USETDW(temp, val);
 313         return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
 314 }
 315
 316 static uint16_t
 317 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
 318 {
 319         uint16_t reg;
 320
 321         ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
 322         reg = (addr & 0x0fff) | 0xb000;
 323
 324         return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
 325 }
 326
 327 static void
 328 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
 329 {
 330         uint16_t reg;
 331
 332         ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
 333         reg = (addr & 0x0fff) | 0xb000;
 334
 335         ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
 336 }
 337
 338 static int
 339 ure_miibus_readreg(device_t dev, int phy, int reg)
 340 {
 341         struct ure_softc *sc;
 342         uint16_t val;
 343         int locked;
 344
 345         sc = device_get_softc(dev);
 346         locked = mtx_owned(&sc->sc_mtx);
 347         if (!locked)
 348                 URE_LOCK(sc);
 349
 350         /* Let the rgephy driver read the URE_GMEDIASTAT register. */
 351         if (reg == URE_GMEDIASTAT) {
 352                 if (!locked)
 353                         URE_UNLOCK(sc);
 354                 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
 355         }
 356
 357         val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
 358
 359         if (!locked)
 360                 URE_UNLOCK(sc);
 361         return (val);
 362 }
 363
 364 static int
 365 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
 366 {
 367         struct ure_softc *sc;
 368         int locked;
 369
 370         sc = device_get_softc(dev);
 371         if (sc->sc_phyno != phy)
 372                 return (0);
 373
 374         locked = mtx_owned(&sc->sc_mtx);
 375         if (!locked)
 376                 URE_LOCK(sc);
 377
 378         ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
 379
 380         if (!locked)
 381                 URE_UNLOCK(sc);
 382         return (0);
 383 }
 384
 385 static void
 386 ure_miibus_statchg(device_t dev)
 387 {
 388         struct ure_softc *sc;
 389         struct mii_data *mii;
 390         struct ifnet *ifp;
 391         int locked;
 392
 393         sc = device_get_softc(dev);
 394         mii = GET_MII(sc);
 395         locked = mtx_owned(&sc->sc_mtx);
 396         if (!locked)
 397                 URE_LOCK(sc);
 398
 399         ifp = uether_getifp(&sc->sc_ue);
 400         if (mii == NULL || ifp == NULL ||
 401             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 402                 goto done;
 403
 404         sc->sc_flags &= ~URE_FLAG_LINK;
 405         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 406             (IFM_ACTIVE | IFM_AVALID)) {
 407                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 408                 case IFM_10_T:
 409                 case IFM_100_TX:
 410                         sc->sc_flags |= URE_FLAG_LINK;
 411                         break;
 412                 case IFM_1000_T:
 413                         if ((sc->sc_flags & URE_FLAG_8152) != 0)
 414                                 break;
 415                         sc->sc_flags |= URE_FLAG_LINK;
 416                         break;
 417                 default:
 418                         break;
 419                 }
 420         }
 421
 422         /* Lost link, do nothing. */
 423         if ((sc->sc_flags & URE_FLAG_LINK) == 0)
 424                 goto done;
 425 done:
 426         if (!locked)
 427                 URE_UNLOCK(sc);
 428 }
 429
 430 /*
 431  * Probe for a RTL8152/RTL8153 chip.
 432  */
 433 static int
 434 ure_probe(device_t dev)
 435 {
 436         struct usb_attach_arg *uaa;
 437
 438         uaa = device_get_ivars(dev);
 439         if (uaa->usb_mode != USB_MODE_HOST)
 440                 return (ENXIO);
 441         if (uaa->info.bConfigIndex != URE_CONFIG_IDX)
 442                 return (ENXIO);
 443         if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
 444                 return (ENXIO);
 445
 446         return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
 447 }
 448
 449 /*
 450  * Attach the interface. Allocate softc structures, do ifmedia
 451  * setup and ethernet/BPF attach.
 452  */
 453 static int
 454 ure_attach(device_t dev)
 455 {
 456         struct usb_attach_arg *uaa = device_get_ivars(dev);
 457         struct ure_softc *sc = device_get_softc(dev);
 458         struct usb_ether *ue = &sc->sc_ue;
 459         uint8_t iface_index;
 460         int error;
 461
 462         sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
 463         device_set_usb_desc(dev);
 464         mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
 465
 466         iface_index = URE_IFACE_IDX;
 467         error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
 468             ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx);
 469         if (error != 0) {
 470                 device_printf(dev, "allocating USB transfers failed\n");
 471                 goto detach;
 472         }
 473
 474         ue->ue_sc = sc;
 475         ue->ue_dev = dev;
 476         ue->ue_udev = uaa->device;
 477         ue->ue_mtx = &sc->sc_mtx;
 478         ue->ue_methods = &ure_ue_methods;
 479
 480         error = uether_ifattach(ue);
 481         if (error != 0) {
 482                 device_printf(dev, "could not attach interface\n");
 483                 goto detach;
 484         }
 485         return (0);                     /* success */
 486
 487 detach:
 488         ure_detach(dev);
 489         return (ENXIO);                 /* failure */
 490 }
 491
 492 static int
 493 ure_detach(device_t dev)
 494 {
 495         struct ure_softc *sc = device_get_softc(dev);
 496         struct usb_ether *ue = &sc->sc_ue;
 497
 498         usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER);
 499         uether_ifdetach(ue);
 500         mtx_destroy(&sc->sc_mtx);
 501
 502         return (0);
 503 }
 504
 505 static void
 506 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
 507 {
 508         struct ure_softc *sc = usbd_xfer_softc(xfer);
 509         struct usb_ether *ue = &sc->sc_ue;
 510         struct ifnet *ifp = uether_getifp(ue);
 511         struct usb_page_cache *pc;
 512         struct ure_rxpkt pkt;
 513         int actlen, len;
 514
 515         usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
 516
 517         switch (USB_GET_STATE(xfer)) {
 518         case USB_ST_TRANSFERRED:
 519                 if (actlen < (int)(sizeof(pkt))) {
 520                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 521                         goto tr_setup;
 522                 }
 523                 pc = usbd_xfer_get_frame(xfer, 0);
 524                 usbd_copy_out(pc, 0, &pkt, sizeof(pkt));
 525                 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
 526                 len -= ETHER_CRC_LEN;
 527                 if (actlen < (int)(len + sizeof(pkt))) {
 528                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 529                         goto tr_setup;
 530                 }
 531
 532                 uether_rxbuf(ue, pc, sizeof(pkt), len);
 533                 /* FALLTHROUGH */
 534         case USB_ST_SETUP:
 535 tr_setup:
 536                 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
 537                 usbd_transfer_submit(xfer);
 538                 uether_rxflush(ue);
 539                 return;
 540
 541         default:                        /* Error */
 542                 DPRINTF("bulk read error, %s\n",
 543                     usbd_errstr(error));
 544
 545                 if (error != USB_ERR_CANCELLED) {
 546                         /* try to clear stall first */
 547                         usbd_xfer_set_stall(xfer);
 548                         goto tr_setup;
 549                 }
 550                 return;
 551         }
 552 }
 553
 554 static void
 555 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
 556 {
 557         struct ure_softc *sc = usbd_xfer_softc(xfer);
 558         struct ifnet *ifp = uether_getifp(&sc->sc_ue);
 559         struct usb_page_cache *pc;
 560         struct mbuf *m;
 561         struct ure_txpkt txpkt;
 562         int len, pos;
 563
 564         switch (USB_GET_STATE(xfer)) {
 565         case USB_ST_TRANSFERRED:
 566                 DPRINTFN(11, "transfer complete\n");
 567                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 568                 /* FALLTHROUGH */
 569         case USB_ST_SETUP:
 570 tr_setup:
 571                 if ((sc->sc_flags & URE_FLAG_LINK) == 0 ||
 572                     (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
 573                         /*
 574                          * don't send anything if there is no link !
 575                          */
 576                         return;
 577                 }
 578                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
 579                 if (m == NULL)
 580                         break;
 581                 pos = 0;
 582                 len = m->m_pkthdr.len;
 583                 pc = usbd_xfer_get_frame(xfer, 0);
 584                 memset(&txpkt, 0, sizeof(txpkt));
 585                 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
 586                     URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
 587                 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
 588                 pos += sizeof(txpkt);
 589                 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
 590                 pos += m->m_pkthdr.len;
 591
 592                 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
 593
 594                 /*
 595                  * If there's a BPF listener, bounce a copy
 596                  * of this frame to him.
 597                  */
 598                 BPF_MTAP(ifp, m);
 599
 600                 m_freem(m);
 601
 602                 /* Set frame length. */
 603                 usbd_xfer_set_frame_len(xfer, 0, pos);
 604
 605                 usbd_transfer_submit(xfer);
 606                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 607                 return;
 608         default:                        /* Error */
 609                 DPRINTFN(11, "transfer error, %s\n",
 610                     usbd_errstr(error));
 611
 612                 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
 613                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 614
 615                 if (error != USB_ERR_CANCELLED) {
 616                         /* try to clear stall first */
 617                         usbd_xfer_set_stall(xfer);
 618                         goto tr_setup;
 619                 }
 620                 return;
 621         }
 622 }
 623
 624 static void
 625 ure_read_chipver(struct ure_softc *sc)
 626 {
 627         uint16_t ver;
 628
 629         ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
 630         switch (ver) {
 631         case 0x4c00:
 632                 sc->sc_chip |= URE_CHIP_VER_4C00;
 633                 break;
 634         case 0x4c10:
 635                 sc->sc_chip |= URE_CHIP_VER_4C10;
 636                 break;
 637         case 0x5c00:
 638                 sc->sc_chip |= URE_CHIP_VER_5C00;
 639                 break;
 640         case 0x5c10:
 641                 sc->sc_chip |= URE_CHIP_VER_5C10;
 642                 break;
 643         case 0x5c20:
 644                 sc->sc_chip |= URE_CHIP_VER_5C20;
 645                 break;
 646         case 0x5c30:
 647                 sc->sc_chip |= URE_CHIP_VER_5C30;
 648                 break;
 649         default:
 650                 device_printf(sc->sc_ue.ue_dev,
 651                     "unknown version 0x%04x\n", ver);
 652                 break;
 653         }
 654 }
 655
 656 static void
 657 ure_attach_post(struct usb_ether *ue)
 658 {
 659         struct ure_softc *sc = uether_getsc(ue);
 660
 661         sc->sc_phyno = 0;
 662
 663         /* Determine the chip version. */
 664         ure_read_chipver(sc);
 665
 666         /* Initialize controller and get station address. */
 667         if (sc->sc_flags & URE_FLAG_8152)
 668                 ure_rtl8152_init(sc);
 669         else
 670                 ure_rtl8153_init(sc);
 671
 672         if (sc->sc_chip & URE_CHIP_VER_4C00)
 673                 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
 674                     ue->ue_eaddr, 8);
 675         else
 676                 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
 677                     ue->ue_eaddr, 8);
 678 }
 679
 680 static int
 681 ure_attach_post_sub(struct usb_ether *ue)
 682 {
 683         struct ure_softc *sc;
 684         struct ifnet *ifp;
 685         int error;
 686
 687         sc = uether_getsc(ue);
 688         ifp = ue->ue_ifp;
 689         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 690         ifp->if_start = uether_start;
 691         ifp->if_ioctl = ure_ioctl;
 692         ifp->if_init = uether_init;
 693         IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
 694         ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
 695         IFQ_SET_READY(&ifp->if_snd);
 696
 697         mtx_lock(&Giant);
 698         error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
 699             uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
 700             BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
 701         mtx_unlock(&Giant);
 702
 703         return (error);
 704 }
 705
 706 static void
 707 ure_init(struct usb_ether *ue)
 708 {
 709         struct ure_softc *sc = uether_getsc(ue);
 710         struct ifnet *ifp = uether_getifp(ue);
 711
 712         URE_LOCK_ASSERT(sc, MA_OWNED);
 713
 714         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 715                 return;
 716
 717         /* Cancel pending I/O. */
 718         ure_stop(ue);
 719
 720         ure_reset(sc);
 721
 722         /* Set MAC address. */
 723         ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
 724             IF_LLADDR(ifp), 8);
 725
 726         /* Reset the packet filter. */
 727         ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
 728             ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) &
 729             ~URE_FMC_FCR_MCU_EN);
 730         ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
 731             ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) |
 732             URE_FMC_FCR_MCU_EN);
 733
 734         /* Enable transmit and receive. */
 735         ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA,
 736             ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE |
 737             URE_CR_TE);
 738
 739         ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
 740             ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) &
 741             ~URE_RXDY_GATED_EN);
 742
 743         /*  Configure RX filters. */
 744         ure_rxfilter(ue);
 745
 746         usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]);
 747
 748         /* Indicate we are up and running. */
 749         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 750
 751         /* Switch to selected media. */
 752         ure_ifmedia_upd(ifp);
 753 }
 754
 755 static void
 756 ure_tick(struct usb_ether *ue)
 757 {
 758         struct ure_softc *sc = uether_getsc(ue);
 759         struct mii_data *mii = GET_MII(sc);
 760
 761         URE_LOCK_ASSERT(sc, MA_OWNED);
 762
 763         mii_tick(mii);
 764         if ((sc->sc_flags & URE_FLAG_LINK) == 0
 765             && mii->mii_media_status & IFM_ACTIVE &&
 766             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
 767                 sc->sc_flags |= URE_FLAG_LINK;
 768                 ure_start(ue);
 769         }
 770 }
 771
 772 /*
 773  * Program the 64-bit multicast hash filter.
 774  */
 775 static void
 776 ure_rxfilter(struct usb_ether *ue)
 777 {
 778         struct ure_softc *sc = uether_getsc(ue);
 779         struct ifnet *ifp = uether_getifp(ue);
 780         struct ifmultiaddr *ifma;
 781         uint32_t h, rxmode;
 782         uint32_t hashes[2] = { 0, 0 };
 783
 784         URE_LOCK_ASSERT(sc, MA_OWNED);
 785
 786         rxmode = URE_RCR_APM;
 787         if (ifp->if_flags & IFF_BROADCAST)
 788                  rxmode |= URE_RCR_AB;
 789         if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
 790                 if (ifp->if_flags & IFF_PROMISC)
 791                         rxmode |= URE_RCR_AAP;
 792                 rxmode |= URE_RCR_AM;
 793                 hashes[0] = hashes[1] = 0xffffffff;
 794                 goto done;
 795         }
 796
 797         rxmode |= URE_RCR_AM;
 798         if_maddr_rlock(ifp);
 799         CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 800                 if (ifma->ifma_addr->sa_family != AF_LINK)
 801                         continue;
 802                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 803                 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
 804                 if (h < 32)
 805                         hashes[0] |= (1 << h);
 806                 else
 807                         hashes[1] |= (1 << (h - 32));
 808         }
 809         if_maddr_runlock(ifp);
 810
 811         h = bswap32(hashes[0]);
 812         hashes[0] = bswap32(hashes[1]);
 813         hashes[1] = h;
 814         rxmode |= URE_RCR_AM;
 815
 816 done:
 817         ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
 818         ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
 819         ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
 820 }
 821
 822 static void
 823 ure_start(struct usb_ether *ue)
 824 {
 825         struct ure_softc *sc = uether_getsc(ue);
 826
 827         /*
 828          * start the USB transfers, if not already started:
 829          */
 830         usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]);
 831         usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]);
 832 }
 833
 834 static void
 835 ure_reset(struct ure_softc *sc)
 836 {
 837         int i;
 838
 839         ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
 840
 841         for (i = 0; i < URE_TIMEOUT; i++) {
 842                 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
 843                     URE_CR_RST))
 844                         break;
 845                 uether_pause(&sc->sc_ue, hz / 100);
 846         }
 847         if (i == URE_TIMEOUT)
 848                 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
 849 }
 850
 851 /*
 852  * Set media options.
 853  */
 854 static int
 855 ure_ifmedia_upd(struct ifnet *ifp)
 856 {
 857         struct ure_softc *sc = ifp->if_softc;
 858         struct mii_data *mii = GET_MII(sc);
 859         struct mii_softc *miisc;
 860         int error;
 861
 862         URE_LOCK_ASSERT(sc, MA_OWNED);
 863
 864         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 865                 PHY_RESET(miisc);
 866         error = mii_mediachg(mii);
 867         return (error);
 868 }
 869
 870 /*
 871  * Report current media status.
 872  */
 873 static void
 874 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 875 {
 876         struct ure_softc *sc;
 877         struct mii_data *mii;
 878
 879         sc = ifp->if_softc;
 880         mii = GET_MII(sc);
 881
 882         URE_LOCK(sc);
 883         mii_pollstat(mii);
 884         ifmr->ifm_active = mii->mii_media_active;
 885         ifmr->ifm_status = mii->mii_media_status;
 886         URE_UNLOCK(sc);
 887 }
 888
 889 static int
 890 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 891 {
 892         struct usb_ether *ue = ifp->if_softc;
 893         struct ure_softc *sc;
 894         struct ifreq *ifr;
 895         int error, mask, reinit;
 896
 897         sc = uether_getsc(ue);
 898         ifr = (struct ifreq *)data;
 899         error = 0;
 900         reinit = 0;
 901         if (cmd == SIOCSIFCAP) {
 902                 URE_LOCK(sc);
 903                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 904                 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
 905                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 906                 else
 907                         reinit = 0;
 908                 URE_UNLOCK(sc);
 909                 if (reinit > 0)
 910                         uether_init(ue);
 911         } else
 912                 error = uether_ioctl(ifp, cmd, data);
 913
 914         return (error);
 915 }
 916
 917 static void
 918 ure_rtl8152_init(struct ure_softc *sc)
 919 {
 920         uint32_t pwrctrl;
 921
 922         /* Disable ALDPS. */
 923         ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
 924             URE_DIS_SDSAVE);
 925         uether_pause(&sc->sc_ue, hz / 50);
 926
 927         if (sc->sc_chip & URE_CHIP_VER_4C00) {
 928                 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
 929                     ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
 930                     ~URE_LED_MODE_MASK);
 931         }
 932
 933         ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB,
 934             ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) &
 935             ~URE_POWER_CUT);
 936         ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB,
 937             ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) &
 938             ~URE_RESUME_INDICATE);
 939
 940         ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
 941             ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
 942             URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
 943         pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
 944         pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
 945         pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
 946         ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
 947         ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
 948             URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
 949             URE_SPDWN_LINKCHG_MSK);
 950
 951         /* Disable Rx aggregation. */
 952         ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
 953             ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
 954             URE_RX_AGG_DISABLE);
 955
 956         /* Disable ALDPS. */
 957         ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
 958             URE_DIS_SDSAVE);
 959         uether_pause(&sc->sc_ue, hz / 50);
 960
 961         ure_init_fifo(sc);
 962
 963         ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
 964             URE_TX_AGG_MAX_THRESHOLD);
 965         ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
 966         ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
 967             URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
 968 }
 969
 970 static void
 971 ure_rtl8153_init(struct ure_softc *sc)
 972 {
 973         uint16_t val;
 974         uint8_t u1u2[8];
 975         int i;
 976
 977         /* Disable ALDPS. */
 978         ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
 979             ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
 980         uether_pause(&sc->sc_ue, hz / 50);
 981
 982         memset(u1u2, 0x00, sizeof(u1u2));
 983         ure_write_mem(sc, URE_USB_TOLERANCE,
 984             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
 985
 986         for (i = 0; i < URE_TIMEOUT; i++) {
 987                 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
 988                     URE_AUTOLOAD_DONE)
 989                         break;
 990                 uether_pause(&sc->sc_ue, hz / 100);
 991         }
 992         if (i == URE_TIMEOUT)
 993                 device_printf(sc->sc_ue.ue_dev,
 994                     "timeout waiting for chip autoload\n");
 995
 996         for (i = 0; i < URE_TIMEOUT; i++) {
 997                 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
 998                     URE_PHY_STAT_MASK;
 999                 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
1000                         break;
1001                 uether_pause(&sc->sc_ue, hz / 100);
1002         }
1003         if (i == URE_TIMEOUT)
1004                 device_printf(sc->sc_ue.ue_dev,
1005                     "timeout waiting for phy to stabilize\n");
1006
1007         ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,
1008             ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) &
1009             ~URE_U2P3_ENABLE);
1010
1011         if (sc->sc_chip & URE_CHIP_VER_5C10) {
1012                 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1013                 val &= ~URE_PWD_DN_SCALE_MASK;
1014                 val |= URE_PWD_DN_SCALE(96);
1015                 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
1016
1017                 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB,
1018                     ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) |
1019                     URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1020         } else if (sc->sc_chip & URE_CHIP_VER_5C20) {
1021                 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA,
1022                     ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) &
1023                     ~URE_ECM_ALDPS);
1024         }
1025         if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1026                 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
1027                 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
1028                     0)
1029                         val &= ~URE_DYNAMIC_BURST;
1030                 else
1031                         val |= URE_DYNAMIC_BURST;
1032                 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
1033         }
1034
1035         ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB,
1036             ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) |
1037             URE_EP4_FULL_FC);
1038
1039         ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB,
1040             ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) &
1041             ~URE_TIMER11_EN);
1042
1043         ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
1044             ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
1045             ~URE_LED_MODE_MASK);
1046
1047         if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
1048             usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
1049                 val = URE_LPM_TIMER_500MS;
1050         else
1051                 val = URE_LPM_TIMER_500US;
1052         ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1053             val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
1054
1055         val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1056         val &= ~URE_SEN_VAL_MASK;
1057         val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1058         ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
1059
1060         ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1061
1062         ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,
1063             ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) &
1064             ~(URE_PWR_EN | URE_PHASE2_EN));
1065         ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB,
1066             ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) &
1067             ~URE_PCUT_STATUS);
1068
1069         memset(u1u2, 0xff, sizeof(u1u2));
1070         ure_write_mem(sc, URE_USB_TOLERANCE,
1071             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1072
1073         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
1074             URE_ALDPS_SPDWN_RATIO);
1075         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1076             URE_EEE_SPDWN_RATIO);
1077         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1078             URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
1079             URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
1080         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
1081             URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
1082             URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
1083             URE_EEE_SPDWN_EN);
1084
1085         val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1086         if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1087                 val |= URE_U2P3_ENABLE;
1088         else
1089                 val &= ~URE_U2P3_ENABLE;
1090         ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1091
1092         memset(u1u2, 0x00, sizeof(u1u2));
1093         ure_write_mem(sc, URE_USB_TOLERANCE,
1094             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1095
1096         /* Disable ALDPS. */
1097         ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1098             ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
1099         uether_pause(&sc->sc_ue, hz / 50);
1100
1101         ure_init_fifo(sc);
1102
1103         /* Disable Rx aggregation. */
1104         ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
1105             ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
1106             URE_RX_AGG_DISABLE);
1107
1108         val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1109         if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1110                 val |= URE_U2P3_ENABLE;
1111         else
1112                 val &= ~URE_U2P3_ENABLE;
1113         ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1114
1115         memset(u1u2, 0xff, sizeof(u1u2));
1116         ure_write_mem(sc, URE_USB_TOLERANCE,
1117             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1118 }
1119
1120 static void
1121 ure_stop(struct usb_ether *ue)
1122 {
1123         struct ure_softc *sc = uether_getsc(ue);
1124         struct ifnet *ifp = uether_getifp(ue);
1125
1126         URE_LOCK_ASSERT(sc, MA_OWNED);
1127
1128         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1129         sc->sc_flags &= ~URE_FLAG_LINK;
1130
1131         /*
1132          * stop all the transfers, if not already stopped:
1133          */
1134         usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]);
1135         usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]);
1136 }
1137
1138 static void
1139 ure_disable_teredo(struct ure_softc *sc)
1140 {
1141
1142         ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
1143             ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) &
1144             ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
1145         ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA,
1146             URE_WDT6_SET_MODE);
1147         ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
1148         ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
1149 }
1150
1151 static void
1152 ure_init_fifo(struct ure_softc *sc)
1153 {
1154         uint32_t rx_fifo1, rx_fifo2;
1155         int i;
1156
1157         ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
1158             ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) |
1159             URE_RXDY_GATED_EN);
1160
1161         ure_disable_teredo(sc);
1162
1163         ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA,
1164             ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) &
1165             ~URE_RCR_ACPT_ALL);
1166
1167         if (!(sc->sc_flags & URE_FLAG_8152)) {
1168                 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1169                     URE_CHIP_VER_5C20)) {
1170                                 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
1171                                     URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1172                 }
1173                 if (sc->sc_chip & URE_CHIP_VER_5C00) {
1174                         ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
1175                             ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
1176                             ~URE_CTAP_SHORT_EN);
1177                 }
1178                 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1179                     ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1180                     URE_EEE_CLKDIV_EN);
1181                 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
1182                     ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
1183                     URE_EN_10M_BGOFF);
1184                 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1185                     ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1186                     URE_EN_10M_PLLOFF);
1187                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE);
1188                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13);
1189                 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
1190                     ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
1191                     URE_PFM_PWM_SWITCH);
1192
1193                 /* Enable LPF corner auto tune. */
1194                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG);
1195                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f);
1196
1197                 /* Adjust 10M amplitude. */
1198                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1);
1199                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af);
1200                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2);
1201                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208);
1202         }
1203
1204         ure_reset(sc);
1205
1206         ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
1207
1208         ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA,
1209             ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1210             ~URE_NOW_IS_OOB);
1211
1212         ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1213             ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) &
1214             ~URE_MCU_BORW_EN);
1215         for (i = 0; i < URE_TIMEOUT; i++) {
1216                 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1217                     URE_LINK_LIST_READY)
1218                         break;
1219                 uether_pause(&sc->sc_ue, hz / 100);
1220         }
1221         if (i == URE_TIMEOUT)
1222                 device_printf(sc->sc_ue.ue_dev,
1223                     "timeout waiting for OOB control\n");
1224         ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1225             ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) |
1226             URE_RE_INIT_LL);
1227         for (i = 0; i < URE_TIMEOUT; i++) {
1228                 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1229                     URE_LINK_LIST_READY)
1230                         break;
1231                 uether_pause(&sc->sc_ue, hz / 100);
1232         }
1233         if (i == URE_TIMEOUT)
1234                 device_printf(sc->sc_ue.ue_dev,
1235                     "timeout waiting for OOB control\n");
1236
1237         ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA,
1238             ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) &
1239             ~URE_CPCR_RX_VLAN);
1240         ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,
1241             ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) |
1242             URE_TCR0_AUTO_FIFO);
1243
1244         /* Configure Rx FIFO threshold. */
1245         ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
1246             URE_RXFIFO_THR1_NORMAL);
1247         if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
1248                 rx_fifo1 = URE_RXFIFO_THR2_FULL;
1249                 rx_fifo2 = URE_RXFIFO_THR3_FULL;
1250         } else {
1251                 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
1252                 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
1253         }
1254         ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
1255         ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
1256
1257         /* Configure Tx FIFO threshold. */
1258         ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
1259             URE_TXFIFO_THR_NORMAL);
1260 }