sys/dev/usb/net/if_ure.c

   1 /*-
   2  * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/condvar.h>
  34 #include <sys/kernel.h>
  35 #include <sys/lock.h>
  36 #include <sys/module.h>
  37 #include <sys/mutex.h>
  38 #include <sys/socket.h>
  39 #include <sys/sysctl.h>
  40 #include <sys/unistd.h>
  41
  42 #include <net/if.h>
  43 #include <net/if_var.h>
  44
  45 #include <dev/usb/usb.h>
  46 #include <dev/usb/usbdi.h>
  47 #include <dev/usb/usbdi_util.h>
  48 #include "usbdevs.h"
  49
  50 #define USB_DEBUG_VAR   ure_debug
  51 #include <dev/usb/usb_debug.h>
  52 #include <dev/usb/usb_process.h>
  53
  54 #include <dev/usb/net/usb_ethernet.h>
  55 #include <dev/usb/net/if_urereg.h>
  56
  57 #ifdef USB_DEBUG
  58 static int ure_debug = 0;
  59
  60 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure");
  61 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
  62     "Debug level");
  63 #endif
  64
  65 /*
  66  * Various supported device vendors/products.
  67  */
  68 static const STRUCT_USB_HOST_ID ure_devs[] = {
  69 #define URE_DEV(v,p,i)  { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
  70         URE_DEV(LENOVO, RTL8153, 0),
  71         URE_DEV(LENOVO, TBT3LAN, 0),
  72         URE_DEV(LENOVO, ONELINK, 0),
  73         URE_DEV(LENOVO, USBCLAN, 0),
  74         URE_DEV(NVIDIA, RTL8153, 0),
  75         URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
  76         URE_DEV(REALTEK, RTL8153, 0),
  77         URE_DEV(TPLINK, RTL8153, 0),
  78 #undef URE_DEV
  79 };
  80
  81 static device_probe_t ure_probe;
  82 static device_attach_t ure_attach;
  83 static device_detach_t ure_detach;
  84
  85 static usb_callback_t ure_bulk_read_callback;
  86 static usb_callback_t ure_bulk_write_callback;
  87
  88 static miibus_readreg_t ure_miibus_readreg;
  89 static miibus_writereg_t ure_miibus_writereg;
  90 static miibus_statchg_t ure_miibus_statchg;
  91
  92 static uether_fn_t ure_attach_post;
  93 static uether_fn_t ure_init;
  94 static uether_fn_t ure_stop;
  95 static uether_fn_t ure_start;
  96 static uether_fn_t ure_tick;
  97 static uether_fn_t ure_rxfilter;
  98
  99 static int      ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
 100                     void *, int);
 101 static int      ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
 102                     int);
 103 static int      ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
 104                     int);
 105 static uint8_t  ure_read_1(struct ure_softc *, uint16_t, uint16_t);
 106 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
 107 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
 108 static int      ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
 109 static int      ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
 110 static int      ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
 111 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
 112 static void     ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
 113
 114 static void     ure_read_chipver(struct ure_softc *);
 115 static int      ure_attach_post_sub(struct usb_ether *);
 116 static void     ure_reset(struct ure_softc *);
 117 static int      ure_ifmedia_upd(struct ifnet *);
 118 static void     ure_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 119 static int      ure_ioctl(struct ifnet *, u_long, caddr_t);
 120 static void     ure_rtl8152_init(struct ure_softc *);
 121 static void     ure_rtl8153_init(struct ure_softc *);
 122 static void     ure_disable_teredo(struct ure_softc *);
 123 static void     ure_init_fifo(struct ure_softc *);
 124
 125 static const struct usb_config ure_config[URE_N_TRANSFER] = {
 126         [URE_BULK_DT_WR] = {
 127                 .type = UE_BULK,
 128                 .endpoint = UE_ADDR_ANY,
 129                 .direction = UE_DIR_OUT,
 130                 .bufsize = MCLBYTES,
 131                 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
 132                 .callback = ure_bulk_write_callback,
 133                 .timeout = 10000,       /* 10 seconds */
 134         },
 135         [URE_BULK_DT_RD] = {
 136                 .type = UE_BULK,
 137                 .endpoint = UE_ADDR_ANY,
 138                 .direction = UE_DIR_IN,
 139                 .bufsize = 16384,
 140                 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
 141                 .callback = ure_bulk_read_callback,
 142                 .timeout = 0,   /* no timeout */
 143         },
 144 };
 145
 146 static device_method_t ure_methods[] = {
 147         /* Device interface. */
 148         DEVMETHOD(device_probe, ure_probe),
 149         DEVMETHOD(device_attach, ure_attach),
 150         DEVMETHOD(device_detach, ure_detach),
 151
 152         /* MII interface. */
 153         DEVMETHOD(miibus_readreg, ure_miibus_readreg),
 154         DEVMETHOD(miibus_writereg, ure_miibus_writereg),
 155         DEVMETHOD(miibus_statchg, ure_miibus_statchg),
 156
 157         DEVMETHOD_END
 158 };
 159
 160 static driver_t ure_driver = {
 161         .name = "ure",
 162         .methods = ure_methods,
 163         .size = sizeof(struct ure_softc),
 164 };
 165
 166 static devclass_t ure_devclass;
 167
 168 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL);
 169 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL);
 170 MODULE_DEPEND(ure, uether, 1, 1, 1);
 171 MODULE_DEPEND(ure, usb, 1, 1, 1);
 172 MODULE_DEPEND(ure, ether, 1, 1, 1);
 173 MODULE_DEPEND(ure, miibus, 1, 1, 1);
 174 MODULE_VERSION(ure, 1);
 175 USB_PNP_HOST_INFO(ure_devs);
 176
 177 static const struct usb_ether_methods ure_ue_methods = {
 178         .ue_attach_post = ure_attach_post,
 179         .ue_attach_post_sub = ure_attach_post_sub,
 180         .ue_start = ure_start,
 181         .ue_init = ure_init,
 182         .ue_stop = ure_stop,
 183         .ue_tick = ure_tick,
 184         .ue_setmulti = ure_rxfilter,
 185         .ue_setpromisc = ure_rxfilter,
 186         .ue_mii_upd = ure_ifmedia_upd,
 187         .ue_mii_sts = ure_ifmedia_sts,
 188 };
 189
 190 static int
 191 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
 192     void *buf, int len)
 193 {
 194         struct usb_device_request req;
 195
 196         URE_LOCK_ASSERT(sc, MA_OWNED);
 197
 198         if (rw == URE_CTL_WRITE)
 199                 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
 200         else
 201                 req.bmRequestType = UT_READ_VENDOR_DEVICE;
 202         req.bRequest = UR_SET_ADDRESS;
 203         USETW(req.wValue, val);
 204         USETW(req.wIndex, index);
 205         USETW(req.wLength, len);
 206
 207         return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
 208 }
 209
 210 static int
 211 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
 212     void *buf, int len)
 213 {
 214
 215         return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
 216 }
 217
 218 static int
 219 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
 220     void *buf, int len)
 221 {
 222
 223         return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
 224 }
 225
 226 static uint8_t
 227 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
 228 {
 229         uint32_t val;
 230         uint8_t temp[4];
 231         uint8_t shift;
 232
 233         shift = (reg & 3) << 3;
 234         reg &= ~3;
 235
 236         ure_read_mem(sc, reg, index, &temp, 4);
 237         val = UGETDW(temp);
 238         val >>= shift;
 239
 240         return (val & 0xff);
 241 }
 242
 243 static uint16_t
 244 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
 245 {
 246         uint32_t val;
 247         uint8_t temp[4];
 248         uint8_t shift;
 249
 250         shift = (reg & 2) << 3;
 251         reg &= ~3;
 252
 253         ure_read_mem(sc, reg, index, &temp, 4);
 254         val = UGETDW(temp);
 255         val >>= shift;
 256
 257         return (val & 0xffff);
 258 }
 259
 260 static uint32_t
 261 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
 262 {
 263         uint8_t temp[4];
 264
 265         ure_read_mem(sc, reg, index, &temp, 4);
 266         return (UGETDW(temp));
 267 }
 268
 269 static int
 270 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
 271 {
 272         uint16_t byen;
 273         uint8_t temp[4];
 274         uint8_t shift;
 275
 276         byen = URE_BYTE_EN_BYTE;
 277         shift = reg & 3;
 278         val &= 0xff;
 279
 280         if (reg & 3) {
 281                 byen <<= shift;
 282                 val <<= (shift << 3);
 283                 reg &= ~3;
 284         }
 285
 286         USETDW(temp, val);
 287         return (ure_write_mem(sc, reg, index | byen, &temp, 4));
 288 }
 289
 290 static int
 291 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
 292 {
 293         uint16_t byen;
 294         uint8_t temp[4];
 295         uint8_t shift;
 296
 297         byen = URE_BYTE_EN_WORD;
 298         shift = reg & 2;
 299         val &= 0xffff;
 300
 301         if (reg & 2) {
 302                 byen <<= shift;
 303                 val <<= (shift << 3);
 304                 reg &= ~3;
 305         }
 306
 307         USETDW(temp, val);
 308         return (ure_write_mem(sc, reg, index | byen, &temp, 4));
 309 }
 310
 311 static int
 312 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
 313 {
 314         uint8_t temp[4];
 315
 316         USETDW(temp, val);
 317         return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
 318 }
 319
 320 static uint16_t
 321 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
 322 {
 323         uint16_t reg;
 324
 325         ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
 326         reg = (addr & 0x0fff) | 0xb000;
 327
 328         return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
 329 }
 330
 331 static void
 332 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
 333 {
 334         uint16_t reg;
 335
 336         ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
 337         reg = (addr & 0x0fff) | 0xb000;
 338
 339         ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
 340 }
 341
 342 static int
 343 ure_miibus_readreg(device_t dev, int phy, int reg)
 344 {
 345         struct ure_softc *sc;
 346         uint16_t val;
 347         int locked;
 348
 349         sc = device_get_softc(dev);
 350         locked = mtx_owned(&sc->sc_mtx);
 351         if (!locked)
 352                 URE_LOCK(sc);
 353
 354         /* Let the rgephy driver read the URE_GMEDIASTAT register. */
 355         if (reg == URE_GMEDIASTAT) {
 356                 if (!locked)
 357                         URE_UNLOCK(sc);
 358                 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
 359         }
 360
 361         val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
 362
 363         if (!locked)
 364                 URE_UNLOCK(sc);
 365         return (val);
 366 }
 367
 368 static int
 369 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
 370 {
 371         struct ure_softc *sc;
 372         int locked;
 373
 374         sc = device_get_softc(dev);
 375         if (sc->sc_phyno != phy)
 376                 return (0);
 377
 378         locked = mtx_owned(&sc->sc_mtx);
 379         if (!locked)
 380                 URE_LOCK(sc);
 381
 382         ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
 383
 384         if (!locked)
 385                 URE_UNLOCK(sc);
 386         return (0);
 387 }
 388
 389 static void
 390 ure_miibus_statchg(device_t dev)
 391 {
 392         struct ure_softc *sc;
 393         struct mii_data *mii;
 394         struct ifnet *ifp;
 395         int locked;
 396
 397         sc = device_get_softc(dev);
 398         mii = GET_MII(sc);
 399         locked = mtx_owned(&sc->sc_mtx);
 400         if (!locked)
 401                 URE_LOCK(sc);
 402
 403         ifp = uether_getifp(&sc->sc_ue);
 404         if (mii == NULL || ifp == NULL ||
 405             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 406                 goto done;
 407
 408         sc->sc_flags &= ~URE_FLAG_LINK;
 409         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 410             (IFM_ACTIVE | IFM_AVALID)) {
 411                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 412                 case IFM_10_T:
 413                 case IFM_100_TX:
 414                         sc->sc_flags |= URE_FLAG_LINK;
 415                         break;
 416                 case IFM_1000_T:
 417                         if ((sc->sc_flags & URE_FLAG_8152) != 0)
 418                                 break;
 419                         sc->sc_flags |= URE_FLAG_LINK;
 420                         break;
 421                 default:
 422                         break;
 423                 }
 424         }
 425
 426         /* Lost link, do nothing. */
 427         if ((sc->sc_flags & URE_FLAG_LINK) == 0)
 428                 goto done;
 429 done:
 430         if (!locked)
 431                 URE_UNLOCK(sc);
 432 }
 433
 434 /*
 435  * Probe for a RTL8152/RTL8153 chip.
 436  */
 437 static int
 438 ure_probe(device_t dev)
 439 {
 440         struct usb_attach_arg *uaa;
 441
 442         uaa = device_get_ivars(dev);
 443         if (uaa->usb_mode != USB_MODE_HOST)
 444                 return (ENXIO);
 445         if (uaa->info.bConfigIndex != URE_CONFIG_IDX)
 446                 return (ENXIO);
 447         if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
 448                 return (ENXIO);
 449
 450         return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
 451 }
 452
 453 /*
 454  * Attach the interface. Allocate softc structures, do ifmedia
 455  * setup and ethernet/BPF attach.
 456  */
 457 static int
 458 ure_attach(device_t dev)
 459 {
 460         struct usb_attach_arg *uaa = device_get_ivars(dev);
 461         struct ure_softc *sc = device_get_softc(dev);
 462         struct usb_ether *ue = &sc->sc_ue;
 463         uint8_t iface_index;
 464         int error;
 465
 466         sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
 467         device_set_usb_desc(dev);
 468         mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
 469
 470         iface_index = URE_IFACE_IDX;
 471         error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
 472             ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx);
 473         if (error != 0) {
 474                 device_printf(dev, "allocating USB transfers failed\n");
 475                 goto detach;
 476         }
 477
 478         ue->ue_sc = sc;
 479         ue->ue_dev = dev;
 480         ue->ue_udev = uaa->device;
 481         ue->ue_mtx = &sc->sc_mtx;
 482         ue->ue_methods = &ure_ue_methods;
 483
 484         error = uether_ifattach(ue);
 485         if (error != 0) {
 486                 device_printf(dev, "could not attach interface\n");
 487                 goto detach;
 488         }
 489         return (0);                     /* success */
 490
 491 detach:
 492         ure_detach(dev);
 493         return (ENXIO);                 /* failure */
 494 }
 495
 496 static int
 497 ure_detach(device_t dev)
 498 {
 499         struct ure_softc *sc = device_get_softc(dev);
 500         struct usb_ether *ue = &sc->sc_ue;
 501
 502         usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER);
 503         uether_ifdetach(ue);
 504         mtx_destroy(&sc->sc_mtx);
 505
 506         return (0);
 507 }
 508
 509 static void
 510 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
 511 {
 512         struct ure_softc *sc = usbd_xfer_softc(xfer);
 513         struct usb_ether *ue = &sc->sc_ue;
 514         struct ifnet *ifp = uether_getifp(ue);
 515         struct usb_page_cache *pc;
 516         struct ure_rxpkt pkt;
 517         int actlen, len;
 518
 519         usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
 520
 521         switch (USB_GET_STATE(xfer)) {
 522         case USB_ST_TRANSFERRED:
 523                 if (actlen < (int)(sizeof(pkt))) {
 524                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 525                         goto tr_setup;
 526                 }
 527                 pc = usbd_xfer_get_frame(xfer, 0);
 528                 usbd_copy_out(pc, 0, &pkt, sizeof(pkt));
 529                 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
 530                 len -= ETHER_CRC_LEN;
 531                 if (actlen < (int)(len + sizeof(pkt))) {
 532                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 533                         goto tr_setup;
 534                 }
 535
 536                 uether_rxbuf(ue, pc, sizeof(pkt), len);
 537                 /* FALLTHROUGH */
 538         case USB_ST_SETUP:
 539 tr_setup:
 540                 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
 541                 usbd_transfer_submit(xfer);
 542                 uether_rxflush(ue);
 543                 return;
 544
 545         default:                        /* Error */
 546                 DPRINTF("bulk read error, %s\n",
 547                     usbd_errstr(error));
 548
 549                 if (error != USB_ERR_CANCELLED) {
 550                         /* try to clear stall first */
 551                         usbd_xfer_set_stall(xfer);
 552                         goto tr_setup;
 553                 }
 554                 return;
 555         }
 556 }
 557
 558 static void
 559 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
 560 {
 561         struct ure_softc *sc = usbd_xfer_softc(xfer);
 562         struct ifnet *ifp = uether_getifp(&sc->sc_ue);
 563         struct usb_page_cache *pc;
 564         struct mbuf *m;
 565         struct ure_txpkt txpkt;
 566         int len, pos;
 567
 568         switch (USB_GET_STATE(xfer)) {
 569         case USB_ST_TRANSFERRED:
 570                 DPRINTFN(11, "transfer complete\n");
 571                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 572                 /* FALLTHROUGH */
 573         case USB_ST_SETUP:
 574 tr_setup:
 575                 if ((sc->sc_flags & URE_FLAG_LINK) == 0 ||
 576                     (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
 577                         /*
 578                          * don't send anything if there is no link !
 579                          */
 580                         return;
 581                 }
 582                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
 583                 if (m == NULL)
 584                         break;
 585                 pos = 0;
 586                 len = m->m_pkthdr.len;
 587                 pc = usbd_xfer_get_frame(xfer, 0);
 588                 memset(&txpkt, 0, sizeof(txpkt));
 589                 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
 590                     URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
 591                 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
 592                 pos += sizeof(txpkt);
 593                 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
 594                 pos += m->m_pkthdr.len;
 595
 596                 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
 597
 598                 /*
 599                  * If there's a BPF listener, bounce a copy
 600                  * of this frame to him.
 601                  */
 602                 BPF_MTAP(ifp, m);
 603
 604                 m_freem(m);
 605
 606                 /* Set frame length. */
 607                 usbd_xfer_set_frame_len(xfer, 0, pos);
 608
 609                 usbd_transfer_submit(xfer);
 610                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 611                 return;
 612         default:                        /* Error */
 613                 DPRINTFN(11, "transfer error, %s\n",
 614                     usbd_errstr(error));
 615
 616                 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
 617                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 618
 619                 if (error != USB_ERR_CANCELLED) {
 620                         /* try to clear stall first */
 621                         usbd_xfer_set_stall(xfer);
 622                         goto tr_setup;
 623                 }
 624                 return;
 625         }
 626 }
 627
 628 static void
 629 ure_read_chipver(struct ure_softc *sc)
 630 {
 631         uint16_t ver;
 632
 633         ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
 634         switch (ver) {
 635         case 0x4c00:
 636                 sc->sc_chip |= URE_CHIP_VER_4C00;
 637                 break;
 638         case 0x4c10:
 639                 sc->sc_chip |= URE_CHIP_VER_4C10;
 640                 break;
 641         case 0x5c00:
 642                 sc->sc_chip |= URE_CHIP_VER_5C00;
 643                 break;
 644         case 0x5c10:
 645                 sc->sc_chip |= URE_CHIP_VER_5C10;
 646                 break;
 647         case 0x5c20:
 648                 sc->sc_chip |= URE_CHIP_VER_5C20;
 649                 break;
 650         case 0x5c30:
 651                 sc->sc_chip |= URE_CHIP_VER_5C30;
 652                 break;
 653         default:
 654                 device_printf(sc->sc_ue.ue_dev,
 655                     "unknown version 0x%04x\n", ver);
 656                 break;
 657         }
 658 }
 659
 660 static void
 661 ure_attach_post(struct usb_ether *ue)
 662 {
 663         struct ure_softc *sc = uether_getsc(ue);
 664
 665         sc->sc_phyno = 0;
 666
 667         /* Determine the chip version. */
 668         ure_read_chipver(sc);
 669
 670         /* Initialize controller and get station address. */
 671         if (sc->sc_flags & URE_FLAG_8152)
 672                 ure_rtl8152_init(sc);
 673         else
 674                 ure_rtl8153_init(sc);
 675
 676         if (sc->sc_chip & URE_CHIP_VER_4C00)
 677                 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
 678                     ue->ue_eaddr, 8);
 679         else
 680                 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
 681                     ue->ue_eaddr, 8);
 682 }
 683
 684 static int
 685 ure_attach_post_sub(struct usb_ether *ue)
 686 {
 687         struct ure_softc *sc;
 688         struct ifnet *ifp;
 689         int error;
 690
 691         sc = uether_getsc(ue);
 692         ifp = ue->ue_ifp;
 693         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 694         ifp->if_start = uether_start;
 695         ifp->if_ioctl = ure_ioctl;
 696         ifp->if_init = uether_init;
 697         IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
 698         ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
 699         IFQ_SET_READY(&ifp->if_snd);
 700
 701         mtx_lock(&Giant);
 702         error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
 703             uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
 704             BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
 705         mtx_unlock(&Giant);
 706
 707         return (error);
 708 }
 709
 710 static void
 711 ure_init(struct usb_ether *ue)
 712 {
 713         struct ure_softc *sc = uether_getsc(ue);
 714         struct ifnet *ifp = uether_getifp(ue);
 715
 716         URE_LOCK_ASSERT(sc, MA_OWNED);
 717
 718         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 719                 return;
 720
 721         /* Cancel pending I/O. */
 722         ure_stop(ue);
 723
 724         ure_reset(sc);
 725
 726         /* Set MAC address. */
 727         ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
 728             IF_LLADDR(ifp), 8);
 729
 730         /* Reset the packet filter. */
 731         ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
 732             ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) &
 733             ~URE_FMC_FCR_MCU_EN);
 734         ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA,
 735             ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) |
 736             URE_FMC_FCR_MCU_EN);
 737
 738         /* Enable transmit and receive. */
 739         ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA,
 740             ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE |
 741             URE_CR_TE);
 742
 743         ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
 744             ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) &
 745             ~URE_RXDY_GATED_EN);
 746
 747         /*  Configure RX filters. */
 748         ure_rxfilter(ue);
 749
 750         usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]);
 751
 752         /* Indicate we are up and running. */
 753         ifp->if_drv_flags |= IFF_DRV_RUNNING;
 754
 755         /* Switch to selected media. */
 756         ure_ifmedia_upd(ifp);
 757 }
 758
 759 static void
 760 ure_tick(struct usb_ether *ue)
 761 {
 762         struct ure_softc *sc = uether_getsc(ue);
 763         struct mii_data *mii = GET_MII(sc);
 764
 765         URE_LOCK_ASSERT(sc, MA_OWNED);
 766
 767         mii_tick(mii);
 768         if ((sc->sc_flags & URE_FLAG_LINK) == 0
 769             && mii->mii_media_status & IFM_ACTIVE &&
 770             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
 771                 sc->sc_flags |= URE_FLAG_LINK;
 772                 ure_start(ue);
 773         }
 774 }
 775
 776 /*
 777  * Program the 64-bit multicast hash filter.
 778  */
 779 static void
 780 ure_rxfilter(struct usb_ether *ue)
 781 {
 782         struct ure_softc *sc = uether_getsc(ue);
 783         struct ifnet *ifp = uether_getifp(ue);
 784         struct ifmultiaddr *ifma;
 785         uint32_t h, rxmode;
 786         uint32_t hashes[2] = { 0, 0 };
 787
 788         URE_LOCK_ASSERT(sc, MA_OWNED);
 789
 790         rxmode = URE_RCR_APM;
 791         if (ifp->if_flags & IFF_BROADCAST)
 792                  rxmode |= URE_RCR_AB;
 793         if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
 794                 if (ifp->if_flags & IFF_PROMISC)
 795                         rxmode |= URE_RCR_AAP;
 796                 rxmode |= URE_RCR_AM;
 797                 hashes[0] = hashes[1] = 0xffffffff;
 798                 goto done;
 799         }
 800
 801         rxmode |= URE_RCR_AM;
 802         if_maddr_rlock(ifp);
 803         CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 804                 if (ifma->ifma_addr->sa_family != AF_LINK)
 805                         continue;
 806                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 807                 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
 808                 if (h < 32)
 809                         hashes[0] |= (1 << h);
 810                 else
 811                         hashes[1] |= (1 << (h - 32));
 812         }
 813         if_maddr_runlock(ifp);
 814
 815         h = bswap32(hashes[0]);
 816         hashes[0] = bswap32(hashes[1]);
 817         hashes[1] = h;
 818         rxmode |= URE_RCR_AM;
 819
 820 done:
 821         ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
 822         ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
 823         ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
 824 }
 825
 826 static void
 827 ure_start(struct usb_ether *ue)
 828 {
 829         struct ure_softc *sc = uether_getsc(ue);
 830
 831         /*
 832          * start the USB transfers, if not already started:
 833          */
 834         usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]);
 835         usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]);
 836 }
 837
 838 static void
 839 ure_reset(struct ure_softc *sc)
 840 {
 841         int i;
 842
 843         ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
 844
 845         for (i = 0; i < URE_TIMEOUT; i++) {
 846                 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
 847                     URE_CR_RST))
 848                         break;
 849                 uether_pause(&sc->sc_ue, hz / 100);
 850         }
 851         if (i == URE_TIMEOUT)
 852                 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
 853 }
 854
 855 /*
 856  * Set media options.
 857  */
 858 static int
 859 ure_ifmedia_upd(struct ifnet *ifp)
 860 {
 861         struct ure_softc *sc = ifp->if_softc;
 862         struct mii_data *mii = GET_MII(sc);
 863         struct mii_softc *miisc;
 864         int error;
 865
 866         URE_LOCK_ASSERT(sc, MA_OWNED);
 867
 868         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 869                 PHY_RESET(miisc);
 870         error = mii_mediachg(mii);
 871         return (error);
 872 }
 873
 874 /*
 875  * Report current media status.
 876  */
 877 static void
 878 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 879 {
 880         struct ure_softc *sc;
 881         struct mii_data *mii;
 882
 883         sc = ifp->if_softc;
 884         mii = GET_MII(sc);
 885
 886         URE_LOCK(sc);
 887         mii_pollstat(mii);
 888         ifmr->ifm_active = mii->mii_media_active;
 889         ifmr->ifm_status = mii->mii_media_status;
 890         URE_UNLOCK(sc);
 891 }
 892
 893 static int
 894 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 895 {
 896         struct usb_ether *ue = ifp->if_softc;
 897         struct ure_softc *sc;
 898         struct ifreq *ifr;
 899         int error, mask, reinit;
 900
 901         sc = uether_getsc(ue);
 902         ifr = (struct ifreq *)data;
 903         error = 0;
 904         reinit = 0;
 905         if (cmd == SIOCSIFCAP) {
 906                 URE_LOCK(sc);
 907                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 908                 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
 909                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 910                 else
 911                         reinit = 0;
 912                 URE_UNLOCK(sc);
 913                 if (reinit > 0)
 914                         uether_init(ue);
 915         } else
 916                 error = uether_ioctl(ifp, cmd, data);
 917
 918         return (error);
 919 }
 920
 921 static void
 922 ure_rtl8152_init(struct ure_softc *sc)
 923 {
 924         uint32_t pwrctrl;
 925
 926         /* Disable ALDPS. */
 927         ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
 928             URE_DIS_SDSAVE);
 929         uether_pause(&sc->sc_ue, hz / 50);
 930
 931         if (sc->sc_chip & URE_CHIP_VER_4C00) {
 932                 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
 933                     ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
 934                     ~URE_LED_MODE_MASK);
 935         }
 936
 937         ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB,
 938             ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) &
 939             ~URE_POWER_CUT);
 940         ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB,
 941             ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) &
 942             ~URE_RESUME_INDICATE);
 943
 944         ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
 945             ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
 946             URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
 947         pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
 948         pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
 949         pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
 950         ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
 951         ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
 952             URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
 953             URE_SPDWN_LINKCHG_MSK);
 954
 955         /* Disable Rx aggregation. */
 956         ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
 957             ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
 958             URE_RX_AGG_DISABLE);
 959
 960         /* Disable ALDPS. */
 961         ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
 962             URE_DIS_SDSAVE);
 963         uether_pause(&sc->sc_ue, hz / 50);
 964
 965         ure_init_fifo(sc);
 966
 967         ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
 968             URE_TX_AGG_MAX_THRESHOLD);
 969         ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
 970         ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
 971             URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
 972 }
 973
 974 static void
 975 ure_rtl8153_init(struct ure_softc *sc)
 976 {
 977         uint16_t val;
 978         uint8_t u1u2[8];
 979         int i;
 980
 981         /* Disable ALDPS. */
 982         ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
 983             ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
 984         uether_pause(&sc->sc_ue, hz / 50);
 985
 986         memset(u1u2, 0x00, sizeof(u1u2));
 987         ure_write_mem(sc, URE_USB_TOLERANCE,
 988             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
 989
 990         for (i = 0; i < URE_TIMEOUT; i++) {
 991                 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
 992                     URE_AUTOLOAD_DONE)
 993                         break;
 994                 uether_pause(&sc->sc_ue, hz / 100);
 995         }
 996         if (i == URE_TIMEOUT)
 997                 device_printf(sc->sc_ue.ue_dev,
 998                     "timeout waiting for chip autoload\n");
 999
1000         for (i = 0; i < URE_TIMEOUT; i++) {
1001                 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
1002                     URE_PHY_STAT_MASK;
1003                 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
1004                         break;
1005                 uether_pause(&sc->sc_ue, hz / 100);
1006         }
1007         if (i == URE_TIMEOUT)
1008                 device_printf(sc->sc_ue.ue_dev,
1009                     "timeout waiting for phy to stabilize\n");
1010
1011         ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,
1012             ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) &
1013             ~URE_U2P3_ENABLE);
1014
1015         if (sc->sc_chip & URE_CHIP_VER_5C10) {
1016                 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1017                 val &= ~URE_PWD_DN_SCALE_MASK;
1018                 val |= URE_PWD_DN_SCALE(96);
1019                 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
1020
1021                 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB,
1022                     ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) |
1023                     URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1024         } else if (sc->sc_chip & URE_CHIP_VER_5C20) {
1025                 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA,
1026                     ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) &
1027                     ~URE_ECM_ALDPS);
1028         }
1029         if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1030                 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
1031                 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
1032                     0)
1033                         val &= ~URE_DYNAMIC_BURST;
1034                 else
1035                         val |= URE_DYNAMIC_BURST;
1036                 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
1037         }
1038
1039         ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB,
1040             ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) |
1041             URE_EP4_FULL_FC);
1042
1043         ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB,
1044             ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) &
1045             ~URE_TIMER11_EN);
1046
1047         ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
1048             ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
1049             ~URE_LED_MODE_MASK);
1050
1051         if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
1052             usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
1053                 val = URE_LPM_TIMER_500MS;
1054         else
1055                 val = URE_LPM_TIMER_500US;
1056         ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1057             val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
1058
1059         val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1060         val &= ~URE_SEN_VAL_MASK;
1061         val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1062         ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
1063
1064         ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1065
1066         ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,
1067             ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) &
1068             ~(URE_PWR_EN | URE_PHASE2_EN));
1069         ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB,
1070             ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) &
1071             ~URE_PCUT_STATUS);
1072
1073         memset(u1u2, 0xff, sizeof(u1u2));
1074         ure_write_mem(sc, URE_USB_TOLERANCE,
1075             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1076
1077         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
1078             URE_ALDPS_SPDWN_RATIO);
1079         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1080             URE_EEE_SPDWN_RATIO);
1081         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1082             URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
1083             URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
1084         ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
1085             URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
1086             URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
1087             URE_EEE_SPDWN_EN);
1088
1089         val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1090         if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1091                 val |= URE_U2P3_ENABLE;
1092         else
1093                 val &= ~URE_U2P3_ENABLE;
1094         ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1095
1096         memset(u1u2, 0x00, sizeof(u1u2));
1097         ure_write_mem(sc, URE_USB_TOLERANCE,
1098             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1099
1100         /* Disable ALDPS. */
1101         ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1102             ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
1103         uether_pause(&sc->sc_ue, hz / 50);
1104
1105         ure_init_fifo(sc);
1106
1107         /* Disable Rx aggregation. */
1108         ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
1109             ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
1110             URE_RX_AGG_DISABLE);
1111
1112         val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1113         if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1114                 val |= URE_U2P3_ENABLE;
1115         else
1116                 val &= ~URE_U2P3_ENABLE;
1117         ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1118
1119         memset(u1u2, 0xff, sizeof(u1u2));
1120         ure_write_mem(sc, URE_USB_TOLERANCE,
1121             URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1122 }
1123
1124 static void
1125 ure_stop(struct usb_ether *ue)
1126 {
1127         struct ure_softc *sc = uether_getsc(ue);
1128         struct ifnet *ifp = uether_getifp(ue);
1129
1130         URE_LOCK_ASSERT(sc, MA_OWNED);
1131
1132         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1133         sc->sc_flags &= ~URE_FLAG_LINK;
1134
1135         /*
1136          * stop all the transfers, if not already stopped:
1137          */
1138         usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]);
1139         usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]);
1140 }
1141
1142 static void
1143 ure_disable_teredo(struct ure_softc *sc)
1144 {
1145
1146         ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
1147             ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) &
1148             ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
1149         ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA,
1150             URE_WDT6_SET_MODE);
1151         ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
1152         ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
1153 }
1154
1155 static void
1156 ure_init_fifo(struct ure_softc *sc)
1157 {
1158         uint32_t rx_fifo1, rx_fifo2;
1159         int i;
1160
1161         ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA,
1162             ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) |
1163             URE_RXDY_GATED_EN);
1164
1165         ure_disable_teredo(sc);
1166
1167         ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA,
1168             ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) &
1169             ~URE_RCR_ACPT_ALL);
1170
1171         if (!(sc->sc_flags & URE_FLAG_8152)) {
1172                 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1173                     URE_CHIP_VER_5C20)) {
1174                                 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
1175                                     URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1176                 }
1177                 if (sc->sc_chip & URE_CHIP_VER_5C00) {
1178                         ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
1179                             ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
1180                             ~URE_CTAP_SHORT_EN);
1181                 }
1182                 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1183                     ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1184                     URE_EEE_CLKDIV_EN);
1185                 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
1186                     ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
1187                     URE_EN_10M_BGOFF);
1188                 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1189                     ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1190                     URE_EN_10M_PLLOFF);
1191                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE);
1192                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13);
1193                 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
1194                     ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
1195                     URE_PFM_PWM_SWITCH);
1196
1197                 /* Enable LPF corner auto tune. */
1198                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG);
1199                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f);
1200
1201                 /* Adjust 10M amplitude. */
1202                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1);
1203                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af);
1204                 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2);
1205                 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208);
1206         }
1207
1208         ure_reset(sc);
1209
1210         ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
1211
1212         ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA,
1213             ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1214             ~URE_NOW_IS_OOB);
1215
1216         ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1217             ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) &
1218             ~URE_MCU_BORW_EN);
1219         for (i = 0; i < URE_TIMEOUT; i++) {
1220                 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1221                     URE_LINK_LIST_READY)
1222                         break;
1223                 uether_pause(&sc->sc_ue, hz / 100);
1224         }
1225         if (i == URE_TIMEOUT)
1226                 device_printf(sc->sc_ue.ue_dev,
1227                     "timeout waiting for OOB control\n");
1228         ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,
1229             ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) |
1230             URE_RE_INIT_LL);
1231         for (i = 0; i < URE_TIMEOUT; i++) {
1232                 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1233                     URE_LINK_LIST_READY)
1234                         break;
1235                 uether_pause(&sc->sc_ue, hz / 100);
1236         }
1237         if (i == URE_TIMEOUT)
1238                 device_printf(sc->sc_ue.ue_dev,
1239                     "timeout waiting for OOB control\n");
1240
1241         ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA,
1242             ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) &
1243             ~URE_CPCR_RX_VLAN);
1244         ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,
1245             ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) |
1246             URE_TCR0_AUTO_FIFO);
1247
1248         /* Configure Rx FIFO threshold. */
1249         ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
1250             URE_RXFIFO_THR1_NORMAL);
1251         if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
1252                 rx_fifo1 = URE_RXFIFO_THR2_FULL;
1253                 rx_fifo2 = URE_RXFIFO_THR3_FULL;
1254         } else {
1255                 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
1256                 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
1257         }
1258         ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
1259         ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
1260
1261         /* Configure Tx FIFO threshold. */
1262         ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
1263             URE_TXFIFO_THR_NORMAL);
1264 }