3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2010 Lev Serebryakov <lev@FreeBSD.org>.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #define UMCS7840_MAX_PORTS 4
34 #define UMCS7840_READ_LENGTH 1 /* bytes */
35 #define UMCS7840_CTRL_TIMEOUT 500 /* ms */
37 /* Read/Wrtire registers vendor commands */
38 #define MCS7840_RDREQ 0x0d
39 #define MCS7840_WRREQ 0x0e
41 /* Read/Wrtie EEPROM values */
42 #define MCS7840_EEPROM_RW_WVALUE 0x0900
45 * All these registers are documented only in full datasheet,
46 * which can be requested from MosChip tech support.
48 #define MCS7840_DEV_REG_SP1 0x00 /* Options for for UART 1, R/W */
49 #define MCS7840_DEV_REG_CONTROL1 0x01 /* Control bits for UART 1,
51 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong
53 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong
55 /* DCRx_1 Registers goes here (see below, they are documented) */
56 #define MCS7840_DEV_REG_GPIO 0x07 /* GPIO_0 and GPIO_1 bits,
57 * undocumented, see notes
59 #define MCS7840_DEV_REG_SP2 0x08 /* Options for for UART 2, R/W */
60 #define MCS7840_DEV_REG_CONTROL2 0x09 /* Control bits for UART 2,
62 #define MCS7840_DEV_REG_SP3 0x0a /* Options for for UART 3, R/W */
63 #define MCS7840_DEV_REG_CONTROL3 0x0b /* Control bits for UART 3,
65 #define MCS7840_DEV_REG_SP4 0x0c /* Options for for UART 4, R/W */
66 #define MCS7840_DEV_REG_CONTROL4 0x0d /* Control bits for UART 4,
68 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */
69 #define MCS7840_DEV_REG_UNKNOWN1 0x0f /* NOT MENTIONED AND NOT USED */
70 #define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */
71 #define MCS7840_DEV_REG_CLOCK_MUX 0x12 /* PLL input clock & Interrupt
72 * endpoint control, R/W */
73 #define MCS7840_DEV_REG_UNKNOWN2 0x11 /* NOT MENTIONED AND NOT USED */
74 #define MCS7840_DEV_REG_CLOCK_SELECT12 0x13 /* Clock source for ports 1 &
76 #define MCS7840_DEV_REG_CLOCK_SELECT34 0x14 /* Clock source for ports 3 &
78 #define MCS7840_DEV_REG_UNKNOWN3 0x15 /* NOT MENTIONED AND NOT USED */
79 /* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */
80 #define MCS7840_DEV_REG_UNKNOWN4 0x1f /* NOT MENTIONED AND NOT USED */
81 #define MCS7840_DEV_REG_UNKNOWN5 0x20 /* NOT MENTIONED AND NOT USED */
82 #define MCS7840_DEV_REG_UNKNOWN6 0x21 /* NOT MENTIONED AND NOT USED */
83 #define MCS7840_DEV_REG_UNKNOWN7 0x22 /* NOT MENTIONED AND NOT USED */
84 #define MCS7840_DEV_REG_UNKNOWN8 0x23 /* NOT MENTIONED AND NOT USED */
85 #define MCS7840_DEV_REG_UNKNOWN9 0x24 /* NOT MENTIONED AND NOT USED */
86 #define MCS7840_DEV_REG_UNKNOWNA 0x25 /* NOT MENTIONED AND NOT USED */
87 #define MCS7840_DEV_REG_UNKNOWNB 0x26 /* NOT MENTIONED AND NOT USED */
88 #define MCS7840_DEV_REG_UNKNOWNC 0x27 /* NOT MENTIONED AND NOT USED */
89 #define MCS7840_DEV_REG_UNKNOWND 0x28 /* NOT MENTIONED AND NOT USED */
90 #define MCS7840_DEV_REG_UNKNOWNE 0x29 /* NOT MENTIONED AND NOT USED */
91 #define MCS7840_DEV_REG_UNKNOWNF 0x2a /* NOT MENTIONED AND NOT USED */
92 #define MCS7840_DEV_REG_MODE 0x2b /* Hardware configuration,
94 #define MCS7840_DEV_REG_SP1_ICG 0x2c /* Inter character gap
95 * configuration for Port 1,
97 #define MCS7840_DEV_REG_SP2_ICG 0x2d /* Inter character gap
98 * configuration for Port 2,
100 #define MCS7840_DEV_REG_SP3_ICG 0x2e /* Inter character gap
101 * configuration for Port 3,
103 #define MCS7840_DEV_REG_SP4_ICG 0x2f /* Inter character gap
104 * configuration for Port 4,
106 #define MCS7840_DEV_REG_RX_SAMPLING12 0x30 /* RX sampling for ports 1 &
108 #define MCS7840_DEV_REG_RX_SAMPLING34 0x31 /* RX sampling for ports 3 &
110 #define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port
111 * 1, contains number of
112 * available bytes, R/Only */
113 #define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port
114 * 1, contains number of
115 * available bytes, R/Only */
116 #define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port
117 * 2, contains number of
118 * available bytes, R/Only */
119 #define MCS7840_DEV_REG_BO_FIFO_STAT2 0x35 /* Bulk-out FIFO Stat for Port
120 * 2, contains number of
121 * available bytes, R/Only */
122 #define MCS7840_DEV_REG_BI_FIFO_STAT3 0x36 /* Bulk-In FIFO Stat for Port
123 * 3, contains number of
124 * available bytes, R/Only */
125 #define MCS7840_DEV_REG_BO_FIFO_STAT3 0x37 /* Bulk-out FIFO Stat for Port
126 * 3, contains number of
127 * available bytes, R/Only */
128 #define MCS7840_DEV_REG_BI_FIFO_STAT4 0x38 /* Bulk-In FIFO Stat for Port
129 * 4, contains number of
130 * available bytes, R/Only */
131 #define MCS7840_DEV_REG_BO_FIFO_STAT4 0x39 /* Bulk-out FIFO Stat for Port
132 * 4, contains number of
133 * available bytes, R/Only */
134 #define MCS7840_DEV_REG_ZERO_PERIOD1 0x3a /* Period between zero out
135 * frames for Port 1, R/W */
136 #define MCS7840_DEV_REG_ZERO_PERIOD2 0x3b /* Period between zero out
137 * frames for Port 1, R/W */
138 #define MCS7840_DEV_REG_ZERO_PERIOD3 0x3c /* Period between zero out
139 * frames for Port 1, R/W */
140 #define MCS7840_DEV_REG_ZERO_PERIOD4 0x3d /* Period between zero out
141 * frames for Port 1, R/W */
142 #define MCS7840_DEV_REG_ZERO_ENABLE 0x3e /* Enable/disable of zero out
144 #define MCS7840_DEV_REG_THR_VAL_LOW1 0x3f /* Low 8 bits of threshold
145 * value for Bulk-Out for Port
147 #define MCS7840_DEV_REG_THR_VAL_HIGH1 0x40 /* High 1 bit of threshold
148 * value for Bulk-Out and
149 * enable flag for Port 1, R/W */
150 #define MCS7840_DEV_REG_THR_VAL_LOW2 0x41 /* Low 8 bits of threshold
151 * value for Bulk-Out for Port
153 #define MCS7840_DEV_REG_THR_VAL_HIGH2 0x42 /* High 1 bit of threshold
154 * value for Bulk-Out and
155 * enable flag for Port 2, R/W */
156 #define MCS7840_DEV_REG_THR_VAL_LOW3 0x43 /* Low 8 bits of threshold
157 * value for Bulk-Out for Port
159 #define MCS7840_DEV_REG_THR_VAL_HIGH3 0x44 /* High 1 bit of threshold
160 * value for Bulk-Out and
161 * enable flag for Port 3, R/W */
162 #define MCS7840_DEV_REG_THR_VAL_LOW4 0x45 /* Low 8 bits of threshold
163 * value for Bulk-Out for Port
165 #define MCS7840_DEV_REG_THR_VAL_HIGH4 0x46 /* High 1 bit of threshold
166 * value for Bulk-Out and
167 * enable flag for Port 4, R/W */
169 /* Bits for SPx registers */
170 #define MCS7840_DEV_SPx_LOOP_PIPES 0x01 /* Loop Bulk-Out FIFO to the
171 * Bulk-In FIFO, default = 0 */
172 #define MCS7840_DEV_SPx_SKIP_ERR_DATA 0x02 /* Drop data bytes from UART,
173 * which were recevied with
174 * errors, default = 0 */
175 #define MCS7840_DEV_SPx_RESET_OUT_FIFO 0x04 /* Reset Bulk-Out FIFO */
176 #define MCS7840_DEV_SPx_RESET_IN_FIFO 0x08 /* Reset Bulk-In FIFO */
177 #define MCS7840_DEV_SPx_CLOCK_MASK 0x70 /* Mask to extract Baud CLK
179 #define MCS7840_DEV_SPx_CLOCK_X1 0x00 /* CLK = 1.8432Mhz, max speed
180 * = 115200 bps, default */
181 #define MCS7840_DEV_SPx_CLOCK_X2 0x10 /* CLK = 3.6864Mhz, max speed
183 #define MCS7840_DEV_SPx_CLOCK_X35 0x20 /* CLK = 6.4512Mhz, max speed
185 #define MCS7840_DEV_SPx_CLOCK_X4 0x30 /* CLK = 7.3728Mhz, max speed
187 #define MCS7840_DEV_SPx_CLOCK_X7 0x40 /* CLK = 12.9024Mhz, max speed
189 #define MCS7840_DEV_SPx_CLOCK_X8 0x50 /* CLK = 14.7456Mhz, max speed
191 #define MCS7840_DEV_SPx_CLOCK_24MHZ 0x60 /* CLK = 24.0000Mhz, max speed
193 #define MCS7840_DEV_SPx_CLOCK_48MHZ 0x70 /* CLK = 48.0000Mhz, max speed
195 #define MCS7840_DEV_SPx_CLOCK_SHIFT 4 /* Value 0..7 can be shifted
196 * to get clock value */
197 #define MCS7840_DEV_SPx_UART_RESET 0x80 /* Reset UART */
199 /* Bits for CONTROLx registers */
200 #define MCS7840_DEV_CONTROLx_HWFC 0x01 /* Enable hardware flow
201 * control (when power
202 * down? It is unclear
205 #define MCS7840_DEV_CONTROLx_UNUNSED1 0x02 /* Reserved */
206 #define MCS7840_DEV_CONTROLx_CTS_ENABLE 0x04 /* CTS changes are
209 #define MCS7840_DEV_CONTROLx_UNUSED2 0x08 /* Reserved for ports
211 #define MCS7840_DEV_CONTROL1_DRIVER_DONE 0x08 /* USB enumerating is
214 * can be used as FIFOs */
215 #define MCS7840_DEV_CONTROLx_RX_NEGATE 0x10 /* Negate RX input,
216 * works for IrDA mode
217 * only, default = 0 */
218 #define MCS7840_DEV_CONTROLx_RX_DISABLE 0x20 /* Disable RX logic,
220 * RS-232/RS-485 mode,
222 #define MCS7840_DEV_CONTROLx_FSM_CONTROL 0x40 /* Disable RX FSM when
224 * works for IrDA mode
225 * only, default = 0 */
226 #define MCS7840_DEV_CONTROLx_UNUSED3 0x80 /* Reserved */
229 * Bits for PINPONGx registers
230 * These registers control how often two input buffers
231 * for Bulk-In FIFOs are swapped. One of buffers is used
232 * for USB trnasfer, other for receiving data from UART.
233 * Exact meaning of 15 bit value in these registers is unknown
235 #define MCS7840_DEV_PINPONGHIGH_MULT 128 /* Only 7 bits in PINPONGLOW
237 #define MCS7840_DEV_PINPONGLOW_BITS 7 /* Only 7 bits in PINPONGLOW
241 * THIS ONE IS UNDOCUMENTED IN FULL DATASHEET, but e-mail from tech support
242 * confirms, that it is register for GPIO_0 and GPIO_1 data input/output.
243 * Chips has 2 GPIO, but first one (lower bit) MUST be used by device
244 * authors as "number of port" indicator, grounded (0) for two-port
245 * devices and pulled-up to 1 for 4-port devices.
247 #define MCS7840_DEV_GPIO_4PORTS 0x01 /* Device has 4 ports
249 #define MCS7840_DEV_GPIO_GPIO_0 0x01 /* The same as above */
250 #define MCS7840_DEV_GPIO_GPIO_1 0x02 /* GPIO_1 data */
253 * Constants for PLL dividers
254 * Ouptut frequency of PLL is:
255 * Fout = (N/M) * Fin.
256 * Default PLL input frequency Fin is 12Mhz (on-chip).
258 #define MCS7840_DEV_PLL_DIV_M_BITS 6 /* Number of useful bits for M
260 #define MCS7840_DEV_PLL_DIV_M_MASK 0x3f /* Mask for M divider */
261 #define MCS7840_DEV_PLL_DIV_M_MIN 1 /* Minimum value for M, 0 is
263 #define MCS7840_DEV_PLL_DIV_M_DEF 1 /* Default value for M */
264 #define MCS7840_DEV_PLL_DIV_M_MAX 63 /* Maximum value for M */
265 #define MCS7840_DEV_PLL_DIV_N_BITS 6 /* Number of useful bits for N
267 #define MCS7840_DEV_PLL_DIV_N_MASK 0x3f /* Mask for N divider */
268 #define MCS7840_DEV_PLL_DIV_N_MIN 1 /* Minimum value for N, 0 is
270 #define MCS7840_DEV_PLL_DIV_N_DEF 8 /* Default value for N */
271 #define MCS7840_DEV_PLL_DIV_N_MAX 63 /* Maximum value for N */
273 /* Bits for CLOCK_MUX register */
274 #define MCS7840_DEV_CLOCK_MUX_INPUTMASK 0x03 /* Mask to extract PLL clock
276 #define MCS7840_DEV_CLOCK_MUX_IN12MHZ 0x00 /* 12Mhz PLL input, default */
277 #define MCS7840_DEV_CLOCK_MUX_INEXTRN 0x01 /* External (device-depended)
279 #define MCS7840_DEV_CLOCK_MUX_INRSV1 0x02 /* Reserved */
280 #define MCS7840_DEV_CLOCK_MUX_INRSV2 0x03 /* Reserved */
281 #define MCS7840_DEV_CLOCK_MUX_PLLHIGH 0x04 /* 0 = PLL Output is
282 * 20MHz-100MHz (default), 1 =
283 * 100MHz-300MHz range */
284 #define MCS7840_DEV_CLOCK_MUX_INTRFIFOS 0x08 /* Enable additional 8 bytes
285 * fro Interrupt USB pipe with
286 * USB FIFOs statuses, default
288 #define MCS7840_DEV_CLOCK_MUX_RESERVED1 0x10 /* Unused */
289 #define MCS7840_DEV_CLOCK_MUX_RESERVED2 0x20 /* Unused */
290 #define MCS7840_DEV_CLOCK_MUX_RESERVED3 0x40 /* Unused */
291 #define MCS7840_DEV_CLOCK_MUX_RESERVED4 0x80 /* Unused */
293 /* Bits for CLOCK_SELECTxx registers */
294 #define MCS7840_DEV_CLOCK_SELECT1_MASK 0x07 /* Bits for port 1 in
296 #define MCS7840_DEV_CLOCK_SELECT1_SHIFT 0 /* Shift for port 1in
298 #define MCS7840_DEV_CLOCK_SELECT2_MASK 0x38 /* Bits for port 2 in
300 #define MCS7840_DEV_CLOCK_SELECT2_SHIFT 3 /* Shift for port 2 in
302 #define MCS7840_DEV_CLOCK_SELECT3_MASK 0x07 /* Bits for port 3 in
304 #define MCS7840_DEV_CLOCK_SELECT3_SHIFT 0 /* Shift for port 3 in
306 #define MCS7840_DEV_CLOCK_SELECT4_MASK 0x38 /* Bits for port 4 in
308 #define MCS7840_DEV_CLOCK_SELECT4_SHIFT 3 /* Shift for port 4 in
310 #define MCS7840_DEV_CLOCK_SELECT_STD 0x00 /* STANDARD baudrate derived
311 * from 96Mhz, default for all
313 #define MCS7840_DEV_CLOCK_SELECT_30MHZ 0x01 /* 30Mhz */
314 #define MCS7840_DEV_CLOCK_SELECT_96MHZ 0x02 /* 96Mhz direct */
315 #define MCS7840_DEV_CLOCK_SELECT_120MHZ 0x03 /* 120Mhz */
316 #define MCS7840_DEV_CLOCK_SELECT_PLL 0x04 /* PLL output (see for M and N
318 #define MCS7840_DEV_CLOCK_SELECT_EXT 0x05 /* External clock input
319 * (device-dependend) */
320 #define MCS7840_DEV_CLOCK_SELECT_RES1 0x06 /* Unused */
321 #define MCS7840_DEV_CLOCK_SELECT_RES2 0x07 /* Unused */
323 /* Bits for MODE register */
324 #define MCS7840_DEV_MODE_RESERVED1 0x01 /* Unused */
325 #define MCS7840_DEV_MODE_RESET 0x02 /* 0: RESET = Active High
326 * (default), 1: Reserved (?) */
327 #define MCS7840_DEV_MODE_SER_PRSNT 0x04 /* 0: Reserved, 1: Do not use
328 * hardocded values (default)
330 #define MCS7840_DEV_MODE_PLLBYPASS 0x08 /* 1: PLL output is bypassed,
332 #define MCS7840_DEV_MODE_PORBYPASS 0x10 /* 1: Power-On Reset is
333 * bypassed, default = 0 */
334 #define MCS7840_DEV_MODE_SELECT24S 0x20 /* 0: 4 Serial Ports / IrDA
335 * active, 1: 2 Serial Ports /
337 #define MCS7840_DEV_MODE_EEPROMWR 0x40 /* EEPROM write is enabled,
339 #define MCS7840_DEV_MODE_IRDA 0x80 /* IrDA mode is activated
340 * (could be turned on),
343 /* Bits for SPx ICG */
344 #define MCS7840_DEV_SPx_ICG_DEF 0x24 /* All 8 bits is used as
345 * number of BAUD clocks of
349 * Bits for RX_SAMPLINGxx registers
350 * These registers control when bit value will be sampled within
352 * 0 is very beginning of period, 15 is very end, 7 is the middle.
354 #define MCS7840_DEV_RX_SAMPLING1_MASK 0x0f /* Bits for port 1 in
356 #define MCS7840_DEV_RX_SAMPLING1_SHIFT 0 /* Shift for port 1in
358 #define MCS7840_DEV_RX_SAMPLING2_MASK 0xf0 /* Bits for port 2 in
360 #define MCS7840_DEV_RX_SAMPLING2_SHIFT 4 /* Shift for port 2 in
362 #define MCS7840_DEV_RX_SAMPLING3_MASK 0x0f /* Bits for port 3 in
364 #define MCS7840_DEV_RX_SAMPLING3_SHIFT 0 /* Shift for port 3 in
366 #define MCS7840_DEV_RX_SAMPLING4_MASK 0xf0 /* Bits for port 4 in
368 #define MCS7840_DEV_RX_SAMPLING4_SHIFT 4 /* Shift for port 4 in
370 #define MCS7840_DEV_RX_SAMPLINGx_MIN 0 /* Max for any RX Sampling */
371 #define MCS7840_DEV_RX_SAMPLINGx_DEF 7 /* Default for any RX
372 * Sampling, center of period */
373 #define MCS7840_DEV_RX_SAMPLINGx_MAX 15 /* Min for any RX Sampling */
375 /* Bits for ZERO_PERIODx */
376 #define MCS7840_DEV_ZERO_PERIODx_DEF 20 /* Number of Bulk-in requests
377 * befor sending zero-sized
380 /* Bits for ZERO_ENABLE */
381 #define MCS7840_DEV_ZERO_ENABLE_PORT1 0x01 /* Enable of sending
382 * zero-sized replies for port
384 #define MCS7840_DEV_ZERO_ENABLE_PORT2 0x02 /* Enable of sending
385 * zero-sized replies for port
387 #define MCS7840_DEV_ZERO_ENABLE_PORT3 0x04 /* Enable of sending
388 * zero-sized replies for port
390 #define MCS7840_DEV_ZERO_ENABLE_PORT4 0x08 /* Enable of sending
391 * zero-sized replies for port
394 /* Bits for THR_VAL_HIGHx */
395 #define MCS7840_DEV_THR_VAL_HIGH_MASK 0x01 /* Only one bit is used */
396 #define MCS7840_DEV_THR_VAL_HIGH_MUL 256 /* This one bit is means "256" */
397 #define MCS7840_DEV_THR_VAL_HIGH_SHIFT 8 /* This one bit is means "256" */
398 #define MCS7840_DEV_THR_VAL_HIGH_ENABLE 0x80 /* Enable threshold */
400 /* These are documented in "public" datasheet */
401 #define MCS7840_DEV_REG_DCR0_1 0x04 /* Device contol register 0 for Port
403 #define MCS7840_DEV_REG_DCR1_1 0x05 /* Device contol register 1 for Port
405 #define MCS7840_DEV_REG_DCR2_1 0x06 /* Device contol register 2 for Port
407 #define MCS7840_DEV_REG_DCR0_2 0x16 /* Device contol register 0 for Port
409 #define MCS7840_DEV_REG_DCR1_2 0x17 /* Device contol register 1 for Port
411 #define MCS7840_DEV_REG_DCR2_2 0x18 /* Device contol register 2 for Port
413 #define MCS7840_DEV_REG_DCR0_3 0x19 /* Device contol register 0 for Port
415 #define MCS7840_DEV_REG_DCR1_3 0x1a /* Device contol register 1 for Port
417 #define MCS7840_DEV_REG_DCR2_3 0x1b /* Device contol register 2 for Port
419 #define MCS7840_DEV_REG_DCR0_4 0x1c /* Device contol register 0 for Port
421 #define MCS7840_DEV_REG_DCR1_4 0x1d /* Device contol register 1 for Port
423 #define MCS7840_DEV_REG_DCR2_4 0x1e /* Device contol register 2 for Port
426 /* Bits of DCR0 registers, documented in datasheet */
427 #define MCS7840_DEV_DCR0_PWRSAVE 0x01 /* Shutdown transiver
428 * when USB Suspend is
429 * engaged, default = 1 */
430 #define MCS7840_DEV_DCR0_RESERVED1 0x02 /* Unused */
431 #define MCS7840_DEV_DCR0_GPIO_MODE_MASK 0x0c /* GPIO Mode bits, WORKS
433 #define MCS7840_DEV_DCR0_GPIO_MODE_IN 0x00 /* GPIO Mode - Input
436 #define MCS7840_DEV_DCR0_GPIO_MODE_OUT 0x08 /* GPIO Mode - Input
439 #define MCS7840_DEV_DCR0_RTS_ACTIVE_HIGH 0x10 /* RTS Active is HIGH,
440 * default = 0 (low) */
441 #define MCS7840_DEV_DCR0_RTS_AUTO 0x20 /* RTS is controlled by
442 * state of TX buffer,
444 * (controlled by MCR) */
445 #define MCS7840_DEV_DCR0_IRDA 0x40 /* IrDA mode */
446 #define MCS7840_DEV_DCR0_RESERVED2 0x80 /* Unused */
448 /* Bits of DCR1 registers, documented in datasheet */
449 #define MCS7840_DEV_DCR1_GPIO_CURRENT_MASK 0x03 /* Mask to extract GPIO
450 * current value, WORKS
452 #define MCS7840_DEV_DCR1_GPIO_CURRENT_6MA 0x00 /* GPIO output current
453 * 6mA, WORKS ONLY FOR
455 #define MCS7840_DEV_DCR1_GPIO_CURRENT_8MA 0x01 /* GPIO output current
456 * 8mA, defauilt, WORKS
458 #define MCS7840_DEV_DCR1_GPIO_CURRENT_10MA 0x02 /* GPIO output current
459 * 10mA, WORKS ONLY FOR
461 #define MCS7840_DEV_DCR1_GPIO_CURRENT_12MA 0x03 /* GPIO output current
462 * 12mA, WORKS ONLY FOR
464 #define MCS7840_DEV_DCR1_UART_CURRENT_MASK 0x0c /* Mask to extract UART
465 * signals current value */
466 #define MCS7840_DEV_DCR1_UART_CURRENT_6MA 0x00 /* UART output current
468 #define MCS7840_DEV_DCR1_UART_CURRENT_8MA 0x04 /* UART output current
470 #define MCS7840_DEV_DCR1_UART_CURRENT_10MA 0x08 /* UART output current
472 #define MCS7840_DEV_DCR1_UART_CURRENT_12MA 0x0c /* UART output current
474 #define MCS7840_DEV_DCR1_WAKEUP_DISABLE 0x10 /* Disable Remote USB
476 #define MCS7840_DEV_DCR1_PLLPWRDOWN_DISABLE 0x20 /* Disable PLL power
477 * down when not needed,
478 * WORKS ONLY FOR PORT 1 */
479 #define MCS7840_DEV_DCR1_LONG_INTERRUPT 0x40 /* Enable 13 bytes of
480 * interrupt data, with
482 * WORKS ONLY FOR PORT 1 */
483 #define MCS7840_DEV_DCR1_RESERVED1 0x80 /* Unused */
486 * Bits of DCR2 registers, documented in datasheet
487 * Wakeup will work only if DCR0_IRDA = 0 (RS-xxx mode) and
488 * DCR1_WAKEUP_DISABLE = 0 (wakeup enabled).
490 #define MCS7840_DEV_DCR2_WAKEUP_CTS 0x01 /* Wakeup on CTS change,
492 #define MCS7840_DEV_DCR2_WAKEUP_DCD 0x02 /* Wakeup on DCD change,
494 #define MCS7840_DEV_DCR2_WAKEUP_RI 0x04 /* Wakeup on RI change,
496 #define MCS7840_DEV_DCR2_WAKEUP_DSR 0x08 /* Wakeup on DSR change,
498 #define MCS7840_DEV_DCR2_WAKEUP_RXD 0x10 /* Wakeup on RX Data change,
500 #define MCS7840_DEV_DCR2_WAKEUP_RESUME 0x20 /* Wakeup issues RESUME
502 * otherwise, default = 1 */
503 #define MCS7840_DEV_DCR2_RESERVED1 0x40 /* Unused */
504 #define MCS7840_DEV_DCR2_SHDN_POLARITY 0x80 /* 0: Pin 12 Active Low, 1:
505 * Pin 12 Active High, default
508 /* Interrupt endpoint bytes & bits */
509 #define MCS7840_IEP_FIFO_STATUS_INDEX 5
511 * Thesse can be calculated as "1 << portnumber" for Bulk-out and
512 * "1 << (portnumber+1)" for Bulk-in
514 #define MCS7840_IEP_BO_PORT1_HASDATA 0x01
515 #define MCS7840_IEP_BI_PORT1_HASDATA 0x02
516 #define MCS7840_IEP_BO_PORT2_HASDATA 0x04
517 #define MCS7840_IEP_BI_PORT2_HASDATA 0x08
518 #define MCS7840_IEP_BO_PORT3_HASDATA 0x10
519 #define MCS7840_IEP_BI_PORT3_HASDATA 0x20
520 #define MCS7840_IEP_BO_PORT4_HASDATA 0x40
521 #define MCS7840_IEP_BI_PORT4_HASDATA 0x80
523 /* Documented UART registers (fully compatible with 16550 UART) */
524 #define MCS7840_UART_REG_THR 0x00 /* Transmitter Holding
526 #define MCS7840_UART_REG_RHR 0x00 /* Receiver Holding Register
528 #define MCS7840_UART_REG_IER 0x01 /* Interrupt enable register -
530 #define MCS7840_UART_REG_FCR 0x02 /* FIFO Control register -
532 #define MCS7840_UART_REG_ISR 0x02 /* Interrupt Status Registter
534 #define MCS7840_UART_REG_LCR 0x03 /* Line control register R/W */
535 #define MCS7840_UART_REG_MCR 0x04 /* Modem control register R/W */
536 #define MCS7840_UART_REG_LSR 0x05 /* Line status register R/Only */
537 #define MCS7840_UART_REG_MSR 0x06 /* Modem status register
539 #define MCS7840_UART_REG_SCRATCHPAD 0x07 /* Scratch pad register */
541 #define MCS7840_UART_REG_DLL 0x00 /* Low bits of BAUD divider */
542 #define MCS7840_UART_REG_DLM 0x01 /* High bits of BAUD divider */
545 #define MCS7840_UART_IER_RXREADY 0x01 /* RX Ready interrumpt mask */
546 #define MCS7840_UART_IER_TXREADY 0x02 /* TX Ready interrumpt mask */
547 #define MCS7840_UART_IER_RXSTAT 0x04 /* RX Status interrumpt mask */
548 #define MCS7840_UART_IER_MODEM 0x08 /* Modem status change
550 #define MCS7840_UART_IER_SLEEP 0x10 /* SLEEP enable */
553 #define MCS7840_UART_FCR_ENABLE 0x01 /* Enable FIFO */
554 #define MCS7840_UART_FCR_FLUSHRHR 0x02 /* Flush RHR and FIFO */
555 #define MCS7840_UART_FCR_FLUSHTHR 0x04 /* Flush THR and FIFO */
556 #define MCS7840_UART_FCR_RTLMASK 0xa0 /* Mask to select RHR
557 * Interrupt Trigger level */
558 #define MCS7840_UART_FCR_RTL_1_1 0x00 /* L1 = 1, L2 = 1 */
559 #define MCS7840_UART_FCR_RTL_1_4 0x40 /* L1 = 1, L2 = 4 */
560 #define MCS7840_UART_FCR_RTL_1_8 0x80 /* L1 = 1, L2 = 8 */
561 #define MCS7840_UART_FCR_RTL_1_14 0xa0 /* L1 = 1, L2 = 14 */
564 #define MCS7840_UART_ISR_NOPENDING 0x01 /* No interrupt pending */
565 #define MCS7840_UART_ISR_INTMASK 0x3f /* Mask to select interrupt
567 #define MCS7840_UART_ISR_RXERR 0x06 /* Recevir error */
568 #define MCS7840_UART_ISR_RXHASDATA 0x04 /* Recevier has data */
569 #define MCS7840_UART_ISR_RXTIMEOUT 0x0c /* Recevier timeout */
570 #define MCS7840_UART_ISR_TXEMPTY 0x02 /* Transmitter empty */
571 #define MCS7840_UART_ISR_MSCHANGE 0x00 /* Modem status change */
574 #define MCS7840_UART_LCR_DATALENMASK 0x03 /* Mask for data length */
575 #define MCS7840_UART_LCR_DATALEN5 0x00 /* 5 data bits */
576 #define MCS7840_UART_LCR_DATALEN6 0x01 /* 6 data bits */
577 #define MCS7840_UART_LCR_DATALEN7 0x02 /* 7 data bits */
578 #define MCS7840_UART_LCR_DATALEN8 0x03 /* 8 data bits */
580 #define MCS7840_UART_LCR_STOPBMASK 0x04 /* Mask for stop bits */
581 #define MCS7840_UART_LCR_STOPB1 0x00 /* 1 stop bit in any case */
582 #define MCS7840_UART_LCR_STOPB2 0x04 /* 1.5-2 stop bits depends on
585 #define MCS7840_UART_LCR_PARITYMASK 0x38 /* Mask for all parity data */
586 #define MCS7840_UART_LCR_PARITYON 0x08 /* Parity ON/OFF - ON */
587 #define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */
588 #define MCS7840_UART_LCR_PARITYEVEN 0x10 /* Parity Even */
589 #define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */
590 #define MCS7840_UART_LCR_PARITYFORCE 0x20 /* Force parity odd/even */
592 #define MCS7840_UART_LCR_BREAK 0x40 /* Send BREAK */
593 #define MCS7840_UART_LCR_DIVISORS 0x80 /* Map DLL/DLM instead of
597 #define MCS7840_UART_LSR_RHRAVAIL 0x01 /* Data available for read */
598 #define MCS7840_UART_LSR_RHROVERRUN 0x02 /* Data FIFO/register overflow */
599 #define MCS7840_UART_LSR_PARITYERR 0x04 /* Parity error */
600 #define MCS7840_UART_LSR_FRAMEERR 0x10 /* Framing error */
601 #define MCS7840_UART_LSR_BREAKERR 0x20 /* BREAK signal received */
602 #define MCS7840_UART_LSR_THREMPTY 0x40 /* THR register is empty,
603 * ready for transmit */
604 #define MCS7840_UART_LSR_HASERR 0x80 /* Has error in receiver FIFO */
607 #define MCS7840_UART_MCR_DTR 0x01 /* Force DTR to be active
609 #define MCS7840_UART_MCR_RTS 0x02 /* Force RTS to be active
611 #define MCS7840_UART_MCR_IE 0x04 /* Enable interrupts (from
612 * code, not documented) */
613 #define MCS7840_UART_MCR_LOOPBACK 0x10 /* Enable local loopback test
615 #define MCS7840_UART_MCR_CTSRTS 0x20 /* Enable CTS/RTS flow control
616 * in 550 (FIFO) mode */
617 #define MCS7840_UART_MCR_DTRDSR 0x40 /* Enable DTR/DSR flow control
618 * in 550 (FIFO) mode */
619 #define MCS7840_UART_MCR_DCD 0x80 /* Enable DCD flow control in
623 #define MCS7840_UART_MSR_DELTACTS 0x01 /* CTS was changed since last
625 #define MCS7840_UART_MSR_DELTADSR 0x02 /* DSR was changed since last
627 #define MCS7840_UART_MSR_DELTARI 0x04 /* RI was changed from low to
628 * high since last read */
629 #define MCS7840_UART_MSR_DELTADCD 0x08 /* DCD was changed since last
631 #define MCS7840_UART_MSR_NEGCTS 0x10 /* Negated CTS signal */
632 #define MCS7840_UART_MSR_NEGDSR 0x20 /* Negated DSR signal */
633 #define MCS7840_UART_MSR_NEGRI 0x40 /* Negated RI signal */
634 #define MCS7840_UART_MSR_NEGDCD 0x80 /* Negated DCD signal */
636 /* SCRATCHPAD bits */
637 #define MCS7840_UART_SCRATCHPAD_RS232 0x00 /* RS-485 disabled */
638 #define MCS7840_UART_SCRATCHPAD_RS485_DTRRX 0x80 /* RS-485 mode, DTR High
640 #define MCS7840_UART_SCRATCHPAD_RS485_DTRTX 0xc0 /* RS-485 mode, DTR High
643 #define MCS7840_CONFIG_INDEX 0
644 #define MCS7840_IFACE_INDEX 0