1 /* $NetBSD: uhcireg.h,v 1.15 2002/02/11 11:41:30 augustss Exp $ */
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Lennart Augustsson (lennart@augustsson.net) at
10 * Carlstedt Research & Technology.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the NetBSD
23 * Foundation, Inc. and its contributors.
24 * 4. Neither the name of The NetBSD Foundation nor the names of its
25 * contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
41 #ifndef _DEV_PCI_UHCIREG_H_
42 #define _DEV_PCI_UHCIREG_H_
44 /*** PCI config registers ***/
46 #define PCI_USBREV 0x60 /* USB protocol revision */
47 #define PCI_USBREV_MASK 0xff
48 #define PCI_USBREV_PRE_1_0 0x00
49 #define PCI_USBREV_1_0 0x10
50 #define PCI_USBREV_1_1 0x11
52 #define PCI_LEGSUP 0xc0 /* Legacy Support register */
53 #define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */
55 #define PCI_CBIO 0x20 /* configuration base IO */
57 #define PCI_INTERFACE_UHCI 0x00
59 /*** UHCI registers ***/
62 #define UHCI_CMD_RS 0x0001
63 #define UHCI_CMD_HCRESET 0x0002
64 #define UHCI_CMD_GRESET 0x0004
65 #define UHCI_CMD_EGSM 0x0008
66 #define UHCI_CMD_FGR 0x0010
67 #define UHCI_CMD_SWDBG 0x0020
68 #define UHCI_CMD_CF 0x0040
69 #define UHCI_CMD_MAXP 0x0080
72 #define UHCI_STS_USBINT 0x0001
73 #define UHCI_STS_USBEI 0x0002
74 #define UHCI_STS_RD 0x0004
75 #define UHCI_STS_HSE 0x0008
76 #define UHCI_STS_HCPE 0x0010
77 #define UHCI_STS_HCH 0x0020
78 #define UHCI_STS_ALLINTRS 0x003f
80 #define UHCI_INTR 0x04
81 #define UHCI_INTR_TOCRCIE 0x0001
82 #define UHCI_INTR_RIE 0x0002
83 #define UHCI_INTR_IOCE 0x0004
84 #define UHCI_INTR_SPIE 0x0008
86 #define UHCI_FRNUM 0x06
87 #define UHCI_FRNUM_MASK 0x03ff
89 #define UHCI_FLBASEADDR 0x08
92 #define UHCI_SOF_MASK 0x7f
94 #define UHCI_PORTSC1 0x010
95 #define UHCI_PORTSC2 0x012
96 #define UHCI_PORTSC_CCS 0x0001
97 #define UHCI_PORTSC_CSC 0x0002
98 #define UHCI_PORTSC_PE 0x0004
99 #define UHCI_PORTSC_POEDC 0x0008
100 #define UHCI_PORTSC_LS 0x0030
101 #define UHCI_PORTSC_LS_SHIFT 4
102 #define UHCI_PORTSC_RD 0x0040
103 #define UHCI_PORTSC_LSDA 0x0100
104 #define UHCI_PORTSC_PR 0x0200
105 #define UHCI_PORTSC_OCI 0x0400
106 #define UHCI_PORTSC_OCIC 0x0800
107 #define UHCI_PORTSC_SUSP 0x1000
110 ((x) & (UHCI_PORTSC_SUSP | UHCI_PORTSC_PR | UHCI_PORTSC_RD | UHCI_PORTSC_PE))
112 #define UHCI_FRAMELIST_COUNT 1024
113 #define UHCI_FRAMELIST_ALIGN 4096
115 #define UHCI_TD_ALIGN 16
116 #define UHCI_QH_ALIGN 16
118 typedef u_int32_t uhci_physaddr_t;
119 #define UHCI_PTR_T 0x00000001
120 #define UHCI_PTR_TD 0x00000000
121 #define UHCI_PTR_QH 0x00000002
122 #define UHCI_PTR_VF 0x00000004
125 * Wait this long after a QH has been removed. This gives that HC a
126 * chance to stop looking at it before it's recycled.
128 #define UHCI_QH_REMOVE_DELAY 5
131 * The Queue Heads and Transfer Descriptors are accessed
132 * by both the CPU and the USB controller which run
133 * concurrently. This means that they have to be accessed
134 * with great care. As long as the data structures are
135 * not linked into the controller's frame list they cannot
136 * be accessed by it and anything goes. As soon as a
137 * TD is accessible by the controller it "owns" the td_status
138 * field; it will not be written by the CPU. Similarly
139 * the controller "owns" the qh_elink field.
143 uhci_physaddr_t td_link;
145 #define UHCI_TD_GET_ACTLEN(s) (((s) + 1) & 0x3ff)
146 #define UHCI_TD_ZERO_ACTLEN(t) ((t) | 0x3ff)
147 #define UHCI_TD_BITSTUFF 0x00020000
148 #define UHCI_TD_CRCTO 0x00040000
149 #define UHCI_TD_NAK 0x00080000
150 #define UHCI_TD_BABBLE 0x00100000
151 #define UHCI_TD_DBUFFER 0x00200000
152 #define UHCI_TD_STALLED 0x00400000
153 #define UHCI_TD_ACTIVE 0x00800000
154 #define UHCI_TD_IOC 0x01000000
155 #define UHCI_TD_IOS 0x02000000
156 #define UHCI_TD_LS 0x04000000
157 #define UHCI_TD_GET_ERRCNT(s) (((s) >> 27) & 3)
158 #define UHCI_TD_SET_ERRCNT(n) ((n) << 27)
159 #define UHCI_TD_SPD 0x20000000
161 #define UHCI_TD_PID_IN 0x00000069
162 #define UHCI_TD_PID_OUT 0x000000e1
163 #define UHCI_TD_PID_SETUP 0x0000002d
164 #define UHCI_TD_GET_PID(s) ((s) & 0xff)
165 #define UHCI_TD_SET_DEVADDR(a) ((a) << 8)
166 #define UHCI_TD_GET_DEVADDR(s) (((s) >> 8) & 0x7f)
167 #define UHCI_TD_SET_ENDPT(e) (((e)&0xf) << 15)
168 #define UHCI_TD_GET_ENDPT(s) (((s) >> 15) & 0xf)
169 #define UHCI_TD_SET_DT(t) ((t) << 19)
170 #define UHCI_TD_GET_DT(s) (((s) >> 19) & 1)
171 #define UHCI_TD_SET_MAXLEN(l) (((l)-1) << 21)
172 #define UHCI_TD_GET_MAXLEN(s) ((((s) >> 21) + 1) & 0x7ff)
173 #define UHCI_TD_MAXLEN_MASK 0xffe00000
177 #define UHCI_TD_ERROR (UHCI_TD_BITSTUFF|UHCI_TD_CRCTO|UHCI_TD_BABBLE|UHCI_TD_DBUFFER|UHCI_TD_STALLED)
179 #define UHCI_TD_SETUP(len, endp, dev) (UHCI_TD_SET_MAXLEN(len) | \
180 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_SETUP)
181 #define UHCI_TD_OUT(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \
182 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | \
183 UHCI_TD_PID_OUT | UHCI_TD_SET_DT(dt))
184 #define UHCI_TD_IN(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \
185 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_IN | \
189 uhci_physaddr_t qh_hlink;
190 uhci_physaddr_t qh_elink;
193 #endif /* _DEV_PCI_UHCIREG_H_ */