2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $
21 #define R92S_REQ_REGS 0x05
26 #define R92S_SYSCFG 0x0000
27 #define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000)
28 #define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002)
29 #define R92S_PMC_FSM (R92S_SYSCFG + 0x004)
30 #define R92S_SYS_CLKR (R92S_SYSCFG + 0x008)
31 #define R92S_EE_9346CR (R92S_SYSCFG + 0x00a)
32 #define R92S_AFE_MISC (R92S_SYSCFG + 0x010)
33 #define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011)
34 #define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018)
35 #define R92S_RF_CTRL (R92S_SYSCFG + 0x01f)
36 #define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020)
37 #define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021)
38 #define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026)
39 #define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028)
40 #define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030)
41 #define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034)
42 #define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8)
44 #define R92S_CMDCTRL 0x0040
45 #define R92S_CR (R92S_CMDCTRL + 0x000)
46 #define R92S_TCR (R92S_CMDCTRL + 0x004)
47 #define R92S_RCR (R92S_CMDCTRL + 0x008)
49 #define R92S_MACIDSETTING 0x0050
50 #define R92S_MACID (R92S_MACIDSETTING + 0x000)
52 #define R92S_GP 0x01e0
53 #define R92S_GPIO_CTRL (R92S_GP + 0x00c)
54 #define R92S_GPIO_IO_SEL (R92S_GP + 0x00e)
55 #define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011)
57 #define R92S_IOCMD_CTRL 0x0370
58 #define R92S_IOCMD_DATA 0x0374
60 #define R92S_USB_HRPWM 0xfe58
62 /* Bits for R92S_SYS_FUNC_EN. */
63 #define R92S_FEN_CPUEN 0x0400
65 /* Bits for R92S_PMC_FSM. */
66 #define R92S_PMC_FSM_CUT_M 0x000f8000
67 #define R92S_PMC_FSM_CUT_S 15
69 /* Bits for R92S_SYS_CLKR. */
70 #define R92S_SYS_CLKSEL 0x0001
71 #define R92S_SYS_PS_CLKSEL 0x0002
72 #define R92S_SYS_CPU_CLKSEL 0x0004
73 #define R92S_MAC_CLK_EN 0x0800
74 #define R92S_SYS_CLK_EN 0x1000
75 #define R92S_SWHW_SEL 0x4000
76 #define R92S_FWHW_SEL 0x8000
78 /* Bits for R92S_EE_9346CR. */
79 #define R92S_9356SEL 0x10
80 #define R92S_EEPROM_EN 0x20
82 /* Bits for R92S_AFE_MISC. */
83 #define R92S_AFE_MISC_BGEN 0x01
84 #define R92S_AFE_MISC_MBEN 0x02
85 #define R92S_AFE_MISC_I32_EN 0x08
87 /* Bits for R92S_SPS1_CTRL. */
88 #define R92S_SPS1_LDEN 0x01
89 #define R92S_SPS1_SWEN 0x02
91 /* Bits for R92S_LDOA15_CTRL. */
92 #define R92S_LDA15_EN 0x01
94 /* Bits for R92S_LDOV12D_CTRL. */
95 #define R92S_LDV12_EN 0x01
97 /* Bits for R92C_EFUSE_CTRL. */
98 #define R92S_EFUSE_CTRL_DATA_M 0x000000ff
99 #define R92S_EFUSE_CTRL_DATA_S 0
100 #define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00
101 #define R92S_EFUSE_CTRL_ADDR_S 8
102 #define R92S_EFUSE_CTRL_VALID 0x80000000
104 /* Bits for R92S_CR. */
105 #define R92S_CR_TXDMA_EN 0x10
107 /* Bits for R92S_TCR. */
108 #define R92S_TCR_IMEM_CODE_DONE 0x01
109 #define R92S_TCR_IMEM_CHK_RPT 0x02
110 #define R92S_TCR_EMEM_CODE_DONE 0x04
111 #define R92S_TCR_EMEM_CHK_RPT 0x08
112 #define R92S_TCR_DMEM_CODE_DONE 0x10
113 #define R92S_TCR_IMEM_RDY 0x20
114 #define R92S_TCR_FWRDY 0x80
116 /* Bits for R92S_GPIO_IO_SEL. */
117 #define R92S_GPIO_WPS 0x10
119 /* Bits for R92S_MAC_PINMUX_CTRL. */
120 #define R92S_GPIOSEL_GPIO_M 0x03
121 #define R92S_GPIOSEL_GPIO_S 0
122 #define R92S_GPIOSEL_GPIO_JTAG 0
123 #define R92S_GPIOSEL_GPIO_PHYDBG 1
124 #define R92S_GPIOSEL_GPIO_BT 2
125 #define R92S_GPIOSEL_GPIO_WLANDBG 3
126 #define R92S_GPIOMUX_EN 0x08
128 /* Bits for R92S_IOCMD_CTRL. */
129 #define R92S_IOCMD_CLASS_M 0xff000000
130 #define R92S_IOCMD_CLASS_S 24
131 #define R92S_IOCMD_CLASS_BB_RF 0xf0
132 #define R92S_IOCMD_VALUE_M 0x00ffff00
133 #define R92S_IOCMD_VALUE_S 8
134 #define R92S_IOCMD_INDEX_M 0x000000ff
135 #define R92S_IOCMD_INDEX_S 0
136 #define R92S_IOCMD_INDEX_BB_READ 0
137 #define R92S_IOCMD_INDEX_BB_WRITE 1
138 #define R92S_IOCMD_INDEX_RF_READ 2
139 #define R92S_IOCMD_INDEX_RF_WRITE 3
141 /* Bits for R92S_USB_HRPWM. */
142 #define R92S_USB_HRPWM_PS_ALL_ON 0x04
143 #define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08
146 * Macros to access subfields in registers.
148 /* Mask and Shift (getter). */
149 #define MS(val, field) \
150 (((val) & field##_M) >> field##_S)
152 /* Shift and Mask (setter). */
153 #define SM(field, val) \
154 (((val) << field##_S) & field##_M)
157 #define RW(var, field, val) \
158 (((var) & ~field##_M) | SM(field, val))
161 * ROM field with RF config.
164 RTL8712_RFCONFIG_1T = 0x10,
165 RTL8712_RFCONFIG_2T = 0x20,
166 RTL8712_RFCONFIG_1R = 0x01,
167 RTL8712_RFCONFIG_2R = 0x02,
168 RTL8712_RFCONFIG_1T1R = 0x11,
169 RTL8712_RFCONFIG_1T2R = 0x12,
170 RTL8712_RFCONFIG_TURBO = 0x92,
171 RTL8712_RFCONFIG_2T2R = 0x22
175 * Firmware image header.
177 struct r92s_fw_priv {
181 #define R92S_HCI_SEL_PCIE 0x01
182 #define R92S_HCI_SEL_USB 0x02
183 #define R92S_HCI_SEL_SDIO 0x04
184 #define R92S_HCI_SEL_8172 0x10
185 #define R92S_HCI_SEL_AP 0x80
187 uint8_t chip_version;
190 //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R
197 uint8_t lowpower_mode;
202 #define R92S_VCS_TYPE_DISABLE 0
203 #define R92S_VCS_TYPE_ENABLE 1
204 #define R92S_VCS_TYPE_AUTO 2
207 #define R92S_VCS_MODE_NONE 0
208 #define R92S_VCS_MODE_RTS_CTS 1
209 #define R92S_VCS_MODE_CTS2SELF 2
215 uint8_t amsdu2ampdu_en;
221 uint8_t beacon_offload;
222 uint8_t mlme_offload;
223 uint8_t hwpc_offload;
224 uint8_t tcpcsum_offload;
227 uint8_t wwlan_offload;
243 uint16_t h2c_resp_addr;
249 struct r92s_fw_priv priv;
252 /* Structure for FW commands and FW events notifications. */
253 struct r92s_fw_cmd_hdr {
257 #define R92S_FW_CMD_MORE 0x80
262 /* FW commands codes. */
263 #define R92S_CMD_READ_MACREG 0
264 #define R92S_CMD_WRITE_MACREG 1
265 #define R92S_CMD_READ_BBREG 2
266 #define R92S_CMD_WRITE_BBREG 3
267 #define R92S_CMD_READ_RFREG 4
268 #define R92S_CMD_WRITE_RFREG 5
269 #define R92S_CMD_READ_EEPROM 6
270 #define R92S_CMD_WRITE_EEPROM 7
271 #define R92S_CMD_READ_EFUSE 8
272 #define R92S_CMD_WRITE_EFUSE 9
273 #define R92S_CMD_READ_CAM 10
274 #define R92S_CMD_WRITE_CAM 11
275 #define R92S_CMD_SET_BCNITV 12
276 #define R92S_CMD_SET_MBIDCFG 13
277 #define R92S_CMD_JOIN_BSS 14
278 #define R92S_CMD_DISCONNECT 15
279 #define R92S_CMD_CREATE_BSS 16
280 #define R92S_CMD_SET_OPMODE 17
281 #define R92S_CMD_SITE_SURVEY 18
282 #define R92S_CMD_SET_AUTH 19
283 #define R92S_CMD_SET_KEY 20
284 #define R92S_CMD_SET_STA_KEY 21
285 #define R92S_CMD_SET_ASSOC_STA 22
286 #define R92S_CMD_DEL_ASSOC_STA 23
287 #define R92S_CMD_SET_STAPWRSTATE 24
288 #define R92S_CMD_SET_BASIC_RATE 25
289 #define R92S_CMD_GET_BASIC_RATE 26
290 #define R92S_CMD_SET_DATA_RATE 27
291 #define R92S_CMD_GET_DATA_RATE 28
292 #define R92S_CMD_SET_PHY_INFO 29
293 #define R92S_CMD_GET_PHY_INFO 30
294 #define R92S_CMD_SET_PHY 31
295 #define R92S_CMD_GET_PHY 32
296 #define R92S_CMD_READ_RSSI 33
297 #define R92S_CMD_READ_GAIN 34
298 #define R92S_CMD_SET_ATIM 35
299 #define R92S_CMD_SET_PWR_MODE 36
300 #define R92S_CMD_JOIN_BSS_RPT 37
301 #define R92S_CMD_SET_RA_TABLE 38
302 #define R92S_CMD_GET_RA_TABLE 39
303 #define R92S_CMD_GET_CCX_REPORT 40
304 #define R92S_CMD_GET_DTM_REPORT 41
305 #define R92S_CMD_GET_TXRATE_STATS 42
306 #define R92S_CMD_SET_USB_SUSPEND 43
307 #define R92S_CMD_SET_H2C_LBK 44
308 #define R92S_CMD_ADDBA_REQ 45
309 #define R92S_CMD_SET_CHANNEL 46
310 #define R92S_CMD_SET_TXPOWER 47
311 #define R92S_CMD_SWITCH_ANTENNA 48
312 #define R92S_CMD_SET_CRYSTAL_CAL 49
313 #define R92S_CMD_SET_SINGLE_CARRIER_TX 50
314 #define R92S_CMD_SET_SINGLE_TONE_TX 51
315 #define R92S_CMD_SET_CARRIER_SUPPR_TX 52
316 #define R92S_CMD_SET_CONTINUOUS_TX 53
317 #define R92S_CMD_SWITCH_BANDWIDTH 54
318 #define R92S_CMD_TX_BEACON 55
319 #define R92S_CMD_SET_POWER_TRACKING 56
320 #define R92S_CMD_AMSDU_TO_AMPDU 57
321 #define R92S_CMD_SET_MAC_ADDRESS 58
322 #define R92S_CMD_GET_H2C_LBK 59
323 #define R92S_CMD_SET_PBREQ_IE 60
324 #define R92S_CMD_SET_ASSOCREQ_IE 61
325 #define R92S_CMD_SET_PBRESP_IE 62
326 #define R92S_CMD_SET_ASSOCRESP_IE 63
327 #define R92S_CMD_GET_CURDATARATE 64
328 #define R92S_CMD_GET_TXRETRY_CNT 65
329 #define R92S_CMD_GET_RXRETRY_CNT 66
330 #define R92S_CMD_GET_BCNOK_CNT 67
331 #define R92S_CMD_GET_BCNERR_CNT 68
332 #define R92S_CMD_GET_CURTXPWR_LEVEL 69
333 #define R92S_CMD_SET_DIG 70
334 #define R92S_CMD_SET_RA 71
335 #define R92S_CMD_SET_PT 72
336 #define R92S_CMD_READ_TSSI 73
338 /* FW events notifications codes. */
339 #define R92S_EVT_READ_MACREG 0
340 #define R92S_EVT_READ_BBREG 1
341 #define R92S_EVT_READ_RFREG 2
342 #define R92S_EVT_READ_EEPROM 3
343 #define R92S_EVT_READ_EFUSE 4
344 #define R92S_EVT_READ_CAM 5
345 #define R92S_EVT_GET_BASICRATE 6
346 #define R92S_EVT_GET_DATARATE 7
347 #define R92S_EVT_SURVEY 8
348 #define R92S_EVT_SURVEY_DONE 9
349 #define R92S_EVT_JOIN_BSS 10
350 #define R92S_EVT_ADD_STA 11
351 #define R92S_EVT_DEL_STA 12
352 #define R92S_EVT_ATIM_DONE 13
353 #define R92S_EVT_TX_REPORT 14
354 #define R92S_EVT_CCX_REPORT 15
355 #define R92S_EVT_DTM_REPORT 16
356 #define R92S_EVT_TXRATE_STATS 17
357 #define R92S_EVT_C2H_LBK 18
358 #define R92S_EVT_FWDBG 19
359 #define R92S_EVT_C2H_FEEDBACK 20
360 #define R92S_EVT_ADDBA 21
361 #define R92S_EVT_C2H_BCN 22
362 #define R92S_EVT_PWR_STATE 23
363 #define R92S_EVT_WPS_PBC 24
364 #define R92S_EVT_ADDBA_REQ_REPORT 25
366 /* Structure for R92S_CMD_SITE_SURVEY. */
367 struct r92s_fw_cmd_sitesurvey {
371 uint8_t ssid[32 + 1];
374 /* Structure for R92S_CMD_SET_AUTH. */
375 struct r92s_fw_cmd_auth {
377 #define R92S_AUTHMODE_OPEN 0
378 #define R92S_AUTHMODE_SHARED 1
379 #define R92S_AUTHMODE_WPA 2
384 /* Structure for R92S_CMD_SET_KEY. */
385 struct r92s_fw_cmd_set_key {
387 #define R92S_KEY_ALGO_NONE 0
388 #define R92S_KEY_ALGO_WEP40 1
389 #define R92S_KEY_ALGO_TKIP 2
390 #define R92S_KEY_ALGO_TKIP_MMIC 3
391 #define R92S_KEY_ALGO_AES 4
392 #define R92S_KEY_ALGO_WEP104 5
399 /* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */
400 /* NDIS_802_11_SSID. */
401 struct ndis_802_11_ssid {
406 /* NDIS_802_11_CONFIGURATION_FH. */
407 struct ndis_802_11_configuration_fh {
414 /* NDIS_802_11_CONFIGURATION. */
415 struct ndis_802_11_configuration {
420 struct ndis_802_11_configuration_fh fhconfig;
423 /* NDIS_WLAN_BSSID_EX. */
424 struct ndis_wlan_bssid_ex {
426 uint8_t macaddr[IEEE80211_ADDR_LEN];
428 struct ndis_802_11_ssid ssid;
431 uint32_t networktype;
432 #define NDIS802_11FH 0
433 #define NDIS802_11DS 1
434 #define NDIS802_11OFDM5 2
435 #define NDIS802_11OFDM24 3
436 #define NDIS802_11AUTOMODE 4
438 struct ndis_802_11_configuration config;
440 #define NDIS802_11IBSS 0
441 #define NDIS802_11INFRASTRUCTURE 1
442 #define NDIS802_11AUTOUNKNOWN 2
443 #define NDIS802_11MONITOR 3
444 #define NDIS802_11APMODE 4
446 uint8_t supprates[16];
448 /* Followed by ``ieslen'' bytes. */
451 /* NDIS_802_11_FIXED_IEs. */
452 struct ndis_802_11_fixed_ies {
455 uint16_t capabilities;
458 /* Structure for R92S_CMD_SET_PWR_MODE. */
459 struct r92s_set_pwr_mode {
461 #define R92S_PS_MODE_ACTIVE 0
462 #define R92S_PS_MODE_MIN 1
463 #define R92S_PS_MODE_MAX 2
464 #define R92S_PS_MODE_DTIM 3
465 #define R92S_PS_MODE_VOIP 4
466 #define R92S_PS_MODE_UAPSD_WMM 5
467 #define R92S_PS_MODE_UAPSD 6
468 #define R92S_PS_MODE_IBSS 7
469 #define R92S_PS_MODE_WWLAN 8
470 #define R92S_PS_MODE_RADIOOFF 9
471 #define R92S_PS_MODE_DISABLE 10
473 uint8_t low_traffic_en;
475 uint8_t rf_low_snr_en;
478 uint8_t bcn_pass_cnt;
482 uint8_t awake_bcn_itv;
484 uint8_t bcn_pass_time;
487 /* Structure for event R92S_EVENT_JOIN_BSS. */
488 struct r92s_event_join_bss {
491 uint32_t networktype;
493 uint32_t lastscanned;
496 struct ndis_wlan_bssid_ex bss;
499 #define R92S_MACID_BSS 5
501 /* Rx MAC descriptor. */
502 struct r92s_rx_stat {
504 #define R92S_RXDW0_PKTLEN_M 0x00003fff
505 #define R92S_RXDW0_PKTLEN_S 0
506 #define R92S_RXDW0_CRCERR 0x00004000
507 #define R92S_RXDW0_INFOSZ_M 0x000f0000
508 #define R92S_RXDW0_INFOSZ_S 16
509 #define R92S_RXDW0_QOS 0x00800000
510 #define R92S_RXDW0_SHIFT_M 0x03000000
511 #define R92S_RXDW0_SHIFT_S 24
512 #define R92S_RXDW0_DECRYPTED 0x08000000
515 #define R92S_RXDW1_MOREFRAG 0x08000000
518 #define R92S_RXDW2_FRAG_M 0x0000f000
519 #define R92S_RXDW2_FRAG_S 12
520 #define R92S_RXDW2_PKTCNT_M 0x00ff0000
521 #define R92S_RXDW2_PKTCNT_S 16
524 #define R92S_RXDW3_RATE_M 0x0000003f
525 #define R92S_RXDW3_RATE_S 0
526 #define R92S_RXDW3_TCPCHKRPT 0x00000800
527 #define R92S_RXDW3_IPCHKRPT 0x00001000
528 #define R92S_RXDW3_TCPCHKVALID 0x00002000
529 #define R92S_RXDW3_HTC 0x00004000
533 } __packed __aligned(4);
535 /* Rx PHY descriptor. */
536 struct r92s_rx_phystat {
545 } __packed __aligned(4);
547 /* Rx PHY CCK descriptor. */
554 /* Tx MAC descriptor. */
555 struct r92s_tx_desc {
557 #define R92S_TXDW0_PKTLEN_M 0x0000ffff
558 #define R92S_TXDW0_PKTLEN_S 0
559 #define R92S_TXDW0_OFFSET_M 0x00ff0000
560 #define R92S_TXDW0_OFFSET_S 16
561 #define R92S_TXDW0_TYPE_M 0x03000000
562 #define R92S_TXDW0_TYPE_S 24
563 #define R92S_TXDW0_LSG 0x04000000
564 #define R92S_TXDW0_FSG 0x08000000
565 #define R92S_TXDW0_LINIP 0x10000000
566 #define R92S_TXDW0_OWN 0x80000000
569 #define R92S_TXDW1_MACID_M 0x0000001f
570 #define R92S_TXDW1_MACID_S 0
571 #define R92S_TXDW1_MOREDATA 0x00000020
572 #define R92S_TXDW1_MOREFRAG 0x00000040
573 #define R92S_TXDW1_QSEL_M 0x00001f00
574 #define R92S_TXDW1_QSEL_S 8
575 #define R92S_TXDW1_QSEL_BE 0x03
576 #define R92S_TXDW1_QSEL_H2C 0x1f
577 #define R92S_TXDW1_NONQOS 0x00010000
578 #define R92S_TXDW1_KEYIDX_M 0x00060000
579 #define R92S_TXDW1_KEYIDX_S 17
580 #define R92S_TXDW1_CIPHER_M 0x00c00000
581 #define R92S_TXDW1_CIPHER_S 22
582 #define R92S_TXDW1_CIPHER_WEP 1
583 #define R92S_TXDW1_CIPHER_TKIP 2
584 #define R92S_TXDW1_CIPHER_AES 3
585 #define R92S_TXDW1_HWPC 0x80000000
588 #define R92S_TXDW2_BMCAST 0x00000080
589 #define R92S_TXDW2_AGGEN 0x20000000
590 #define R92S_TXDW2_BK 0x40000000
593 #define R92S_TXDW3_SEQ_M 0x0fff0000
594 #define R92S_TXDW3_SEQ_S 16
595 #define R92S_TXDW3_FRAG_M 0xf0000000
596 #define R92S_TXDW3_FRAG_S 28
599 #define R92S_TXDW4_TXBW 0x00040000
602 #define R92S_TXDW5_DISFB 0x00008000
609 } __packed __aligned(4);
611 struct r92s_add_ba_event {
612 uint8_t mac_addr[IEEE80211_ADDR_LEN];
617 struct r92s_add_ba_req {
622 * Driver definitions.
624 #define RSU_RX_LIST_COUNT 100
625 #define RSU_TX_LIST_COUNT 32
627 #define RSU_HOST_CMD_RING_COUNT 32
629 #define RSU_RXBUFSZ (8 * 1024)
630 #define RSU_TXBUFSZ \
631 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3)
633 #define RSU_TX_TIMEOUT 5000 /* ms */
634 #define RSU_CMD_TIMEOUT 2000 /* ms */
636 /* Queue ids (used by soft only). */
637 #define RSU_QID_BCN 0
638 #define RSU_QID_MGT 1
639 #define RSU_QID_BMC 2
644 #define RSU_QID_RXOFF 7
645 #define RSU_QID_H2C 8
646 #define RSU_QID_C2H 9
648 /* Map AC to queue id. */
649 static const uint8_t rsu_ac2qid[WME_NUM_AC] = {
656 /* Pipe index to endpoint address mapping. */
657 static const uint8_t r92s_epaddr[] =
658 { 0x83, 0x04, 0x06, 0x0d,
660 0x89, 0x0a, 0x0b, 0x0c };
662 /* Queue id to pipe index mapping for 4 endpoints configurations. */
663 static const uint8_t rsu_qid2idx_4ep[] =
664 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 };
666 /* Queue id to pipe index mapping for 6 endpoints configurations. */
667 static const uint8_t rsu_qid2idx_6ep[] =
668 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 };
670 /* Queue id to pipe index mapping for 11 endpoints configurations. */
671 static const uint8_t rsu_qid2idx_11ep[] =
672 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 };
674 struct rsu_rx_radiotap_header {
675 struct ieee80211_radiotap_header wr_ihdr;
678 uint16_t wr_chan_freq;
679 uint16_t wr_chan_flags;
680 uint8_t wr_dbm_antsignal;
681 } __packed __aligned(8);
683 #define RSU_RX_RADIOTAP_PRESENT \
684 (1 << IEEE80211_RADIOTAP_FLAGS | \
685 1 << IEEE80211_RADIOTAP_RATE | \
686 1 << IEEE80211_RADIOTAP_CHANNEL | \
687 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)
689 struct rsu_tx_radiotap_header {
690 struct ieee80211_radiotap_header wt_ihdr;
693 uint16_t wt_chan_freq;
694 uint16_t wt_chan_flags;
697 #define RSU_TX_RADIOTAP_PRESENT \
698 (1 << IEEE80211_RADIOTAP_FLAGS | \
699 1 << IEEE80211_RADIOTAP_CHANNEL)
703 struct rsu_host_cmd {
704 void (*cb)(struct rsu_softc *, void *);
708 struct rsu_cmd_newstate {
709 enum ieee80211_state state;
714 struct ieee80211_key key;
717 struct rsu_host_cmd_ring {
718 struct rsu_host_cmd cmd[RSU_HOST_CMD_RING_COUNT];
726 RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */
727 RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */
728 RSU_BULK_TX_H2C, /* H2C */
733 struct rsu_softc *sc;
737 struct ieee80211_node *ni;
738 STAILQ_ENTRY(rsu_data) next;
742 struct ieee80211vap vap;
744 int (*newstate)(struct ieee80211vap *,
745 enum ieee80211_state, int);
747 #define RSU_VAP(vap) ((struct rsu_vap *)(vap))
749 #define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
750 #define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
751 #define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
754 struct ieee80211com sc_ic;
757 struct usb_device *sc_udev;
758 int (*sc_newstate)(struct ieee80211com *,
759 enum ieee80211_state, int);
760 struct usbd_interface *sc_iface;
761 struct timeout_task calib_task;
763 const uint8_t *qid2idx;
778 struct rsu_host_cmd_ring cmdq;
779 struct rsu_data sc_rx[RSU_RX_LIST_COUNT];
780 struct rsu_data sc_tx[RSU_TX_LIST_COUNT];
781 struct rsu_data *fwcmd_data;
784 struct usb_xfer *sc_xfer[RSU_N_TRANSFER];
786 STAILQ_HEAD(, rsu_data) sc_rx_active;
787 STAILQ_HEAD(, rsu_data) sc_rx_inactive;
788 STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER];
789 STAILQ_HEAD(, rsu_data) sc_tx_inactive;
790 STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER];
793 struct rsu_rx_radiotap_header th;
796 #define sc_rxtap sc_rxtapu.th
799 struct rsu_tx_radiotap_header th;
802 #define sc_txtap sc_txtapu.th