2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $
21 #define R92S_REQ_REGS 0x05
26 #define R92S_SYSCFG 0x0000
27 #define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000)
28 #define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002)
29 #define R92S_PMC_FSM (R92S_SYSCFG + 0x004)
30 #define R92S_SYS_CLKR (R92S_SYSCFG + 0x008)
31 #define R92S_EE_9346CR (R92S_SYSCFG + 0x00a)
32 #define R92S_AFE_MISC (R92S_SYSCFG + 0x010)
33 #define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011)
34 #define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018)
35 #define R92S_RF_CTRL (R92S_SYSCFG + 0x01f)
36 #define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020)
37 #define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021)
38 #define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026)
39 #define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028)
40 #define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030)
41 #define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034)
42 #define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8)
44 #define R92S_CMDCTRL 0x0040
45 #define R92S_CR (R92S_CMDCTRL + 0x000)
46 #define R92S_TXPAUSE (R92S_CMDCTRL + 0x002)
47 #define R92S_TCR (R92S_CMDCTRL + 0x004)
48 #define R92S_RCR (R92S_CMDCTRL + 0x008)
50 #define R92S_MACIDSETTING 0x0050
51 #define R92S_MACID (R92S_MACIDSETTING + 0x000)
52 #define R92S_MAR (R92S_MACIDSETTING + 0x010)
54 #define R92S_TIMECTRL 0x0080
55 #define R92S_TSFTR (R92S_TIMECTRL + 0x000)
57 #define R92S_FIFOCTRL 0x00a0
58 #define R92S_RXFLTMAP_MGT (R92S_FIFOCTRL + 0x076)
59 #define R92S_RXFLTMAP_CTL (R92S_FIFOCTRL + 0x078)
60 #define R92S_RXFLTMAP_DATA (R92S_FIFOCTRL + 0x07a)
61 #define R92S_RXFLTMAP_MESH (R92S_FIFOCTRL + 0x07c)
63 #define R92S_SECURITY 0x0240
64 #define R92S_CAMCMD (R92S_SECURITY + 0x000)
65 #define R92S_CAMWRITE (R92S_SECURITY + 0x004)
66 #define R92S_CAMREAD (R92S_SECURITY + 0x008)
68 #define R92S_GP 0x02e0
69 #define R92S_GPIO_CTRL (R92S_GP + 0x00c)
70 #define R92S_GPIO_IO_SEL (R92S_GP + 0x00e)
71 #define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011)
72 #define R92S_LEDCFG (R92S_GP + 0x012)
74 #define R92S_IOCMD_CTRL 0x0370
75 #define R92S_IOCMD_DATA 0x0374
77 #define R92S_USB_HRPWM 0xfe58
79 /* Bits for R92S_SYS_FUNC_EN. */
80 #define R92S_FEN_CPUEN 0x0400
82 /* Bits for R92S_PMC_FSM. */
83 #define R92S_PMC_FSM_CUT_M 0x000f8000
84 #define R92S_PMC_FSM_CUT_S 15
86 /* Bits for R92S_SYS_CLKR. */
87 #define R92S_SYS_CLKSEL 0x0001
88 #define R92S_SYS_PS_CLKSEL 0x0002
89 #define R92S_SYS_CPU_CLKSEL 0x0004
90 #define R92S_MAC_CLK_EN 0x0800
91 #define R92S_SYS_CLK_EN 0x1000
92 #define R92S_SWHW_SEL 0x4000
93 #define R92S_FWHW_SEL 0x8000
95 /* Bits for R92S_EE_9346CR. */
96 #define R92S_9356SEL 0x10
97 #define R92S_EEPROM_EN 0x20
99 /* Bits for R92S_AFE_MISC. */
100 #define R92S_AFE_MISC_BGEN 0x01
101 #define R92S_AFE_MISC_MBEN 0x02
102 #define R92S_AFE_MISC_I32_EN 0x08
104 /* Bits for R92S_SPS1_CTRL. */
105 #define R92S_SPS1_LDEN 0x01
106 #define R92S_SPS1_SWEN 0x02
108 /* Bits for R92S_LDOA15_CTRL. */
109 #define R92S_LDA15_EN 0x01
111 /* Bits for R92S_LDOV12D_CTRL. */
112 #define R92S_LDV12_EN 0x01
114 /* Bits for R92C_EFUSE_CTRL. */
115 #define R92S_EFUSE_CTRL_DATA_M 0x000000ff
116 #define R92S_EFUSE_CTRL_DATA_S 0
117 #define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00
118 #define R92S_EFUSE_CTRL_ADDR_S 8
119 #define R92S_EFUSE_CTRL_VALID 0x80000000
121 /* Bits for R92S_CR. */
122 #define R92S_CR_TXDMA_EN 0x10
124 /* Bits for R92S_TXPAUSE. */
125 #define R92S_TXPAUSE_VO 0x01
126 #define R92S_TXPAUSE_VI 0x02
127 #define R92S_TXPAUSE_BE 0x04
128 #define R92S_TXPAUSE_BK 0x08
129 #define R92S_TXPAUSE_MGT 0x10
130 #define R92S_TXPAUSE_HIGH 0x20
131 #define R92S_TXPAUSE_HCCA 0x40
134 #define R92S_TXPAUSE_AC \
135 (R92S_TXPAUSE_VO | R92S_TXPAUSE_VI | \
136 R92S_TXPAUSE_BE | R92S_TXPAUSE_BK)
138 #define R92S_TXPAUSE_ALL \
139 (R92S_TXPAUSE_AC | R92S_TXPAUSE_MGT | \
140 R92S_TXPAUSE_HIGH | R92S_TXPAUSE_HCCA | 0x80)
142 /* Bits for R92S_TCR. */
143 #define R92S_TCR_IMEM_CODE_DONE 0x01
144 #define R92S_TCR_IMEM_CHK_RPT 0x02
145 #define R92S_TCR_EMEM_CODE_DONE 0x04
146 #define R92S_TCR_EMEM_CHK_RPT 0x08
147 #define R92S_TCR_DMEM_CODE_DONE 0x10
148 #define R92S_TCR_IMEM_RDY 0x20
149 #define R92S_TCR_FWRDY 0x80
151 /* Bits for R92S_RCR. */
152 #define R92S_RCR_AAP 0x00000001
153 #define R92S_RCR_APM 0x00000002
154 #define R92S_RCR_AM 0x00000004
155 #define R92S_RCR_AB 0x00000008
156 #define R92S_RCR_ACRC32 0x00000020
157 #define R92S_RCR_AICV 0x00001000
158 #define R92S_RCR_APP_ICV 0x00010000
159 #define R92S_RCR_APP_MIC 0x00020000
160 #define R92S_RCR_ADF 0x00040000
161 #define R92S_RCR_ACF 0x00080000
162 #define R92S_RCR_AMF 0x00100000
163 #define R92S_RCR_ADD3 0x00200000
164 #define R92S_RCR_APWRMGT 0x00400000
165 #define R92S_RCR_CBSSID 0x00800000
166 #define R92S_RCR_APP_PHYSTS 0x02000000
167 #define R92S_RCR_TCP_OFFLD_EN 0x04000000
168 #define R92S_RCR_ENMBID 0x08000000
170 /* Bits for R92S_RXFLTMAP*. */
171 #define R92S_RXFLTMAP_MGT_DEF 0x3f3f
172 #define R92S_RXFLTMAP_FW(subtype) \
173 (1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT))
175 /* Bits for R92S_GPIO_IO_SEL. */
176 #define R92S_GPIO_WPS 0x10
178 /* Bits for R92S_MAC_PINMUX_CTRL. */
179 #define R92S_GPIOSEL_GPIO_M 0x03
180 #define R92S_GPIOSEL_GPIO_S 0
181 #define R92S_GPIOSEL_GPIO_JTAG 0
182 #define R92S_GPIOSEL_GPIO_PHYDBG 1
183 #define R92S_GPIOSEL_GPIO_BT 2
184 #define R92S_GPIOSEL_GPIO_WLANDBG 3
185 #define R92S_GPIOMUX_EN 0x08
187 /* Bits for R92S_CAMCMD. */
188 #define R92S_CAMCMD_ADDR_M 0x000000ff
189 #define R92S_CAMCMD_ADDR_S 0
190 #define R92S_CAMCMD_READ 0x00000000
191 #define R92S_CAMCMD_WRITE 0x00010000
192 #define R92S_CAMCMD_POLLING 0x80000000
197 #define R92S_CAM_ENTRY_LIMIT 32
198 #define R92S_CAM_ENTRY_BYTES howmany(R92S_CAM_ENTRY_LIMIT, NBBY)
200 #define R92S_CAM_CTL0(entry) ((entry) * 8 + 0)
201 #define R92S_CAM_CTL1(entry) ((entry) * 8 + 1)
202 #define R92S_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i))
204 /* Bits for R92S_CAM_CTL0(i). */
205 #define R92S_CAM_KEYID_M 0x00000003
206 #define R92S_CAM_KEYID_S 0
207 #define R92S_CAM_ALGO_M 0x0000001c
208 #define R92S_CAM_ALGO_S 2
209 #define R92S_CAM_VALID 0x00008000
210 #define R92S_CAM_MACLO_M 0xffff0000
211 #define R92S_CAM_MACLO_S 16
213 /* Bits for R92S_IOCMD_CTRL. */
214 #define R92S_IOCMD_CLASS_M 0xff000000
215 #define R92S_IOCMD_CLASS_S 24
216 #define R92S_IOCMD_CLASS_BB_RF 0xf0
217 #define R92S_IOCMD_VALUE_M 0x00ffff00
218 #define R92S_IOCMD_VALUE_S 8
219 #define R92S_IOCMD_INDEX_M 0x000000ff
220 #define R92S_IOCMD_INDEX_S 0
221 #define R92S_IOCMD_INDEX_BB_READ 0
222 #define R92S_IOCMD_INDEX_BB_WRITE 1
223 #define R92S_IOCMD_INDEX_RF_READ 2
224 #define R92S_IOCMD_INDEX_RF_WRITE 3
226 /* Bits for R92S_USB_HRPWM. */
227 #define R92S_USB_HRPWM_PS_ALL_ON 0x04
228 #define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08
231 * Macros to access subfields in registers.
233 /* Mask and Shift (getter). */
234 #define MS(val, field) \
235 (((val) & field##_M) >> field##_S)
237 /* Shift and Mask (setter). */
238 #define SM(field, val) \
239 (((val) << field##_S) & field##_M)
242 #define RW(var, field, val) \
243 (((var) & ~field##_M) | SM(field, val))
246 * ROM field with RF config.
249 RTL8712_RFCONFIG_1T = 0x10,
250 RTL8712_RFCONFIG_2T = 0x20,
251 RTL8712_RFCONFIG_1R = 0x01,
252 RTL8712_RFCONFIG_2R = 0x02,
253 RTL8712_RFCONFIG_1T1R = 0x11,
254 RTL8712_RFCONFIG_1T2R = 0x12,
255 RTL8712_RFCONFIG_TURBO = 0x92,
256 RTL8712_RFCONFIG_2T2R = 0x22
260 * Firmware image header.
262 struct r92s_fw_priv {
266 #define R92S_HCI_SEL_PCIE 0x01
267 #define R92S_HCI_SEL_USB 0x02
268 #define R92S_HCI_SEL_SDIO 0x04
269 #define R92S_HCI_SEL_8172 0x10
270 #define R92S_HCI_SEL_AP 0x80
272 uint8_t chip_version;
275 //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R
282 uint8_t lowpower_mode;
287 #define R92S_VCS_TYPE_DISABLE 0
288 #define R92S_VCS_TYPE_ENABLE 1
289 #define R92S_VCS_TYPE_AUTO 2
292 #define R92S_VCS_MODE_NONE 0
293 #define R92S_VCS_MODE_RTS_CTS 1
294 #define R92S_VCS_MODE_CTS2SELF 2
300 uint8_t amsdu2ampdu_en;
306 uint8_t beacon_offload;
307 uint8_t mlme_offload;
308 uint8_t hwpc_offload;
309 uint8_t tcpcsum_offload;
312 uint8_t wwlan_offload;
328 uint16_t h2c_resp_addr;
334 struct r92s_fw_priv priv;
337 /* Structure for FW commands and FW events notifications. */
338 struct r92s_fw_cmd_hdr {
342 #define R92S_FW_CMD_MORE 0x80
347 /* FW commands codes. */
348 #define R92S_CMD_READ_MACREG 0
349 #define R92S_CMD_WRITE_MACREG 1
350 #define R92S_CMD_READ_BBREG 2
351 #define R92S_CMD_WRITE_BBREG 3
352 #define R92S_CMD_READ_RFREG 4
353 #define R92S_CMD_WRITE_RFREG 5
354 #define R92S_CMD_READ_EEPROM 6
355 #define R92S_CMD_WRITE_EEPROM 7
356 #define R92S_CMD_READ_EFUSE 8
357 #define R92S_CMD_WRITE_EFUSE 9
358 #define R92S_CMD_READ_CAM 10
359 #define R92S_CMD_WRITE_CAM 11
360 #define R92S_CMD_SET_BCNITV 12
361 #define R92S_CMD_SET_MBIDCFG 13
362 #define R92S_CMD_JOIN_BSS 14
363 #define R92S_CMD_DISCONNECT 15
364 #define R92S_CMD_CREATE_BSS 16
365 #define R92S_CMD_SET_OPMODE 17
366 #define R92S_CMD_SITE_SURVEY 18
367 #define R92S_CMD_SET_AUTH 19
368 #define R92S_CMD_SET_KEY 20
369 #define R92S_CMD_SET_STA_KEY 21
370 #define R92S_CMD_SET_ASSOC_STA 22
371 #define R92S_CMD_DEL_ASSOC_STA 23
372 #define R92S_CMD_SET_STAPWRSTATE 24
373 #define R92S_CMD_SET_BASIC_RATE 25
374 #define R92S_CMD_GET_BASIC_RATE 26
375 #define R92S_CMD_SET_DATA_RATE 27
376 #define R92S_CMD_GET_DATA_RATE 28
377 #define R92S_CMD_SET_PHY_INFO 29
378 #define R92S_CMD_GET_PHY_INFO 30
379 #define R92S_CMD_SET_PHY 31
380 #define R92S_CMD_GET_PHY 32
381 #define R92S_CMD_READ_RSSI 33
382 #define R92S_CMD_READ_GAIN 34
383 #define R92S_CMD_SET_ATIM 35
384 #define R92S_CMD_SET_PWR_MODE 36
385 #define R92S_CMD_JOIN_BSS_RPT 37
386 #define R92S_CMD_SET_RA_TABLE 38
387 #define R92S_CMD_GET_RA_TABLE 39
388 #define R92S_CMD_GET_CCX_REPORT 40
389 #define R92S_CMD_GET_DTM_REPORT 41
390 #define R92S_CMD_GET_TXRATE_STATS 42
391 #define R92S_CMD_SET_USB_SUSPEND 43
392 #define R92S_CMD_SET_H2C_LBK 44
393 #define R92S_CMD_ADDBA_REQ 45
394 #define R92S_CMD_SET_CHANNEL 46
395 #define R92S_CMD_SET_TXPOWER 47
396 #define R92S_CMD_SWITCH_ANTENNA 48
397 #define R92S_CMD_SET_CRYSTAL_CAL 49
398 #define R92S_CMD_SET_SINGLE_CARRIER_TX 50
399 #define R92S_CMD_SET_SINGLE_TONE_TX 51
400 #define R92S_CMD_SET_CARRIER_SUPPR_TX 52
401 #define R92S_CMD_SET_CONTINUOUS_TX 53
402 #define R92S_CMD_SWITCH_BANDWIDTH 54
403 #define R92S_CMD_TX_BEACON 55
404 #define R92S_CMD_SET_POWER_TRACKING 56
405 #define R92S_CMD_AMSDU_TO_AMPDU 57
406 #define R92S_CMD_SET_MAC_ADDRESS 58
407 #define R92S_CMD_GET_H2C_LBK 59
408 #define R92S_CMD_SET_PBREQ_IE 60
409 #define R92S_CMD_SET_ASSOCREQ_IE 61
410 #define R92S_CMD_SET_PBRESP_IE 62
411 #define R92S_CMD_SET_ASSOCRESP_IE 63
412 #define R92S_CMD_GET_CURDATARATE 64
413 #define R92S_CMD_GET_TXRETRY_CNT 65
414 #define R92S_CMD_GET_RXRETRY_CNT 66
415 #define R92S_CMD_GET_BCNOK_CNT 67
416 #define R92S_CMD_GET_BCNERR_CNT 68
417 #define R92S_CMD_GET_CURTXPWR_LEVEL 69
418 #define R92S_CMD_SET_DIG 70
419 #define R92S_CMD_SET_RA 71
420 #define R92S_CMD_SET_PT 72
421 #define R92S_CMD_READ_TSSI 73
423 /* FW events notifications codes. */
424 #define R92S_EVT_READ_MACREG 0
425 #define R92S_EVT_READ_BBREG 1
426 #define R92S_EVT_READ_RFREG 2
427 #define R92S_EVT_READ_EEPROM 3
428 #define R92S_EVT_READ_EFUSE 4
429 #define R92S_EVT_READ_CAM 5
430 #define R92S_EVT_GET_BASICRATE 6
431 #define R92S_EVT_GET_DATARATE 7
432 #define R92S_EVT_SURVEY 8
433 #define R92S_EVT_SURVEY_DONE 9
434 #define R92S_EVT_JOIN_BSS 10
435 #define R92S_EVT_ADD_STA 11
436 #define R92S_EVT_DEL_STA 12
437 #define R92S_EVT_ATIM_DONE 13
438 #define R92S_EVT_TX_REPORT 14
439 #define R92S_EVT_CCX_REPORT 15
440 #define R92S_EVT_DTM_REPORT 16
441 #define R92S_EVT_TXRATE_STATS 17
442 #define R92S_EVT_C2H_LBK 18
443 #define R92S_EVT_FWDBG 19
444 #define R92S_EVT_C2H_FEEDBACK 20
445 #define R92S_EVT_ADDBA 21
446 #define R92S_EVT_C2H_BCN 22
447 #define R92S_EVT_PWR_STATE 23
448 #define R92S_EVT_WPS_PBC 24
449 #define R92S_EVT_ADDBA_REQ_REPORT 25
451 /* Structure for R92S_CMD_SITE_SURVEY. */
452 struct r92s_fw_cmd_sitesurvey {
456 uint8_t ssid[32 + 1];
459 /* Structure for R92S_CMD_SET_AUTH. */
460 struct r92s_fw_cmd_auth {
462 #define R92S_AUTHMODE_OPEN 0
463 #define R92S_AUTHMODE_SHARED 1
464 #define R92S_AUTHMODE_WPA 2
469 /* Structure for R92S_CMD_SET_KEY. */
470 struct r92s_fw_cmd_set_key {
472 #define R92S_KEY_ALGO_NONE 0
473 #define R92S_KEY_ALGO_WEP40 1
474 #define R92S_KEY_ALGO_TKIP 2
475 #define R92S_KEY_ALGO_TKIP_MMIC 3
476 #define R92S_KEY_ALGO_AES 4
477 #define R92S_KEY_ALGO_WEP104 5
478 #define R92S_KEY_ALGO_INVALID 0xff /* for rsu_crypto_mode() only */
482 uint8_t key[IEEE80211_KEYBUF_SIZE];
485 /* Structure for R92S_CMD_SET_STA_KEY. */
486 struct r92s_fw_cmd_set_key_mac {
487 uint8_t macaddr[IEEE80211_ADDR_LEN];
489 uint8_t key[IEEE80211_KEYBUF_SIZE];
492 /* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */
493 /* NDIS_802_11_SSID. */
494 struct ndis_802_11_ssid {
499 /* NDIS_802_11_CONFIGURATION_FH. */
500 struct ndis_802_11_configuration_fh {
507 /* NDIS_802_11_CONFIGURATION. */
508 struct ndis_802_11_configuration {
513 struct ndis_802_11_configuration_fh fhconfig;
516 /* NDIS_WLAN_BSSID_EX. */
517 struct ndis_wlan_bssid_ex {
519 uint8_t macaddr[IEEE80211_ADDR_LEN];
521 struct ndis_802_11_ssid ssid;
524 uint32_t networktype;
525 #define NDIS802_11FH 0
526 #define NDIS802_11DS 1
527 #define NDIS802_11OFDM5 2
528 #define NDIS802_11OFDM24 3
529 #define NDIS802_11AUTOMODE 4
531 struct ndis_802_11_configuration config;
533 #define NDIS802_11IBSS 0
534 #define NDIS802_11INFRASTRUCTURE 1
535 #define NDIS802_11AUTOUNKNOWN 2
536 #define NDIS802_11MONITOR 3
537 #define NDIS802_11APMODE 4
539 uint8_t supprates[16];
541 /* Followed by ``ieslen'' bytes. */
544 /* NDIS_802_11_FIXED_IEs. */
545 struct ndis_802_11_fixed_ies {
548 uint16_t capabilities;
551 /* Structure for R92S_CMD_SET_PWR_MODE. */
552 struct r92s_set_pwr_mode {
554 #define R92S_PS_MODE_ACTIVE 0
555 #define R92S_PS_MODE_MIN 1
556 #define R92S_PS_MODE_MAX 2
557 #define R92S_PS_MODE_DTIM 3
558 #define R92S_PS_MODE_VOIP 4
559 #define R92S_PS_MODE_UAPSD_WMM 5
560 #define R92S_PS_MODE_UAPSD 6
561 #define R92S_PS_MODE_IBSS 7
562 #define R92S_PS_MODE_WWLAN 8
563 #define R92S_PS_MODE_RADIOOFF 9
564 #define R92S_PS_MODE_DISABLE 10
566 uint8_t low_traffic_en;
568 uint8_t rf_low_snr_en;
571 uint8_t bcn_pass_cnt;
575 uint8_t awake_bcn_itv;
577 uint8_t bcn_pass_time;
580 /* Structure for R92S_CMD_SET_CHANNEL. */
581 struct r92s_set_channel {
585 /* Structure for event R92S_EVENT_JOIN_BSS. */
586 struct r92s_event_join_bss {
589 uint32_t networktype;
591 uint32_t lastscanned;
594 struct ndis_wlan_bssid_ex bss;
597 #define R92S_MACID_BSS 5 /* XXX hardcoded somewhere */
599 /* Rx MAC descriptor. */
600 struct r92s_rx_stat {
602 #define R92S_RXDW0_PKTLEN_M 0x00003fff
603 #define R92S_RXDW0_PKTLEN_S 0
604 #define R92S_RXDW0_CRCERR 0x00004000
605 #define R92S_RXDW0_ICVERR 0x00008000
606 #define R92S_RXDW0_INFOSZ_M 0x000f0000
607 #define R92S_RXDW0_INFOSZ_S 16
608 #define R92S_RXDW0_CIPHER_M 0x00700000
609 #define R92S_RXDW0_CIPHER_S 20
610 #define R92S_RXDW0_QOS 0x00800000
611 #define R92S_RXDW0_SHIFT_M 0x03000000
612 #define R92S_RXDW0_SHIFT_S 24
613 #define R92S_RXDW0_PHYST 0x04000000
614 #define R92S_RXDW0_DECRYPTED 0x08000000
617 #define R92S_RXDW1_MOREFRAG 0x08000000
620 #define R92S_RXDW2_FRAG_M 0x0000f000
621 #define R92S_RXDW2_FRAG_S 12
622 #define R92S_RXDW2_PKTCNT_M 0x00ff0000
623 #define R92S_RXDW2_PKTCNT_S 16
626 #define R92S_RXDW3_RATE_M 0x0000003f
627 #define R92S_RXDW3_RATE_S 0
628 #define R92S_RXDW3_TCPCHKRPT 0x00000800
629 #define R92S_RXDW3_IPCHKRPT 0x00001000
630 #define R92S_RXDW3_TCPCHKVALID 0x00002000
631 #define R92S_RXDW3_HTC 0x00004000
635 } __packed __aligned(4);
637 /* Rx PHY descriptor. */
638 struct r92s_rx_phystat {
647 } __packed __aligned(4);
649 /* Rx PHY CCK descriptor. */
656 /* Tx MAC descriptor. */
657 struct r92s_tx_desc {
659 #define R92S_TXDW0_PKTLEN_M 0x0000ffff
660 #define R92S_TXDW0_PKTLEN_S 0
661 #define R92S_TXDW0_OFFSET_M 0x00ff0000
662 #define R92S_TXDW0_OFFSET_S 16
663 #define R92S_TXDW0_TYPE_M 0x03000000
664 #define R92S_TXDW0_TYPE_S 24
665 #define R92S_TXDW0_LSG 0x04000000
666 #define R92S_TXDW0_FSG 0x08000000
667 #define R92S_TXDW0_LINIP 0x10000000
668 #define R92S_TXDW0_OWN 0x80000000
671 #define R92S_TXDW1_MACID_M 0x0000001f
672 #define R92S_TXDW1_MACID_S 0
673 #define R92S_TXDW1_MOREDATA 0x00000020
674 #define R92S_TXDW1_MOREFRAG 0x00000040
675 #define R92S_TXDW1_QSEL_M 0x00001f00
676 #define R92S_TXDW1_QSEL_S 8
677 #define R92S_TXDW1_QSEL_BE 0x03
678 #define R92S_TXDW1_QSEL_H2C 0x13
679 #define R92S_TXDW1_NONQOS 0x00010000
680 #define R92S_TXDW1_KEYIDX_M 0x00060000
681 #define R92S_TXDW1_KEYIDX_S 17
682 #define R92S_TXDW1_CIPHER_M 0x00c00000
683 #define R92S_TXDW1_CIPHER_S 22
684 #define R92S_TXDW1_CIPHER_NONE 0
685 #define R92S_TXDW1_CIPHER_WEP 1
686 #define R92S_TXDW1_CIPHER_TKIP 2
687 #define R92S_TXDW1_CIPHER_AES 3
688 #define R92S_TXDW1_HWPC 0x80000000
691 #define R92S_TXDW2_RTY_LMT_M 0x0000003f
692 #define R92S_TXDW2_RTY_LMT_S 0
693 #define R92S_TXDW2_RTY_LMT_ENA 0x00000040
694 #define R92S_TXDW2_BMCAST 0x00000080
695 #define R92S_TXDW2_AGGEN 0x20000000
696 #define R92S_TXDW2_BK 0x40000000
699 #define R92S_TXDW3_SEQ_M 0x0fff0000
700 #define R92S_TXDW3_SEQ_S 16
701 #define R92S_TXDW3_FRAG_M 0xf0000000
702 #define R92S_TXDW3_FRAG_S 28
705 #define R92S_TXDW4_TXBW 0x00040000
706 #define R92S_TXDW4_DRVRATE 0x80000000
709 #define R92S_TXDW5_DATARATE_M 0x00007e00
710 #define R92S_TXDW5_DATARATE_S 9
711 #define R92S_TXDW5_DISFB 0x00008000
712 #define R92S_TXDW5_DATARATE_FB_LMT_M 0x001f0000
713 #define R92S_TXDW5_DATARATE_FB_LMT_S 16
720 } __packed __aligned(4);
722 struct r92s_add_ba_event {
723 uint8_t mac_addr[IEEE80211_ADDR_LEN];
728 struct r92s_add_ba_req {
733 * Driver definitions.
735 #define RSU_RX_LIST_COUNT 1
736 #define RSU_TX_LIST_COUNT 32
738 #define RSU_RXBUFSZ (30 * 1024)
739 #define RSU_TXBUFSZ \
740 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3)
742 #define RSU_TX_TIMEOUT 5000 /* ms */
743 #define RSU_CMD_TIMEOUT 2000 /* ms */
745 /* Queue ids (used by soft only). */
746 #define RSU_QID_BCN 0
747 #define RSU_QID_MGT 1
748 #define RSU_QID_BMC 2
753 #define RSU_QID_RXOFF 7
754 #define RSU_QID_H2C 8
755 #define RSU_QID_C2H 9
757 /* Map AC to queue id. */
758 static const uint8_t rsu_ac2qid[WME_NUM_AC] = {
765 /* Pipe index to endpoint address mapping. */
766 static const uint8_t r92s_epaddr[] =
767 { 0x83, 0x04, 0x06, 0x0d,
769 0x89, 0x0a, 0x0b, 0x0c };
771 /* Queue id to pipe index mapping for 4 endpoints configurations. */
772 static const uint8_t rsu_qid2idx_4ep[] =
773 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 };
775 /* Queue id to pipe index mapping for 6 endpoints configurations. */
776 static const uint8_t rsu_qid2idx_6ep[] =
777 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 };
779 /* Queue id to pipe index mapping for 11 endpoints configurations. */
780 static const uint8_t rsu_qid2idx_11ep[] =
781 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 };
783 struct rsu_rx_radiotap_header {
784 struct ieee80211_radiotap_header wr_ihdr;
788 uint16_t wr_chan_freq;
789 uint16_t wr_chan_flags;
790 uint8_t wr_dbm_antsignal;
791 } __packed __aligned(8);
793 #define RSU_RX_RADIOTAP_PRESENT \
794 (1 << IEEE80211_RADIOTAP_TSFT | \
795 1 << IEEE80211_RADIOTAP_FLAGS | \
796 1 << IEEE80211_RADIOTAP_RATE | \
797 1 << IEEE80211_RADIOTAP_CHANNEL | \
798 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)
800 struct rsu_tx_radiotap_header {
801 struct ieee80211_radiotap_header wt_ihdr;
803 uint16_t wt_chan_freq;
804 uint16_t wt_chan_flags;
805 } __packed __aligned(8);
807 #define RSU_TX_RADIOTAP_PRESENT \
808 (1 << IEEE80211_RADIOTAP_FLAGS | \
809 1 << IEEE80211_RADIOTAP_CHANNEL)
815 RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */
816 RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */
817 RSU_BULK_TX_H2C, /* H2C */
822 struct rsu_softc *sc;
826 struct ieee80211_node *ni;
827 STAILQ_ENTRY(rsu_data) next;
831 struct ieee80211vap vap;
833 int (*newstate)(struct ieee80211vap *,
834 enum ieee80211_state, int);
836 #define RSU_VAP(vap) ((struct rsu_vap *)(vap))
838 #define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
839 #define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
840 #define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
842 #define RSU_DELKEY_BMAP_LOCK_INIT(_sc) \
843 mtx_init(&(_sc)->free_keys_bmap_mtx, "bmap lock", NULL, MTX_DEF)
844 #define RSU_DELKEY_BMAP_LOCK(_sc) mtx_lock(&(_sc)->free_keys_bmap_mtx)
845 #define RSU_DELKEY_BMAP_UNLOCK(_sc) mtx_unlock(&(_sc)->free_keys_bmap_mtx)
846 #define RSU_DELKEY_BMAP_LOCK_DESTROY(_sc) \
847 mtx_destroy(&(_sc)->free_keys_bmap_mtx)
850 struct ieee80211com sc_ic;
853 struct usb_device *sc_udev;
855 struct timeout_task calib_task;
865 sc_rx_checksum_enable:1,
873 struct rsu_data sc_rx[RSU_RX_LIST_COUNT];
874 struct rsu_data sc_tx[RSU_TX_LIST_COUNT];
877 struct usb_xfer *sc_xfer[RSU_N_TRANSFER];
879 STAILQ_HEAD(, rsu_data) sc_rx_active;
880 STAILQ_HEAD(, rsu_data) sc_rx_inactive;
881 STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER];
882 STAILQ_HEAD(, rsu_data) sc_tx_inactive;
883 STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER];
885 struct task del_key_task;
886 uint8_t keys_bmap[R92S_CAM_ENTRY_BYTES];
887 const struct ieee80211_key *group_keys[IEEE80211_WEP_NKID];
889 struct mtx free_keys_bmap_mtx;
890 uint8_t free_keys_bmap[R92S_CAM_ENTRY_BYTES];
893 struct rsu_rx_radiotap_header th;
896 #define sc_rxtap sc_rxtapu.th
899 struct rsu_tx_radiotap_header th;
902 #define sc_txtap sc_txtapu.th