1 /* $OpenBSD: if_uathreg.h,v 1.2 2006/09/18 16:34:23 damien Exp $ */
5 * Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2006 Sam Leffler, Errno Consulting
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #define UATH_CONFIG_INDEX 0
22 #define UATH_IFACE_INDEX 0
24 /* all fields are big endian */
27 #define UATH_WRITE_BLOCK (1 << 4)
30 #define UATH_MAX_FWBLOCK_SIZE 2048
38 #define UATH_MAX_CMDSZ 512
41 * Messages are passed in Target Endianness. All fixed-size
42 * fields of a WDS Control Message are treated as 32-bit
43 * values and Control Msgs are guaranteed to be 32-bit aligned.
45 * The format of a WDS Control Message is as follows:
46 * Message Length 32 bits
47 * Message Opcode 32 bits
53 * A variable-length parameter, or a parameter that is larger than
54 * 32 bits is passed as <length, data> pair, where length is a
55 * 32-bit quantity and data is padded to 32 bits.
58 uint32_t len; /* msg length including header */
59 uint32_t code; /* operation code */
60 /* NB: these are defined for rev 1.5 firmware; rev 1.6 is different */
61 /* messages from Host -> Target */
62 #define WDCMSG_HOST_AVAILABLE 0x01
63 #define WDCMSG_BIND 0x02
64 #define WDCMSG_TARGET_RESET 0x03
65 #define WDCMSG_TARGET_GET_CAPABILITY 0x04
66 #define WDCMSG_TARGET_SET_CONFIG 0x05
67 #define WDCMSG_TARGET_GET_STATUS 0x06
68 #define WDCMSG_TARGET_GET_STATS 0x07
69 #define WDCMSG_TARGET_START 0x08
70 #define WDCMSG_TARGET_STOP 0x09
71 #define WDCMSG_TARGET_ENABLE 0x0a
72 #define WDCMSG_TARGET_DISABLE 0x0b
73 #define WDCMSG_CREATE_CONNECTION 0x0c
74 #define WDCMSG_UPDATE_CONNECT_ATTR 0x0d
75 #define WDCMSG_DELETE_CONNECT 0x0e
76 #define WDCMSG_SEND 0x0f
77 #define WDCMSG_FLUSH 0x10
78 /* messages from Target -> Host */
79 #define WDCMSG_STATS_UPDATE 0x11
80 #define WDCMSG_BMISS 0x12
81 #define WDCMSG_DEVICE_AVAIL 0x13
82 #define WDCMSG_SEND_COMPLETE 0x14
83 #define WDCMSG_DATA_AVAIL 0x15
84 #define WDCMSG_SET_PWR_MODE 0x16
85 #define WDCMSG_BMISS_ACK 0x17
86 #define WDCMSG_SET_LED_STEADY 0x18
87 #define WDCMSG_SET_LED_BLINK 0x19
89 #define WDCMSG_SETUP_BEACON_DESC 0x1a
90 #define WDCMSG_BEACON_INIT 0x1b
91 #define WDCMSG_RESET_KEY_CACHE 0x1c
92 #define WDCMSG_RESET_KEY_CACHE_ENTRY 0x1d
93 #define WDCMSG_SET_KEY_CACHE_ENTRY 0x1e
94 #define WDCMSG_SET_DECOMP_MASK 0x1f
95 #define WDCMSG_SET_REGULATORY_DOMAIN 0x20
96 #define WDCMSG_SET_LED_STATE 0x21
97 #define WDCMSG_WRITE_ASSOCID 0x22
98 #define WDCMSG_SET_STA_BEACON_TIMERS 0x23
99 #define WDCMSG_GET_TSF 0x24
100 #define WDCMSG_RESET_TSF 0x25
101 #define WDCMSG_SET_ADHOC_MODE 0x26
102 #define WDCMSG_SET_BASIC_RATE 0x27
103 #define WDCMSG_MIB_CONTROL 0x28
104 #define WDCMSG_GET_CHANNEL_DATA 0x29
105 #define WDCMSG_GET_CUR_RSSI 0x2a
106 #define WDCMSG_SET_ANTENNA_SWITCH 0x2b
107 #define WDCMSG_USE_SHORT_SLOT_TIME 0x2f
108 #define WDCMSG_SET_POWER_MODE 0x30
109 #define WDCMSG_SETUP_PSPOLL_DESC 0x31
110 #define WDCMSG_SET_RX_MULTICAST_FILTER 0x32
111 #define WDCMSG_RX_FILTER 0x33
112 #define WDCMSG_PER_CALIBRATION 0x34
113 #define WDCMSG_RESET 0x35
114 #define WDCMSG_DISABLE 0x36
115 #define WDCMSG_PHY_DISABLE 0x37
116 #define WDCMSG_SET_TX_POWER_LIMIT 0x38
117 #define WDCMSG_SET_TX_QUEUE_PARAMS 0x39
118 #define WDCMSG_SETUP_TX_QUEUE 0x3a
119 #define WDCMSG_RELEASE_TX_QUEUE 0x3b
120 #define WDCMSG_SET_DEFAULT_KEY 0x43
121 uint32_t msgid; /* msg id (supplied by host) */
122 uint32_t magic; /* response desired/target status */
123 uint32_t debug[4]; /* debug data area */
124 /* msg data follows */
128 uint8_t seqnum; /* sequence number for ordering */
130 #define UATH_CFLAGS_FINAL 0x01 /* final chunk of a msg */
131 #define UATH_CFLAGS_RXMSG 0x02 /* chunk contains rx completion */
132 #define UATH_CFLAGS_DEBUG 0x04 /* for debugging */
133 uint16_t length; /* chunk size in bytes */
134 /* chunk data follows */
137 #define UATH_RX_DUMMYSIZE 4
140 * Message format for a WDCMSG_DATA_AVAIL message from Target to Host.
142 struct uath_rx_desc {
143 uint32_t len; /* msg length including header */
144 uint32_t code; /* WDCMSG_DATA_AVAIL */
145 uint32_t gennum; /* generation number */
146 uint32_t status; /* start of RECEIVE_INFO */
147 #define UATH_STATUS_OK 0
148 #define UATH_STATUS_STOP_IN_PROGRESS 1
149 #define UATH_STATUS_CRC_ERR 2
150 #define UATH_STATUS_PHY_ERR 3
151 #define UATH_STATUS_DECRYPT_CRC_ERR 4
152 #define UATH_STATUS_DECRYPT_MIC_ERR 5
153 #define UATH_STATUS_DECOMP_ERR 6
154 #define UATH_STATUS_KEY_ERR 7
155 #define UATH_STATUS_ERR 8
156 uint32_t tstamp_low; /* low-order 32-bits of rx timestamp */
157 uint32_t tstamp_high; /* high-order 32-bits of rx timestamp */
158 uint32_t framelen; /* frame length */
159 uint32_t rate; /* rx rate code */
164 uint32_t connix; /* key table ix for bss traffic */
165 uint32_t decrypterror;
166 uint32_t keycachemiss;
167 uint32_t pad; /* XXX? */
170 struct uath_tx_desc {
172 uint32_t msgid; /* msg id (supplied by host) */
173 uint32_t type; /* opcode: WDMSG_SEND or WDCMSG_FLUSH */
174 uint32_t txqid; /* tx queue id and flags */
175 #define UATH_TXQID_MASK 0x0f
176 #define UATH_TXQID_MINRATE 0x10 /* use min tx rate */
177 #define UATH_TXQID_FF 0x20 /* content is fast frame */
178 uint32_t connid; /* tx connection id */
179 #define UATH_ID_INVALID 0xffffffff /* for sending prior to connection */
180 uint32_t flags; /* non-zero if response desired */
181 #define UATH_TX_NOTIFY (1 << 24) /* f/w will send a UATH_NOTIF_TX */
182 uint32_t buflen; /* payload length */
185 struct uath_cmd_host_available {
186 uint32_t sw_ver_major;
187 uint32_t sw_ver_minor;
188 uint32_t sw_ver_patch;
189 uint32_t sw_ver_build;
191 #define ATH_SW_VER_MAJOR 1
192 #define ATH_SW_VER_MINOR 5
193 #define ATH_SW_VER_PATCH 0
194 #define ATH_SW_VER_BUILD 9999
196 struct uath_cmd_bind {
197 uint32_t targethandle;
198 uint32_t hostapiversion;
201 /* structure for command WDCMSG_RESET */
202 struct uath_cmd_reset {
203 uint32_t flags; /* channel flags */
204 #define UATH_CHAN_TURBO 0x0100
205 #define UATH_CHAN_CCK 0x0200
206 #define UATH_CHAN_OFDM 0x0400
207 #define UATH_CHAN_2GHZ 0x1000
208 #define UATH_CHAN_5GHZ 0x2000
209 uint32_t freq; /* channel frequency */
212 uint32_t twiceantennareduction;
213 uint32_t channelchange;
214 uint32_t keeprccontent;
217 /* structure for commands UATH_CMD_READ_MAC and UATH_CMD_READ_EEPROM */
218 struct uath_read_mac {
223 /* structure for command UATH_CMD_WRITE_MAC */
224 struct uath_write_mac {
230 /* structure for command UATH_CMD_STA_JOIN */
231 struct uath_cmd_join_bss {
232 uint32_t bssid; /* NB: use zero */
233 uint32_t bssmac[2]; /* bssid mac address */
236 uint32_t beaconinterval;
237 uint32_t dtiminterval;
238 uint32_t cfpinterval;
240 uint32_t defaultrateix;
241 uint32_t shortslottime11g;
242 uint32_t sleepduration;
243 uint32_t bmissthreshold;
244 uint32_t tcppowerlimit;
245 uint32_t quietduration;
246 uint32_t quietoffset;
247 uint32_t quietackctsallow;
248 uint32_t bssdefaultkey; /* XXX? */
251 struct uath_cmd_assoc_bss {
256 struct uath_cmd_start_bss {
260 /* structure for command UATH_CMD_0C */
267 struct uath_cmd_ledsteady { /* WDCMSG_SET_LED_STEADY */
269 #define UATH_LED_LINK 0
270 #define UATH_LED_ACTIVITY 1
272 #define UATH_LED_OFF 0
273 #define UATH_LED_ON 1
276 struct uath_cmd_ledblink { /* WDCMSG_SET_LED_BLINK */
283 struct uath_cmd_ledstate { /* WDCMSG_SET_LED_STATE */
287 struct uath_connkey_rec {
288 uint8_t bssid[IEEE80211_ADDR_LEN];
293 uint16_t keytype; /* WEP, TKIP or AES */
294 /* As far as I know, MIPS 4Kp is 32-bit processor */
298 uint8_t aes_keyval[16];
299 uint8_t mic_txkeyval[8];
300 uint8_t mic_rxkeyval[8];
303 int32_t keyexttsc[17];
306 /* structure for command UATH_CMD_CRYPTO */
307 struct uath_cmd_crypto {
309 #define UATH_DEFAULT_KEY 6
312 struct uath_connkey_rec rec;
315 struct uath_cmd_rateset {
317 #define UATH_MAX_NRATES 32
318 uint8_t set[UATH_MAX_NRATES];
321 /* structure for command WDCMSG_SET_BASIC_RATE */
322 struct uath_cmd_rates {
324 uint32_t keeprccontent;
326 struct uath_cmd_rateset rateset;
336 WLAN_MODE_11a_TURBO_PRIME,
337 WLAN_MODE_11g_TURBO_PRIME,
342 struct uath_cmd_connection_attr {
343 uint32_t longpreambleonly;
344 struct uath_cmd_rateset rateset;
348 /* structure for command WDCMSG_CREATE_CONNECTION */
349 struct uath_cmd_create_connection {
353 struct uath_cmd_connection_attr connattr;
356 struct uath_cmd_txq_setparams { /* WDCMSG_SET_TX_QUEUE_PARAMS */
365 struct uath_cmd_txq_attr {
375 struct uath_cmd_txq_setup { /* WDCMSG_SETUP_TX_QUEUE */
378 struct uath_cmd_txq_attr attr;
381 struct uath_cmd_stoptxdma { /* WDCMSG_STOP_TX_DMA */
386 /* structure for command UATH_CMD_31 */
392 struct uath_cmd_rx_filter { /* WDCMSG_RX_FILTER */
394 #define UATH_FILTER_RX_UCAST 0x00000001
395 #define UATH_FILTER_RX_MCAST 0x00000002
396 #define UATH_FILTER_RX_BCAST 0x00000004
397 #define UATH_FILTER_RX_CONTROL 0x00000008
398 #define UATH_FILTER_RX_BEACON 0x00000010 /* beacon frames */
399 #define UATH_FILTER_RX_PROM 0x00000020 /* promiscuous mode */
400 #define UATH_FILTER_RX_PHY_ERR 0x00000040 /* phy errors */
401 #define UATH_FILTER_RX_PHY_RADAR 0x00000080 /* radar phy errors */
402 #define UATH_FILTER_RX_XR_POOL 0x00000400 /* XR group polls */
403 #define UATH_FILTER_RX_PROBE_REQ 0x00000800
405 #define UATH_FILTER_OP_INIT 0x0
406 #define UATH_FILTER_OP_SET 0x1
407 #define UATH_FILTER_OP_CLEAR 0x2
408 #define UATH_FILTER_OP_TEMP 0x3
409 #define UATH_FILTER_OP_RESTORE 0x4
412 struct uath_cmd_rx_mcast_filter { /* WDCMSG_SET_RX_MCAST_FILTER */
417 struct uath_cmd_set_associd { /* WDCMSG_WRITE_ASSOCID */
418 uint32_t defaultrateix;
425 struct uath_cmd_set_stabeacon_timers { /* WDCMSG_SET_STA_BEACON_TIMERS */
429 uint32_t beaconperiod;
432 uint32_t cfpduration;
433 uint32_t sleepduration;
434 uint32_t bsmissthreshold;
438 CFG_NONE, /* Sentinal to indicate "no config" */
439 CFG_REG_DOMAIN, /* Regulatory Domain */
440 CFG_RATE_CONTROL_ENABLE,
441 CFG_DEF_XMIT_DATA_RATE, /* NB: if rate control is not enabled */
444 CFG_SLOW_CLOCK_ENABLE,
446 CFG_USER_RTS_THRESHOLD,
447 CFG_XR2NORM_RATE_THRESHOLD,
448 CFG_XRMODE_SWITCH_COUNT,
450 CFG_BURST_SEQ_THRESHOLD,
452 CFG_IQ_LOG_COUNT_MAX,
457 /* MAC Address to use. Overrides EEPROM */
461 /* An ID for use in error & debug messages */
470 CFG_GMODE_PROTECTION,
471 CFG_GMODE_PROTECT_RATE_INDEX,
472 CFG_GMODE_NON_ERP_PREAMBLE,
473 CFG_WDC_TRANSPORT_CHUNK_SIZE,
477 /* Sentinal to indicate "no capability" */
479 CAP_ALL, /* ALL capabilities */
485 CAP_ANALOG_5GHz_REVISION,
486 CAP_ANALOG_2GHz_REVISION,
487 /* Target supports WDC message debug features */
488 CAP_DEBUG_WDCMSG_SUPPORT,
495 CAP_CHAN_SPREAD_SUPPORT,
496 CAP_SLEEP_AFTER_BEACON_BROKEN,
497 CAP_COMPRESS_SUPPORT,
499 CAP_FAST_FRAMES_SUPPORT,
500 CAP_CHAP_TUNING_SUPPORT,
502 CAP_TURBO_PRIME_SUPPORT,
507 CAP_CONNECTION_ID_MAX, /* Should absorb CAP_KEY_CACHE_SIZE */
522 CAP_TWICE_ANTENNAGAIN_5G,
523 CAP_TWICE_ANTENNAGAIN_2G,
527 ST_NONE, /* Sentinal to indicate "no status" */
534 ST_PS_FRAMES_DROPPED,
536 ST_COUNT_OTHER_RX_ANT,
537 ST_USE_FAST_DIVERSITY,
539 ST_RX_GENERATION_NUM,
542 ST_WDC_TRANSPORT_CHUNK_SIZE,
546 BSS_ATTR_BEACON_INTERVAL,
547 BSS_ATTR_DTIM_INTERVAL,
548 BSS_ATTR_CFP_INTERVAL,
549 BSS_ATTR_CFP_MAX_DURATION,
550 BSS_ATTR_ATIM_WINDOW,
551 BSS_ATTR_DEFAULT_RATE_INDEX,
552 BSS_ATTR_SHORT_SLOT_TIME_11g,
553 BSS_ATTR_SLEEP_DURATION,
554 BSS_ATTR_BMISS_THRESHOLD,
555 BSS_ATTR_TPC_POWER_LIMIT,
556 BSS_ATTR_BSS_KEY_UPDATE,
559 struct uath_cmd_update_bss_attribute {
561 uint32_t attribute; /* BSS_ATTR_BEACON_INTERVAL, et al. */
562 uint32_t cfgsize; /* should be zero 0 */
566 struct uath_cmd_update_bss_attribute_key {
568 uint32_t attribute; /* BSS_ATTR_BSS_KEY_UPDATE */
569 uint32_t cfgsize; /* size of remaining data */
571 uint32_t isdefaultkey;
572 uint32_t keyiv; /* IV generation control */
573 uint32_t extkeyiv; /* extended IV for TKIP & CCM */
576 uint32_t initvalue; /* XXX */
578 uint32_t mictxkeyval[2];
579 uint32_t micrxkeyval[2];
587 TARGET_DEVICE_PWRSAVE,
588 TARGET_DEVICE_SUSPEND,
589 TARGET_DEVICE_RESUME,
592 #define UATH_MAX_TXBUFSZ \
593 (sizeof(struct uath_chunk) + sizeof(struct uath_tx_desc) + \
597 * it's not easy to measure how the chunk is passed into the host if the target
598 * passed the multi-chunks so just we check a minimal size we can imagine.
600 #define UATH_MIN_RXBUFSZ (sizeof(struct uath_chunk))