2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <sys/cdefs.h>
18 __FBSDID("$FreeBSD$");
19 #include <sys/param.h>
20 #include <sys/sockio.h>
21 #include <sys/sysctl.h>
23 #include <sys/mutex.h>
25 #include <sys/kernel.h>
26 #include <sys/socket.h>
27 #include <sys/systm.h>
28 #include <sys/malloc.h>
29 #include <sys/module.h>
31 #include <sys/endian.h>
34 #include <machine/bus.h>
35 #include <machine/resource.h>
39 #include <net/if_arp.h>
40 #include <net/ethernet.h>
41 #include <net/if_dl.h>
42 #include <net/if_media.h>
43 #include <net/if_types.h>
46 #include <netinet/in.h>
47 #include <netinet/in_systm.h>
48 #include <netinet/in_var.h>
49 #include <netinet/if_ether.h>
50 #include <netinet/ip.h>
53 #include <net80211/ieee80211_var.h>
54 #include <net80211/ieee80211_regdomain.h>
55 #include <net80211/ieee80211_radiotap.h>
57 #include <dev/usb/usb.h>
58 #include <dev/usb/usb_core.h>
59 #include <dev/usb/usb_busdma.h>
60 #include <dev/usb/usb_debug.h>
61 #include <dev/usb/usb_error.h>
62 #include <dev/usb/usb_lookup.h>
63 #include <dev/usb/usb_request.h>
64 #include <dev/usb/usb_util.h>
67 #include <dev/usb/wlan/if_urtwreg.h>
68 #include <dev/usb/wlan/if_urtwvar.h>
70 SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L");
73 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RW, &urtw_debug, 0,
74 "control debugging printfs");
75 TUNABLE_INT("hw.usb.urtw.debug", &urtw_debug);
77 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
78 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */
79 URTW_DEBUG_RESET = 0x00000004, /* reset processing */
80 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
81 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
82 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */
83 URTW_DEBUG_STAT = 0x00000040, /* statistic */
84 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */
85 URTW_DEBUG_ANY = 0xffffffff
87 #define DPRINTF(sc, m, fmt, ...) do { \
88 if (sc->sc_debug & (m)) \
89 printf(fmt, __VA_ARGS__); \
92 #define DPRINTF(sc, m, fmt, ...) do { \
96 int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG;
97 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RW,
98 &urtw_preamble_mode, 0, "set the preable mode (long or short)");
99 TUNABLE_INT("hw.usb.urtw.preamble_mode", &urtw_preamble_mode);
101 /* recognized device vendors/products */
102 #define urtw_lookup(v, p) \
103 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p))
104 #define URTW_DEV_B(v,p) \
105 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) }
106 #define URTW_DEV_L(v,p) \
107 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) }
108 #define URTW_REV_RTL8187B 0
109 #define URTW_REV_RTL8187L 1
110 static const struct usb2_device_id urtw_devs[] = {
111 { USB_VPI(USB_VENDOR_BELKIN, 0x705e, URTW_REV_RTL8187B) },
112 { USB_VPI(USB_VENDOR_REALTEK, 0x8189, URTW_REV_RTL8187B) },
113 { USB_VPI(USB_VENDOR_REALTEK, 0x8197, URTW_REV_RTL8187B) },
114 { USB_VPI(USB_VENDOR_REALTEK, 0x8198, URTW_REV_RTL8187B) },
115 { USB_VPI(USB_VENDOR_NETGEAR, 0x4260, URTW_REV_RTL8187B) },
116 { USB_VPI(0x1b75, 0x8187, URTW_REV_RTL8187L) },
117 { USB_VPI(USB_VENDOR_ASUS, 0x171d, URTW_REV_RTL8187L) },
118 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) },
119 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) },
120 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) },
121 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) },
122 URTW_DEV_L(NETGEAR, WG111V2),
123 URTW_DEV_L(REALTEK, RTL8187),
124 { USB_VPI(USB_VENDOR_SITECOMEU, 0x000d, URTW_REV_RTL8187L) },
125 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) },
126 { USB_VPI(USB_VENDOR_SURECOM, 0x11f2, URTW_REV_RTL8187L) },
127 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) },
132 #define urtw_read8_m(sc, val, data) do { \
133 error = urtw_read8_c(sc, val, data); \
137 #define urtw_write8_m(sc, val, data) do { \
138 error = urtw_write8_c(sc, val, data); \
142 #define urtw_read16_m(sc, val, data) do { \
143 error = urtw_read16_c(sc, val, data); \
147 #define urtw_write16_m(sc, val, data) do { \
148 error = urtw_write16_c(sc, val, data); \
152 #define urtw_read32_m(sc, val, data) do { \
153 error = urtw_read32_c(sc, val, data); \
157 #define urtw_write32_m(sc, val, data) do { \
158 error = urtw_write32_c(sc, val, data); \
162 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \
163 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
167 #define urtw_8187_write_phy_cck(sc, val, data) do { \
168 error = urtw_8187_write_phy_cck_c(sc, val, data); \
172 #define urtw_8225_write(sc, val, data) do { \
173 error = urtw_8225_write_c(sc, val, data); \
183 static uint8_t urtw_8225_agc[] = {
184 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b,
185 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90,
186 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85,
187 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a,
188 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f,
189 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24,
190 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19,
191 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
192 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
193 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
194 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
195 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
198 static uint8_t urtw_8225z2_agc[] = {
199 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51,
200 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b,
201 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25,
202 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f,
203 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
204 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19,
205 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23,
206 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a,
207 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d,
208 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31,
209 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
210 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
213 static uint32_t urtw_8225_channel[] = {
214 0x0000, /* dummy channel 0 */
231 static uint8_t urtw_8225_gain[] = {
232 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
233 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
234 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
235 0x33, 0x80, 0x79, 0xc5, /* -78dbm */
236 0x43, 0x78, 0x76, 0xc5, /* -74dbm */
237 0x53, 0x60, 0x73, 0xc5, /* -70dbm */
238 0x63, 0x58, 0x70, 0xc5, /* -66dbm */
241 static struct urtw_pair urtw_8225_rf_part1[] = {
242 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
243 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a },
244 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 },
245 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 },
248 static struct urtw_pair urtw_8225_rf_part2[] = {
249 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
250 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
251 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 },
252 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 },
253 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 },
254 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef },
255 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 },
256 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 },
257 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 },
261 static struct urtw_pair urtw_8225_rf_part3[] = {
262 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
263 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b },
264 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 },
265 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d },
266 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e },
267 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a },
268 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
271 static uint16_t urtw_8225_rxgain[] = {
272 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
273 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
274 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
275 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
276 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
277 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
278 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
279 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
280 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
281 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
282 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
283 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
286 static uint8_t urtw_8225_threshold[] = {
287 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
290 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = {
291 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
294 static uint8_t urtw_8225_txpwr_cck[] = {
295 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
296 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
297 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
298 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
299 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
300 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
303 static uint8_t urtw_8225_txpwr_cck_ch14[] = {
304 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
305 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
306 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
307 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
308 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
309 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
312 static uint8_t urtw_8225_txpwr_ofdm[]={
313 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
316 static uint8_t urtw_8225v2_gain_bg[]={
317 0x23, 0x15, 0xa5, /* -82-1dbm */
318 0x23, 0x15, 0xb5, /* -82-2dbm */
319 0x23, 0x15, 0xc5, /* -82-3dbm */
320 0x33, 0x15, 0xc5, /* -78dbm */
321 0x43, 0x15, 0xc5, /* -74dbm */
322 0x53, 0x15, 0xc5, /* -70dbm */
323 0x63, 0x15, 0xc5, /* -66dbm */
326 static struct urtw_pair urtw_8225v2_rf_part1[] = {
327 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
328 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
329 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
330 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
333 static struct urtw_pair urtw_8225v2b_rf_part1[] = {
334 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
335 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
336 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
337 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
340 static struct urtw_pair urtw_8225v2_rf_part2[] = {
341 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
342 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
343 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 },
344 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 },
345 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 },
346 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 },
347 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 },
348 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 },
349 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 },
350 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 }
353 static struct urtw_pair urtw_8225v2b_rf_part2[] = {
354 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 },
355 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 },
356 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 },
357 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 },
358 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 },
359 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 },
360 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 },
361 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 },
362 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a },
363 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f },
364 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 },
365 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 },
366 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 },
367 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e },
368 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 }
371 static struct urtw_pair urtw_8225v2_rf_part3[] = {
372 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
373 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 },
374 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 },
375 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 },
376 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d },
377 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 },
378 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 },
379 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 }
382 static uint16_t urtw_8225v2_rxgain[] = {
383 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009,
384 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141,
385 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183,
386 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244,
387 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288,
388 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345,
389 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389,
390 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393,
391 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d,
392 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9,
393 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
394 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
397 static uint16_t urtw_8225v2b_rxgain[] = {
398 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
399 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
400 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
401 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
402 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
403 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
404 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
405 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
406 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
407 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
408 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
409 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
412 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = {
413 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
414 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
415 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
416 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
417 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
418 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
421 static uint8_t urtw_8225v2_txpwr_cck[] = {
422 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
425 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = {
426 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
429 static uint8_t urtw_8225v2b_txpwr_cck[] = {
430 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
431 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
432 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
433 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
436 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = {
437 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
438 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
439 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
440 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
443 static struct urtw_pair urtw_ratetable[] = {
444 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 },
445 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 },
446 { 96, 10 }, { 108, 11 }
449 static const uint8_t urtw_8187b_reg_table[][3] = {
450 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 },
451 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 },
452 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 },
453 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 },
454 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 },
455 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 },
456 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 },
457 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 },
458 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 },
459 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 },
460 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 },
461 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 },
462 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 },
463 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 },
464 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 },
465 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 },
466 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 },
467 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 },
468 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 },
469 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 },
470 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 },
471 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 },
472 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 },
473 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 },
474 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 },
475 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 },
476 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 },
477 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 },
478 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 },
479 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 },
480 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 }
483 static usb2_callback_t urtw_bulk_rx_callback;
484 static usb2_callback_t urtw_bulk_tx_callback;
486 static const struct usb2_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = {
487 [URTW_8187B_BULK_RX] = {
490 .direction = UE_DIR_IN,
497 .callback = urtw_bulk_rx_callback
499 [URTW_8187B_BULK_TX_BE] = {
501 .endpoint = URTW_8187B_TXPIPE_BE,
502 .direction = UE_DIR_OUT,
503 .bufsize = URTW_TX_MAXSIZE,
506 .force_short_xfer = 1,
509 .callback = urtw_bulk_tx_callback,
510 .timeout = URTW_DATA_TIMEOUT
512 [URTW_8187B_BULK_TX_BK] = {
514 .endpoint = URTW_8187B_TXPIPE_BK,
515 .direction = UE_DIR_OUT,
516 .bufsize = URTW_TX_MAXSIZE,
519 .force_short_xfer = 1,
522 .callback = urtw_bulk_tx_callback,
523 .timeout = URTW_DATA_TIMEOUT
525 [URTW_8187B_BULK_TX_VI] = {
527 .endpoint = URTW_8187B_TXPIPE_VI,
528 .direction = UE_DIR_OUT,
529 .bufsize = URTW_TX_MAXSIZE,
532 .force_short_xfer = 1,
535 .callback = urtw_bulk_tx_callback,
536 .timeout = URTW_DATA_TIMEOUT
538 [URTW_8187B_BULK_TX_VO] = {
540 .endpoint = URTW_8187B_TXPIPE_VO,
541 .direction = UE_DIR_OUT,
542 .bufsize = URTW_TX_MAXSIZE,
545 .force_short_xfer = 1,
548 .callback = urtw_bulk_tx_callback,
549 .timeout = URTW_DATA_TIMEOUT
551 [URTW_8187B_BULK_TX_EP12] = {
554 .direction = UE_DIR_OUT,
555 .bufsize = URTW_TX_MAXSIZE,
558 .force_short_xfer = 1,
561 .callback = urtw_bulk_tx_callback,
562 .timeout = URTW_DATA_TIMEOUT
566 static const struct usb2_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = {
567 [URTW_8187L_BULK_RX] = {
570 .direction = UE_DIR_IN,
577 .callback = urtw_bulk_rx_callback
579 [URTW_8187L_BULK_TX_LOW] = {
582 .direction = UE_DIR_OUT,
583 .bufsize = URTW_TX_MAXSIZE,
586 .force_short_xfer = 1,
589 .callback = urtw_bulk_tx_callback,
590 .timeout = URTW_DATA_TIMEOUT
592 [URTW_8187L_BULK_TX_NORMAL] = {
595 .direction = UE_DIR_OUT,
596 .bufsize = URTW_TX_MAXSIZE,
599 .force_short_xfer = 1,
602 .callback = urtw_bulk_tx_callback,
603 .timeout = URTW_DATA_TIMEOUT
607 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *,
608 const char name[IFNAMSIZ], int unit, int opmode,
609 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
610 const uint8_t mac[IEEE80211_ADDR_LEN]);
611 static void urtw_vap_delete(struct ieee80211vap *);
612 static void urtw_init(void *);
613 static void urtw_stop(struct ifnet *, int);
614 static void urtw_stop_locked(struct ifnet *, int);
615 static int urtw_ioctl(struct ifnet *, u_long, caddr_t);
616 static void urtw_start(struct ifnet *);
617 static int urtw_alloc_rx_data_list(struct urtw_softc *);
618 static int urtw_alloc_tx_data_list(struct urtw_softc *);
619 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *,
620 const struct ieee80211_bpf_params *);
621 static void urtw_scan_start(struct ieee80211com *);
622 static void urtw_scan_end(struct ieee80211com *);
623 static void urtw_set_channel(struct ieee80211com *);
624 static void urtw_update_mcast(struct ifnet *);
625 static int urtw_tx_start(struct urtw_softc *,
626 struct ieee80211_node *, struct mbuf *,
627 struct urtw_data *, int);
628 static int urtw_newstate(struct ieee80211vap *,
629 enum ieee80211_state, int);
630 static void urtw_led_ch(void *);
631 static void urtw_ledtask(void *, int);
632 static void urtw_watchdog(void *);
633 static void urtw_set_multi(void *);
634 static int urtw_isbmode(uint16_t);
635 static uint16_t urtw_rate2rtl(int);
636 static uint16_t urtw_rtl2rate(int);
637 static usb2_error_t urtw_set_rate(struct urtw_softc *);
638 static usb2_error_t urtw_update_msr(struct urtw_softc *);
639 static usb2_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *);
640 static usb2_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *);
641 static usb2_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *);
642 static usb2_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t);
643 static usb2_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t);
644 static usb2_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t);
645 static usb2_error_t urtw_eprom_cs(struct urtw_softc *, int);
646 static usb2_error_t urtw_eprom_ck(struct urtw_softc *);
647 static usb2_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *,
649 static usb2_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t,
651 static usb2_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *);
652 static usb2_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t);
653 static usb2_error_t urtw_get_macaddr(struct urtw_softc *);
654 static usb2_error_t urtw_get_txpwr(struct urtw_softc *);
655 static usb2_error_t urtw_get_rfchip(struct urtw_softc *);
656 static usb2_error_t urtw_led_init(struct urtw_softc *);
657 static usb2_error_t urtw_8185_rf_pins_enable(struct urtw_softc *);
658 static usb2_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t);
659 static usb2_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t,
661 static usb2_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *,
663 static usb2_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t,
665 static usb2_error_t urtw_8225_setgain(struct urtw_softc *, int16_t);
666 static usb2_error_t urtw_8225_usb_init(struct urtw_softc *);
667 static usb2_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t,
669 static usb2_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int,
671 static usb2_error_t urtw_8225_read(struct urtw_softc *, uint8_t,
673 static usb2_error_t urtw_8225_rf_init(struct urtw_softc *);
674 static usb2_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int);
675 static usb2_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int);
676 static usb2_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int);
677 static usb2_error_t urtw_8225_rf_stop(struct urtw_softc *);
678 static usb2_error_t urtw_8225v2_rf_init(struct urtw_softc *);
679 static usb2_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int);
680 static usb2_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int);
681 static usb2_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t);
682 static usb2_error_t urtw_8225_isv2(struct urtw_softc *, int *);
683 static usb2_error_t urtw_8225v2b_rf_init(struct urtw_softc *);
684 static usb2_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int);
685 static usb2_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *);
686 static usb2_error_t urtw_write8e(struct urtw_softc *, int, uint8_t);
687 static usb2_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t);
688 static usb2_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t);
689 static usb2_error_t urtw_intr_enable(struct urtw_softc *);
690 static usb2_error_t urtw_intr_disable(struct urtw_softc *);
691 static usb2_error_t urtw_reset(struct urtw_softc *);
692 static usb2_error_t urtw_led_on(struct urtw_softc *, int);
693 static usb2_error_t urtw_led_ctl(struct urtw_softc *, int);
694 static usb2_error_t urtw_led_blink(struct urtw_softc *);
695 static usb2_error_t urtw_led_mode0(struct urtw_softc *, int);
696 static usb2_error_t urtw_led_mode1(struct urtw_softc *, int);
697 static usb2_error_t urtw_led_mode2(struct urtw_softc *, int);
698 static usb2_error_t urtw_led_mode3(struct urtw_softc *, int);
699 static usb2_error_t urtw_rx_setconf(struct urtw_softc *);
700 static usb2_error_t urtw_rx_enable(struct urtw_softc *);
701 static usb2_error_t urtw_tx_enable(struct urtw_softc *sc);
702 static void urtw_free_tx_data_list(struct urtw_softc *);
703 static void urtw_free_rx_data_list(struct urtw_softc *);
704 static void urtw_free_data_list(struct urtw_softc *,
705 struct urtw_data data[], int, int);
706 static usb2_error_t urtw_adapter_start(struct urtw_softc *);
707 static usb2_error_t urtw_adapter_start_b(struct urtw_softc *);
708 static usb2_error_t urtw_set_mode(struct urtw_softc *, uint32_t);
709 static usb2_error_t urtw_8187b_cmd_reset(struct urtw_softc *);
710 static usb2_error_t urtw_write16_i(struct urtw_softc *, int, uint16_t, int);
711 static usb2_error_t urtw_write8_i(struct urtw_softc *, int, uint8_t, int);
712 static usb2_error_t urtw_write32_i(struct urtw_softc *, int, uint32_t, int);
713 static usb2_error_t urtw_do_request(struct urtw_softc *,
714 struct usb2_device_request *, void *);
715 static usb2_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int);
716 static usb2_error_t urtw_led_off(struct urtw_softc *, int);
717 static void urtw_abort_xfers(struct urtw_softc *);
718 static struct urtw_data *
719 urtw_getbuf(struct urtw_softc *sc);
722 urtw_match(device_t dev)
724 struct usb2_attach_arg *uaa = device_get_ivars(dev);
726 if (uaa->usb_mode != USB_MODE_HOST)
728 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX)
730 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX)
733 return (usb2_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa));
737 urtw_attach(device_t dev)
739 const struct usb2_config *setup_start;
741 struct urtw_softc *sc = device_get_softc(dev);
742 struct usb2_attach_arg *uaa = device_get_ivars(dev);
743 struct ieee80211com *ic;
745 uint8_t bands, iface_index = URTW_IFACE_INDEX; /* XXX */
750 device_set_usb2_desc(dev);
753 sc->sc_udev = uaa->device;
754 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B)
755 sc->sc_flags |= URTW_RTL8187B;
757 sc->sc_debug = urtw_debug;
760 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK,
762 usb2_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0);
763 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc);
764 callout_init(&sc->sc_watchdog_ch, 0);
766 if (sc->sc_flags & URTW_RTL8187B) {
767 setup_start = urtw_8187b_usbconfig;
768 n_setup = URTW_8187B_N_XFERS;
770 setup_start = urtw_8187l_usbconfig;
771 n_setup = URTW_8187L_N_XFERS;
774 error = usb2_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
775 setup_start, n_setup, sc, &sc->sc_mtx);
777 device_printf(dev, "could not allocate USB transfers, "
778 "err=%s\n", usb2_errstr(error));
785 urtw_read32_m(sc, URTW_RX, &data);
786 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 :
789 error = urtw_get_rfchip(sc);
792 error = urtw_get_macaddr(sc);
795 error = urtw_get_txpwr(sc);
798 error = urtw_led_init(sc);
804 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY;
805 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY;
807 sc->sc_preamble_mode = urtw_preamble_mode;
809 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
811 device_printf(sc->sc_dev, "can not allocate ifnet\n");
817 if_initname(ifp, "urtw", device_get_unit(sc->sc_dev));
818 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
819 ifp->if_init = urtw_init;
820 ifp->if_ioctl = urtw_ioctl;
821 ifp->if_start = urtw_start;
822 /* XXX URTW_TX_DATA_LIST_COUNT */
823 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
824 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
825 IFQ_SET_READY(&ifp->if_snd);
829 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
830 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
832 /* set device capabilities */
834 IEEE80211_C_STA | /* station mode */
835 IEEE80211_C_MONITOR | /* monitor mode supported */
836 IEEE80211_C_TXPMGT | /* tx power management */
837 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
838 IEEE80211_C_SHSLOT | /* short slot time supported */
839 IEEE80211_C_BGSCAN | /* capable of bg scanning */
840 IEEE80211_C_WPA; /* 802.11i */
843 setbit(&bands, IEEE80211_MODE_11B);
844 setbit(&bands, IEEE80211_MODE_11G);
845 ieee80211_init_channels(ic, NULL, &bands);
847 ieee80211_ifattach(ic, sc->sc_bssid);
848 ic->ic_raw_xmit = urtw_raw_xmit;
849 ic->ic_scan_start = urtw_scan_start;
850 ic->ic_scan_end = urtw_scan_end;
851 ic->ic_set_channel = urtw_set_channel;
853 ic->ic_vap_create = urtw_vap_create;
854 ic->ic_vap_delete = urtw_vap_delete;
855 ic->ic_update_mcast = urtw_update_mcast;
857 ieee80211_radiotap_attach(ic,
858 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
859 URTW_TX_RADIOTAP_PRESENT,
860 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
861 URTW_RX_RADIOTAP_PRESENT);
864 ieee80211_announce(ic);
867 fail: URTW_UNLOCK(sc);
868 fail1: usb2_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ?
869 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS);
875 urtw_detach(device_t dev)
877 struct urtw_softc *sc = device_get_softc(dev);
878 struct ifnet *ifp = sc->sc_ifp;
879 struct ieee80211com *ic = ifp->if_l2com;
881 if (!device_is_attached(dev))
885 ieee80211_draintask(ic, &sc->sc_led_task);
887 usb2_callout_drain(&sc->sc_led_ch);
888 callout_drain(&sc->sc_watchdog_ch);
890 usb2_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ?
891 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS);
892 ieee80211_ifdetach(ic);
894 urtw_free_tx_data_list(sc);
895 urtw_free_rx_data_list(sc);
898 mtx_destroy(&sc->sc_mtx);
904 urtw_free_tx_data_list(struct urtw_softc *sc)
907 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0);
911 urtw_free_rx_data_list(struct urtw_softc *sc)
914 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1);
918 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata,
923 for (i = 0; i < ndata; i++) {
924 struct urtw_data *dp = &data[i];
933 if (dp->buf != NULL) {
934 free(dp->buf, M_USBDEV);
938 if (dp->ni != NULL) {
939 ieee80211_free_node(dp->ni);
945 static struct ieee80211vap *
946 urtw_vap_create(struct ieee80211com *ic,
947 const char name[IFNAMSIZ], int unit, int opmode, int flags,
948 const uint8_t bssid[IEEE80211_ADDR_LEN],
949 const uint8_t mac[IEEE80211_ADDR_LEN])
951 struct urtw_vap *uvp;
952 struct ieee80211vap *vap;
954 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
956 uvp = (struct urtw_vap *) malloc(sizeof(struct urtw_vap),
957 M_80211_VAP, M_NOWAIT | M_ZERO);
961 /* enable s/w bmiss handling for sta mode */
962 ieee80211_vap_setup(ic, vap, name, unit, opmode,
963 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac);
965 /* override state transition machine */
966 uvp->newstate = vap->iv_newstate;
967 vap->iv_newstate = urtw_newstate;
970 ieee80211_vap_attach(vap, ieee80211_media_change,
971 ieee80211_media_status);
972 ic->ic_opmode = opmode;
977 urtw_vap_delete(struct ieee80211vap *vap)
979 struct urtw_vap *uvp = URTW_VAP(vap);
981 ieee80211_vap_detach(vap);
982 free(uvp, M_80211_VAP);
986 urtw_init_locked(void *arg)
989 struct urtw_softc *sc = arg;
990 struct ifnet *ifp = sc->sc_ifp;
993 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
994 urtw_stop_locked(ifp, 0);
996 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) :
997 urtw_adapter_start(sc);
1001 /* reset softc variables */
1004 if (!(sc->sc_flags & URTW_INIT_ONCE)) {
1005 ret = urtw_alloc_rx_data_list(sc);
1008 ret = urtw_alloc_tx_data_list(sc);
1011 sc->sc_flags |= URTW_INIT_ONCE;
1014 error = urtw_rx_enable(sc);
1017 error = urtw_tx_enable(sc);
1021 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1022 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1024 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1030 urtw_init(void *arg)
1032 struct urtw_softc *sc = arg;
1035 urtw_init_locked(arg);
1040 urtw_adapter_start_b(struct urtw_softc *sc)
1042 #define N(a) (sizeof(a) / sizeof((a)[0]))
1047 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1051 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1052 urtw_write8_m(sc, URTW_CONFIG3,
1053 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT);
1054 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON);
1055 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON);
1056 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON);
1058 urtw_write8_m(sc, 0x61, 0x10);
1059 urtw_read8_m(sc, 0x62, &data8);
1060 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5));
1061 urtw_write8_m(sc, 0x62, data8 | (1 << 5));
1063 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1064 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE;
1065 urtw_write8_m(sc, URTW_CONFIG3, data8);
1067 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1071 error = urtw_8187b_cmd_reset(sc);
1075 urtw_write16_m(sc, 0x2d, 0xfff);
1076 urtw_read8_m(sc, URTW_CW_CONF, &data8);
1077 urtw_write8_m(sc, URTW_CW_CONF, data8 | URTW_CW_CONF_PERPACKET_RETRY);
1078 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
1079 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN |
1080 URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
1081 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
1083 error = urtw_write16_i(sc, 0xe0, 0xfff, 1);
1087 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8);
1088 urtw_write8_m(sc, URTW_RATE_FALLBACK, data8 | URTW_RATE_FALLBACK_ENABLE);
1090 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1091 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1092 error = urtw_write16_i(sc, 0xd4, 0xffff, 1);
1096 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1099 urtw_read8_m(sc, URTW_CONFIG1, &data8);
1100 urtw_write8_m(sc, URTW_CONFIG1, (data8 & 0x3f) | 0x80);
1101 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1105 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
1106 for (i = 0; i < N(urtw_8187b_reg_table); i++) {
1107 error = urtw_write8_i(sc, urtw_8187b_reg_table[i][0],
1108 urtw_8187b_reg_table[i][1], urtw_8187b_reg_table[i][2]);
1113 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50);
1114 urtw_write16_m(sc, URTW_INT_MIG, 0);
1116 error = urtw_write32_i(sc, 0xf0, 0, 1);
1119 error = urtw_write32_i(sc, 0xf4, 0, 1);
1122 error = urtw_write8_i(sc, 0xf8, 0, 1);
1126 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001);
1128 error = urtw_write16_i(sc, 0x72, 0x569a, 2);
1132 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1135 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1136 urtw_write8_m(sc, URTW_CONFIG3, data8 | URTW_CONFIG3_ANAPARAM_WRITE);
1137 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1141 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480);
1142 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488);
1143 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff);
1144 usb2_pause_mtx(&sc->sc_mtx, 100);
1146 error = sc->sc_rf_init(sc);
1150 error = urtw_intr_enable(sc);
1154 error = urtw_write8e(sc, 0x41, 0xf4);
1157 error = urtw_write8e(sc, 0x40, 0x00);
1160 error = urtw_write8e(sc, 0x42, 0x00);
1163 error = urtw_write8e(sc, 0x42, 0x01);
1166 error = urtw_write8e(sc, 0x40, 0x0f);
1169 error = urtw_write8e(sc, 0x42, 0x00);
1172 error = urtw_write8e(sc, 0x42, 0x01);
1176 urtw_read8_m(sc, 0xdb, &data8);
1177 urtw_write8_m(sc, 0xdb, data8 | (1 << 2));
1178 error = urtw_write16_i(sc, 0x72, 0x59fa, 3);
1181 error = urtw_write16_i(sc, 0x74, 0x59d2, 3);
1184 error = urtw_write16_i(sc, 0x76, 0x59d2, 3);
1187 error = urtw_write16_i(sc, 0x78, 0x19fa, 3);
1190 error = urtw_write16_i(sc, 0x7a, 0x19fa, 3);
1193 error = urtw_write16_i(sc, 0x7c, 0x00d0, 3);
1196 urtw_write8_m(sc, 0x61, 0);
1197 error = urtw_write8_i(sc, 0x80, 0x0f, 1);
1200 error = urtw_write8_i(sc, 0x83, 0x03, 1);
1203 urtw_write8_m(sc, 0xda, 0x10);
1204 error = urtw_write8_i(sc, 0x4d, 0x08, 2);
1208 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321B);
1210 error = urtw_write16_i(sc, 0xec, 0x800, 1);
1220 urtw_adapter_start(struct urtw_softc *sc)
1224 error = urtw_reset(sc);
1228 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0);
1229 urtw_write8_m(sc, URTW_GPIO, 0);
1232 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1233 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON);
1237 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1240 /* applying MAC address again. */
1241 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)sc->sc_bssid)[0]);
1242 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)sc->sc_bssid)[1] & 0xffff);
1243 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1247 error = urtw_update_msr(sc);
1251 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0);
1252 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
1253 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1);
1254 error = urtw_set_rate(sc);
1258 error = sc->sc_rf_init(sc);
1261 if (sc->sc_rf_set_sens != NULL)
1262 sc->sc_rf_set_sens(sc, sc->sc_sens);
1264 /* XXX correct? to call write16 */
1265 urtw_write16_m(sc, URTW_PSR, 1);
1266 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10);
1267 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80);
1268 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60);
1269 /* XXX correct? to call write16 */
1270 urtw_write16_m(sc, URTW_PSR, 0);
1271 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1273 error = urtw_intr_enable(sc);
1282 urtw_set_mode(struct urtw_softc *sc, uint32_t mode)
1287 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1288 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT);
1289 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK);
1290 urtw_write8_m(sc, URTW_EPROM_CMD, data);
1296 urtw_8187b_cmd_reset(struct urtw_softc *sc)
1302 /* XXX the code can be duplicate with urtw_reset(). */
1303 urtw_read8_m(sc, URTW_CMD, &data8);
1304 data8 = (data8 & 0x2) | URTW_CMD_RST;
1305 urtw_write8_m(sc, URTW_CMD, data8);
1307 for (i = 0; i < 20; i++) {
1308 usb2_pause_mtx(&sc->sc_mtx, 2);
1309 urtw_read8_m(sc, URTW_CMD, &data8);
1310 if (!(data8 & URTW_CMD_RST))
1314 device_printf(sc->sc_dev, "reset timeout\n");
1318 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
1322 for (i = 0; i < 20; i++) {
1323 usb2_pause_mtx(&sc->sc_mtx, 4);
1324 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
1325 if (!(data8 & URTW_EPROM_CMD_CONFIG))
1329 device_printf(sc->sc_dev, "eeprom reset timeout\n");
1338 urtw_write16_i(struct urtw_softc *sc, int val, uint16_t data, int idx)
1340 struct usb2_device_request req;
1342 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1343 req.bRequest = URTW_8187_SETREGS_REQ;
1344 USETW(req.wValue, val | 0xff00);
1345 USETW(req.wIndex, idx & 0x3);
1346 USETW(req.wLength, sizeof(uint16_t));
1348 return (urtw_do_request(sc, &req, &data));
1352 urtw_do_request(struct urtw_softc *sc,
1353 struct usb2_device_request *req, void *data)
1358 URTW_ASSERT_LOCKED(sc);
1361 err = usb2_do_request_flags(sc->sc_udev, &sc->sc_mtx,
1362 req, data, 0, NULL, 250 /* ms */);
1366 DPRINTF(sc, URTW_DEBUG_INIT,
1367 "Control request failed, %s (retrying)\n",
1369 usb2_pause_mtx(&sc->sc_mtx, hz / 100);
1375 urtw_write8_i(struct urtw_softc *sc, int val, uint8_t data, int idx)
1377 struct usb2_device_request req;
1379 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1380 req.bRequest = URTW_8187_SETREGS_REQ;
1381 USETW(req.wValue, val | 0xff00);
1382 USETW(req.wIndex, idx & 0x3);
1383 USETW(req.wLength, sizeof(uint8_t));
1385 return (urtw_do_request(sc, &req, &data));
1389 urtw_write32_i(struct urtw_softc *sc, int val, uint32_t data, int idx)
1391 struct usb2_device_request req;
1393 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1394 req.bRequest = URTW_8187_SETREGS_REQ;
1395 USETW(req.wValue, val | 0xff00);
1396 USETW(req.wIndex, idx & 0x3);
1397 USETW(req.wLength, sizeof(uint32_t));
1399 return (urtw_do_request(sc, &req, &data));
1403 urtw_stop_locked(struct ifnet *ifp, int disable)
1405 struct urtw_softc *sc = ifp->if_softc;
1410 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1412 error = urtw_intr_disable(sc);
1415 urtw_read8_m(sc, URTW_CMD, &data8);
1416 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1417 urtw_write8_m(sc, URTW_CMD, data8);
1419 error = sc->sc_rf_stop(sc);
1423 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1426 urtw_read8_m(sc, URTW_CONFIG4, &data8);
1427 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF);
1428 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1433 device_printf(sc->sc_dev, "failed to stop (%s)\n",
1434 usb2_errstr(error));
1436 usb2_callout_stop(&sc->sc_led_ch);
1437 callout_stop(&sc->sc_watchdog_ch);
1439 urtw_abort_xfers(sc);
1443 urtw_stop(struct ifnet *ifp, int disable)
1445 struct urtw_softc *sc = ifp->if_softc;
1448 urtw_stop_locked(ifp, disable);
1453 urtw_abort_xfers(struct urtw_softc *sc)
1457 URTW_ASSERT_LOCKED(sc);
1459 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS :
1462 /* abort any pending transfers */
1463 for (i = 0; i < max; i++)
1464 usb2_transfer_stop(sc->sc_xfer[i]);
1468 urtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1470 struct urtw_softc *sc = ifp->if_softc;
1471 struct ieee80211com *ic = ifp->if_l2com;
1472 struct ifreq *ifr = (struct ifreq *) data;
1473 int error = 0, startall = 0;
1477 if (ifp->if_flags & IFF_UP) {
1478 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1479 if ((ifp->if_flags ^ sc->sc_if_flags) &
1480 (IFF_ALLMULTI | IFF_PROMISC))
1483 urtw_init(ifp->if_softc);
1487 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1490 sc->sc_if_flags = ifp->if_flags;
1492 ieee80211_start_all(ic);
1495 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1498 error = ether_ioctl(ifp, cmd, data);
1509 urtw_start(struct ifnet *ifp)
1511 struct urtw_data *bf;
1512 struct urtw_softc *sc = ifp->if_softc;
1513 struct ieee80211_node *ni;
1516 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1521 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1524 bf = urtw_getbuf(sc);
1526 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1530 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1531 m->m_pkthdr.rcvif = NULL;
1533 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) {
1535 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1536 ieee80211_free_node(ni);
1546 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[],
1547 int ndata, int maxsz, int fillmbuf)
1551 for (i = 0; i < ndata; i++) {
1552 struct urtw_data *dp = &data[i];
1556 dp->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1557 if (dp->m == NULL) {
1558 device_printf(sc->sc_dev,
1559 "could not allocate rx mbuf\n");
1563 dp->buf = mtod(dp->m, uint8_t *);
1566 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT);
1567 if (dp->buf == NULL) {
1568 device_printf(sc->sc_dev,
1569 "could not allocate buffer\n");
1573 if (((unsigned long)dp->buf) % 4)
1574 device_printf(sc->sc_dev,
1575 "warn: unaligned buffer %p\n", dp->buf);
1582 fail: urtw_free_data_list(sc, data, ndata, fillmbuf);
1587 urtw_alloc_rx_data_list(struct urtw_softc *sc)
1591 error = urtw_alloc_data_list(sc,
1592 sc->sc_rx, URTW_RX_DATA_LIST_COUNT, MCLBYTES, 1 /* mbufs */);
1596 STAILQ_INIT(&sc->sc_rx_active);
1597 STAILQ_INIT(&sc->sc_rx_inactive);
1599 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++)
1600 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1606 urtw_alloc_tx_data_list(struct urtw_softc *sc)
1610 error = urtw_alloc_data_list(sc,
1611 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE,
1616 STAILQ_INIT(&sc->sc_tx_active);
1617 STAILQ_INIT(&sc->sc_tx_inactive);
1618 STAILQ_INIT(&sc->sc_tx_pending);
1620 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++)
1621 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i],
1628 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1629 const struct ieee80211_bpf_params *params)
1631 struct ieee80211com *ic = ni->ni_ic;
1632 struct ifnet *ifp = ic->ic_ifp;
1633 struct urtw_data *bf;
1634 struct urtw_softc *sc = ifp->if_softc;
1636 /* prevent management frames from being sent if we're not ready */
1637 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1639 ieee80211_free_node(ni);
1643 bf = urtw_getbuf(sc);
1645 ieee80211_free_node(ni);
1648 return (ENOBUFS); /* XXX */
1652 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) {
1653 ieee80211_free_node(ni);
1655 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1666 urtw_scan_start(struct ieee80211com *ic)
1669 /* XXX do nothing? */
1673 urtw_scan_end(struct ieee80211com *ic)
1676 /* XXX do nothing? */
1680 urtw_set_channel(struct ieee80211com *ic)
1682 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1683 struct ifnet *ifp = sc->sc_ifp;
1684 uint32_t data, orig;
1688 * if the user set a channel explicitly using ifconfig(8) this function
1689 * can be called earlier than we're expected that in some cases the
1690 * initialization would be failed if setting a channel is called before
1691 * the init have done.
1693 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1696 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan)
1702 * during changing th channel we need to temporarily be disable
1705 urtw_read32_m(sc, URTW_TX_CONF, &orig);
1706 data = orig & ~URTW_TX_LOOPBACK_MASK;
1707 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
1709 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan));
1712 usb2_pause_mtx(&sc->sc_mtx, 10);
1713 urtw_write32_m(sc, URTW_TX_CONF, orig);
1715 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1716 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1717 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1718 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1723 sc->sc_curchan = ic->ic_curchan;
1726 device_printf(sc->sc_dev, "could not change the channel\n");
1730 urtw_update_mcast(struct ifnet *ifp)
1733 /* XXX do nothing? */
1737 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0,
1738 struct urtw_data *data, int prior)
1741 struct ifnet *ifp = sc->sc_ifp;
1742 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1743 struct ieee80211_key *k;
1744 const struct ieee80211_txparam *tp;
1745 struct ieee80211com *ic = ifp->if_l2com;
1746 struct ieee80211vap *vap = ni->ni_vap;
1747 struct urtw_8187b_txhdr *hdr;
1748 struct usb2_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = {
1749 sc->sc_xfer[URTW_8187B_BULK_TX_BE],
1750 sc->sc_xfer[URTW_8187B_BULK_TX_BK],
1751 sc->sc_xfer[URTW_8187B_BULK_TX_VI],
1752 sc->sc_xfer[URTW_8187B_BULK_TX_VO]
1754 struct usb2_xfer *xfer;
1757 URTW_ASSERT_LOCKED(sc);
1762 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1763 k = ieee80211_crypto_encap(ni, m0);
1765 device_printf(sc->sc_dev,
1766 "ieee80211_crypto_encap returns NULL.\n");
1767 /* XXX we don't expect the fragmented frames */
1772 /* in case packet header moved, reset pointer */
1773 wh = mtod(m0, struct ieee80211_frame *);
1776 if (ieee80211_radiotap_active_vap(vap)) {
1777 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap;
1779 /* XXX Are variables correct? */
1781 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1782 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1784 ieee80211_radiotap_tx(vap, m0);
1787 xferlen = m0->m_pkthdr.len;
1788 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3);
1789 if ((0 == xferlen % 64) || (0 == xferlen % 512))
1792 bzero(data->buf, URTW_TX_MAXSIZE);
1793 data->buf[0] = m0->m_pkthdr.len & 0xff;
1794 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8;
1795 data->buf[1] |= (1 << 7);
1797 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1798 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) &&
1799 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) &&
1800 (sc->sc_currate != 0))
1802 if ((m0->m_pkthdr.len > vap->iv_rtsthreshold) &&
1803 prior == URTW_PRIORITY_LOW) {
1804 device_printf(sc->sc_dev, "TODO tx.\n");
1807 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1808 data->buf[2] |= (1 << 1);
1809 /* RTS rate - 10 means we use a basic rate. */
1810 data->buf[2] |= (urtw_rate2rtl(2) << 3);
1812 * XXX currently TX rate control depends on the rate value of
1813 * RX descriptor because I don't know how to we can control TX rate
1814 * in more smart way. Please fix me you find a thing.
1816 data->buf[3] = sc->sc_currate;
1817 if (prior == URTW_PRIORITY_NORMAL) {
1818 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1819 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1820 data->buf[3] = urtw_rate2rtl(tp->mcastrate);
1821 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1822 data->buf[3] = urtw_rate2rtl(tp->ucastrate);
1825 if (sc->sc_flags & URTW_RTL8187B) {
1826 hdr = (struct urtw_8187b_txhdr *)data->buf;
1827 hdr->rts_duration = 0;
1829 hdr->retry = 3 | (7 << 4) | 11;
1830 hdr->tx_duration = ieee80211_compute_duration(ic->ic_rt,
1831 m0->m_pkthdr.len + IEEE80211_CRC_LEN,
1832 urtw_rtl2rate(data->buf[3]),
1833 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0);
1834 /* XXX MUST fill another variables like rts_duration, tx_.. */
1835 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[32]);
1837 data->buf[8] = 3; /* CW minimum */
1838 data->buf[8] |= (7 << 4); /* CW maximum */
1839 data->buf[9] |= 11; /* retry limitation */
1840 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[12]);
1843 data->buflen = xferlen;
1847 if (sc->sc_flags & URTW_RTL8187B) {
1848 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1849 case IEEE80211_FC0_TYPE_CTL:
1850 case IEEE80211_FC0_TYPE_MGT:
1851 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12];
1854 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX,
1855 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1856 xfer = rtl8187b_pipes[M_WME_GETAC(m0)];
1860 xfer = (prior == URTW_PRIORITY_LOW) ?
1861 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] :
1862 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL];
1864 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1865 usb2_transfer_start(xfer);
1867 error = urtw_led_ctl(sc, URTW_LED_CTL_TX);
1869 device_printf(sc->sc_dev, "could not control LED (%d)\n",
1875 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1877 struct ieee80211_node *ni = vap->iv_bss;
1878 struct ieee80211com *ic = vap->iv_ic;
1879 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1880 struct urtw_vap *uvp = URTW_VAP(vap);
1881 usb2_error_t error = 0;
1883 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1884 ieee80211_state_name[vap->iv_state],
1885 ieee80211_state_name[nstate]);
1887 sc->sc_state = nstate;
1889 IEEE80211_UNLOCK(ic);
1891 usb2_callout_stop(&sc->sc_led_ch);
1892 callout_stop(&sc->sc_watchdog_ch);
1895 case IEEE80211_S_INIT:
1896 case IEEE80211_S_SCAN:
1897 case IEEE80211_S_AUTH:
1898 case IEEE80211_S_ASSOC:
1900 case IEEE80211_S_RUN:
1901 /* setting bssid. */
1902 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]);
1903 urtw_write16_m(sc, URTW_BSSID + 4,
1904 ((uint16_t *)ni->ni_bssid)[2]);
1905 urtw_update_msr(sc);
1906 /* XXX maybe the below would be incorrect. */
1907 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1908 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1909 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
1910 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1911 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
1913 device_printf(sc->sc_dev,
1914 "could not control LED (%d)\n", error);
1922 return (uvp->newstate(vap, nstate, arg));
1926 urtw_watchdog(void *arg)
1928 struct urtw_softc *sc = arg;
1929 struct ifnet *ifp = sc->sc_ifp;
1931 if (sc->sc_txtimer > 0) {
1932 if (--sc->sc_txtimer == 0) {
1933 device_printf(sc->sc_dev, "device timeout\n");
1937 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1942 urtw_set_multi(void *arg)
1944 struct urtw_softc *sc = arg;
1945 struct ifnet *ifp = sc->sc_ifp;
1947 if (!(ifp->if_flags & IFF_UP))
1951 * XXX don't know how to set a device. Lack of docs. Just try to set
1952 * IFF_ALLMULTI flag here.
1955 ifp->if_flags |= IFF_ALLMULTI;
1956 IF_ADDR_UNLOCK(ifp);
1960 urtw_set_rate(struct urtw_softc *sc)
1962 int i, basic_rate, min_rr_rate, max_rr_rate;
1966 basic_rate = urtw_rate2rtl(48);
1967 min_rr_rate = urtw_rate2rtl(12);
1968 max_rr_rate = urtw_rate2rtl(48);
1970 urtw_write8_m(sc, URTW_RESP_RATE,
1971 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
1972 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT);
1974 urtw_read16_m(sc, URTW_BRSR, &data);
1975 data &= ~URTW_BRSR_MBR_8185;
1977 for (i = 0; i <= basic_rate; i++)
1980 urtw_write16_m(sc, URTW_BRSR, data);
1986 urtw_rate2rtl(int rate)
1988 #define N(a) (sizeof(a) / sizeof((a)[0]))
1991 for (i = 0; i < N(urtw_ratetable); i++) {
1992 if (rate == urtw_ratetable[i].reg)
1993 return urtw_ratetable[i].val;
2001 urtw_rtl2rate(int rate)
2003 #define N(a) (sizeof(a) / sizeof((a)[0]))
2006 for (i = 0; i < N(urtw_ratetable); i++) {
2007 if (rate == urtw_ratetable[i].val)
2008 return urtw_ratetable[i].reg;
2016 urtw_update_msr(struct urtw_softc *sc)
2018 struct ifnet *ifp = sc->sc_ifp;
2019 struct ieee80211com *ic = ifp->if_l2com;
2023 urtw_read8_m(sc, URTW_MSR, &data);
2024 data &= ~URTW_MSR_LINK_MASK;
2026 if (sc->sc_state == IEEE80211_S_RUN) {
2027 switch (ic->ic_opmode) {
2028 case IEEE80211_M_STA:
2029 case IEEE80211_M_MONITOR:
2030 data |= URTW_MSR_LINK_STA;
2031 if (sc->sc_flags & URTW_RTL8187B)
2032 data |= URTW_MSR_LINK_ENEDCA;
2034 case IEEE80211_M_IBSS:
2035 data |= URTW_MSR_LINK_ADHOC;
2037 case IEEE80211_M_HOSTAP:
2038 data |= URTW_MSR_LINK_HOSTAP;
2041 panic("unsupported operation mode 0x%x\n",
2046 data |= URTW_MSR_LINK_NONE;
2048 urtw_write8_m(sc, URTW_MSR, data);
2054 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data)
2056 struct usb2_device_request req;
2059 URTW_ASSERT_LOCKED(sc);
2061 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2062 req.bRequest = URTW_8187_GETREGS_REQ;
2063 USETW(req.wValue, val | 0xff00);
2064 USETW(req.wIndex, 0);
2065 USETW(req.wLength, sizeof(uint8_t));
2067 error = urtw_do_request(sc, &req, data);
2072 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data)
2074 struct usb2_device_request req;
2077 URTW_ASSERT_LOCKED(sc);
2079 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2080 req.bRequest = URTW_8187_GETREGS_REQ;
2081 USETW(req.wValue, val | 0xff00);
2082 USETW(req.wIndex, 0);
2083 USETW(req.wLength, sizeof(uint16_t));
2085 error = urtw_do_request(sc, &req, data);
2090 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data)
2092 struct usb2_device_request req;
2095 URTW_ASSERT_LOCKED(sc);
2097 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2098 req.bRequest = URTW_8187_GETREGS_REQ;
2099 USETW(req.wValue, val | 0xff00);
2100 USETW(req.wIndex, 0);
2101 USETW(req.wLength, sizeof(uint32_t));
2103 error = urtw_do_request(sc, &req, data);
2108 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data)
2110 struct usb2_device_request req;
2112 URTW_ASSERT_LOCKED(sc);
2114 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2115 req.bRequest = URTW_8187_SETREGS_REQ;
2116 USETW(req.wValue, val | 0xff00);
2117 USETW(req.wIndex, 0);
2118 USETW(req.wLength, sizeof(uint8_t));
2120 return (urtw_do_request(sc, &req, &data));
2124 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data)
2126 struct usb2_device_request req;
2128 URTW_ASSERT_LOCKED(sc);
2130 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2131 req.bRequest = URTW_8187_SETREGS_REQ;
2132 USETW(req.wValue, val | 0xff00);
2133 USETW(req.wIndex, 0);
2134 USETW(req.wLength, sizeof(uint16_t));
2136 return (urtw_do_request(sc, &req, &data));
2140 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data)
2142 struct usb2_device_request req;
2144 URTW_ASSERT_LOCKED(sc);
2146 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2147 req.bRequest = URTW_8187_SETREGS_REQ;
2148 USETW(req.wValue, val | 0xff00);
2149 USETW(req.wIndex, 0);
2150 USETW(req.wLength, sizeof(uint32_t));
2152 return (urtw_do_request(sc, &req, &data));
2156 urtw_get_macaddr(struct urtw_softc *sc)
2161 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
2164 sc->sc_bssid[0] = data & 0xff;
2165 sc->sc_bssid[1] = (data & 0xff00) >> 8;
2166 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
2169 sc->sc_bssid[2] = data & 0xff;
2170 sc->sc_bssid[3] = (data & 0xff00) >> 8;
2171 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
2174 sc->sc_bssid[4] = data & 0xff;
2175 sc->sc_bssid[5] = (data & 0xff00) >> 8;
2181 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
2183 #define URTW_READCMD_LEN 3
2185 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 };
2188 /* NB: make sure the buffer is initialized */
2191 /* enable EPROM programming */
2192 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE);
2193 DELAY(URTW_EPROM_DELAY);
2195 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
2198 error = urtw_eprom_ck(sc);
2201 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
2204 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
2206 addrstr[0] = addr & (1 << 7);
2207 addrstr[1] = addr & (1 << 6);
2208 addrstr[2] = addr & (1 << 5);
2209 addrstr[3] = addr & (1 << 4);
2210 addrstr[4] = addr & (1 << 3);
2211 addrstr[5] = addr & (1 << 2);
2212 addrstr[6] = addr & (1 << 1);
2213 addrstr[7] = addr & (1 << 0);
2216 addrstr[0] = addr & (1 << 5);
2217 addrstr[1] = addr & (1 << 4);
2218 addrstr[2] = addr & (1 << 3);
2219 addrstr[3] = addr & (1 << 2);
2220 addrstr[4] = addr & (1 << 1);
2221 addrstr[5] = addr & (1 << 0);
2223 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
2227 error = urtw_eprom_writebit(sc, 0);
2231 for (i = 0; i < 16; i++) {
2232 error = urtw_eprom_ck(sc);
2235 error = urtw_eprom_readbit(sc, &data16);
2239 (*data) |= (data16 << (15 - i));
2242 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
2245 error = urtw_eprom_ck(sc);
2249 /* now disable EPROM programming */
2250 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE);
2253 #undef URTW_READCMD_LEN
2257 urtw_eprom_cs(struct urtw_softc *sc, int able)
2262 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2263 if (able == URTW_EPROM_ENABLE)
2264 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
2266 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
2267 DELAY(URTW_EPROM_DELAY);
2273 urtw_eprom_ck(struct urtw_softc *sc)
2279 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2280 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
2281 DELAY(URTW_EPROM_DELAY);
2283 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2284 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
2285 DELAY(URTW_EPROM_DELAY);
2291 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
2296 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
2297 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
2298 DELAY(URTW_EPROM_DELAY);
2305 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
2310 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2312 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
2314 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
2315 DELAY(URTW_EPROM_DELAY);
2321 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
2324 usb2_error_t error = 0;
2326 for (i = 0; i < buflen; i++) {
2327 error = urtw_eprom_writebit(sc, buf[i]);
2330 error = urtw_eprom_ck(sc);
2340 urtw_get_txpwr(struct urtw_softc *sc)
2346 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
2349 sc->sc_txpwr_cck_base = data & 0xf;
2350 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
2352 for (i = 1, j = 0; i < 6; i += 2, j++) {
2353 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
2356 sc->sc_txpwr_cck[i] = data & 0xf;
2357 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
2358 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
2359 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
2361 for (i = 1, j = 0; i < 4; i += 2, j++) {
2362 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
2365 sc->sc_txpwr_cck[i + 6] = data & 0xf;
2366 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
2367 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
2368 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
2370 if (sc->sc_flags & URTW_RTL8187B) {
2371 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data);
2374 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf;
2375 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4;
2376 error = urtw_eprom_read32(sc, 0x0a, &data);
2379 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf;
2380 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4;
2381 error = urtw_eprom_read32(sc, 0x1c, &data);
2384 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf;
2385 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8;
2386 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4;
2387 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12;
2389 for (i = 1, j = 0; i < 4; i += 2, j++) {
2390 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
2394 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
2395 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
2396 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
2397 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12;
2406 urtw_get_rfchip(struct urtw_softc *sc)
2413 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
2416 switch (data & 0xff) {
2417 case URTW_EPROM_RFCHIPID_RTL8225U:
2418 error = urtw_8225_isv2(sc, &ret);
2422 sc->sc_rf_init = urtw_8225_rf_init;
2423 sc->sc_rf_set_sens = urtw_8225_rf_set_sens;
2424 sc->sc_rf_set_chan = urtw_8225_rf_set_chan;
2425 sc->sc_rf_stop = urtw_8225_rf_stop;
2427 sc->sc_rf_init = urtw_8225v2_rf_init;
2428 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan;
2429 sc->sc_rf_stop = urtw_8225_rf_stop;
2431 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2432 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2434 case URTW_EPROM_RFCHIPID_RTL8225Z2:
2435 sc->sc_rf_init = urtw_8225v2b_rf_init;
2436 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan;
2437 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2438 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2439 sc->sc_rf_stop = urtw_8225_rf_stop;
2442 panic("unsupported RF chip %d\n", data & 0xff);
2446 if (sc->sc_flags & URTW_RTL8187B) {
2447 urtw_read8_m(sc, 0xe1, &data8);
2448 sc->sc_flags |= (data8 == 0) ? URTW_RTL8187B_REV_B :
2449 (data8 == 1) ? URTW_RTL8187B_REV_D : URTW_RTL8187B_REV_E;
2452 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n",
2453 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l",
2454 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" :
2456 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" :
2457 (data8 == 1) ? "d" : "e") : "none");
2465 urtw_led_init(struct urtw_softc *sc)
2470 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr);
2471 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
2475 switch (rev & URTW_EPROM_CID_MASK) {
2476 case URTW_EPROM_CID_ALPHA0:
2477 sc->sc_strategy = URTW_SW_LED_MODE1;
2479 case URTW_EPROM_CID_SERCOMM_PS:
2480 sc->sc_strategy = URTW_SW_LED_MODE3;
2482 case URTW_EPROM_CID_HW_LED:
2483 sc->sc_strategy = URTW_HW_LED;
2485 case URTW_EPROM_CID_RSVD0:
2486 case URTW_EPROM_CID_RSVD1:
2488 sc->sc_strategy = URTW_SW_LED_MODE0;
2492 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
2500 urtw_8225_rf_init(struct urtw_softc *sc)
2502 #define N(a) (sizeof(a) / sizeof((a)[0]))
2507 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2511 error = urtw_8225_usb_init(sc);
2515 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2516 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2517 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2518 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2520 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2523 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2524 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2528 error = urtw_8185_rf_pins_enable(sc);
2531 usb2_pause_mtx(&sc->sc_mtx, 1000);
2533 for (i = 0; i < N(urtw_8225_rf_part1); i++) {
2534 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
2535 urtw_8225_rf_part1[i].val);
2536 usb2_pause_mtx(&sc->sc_mtx, 1);
2538 usb2_pause_mtx(&sc->sc_mtx, 100);
2540 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2541 usb2_pause_mtx(&sc->sc_mtx, 200);
2543 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2544 usb2_pause_mtx(&sc->sc_mtx, 200);
2546 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3);
2548 for (i = 0; i < 95; i++) {
2549 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2550 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]);
2554 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4);
2556 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5);
2558 for (i = 0; i < 128; i++) {
2559 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2560 usb2_pause_mtx(&sc->sc_mtx, 1);
2561 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2562 usb2_pause_mtx(&sc->sc_mtx, 1);
2565 for (i = 0; i < N(urtw_8225_rf_part2); i++) {
2566 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
2567 urtw_8225_rf_part2[i].val);
2568 usb2_pause_mtx(&sc->sc_mtx, 1);
2571 error = urtw_8225_setgain(sc, 4);
2575 for (i = 0; i < N(urtw_8225_rf_part3); i++) {
2576 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
2577 urtw_8225_rf_part3[i].val);
2578 usb2_pause_mtx(&sc->sc_mtx, 1);
2581 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2583 error = urtw_8225_set_txpwrlvl(sc, 1);
2587 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2588 usb2_pause_mtx(&sc->sc_mtx, 1);
2589 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2590 usb2_pause_mtx(&sc->sc_mtx, 1);
2592 /* TX ant A, 0x0 for B */
2593 error = urtw_8185_tx_antenna(sc, 0x3);
2596 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2598 error = urtw_8225_rf_set_chan(sc, 1);
2605 urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2607 usb2_error_t error = 0;
2609 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7);
2615 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2619 urtw_write8_m(sc, URTW_TX_ANTENNA, ant);
2620 usb2_pause_mtx(&sc->sc_mtx, 1);
2626 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2630 return urtw_8187_write_phy(sc, addr, data);
2634 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2638 return urtw_8187_write_phy(sc, addr, data | 0x10000);
2642 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2647 phyw = ((data << 8) | (addr | 0x80));
2648 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24));
2649 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16));
2650 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8));
2651 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff)));
2652 usb2_pause_mtx(&sc->sc_mtx, 1);
2658 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2662 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]);
2663 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]);
2664 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]);
2665 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]);
2671 urtw_8225_usb_init(struct urtw_softc *sc)
2676 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0);
2677 urtw_write8_m(sc, URTW_GPIO, 0);
2678 error = urtw_read8e(sc, 0x53, &data);
2681 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2684 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4);
2685 urtw_write8_m(sc, URTW_GPIO, 0x20);
2686 urtw_write8_m(sc, URTW_GP_ENABLE, 0);
2688 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80);
2689 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80);
2690 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80);
2692 usb2_pause_mtx(&sc->sc_mtx, 500);
2698 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
2700 uint16_t d80, d82, d84;
2703 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80);
2704 d80 &= URTW_RF_PINS_MAGIC1;
2705 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82);
2706 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84);
2707 d84 &= URTW_RF_PINS_MAGIC2;
2708 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3);
2709 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3);
2712 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2714 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80);
2717 error = urtw_8225_write_s16(sc, addr, 0x8225, &data);
2721 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2723 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2724 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84);
2725 usb2_pause_mtx(&sc->sc_mtx, 2);
2730 /* XXX why we should allocalte memory buffer instead of using memory stack? */
2732 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index,
2737 struct usb2_device_request *req;
2738 usb2_error_t error = 0;
2741 req = (usb_device_request_t *)malloc(sizeof(usb_device_request_t),
2742 M_80211_VAP, M_NOWAIT | M_ZERO);
2744 device_printf(sc->sc_dev, "could not allocate a memory\n");
2747 buf = (uint8_t *)malloc(2, M_80211_VAP, M_NOWAIT | M_ZERO);
2749 device_printf(sc->sc_dev, "could not allocate a memory\n");
2753 req->bmRequestType = UT_WRITE_VENDOR_DEVICE;
2754 req->bRequest = URTW_8187_SETREGS_REQ;
2755 USETW(req->wValue, addr);
2756 USETW(req->wIndex, index);
2757 USETW(req->wLength, sizeof(uint16_t));
2758 buf[0] = (data16 & 0x00ff);
2759 buf[1] = (data16 & 0xff00) >> 8;
2761 error = urtw_do_request(sc, req, buf);
2763 free(buf, M_80211_VAP);
2764 fail1: free(req, M_80211_VAP);
2765 fail0: return (error);
2769 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan)
2771 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2772 struct ieee80211_channel *c = ic->ic_curchan;
2775 error = urtw_8225_set_txpwrlvl(sc, chan);
2778 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2779 usb2_pause_mtx(&sc->sc_mtx, 10);
2781 urtw_write8_m(sc, URTW_SIFS, 0x22);
2783 if (sc->sc_state == IEEE80211_S_ASSOC &&
2784 ic->ic_flags & IEEE80211_F_SHSLOT)
2785 urtw_write8_m(sc, URTW_SLOT, 0x9);
2787 urtw_write8_m(sc, URTW_SLOT, 0x14);
2789 if (IEEE80211_IS_CHAN_G(c)) {
2791 urtw_write8_m(sc, URTW_DIFS, 0x14);
2792 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
2793 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
2796 urtw_write8_m(sc, URTW_DIFS, 0x24);
2797 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24);
2798 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
2806 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens)
2810 if (sens < 0 || sens > 6)
2815 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1);
2818 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2);
2821 error = urtw_8225_setgain(sc, sens);
2825 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]);
2832 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2835 uint8_t *cck_pwltable;
2836 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max;
2837 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2838 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2841 cck_pwrlvl_max = 11;
2842 ofdm_pwrlvl_max = 25; /* 12 -> 25 */
2843 ofdm_pwrlvl_min = 10;
2845 /* CCK power setting */
2846 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
2847 idx = cck_pwrlvl % 6;
2848 set = cck_pwrlvl / 6;
2849 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 :
2850 urtw_8225_txpwr_cck;
2852 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
2853 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2854 for (i = 0; i < 8; i++) {
2855 urtw_8187_write_phy_cck(sc, 0x44 + i,
2856 cck_pwltable[idx * 8 + i]);
2858 usb2_pause_mtx(&sc->sc_mtx, 1);
2860 /* OFDM power setting */
2861 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2862 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2863 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2865 idx = ofdm_pwrlvl % 6;
2866 set = ofdm_pwrlvl / 6;
2868 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
2871 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
2872 urtw_8187_write_phy_ofdm(sc, 6, 0);
2873 urtw_8187_write_phy_ofdm(sc, 8, 0);
2875 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
2876 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2877 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]);
2878 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]);
2879 usb2_pause_mtx(&sc->sc_mtx, 1);
2886 urtw_8225_rf_stop(struct urtw_softc *sc)
2891 urtw_8225_write(sc, 0x4, 0x1f);
2893 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2897 urtw_read8_m(sc, URTW_CONFIG3, &data);
2898 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
2899 if (sc->sc_flags & URTW_RTL8187B) {
2900 urtw_write32_m(sc, URTW_ANAPARAM2,
2901 URTW_8187B_8225_ANAPARAM2_OFF);
2902 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF);
2903 urtw_write32_m(sc, URTW_ANAPARAM3,
2904 URTW_8187B_8225_ANAPARAM3_OFF);
2906 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF);
2907 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF);
2910 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
2911 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2920 urtw_8225v2_rf_init(struct urtw_softc *sc)
2922 #define N(a) (sizeof(a) / sizeof((a)[0]))
2928 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2932 error = urtw_8225_usb_init(sc);
2936 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2937 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2938 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2939 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2941 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2944 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2945 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2949 error = urtw_8185_rf_pins_enable(sc);
2953 usb2_pause_mtx(&sc->sc_mtx, 500);
2955 for (i = 0; i < N(urtw_8225v2_rf_part1); i++) {
2956 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
2957 urtw_8225v2_rf_part1[i].val);
2959 usb2_pause_mtx(&sc->sc_mtx, 50);
2962 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
2964 for (i = 0; i < 95; i++) {
2965 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2966 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
2967 urtw_8225v2_rxgain[i]);
2971 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1);
2973 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1);
2975 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2);
2977 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2978 usb2_pause_mtx(&sc->sc_mtx, 100);
2980 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2981 usb2_pause_mtx(&sc->sc_mtx, 100);
2983 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2986 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1)
2987 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32);
2988 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) {
2990 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2991 usb2_pause_mtx(&sc->sc_mtx, 100);
2993 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2994 usb2_pause_mtx(&sc->sc_mtx, 50);
2995 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2998 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2))
2999 device_printf(sc->sc_dev, "RF calibration failed\n");
3001 usb2_pause_mtx(&sc->sc_mtx, 100);
3004 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6);
3005 for (i = 0; i < 128; i++) {
3006 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
3007 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
3010 for (i = 0; i < N(urtw_8225v2_rf_part2); i++) {
3011 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
3012 urtw_8225v2_rf_part2[i].val);
3015 error = urtw_8225v2_setgain(sc, 4);
3019 for (i = 0; i < N(urtw_8225v2_rf_part3); i++) {
3020 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
3021 urtw_8225v2_rf_part3[i].val);
3024 urtw_write8_m(sc, URTW_TESTR, 0x0d);
3026 error = urtw_8225v2_set_txpwrlvl(sc, 1);
3030 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
3031 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
3033 /* TX ant A, 0x0 for B */
3034 error = urtw_8185_tx_antenna(sc, 0x3);
3037 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
3039 error = urtw_8225_rf_set_chan(sc, 1);
3046 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan)
3048 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3049 struct ieee80211_channel *c = ic->ic_curchan;
3052 error = urtw_8225v2_set_txpwrlvl(sc, chan);
3056 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3057 usb2_pause_mtx(&sc->sc_mtx, 10);
3059 urtw_write8_m(sc, URTW_SIFS, 0x22);
3061 if(sc->sc_state == IEEE80211_S_ASSOC &&
3062 ic->ic_flags & IEEE80211_F_SHSLOT)
3063 urtw_write8_m(sc, URTW_SLOT, 0x9);
3065 urtw_write8_m(sc, URTW_SLOT, 0x14);
3067 if (IEEE80211_IS_CHAN_G(c)) {
3069 urtw_write8_m(sc, URTW_DIFS, 0x14);
3070 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
3071 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
3074 urtw_write8_m(sc, URTW_DIFS, 0x24);
3075 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24);
3076 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
3084 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
3088 uint8_t rlen = 12, wlen = 6;
3089 uint16_t o1, o2, o3, tmp;
3090 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;
3091 uint32_t mask = 0x80000000, value = 0;
3094 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1);
3095 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2);
3096 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3);
3097 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4);
3098 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4);
3099 o1 &= ~URTW_RF_PINS_MAGIC4;
3100 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN);
3102 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1);
3105 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {
3106 bit = ((d2w & mask) != 0) ? 1 : 0;
3108 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3110 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3111 URTW_BB_HOST_BANG_CLK);
3113 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3114 URTW_BB_HOST_BANG_CLK);
3119 bit = ((d2w & mask) != 0) ? 1 : 0;
3120 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3121 URTW_BB_HOST_BANG_CLK);
3123 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3124 URTW_BB_HOST_BANG_CLK);
3126 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3129 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW |
3130 URTW_BB_HOST_BANG_CLK);
3132 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW);
3134 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW);
3138 for (i = 0; i < rlen; i++, mask = mask >> 1) {
3139 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3140 o1 | URTW_BB_HOST_BANG_RW);
3142 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3143 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3145 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3146 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3148 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3149 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3152 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
3153 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
3154 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3155 o1 | URTW_BB_HOST_BANG_RW);
3159 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN |
3160 URTW_BB_HOST_BANG_RW);
3163 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2);
3164 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3);
3165 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1);
3175 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
3178 uint8_t *cck_pwrtable;
3179 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10;
3180 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3181 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3184 /* CCK power setting */
3185 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
3186 cck_pwrlvl += sc->sc_txpwr_cck_base;
3187 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3188 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
3189 urtw_8225v2_txpwr_cck;
3191 for (i = 0; i < 8; i++)
3192 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3194 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3195 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]);
3196 usb2_pause_mtx(&sc->sc_mtx, 1);
3198 /* OFDM power setting */
3199 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
3200 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
3201 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3202 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3204 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3208 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
3209 urtw_8187_write_phy_ofdm(sc, 5, 0x0);
3210 urtw_8187_write_phy_ofdm(sc, 6, 0x40);
3211 urtw_8187_write_phy_ofdm(sc, 7, 0x0);
3212 urtw_8187_write_phy_ofdm(sc, 8, 0x40);
3214 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3215 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]);
3216 usb2_pause_mtx(&sc->sc_mtx, 1);
3222 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
3228 gainp = urtw_8225v2_gain_bg;
3229 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]);
3230 usb2_pause_mtx(&sc->sc_mtx, 1);
3231 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]);
3232 usb2_pause_mtx(&sc->sc_mtx, 1);
3233 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]);
3234 usb2_pause_mtx(&sc->sc_mtx, 1);
3235 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17);
3236 usb2_pause_mtx(&sc->sc_mtx, 1);
3242 urtw_8225_isv2(struct urtw_softc *sc, int *ret)
3249 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5);
3250 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5);
3251 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5);
3252 usb2_pause_mtx(&sc->sc_mtx, 500);
3254 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3255 URTW_8225_ADDR_0_DATA_MAGIC1);
3257 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data);
3260 if (data != URTW_8225_ADDR_8_DATA_MAGIC1)
3263 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data);
3266 if (data != URTW_8225_ADDR_9_DATA_MAGIC1)
3270 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3271 URTW_8225_ADDR_0_DATA_MAGIC2);
3277 urtw_8225v2b_rf_init(struct urtw_softc *sc)
3279 #define N(a) (sizeof(a) / sizeof((a)[0]))
3283 for (i = 0; i < N(urtw_8225v2b_rf_part1); i++)
3284 urtw_8225_write(sc, urtw_8225v2b_rf_part1[i].reg,
3285 urtw_8225v2b_rf_part1[i].val);
3288 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
3290 for (i = 0; i < N(urtw_8225v2b_rxgain); i++) {
3291 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
3292 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
3293 urtw_8225v2b_rxgain[i]);
3296 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080);
3297 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004);
3298 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7);
3299 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d);
3300 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d);
3301 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf);
3303 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03);
3304 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07);
3305 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03);
3307 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12);
3308 for (i = 0; i < N(urtw_8225z2_agc); i++) {
3309 urtw_8187_write_phy_ofdm(sc, 0xf, urtw_8225z2_agc[i]);
3310 urtw_8187_write_phy_ofdm(sc, 0xe, 0x80 + i);
3311 urtw_8187_write_phy_ofdm(sc, 0xe, 0);
3313 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10);
3315 for (i = 0; i < N(urtw_8225v2b_rf_part2); i++)
3316 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val);
3318 urtw_write32_m(sc, 0xf0, (7 << 12) | (3 << 8) | 0x1c);
3319 urtw_write32_m(sc, 0xf4, (7 << 12) | (3 << 8) | 0x1c);
3320 urtw_write32_m(sc, 0xf8, (7 << 12) | (3 << 8) | 0x1c);
3321 urtw_write32_m(sc, 0xfc, (7 << 12) | (3 << 8) | 0x1c);
3322 urtw_write8_m(sc, URTW_ACM_CONTROL, 0);
3324 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46);
3325 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6);
3326 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc);
3327 urtw_8187_write_phy_cck(sc, 0xc1, 0x88);
3334 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan)
3337 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3340 error = urtw_8225v2b_set_txpwrlvl(sc, chan);
3344 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3345 usb2_pause_mtx(&sc->sc_mtx, 10);
3347 urtw_write8_m(sc, URTW_SIFS, 0xa);
3348 if (ic->ic_flags & IEEE80211_F_SHSLOT) {
3349 urtw_write8_m(sc, URTW_SLOT, 0x9);
3350 urtw_write8_m(sc, URTW_DIFS, 0x1c);
3351 /* In 8187B, BRSR + 1 ==> EIFS register */
3352 urtw_write8_m(sc, URTW_BRSR + 1, 0x53);
3354 ack = 112 + 48 + 0x1c;
3355 ack += (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ?
3357 urtw_write8_m(sc, URTW_CARRIER_SCOUNT,
3360 urtw_write8_m(sc, URTW_SLOT, 0x14);
3361 urtw_write8_m(sc, URTW_DIFS, 0x32);
3362 /* In 8187B, BRSR + 1 ==> EIFS register */
3363 urtw_write8_m(sc, URTW_BRSR + 1, 0x5b);
3365 ack = 112 + 48 + 0x32;
3366 ack += (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ?
3368 urtw_write8_m(sc, URTW_CARRIER_SCOUNT,
3378 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3381 uint8_t *cck_pwrtable;
3382 uint8_t cck_pwrlvl_max = 15;
3383 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3384 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3387 /* CCK power setting */
3388 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
3389 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) :
3390 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7));
3391 cck_pwrlvl += sc->sc_txpwr_cck_base;
3392 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3393 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 :
3394 urtw_8225v2b_txpwr_cck;
3396 if (sc->sc_flags & URTW_RTL8187B_REV_B)
3397 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 :
3398 ((cck_pwrlvl <= 11) ? 8 : 16);
3400 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 :
3401 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24));
3403 for (i = 0; i < 8; i++)
3404 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3406 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3407 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1);
3408 usb2_pause_mtx(&sc->sc_mtx, 1);
3410 /* OFDM power setting */
3411 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ?
3412 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) :
3413 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10));
3414 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3415 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3417 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3418 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1);
3420 if (sc->sc_flags & URTW_RTL8187B_REV_B) {
3421 if (ofdm_pwrlvl <= 11) {
3422 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60);
3423 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60);
3425 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3426 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3429 if (ofdm_pwrlvl <= 11) {
3430 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3431 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3432 } else if (ofdm_pwrlvl <= 17) {
3433 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54);
3434 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54);
3436 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50);
3437 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50);
3440 usb2_pause_mtx(&sc->sc_mtx, 1);
3446 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
3448 struct usb2_device_request req;
3451 req.bmRequestType = UT_READ_VENDOR_DEVICE;
3452 req.bRequest = URTW_8187_GETREGS_REQ;
3453 USETW(req.wValue, val | 0xfe00);
3454 USETW(req.wIndex, 0);
3455 USETW(req.wLength, sizeof(uint8_t));
3457 error = urtw_do_request(sc, &req, data);
3462 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
3464 struct usb2_device_request req;
3466 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
3467 req.bRequest = URTW_8187_SETREGS_REQ;
3468 USETW(req.wValue, val | 0xfe00);
3469 USETW(req.wIndex, 0);
3470 USETW(req.wLength, sizeof(uint8_t));
3472 return (urtw_do_request(sc, &req, &data));
3476 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
3481 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3485 urtw_read8_m(sc, URTW_CONFIG3, &data);
3486 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3487 urtw_write32_m(sc, URTW_ANAPARAM, val);
3488 urtw_read8_m(sc, URTW_CONFIG3, &data);
3489 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3491 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3499 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
3504 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3508 urtw_read8_m(sc, URTW_CONFIG3, &data);
3509 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3510 urtw_write32_m(sc, URTW_ANAPARAM2, val);
3511 urtw_read8_m(sc, URTW_CONFIG3, &data);
3512 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3514 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3522 urtw_intr_enable(struct urtw_softc *sc)
3526 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff);
3532 urtw_intr_disable(struct urtw_softc *sc)
3536 urtw_write16_m(sc, URTW_INTR_MASK, 0);
3542 urtw_reset(struct urtw_softc *sc)
3547 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3550 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3554 error = urtw_intr_disable(sc);
3557 usb2_pause_mtx(&sc->sc_mtx, 100);
3559 error = urtw_write8e(sc, 0x18, 0x10);
3562 error = urtw_write8e(sc, 0x18, 0x11);
3565 error = urtw_write8e(sc, 0x18, 0x00);
3568 usb2_pause_mtx(&sc->sc_mtx, 100);
3570 urtw_read8_m(sc, URTW_CMD, &data);
3571 data = (data & 0x2) | URTW_CMD_RST;
3572 urtw_write8_m(sc, URTW_CMD, data);
3573 usb2_pause_mtx(&sc->sc_mtx, 100);
3575 urtw_read8_m(sc, URTW_CMD, &data);
3576 if (data & URTW_CMD_RST) {
3577 device_printf(sc->sc_dev, "reset timeout\n");
3581 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
3584 usb2_pause_mtx(&sc->sc_mtx, 100);
3586 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3589 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3597 urtw_led_ctl(struct urtw_softc *sc, int mode)
3599 usb2_error_t error = 0;
3601 switch (sc->sc_strategy) {
3602 case URTW_SW_LED_MODE0:
3603 error = urtw_led_mode0(sc, mode);
3605 case URTW_SW_LED_MODE1:
3606 error = urtw_led_mode1(sc, mode);
3608 case URTW_SW_LED_MODE2:
3609 error = urtw_led_mode2(sc, mode);
3611 case URTW_SW_LED_MODE3:
3612 error = urtw_led_mode3(sc, mode);
3615 panic("unsupported LED mode %d\n", sc->sc_strategy);
3623 urtw_led_mode0(struct urtw_softc *sc, int mode)
3627 case URTW_LED_CTL_POWER_ON:
3628 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
3630 case URTW_LED_CTL_TX:
3631 if (sc->sc_gpio_ledinprogress == 1)
3634 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
3635 sc->sc_gpio_blinktime = 2;
3637 case URTW_LED_CTL_LINK:
3638 sc->sc_gpio_ledstate = URTW_LED_ON;
3641 panic("unsupported LED mode 0x%x", mode);
3645 switch (sc->sc_gpio_ledstate) {
3647 if (sc->sc_gpio_ledinprogress != 0)
3649 urtw_led_on(sc, URTW_LED_GPIO);
3651 case URTW_LED_BLINK_NORMAL:
3652 if (sc->sc_gpio_ledinprogress != 0)
3654 sc->sc_gpio_ledinprogress = 1;
3655 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
3656 URTW_LED_OFF : URTW_LED_ON;
3657 usb2_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3659 case URTW_LED_POWER_ON_BLINK:
3660 urtw_led_on(sc, URTW_LED_GPIO);
3661 usb2_pause_mtx(&sc->sc_mtx, 100);
3662 urtw_led_off(sc, URTW_LED_GPIO);
3665 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate);
3672 urtw_led_mode1(struct urtw_softc *sc, int mode)
3675 return (USB_ERR_INVAL);
3679 urtw_led_mode2(struct urtw_softc *sc, int mode)
3682 return (USB_ERR_INVAL);
3686 urtw_led_mode3(struct urtw_softc *sc, int mode)
3689 return (USB_ERR_INVAL);
3693 urtw_led_on(struct urtw_softc *sc, int type)
3697 if (type == URTW_LED_GPIO) {
3698 switch (sc->sc_gpio_ledpin) {
3699 case URTW_LED_PIN_GPIO0:
3700 urtw_write8_m(sc, URTW_GPIO, 0x01);
3701 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00);
3704 panic("unsupported LED PIN type 0x%x",
3705 sc->sc_gpio_ledpin);
3709 panic("unsupported LED type 0x%x", type);
3713 sc->sc_gpio_ledon = 1;
3719 urtw_led_off(struct urtw_softc *sc, int type)
3723 if (type == URTW_LED_GPIO) {
3724 switch (sc->sc_gpio_ledpin) {
3725 case URTW_LED_PIN_GPIO0:
3726 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1);
3728 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1);
3731 panic("unsupported LED PIN type 0x%x",
3732 sc->sc_gpio_ledpin);
3736 panic("unsupported LED type 0x%x", type);
3740 sc->sc_gpio_ledon = 0;
3747 urtw_led_ch(void *arg)
3749 struct urtw_softc *sc = arg;
3750 struct ifnet *ifp = sc->sc_ifp;
3751 struct ieee80211com *ic = ifp->if_l2com;
3753 ieee80211_runtask(ic, &sc->sc_led_task);
3757 urtw_ledtask(void *arg, int pending)
3759 struct urtw_softc *sc = arg;
3761 if (sc->sc_strategy != URTW_SW_LED_MODE0)
3762 panic("could not process a LED strategy 0x%x", sc->sc_strategy);
3770 urtw_led_blink(struct urtw_softc *sc)
3775 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
3776 error = urtw_led_on(sc, URTW_LED_GPIO);
3778 error = urtw_led_off(sc, URTW_LED_GPIO);
3779 sc->sc_gpio_blinktime--;
3780 if (sc->sc_gpio_blinktime == 0)
3783 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
3784 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
3785 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
3789 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
3790 sc->sc_gpio_ledon == 0)
3791 error = urtw_led_on(sc, URTW_LED_GPIO);
3792 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
3793 sc->sc_gpio_ledon == 1)
3794 error = urtw_led_off(sc, URTW_LED_GPIO);
3796 sc->sc_gpio_blinktime = 0;
3797 sc->sc_gpio_ledinprogress = 0;
3801 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
3802 URTW_LED_ON : URTW_LED_OFF;
3804 switch (sc->sc_gpio_ledstate) {
3805 case URTW_LED_BLINK_NORMAL:
3806 usb2_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3809 panic("unknown LED status 0x%x", sc->sc_gpio_ledstate);
3816 urtw_rx_enable(struct urtw_softc *sc)
3821 usb2_transfer_start((sc->sc_flags & URTW_RTL8187B) ?
3822 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]);
3824 error = urtw_rx_setconf(sc);
3828 urtw_read8_m(sc, URTW_CMD, &data);
3829 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
3835 urtw_tx_enable(struct urtw_softc *sc)
3841 if (sc->sc_flags & URTW_RTL8187B) {
3842 urtw_read32_m(sc, URTW_TX_CONF, &data);
3843 data &= ~URTW_TX_LOOPBACK_MASK;
3844 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3845 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3846 data &= ~URTW_TX_SWPLCPLEN;
3847 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE |
3848 (7 << 8) | /* short retry limit */
3849 (7 << 0) | /* long retry limit */
3850 (7 << 21); /* MAX TX DMA */
3851 urtw_write32_m(sc, URTW_TX_CONF, data);
3853 urtw_read8_m(sc, URTW_CMD, &data8);
3854 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3858 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3859 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY);
3860 urtw_write8_m(sc, URTW_CW_CONF, data8);
3862 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3863 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN;
3864 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
3865 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT;
3866 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3868 urtw_read32_m(sc, URTW_TX_CONF, &data);
3869 data &= ~URTW_TX_LOOPBACK_MASK;
3870 data |= URTW_TX_LOOPBACK_NONE;
3871 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3872 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
3873 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
3874 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3875 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
3876 data &= ~URTW_TX_SWPLCPLEN;
3877 data |= URTW_TX_NOICV;
3878 urtw_write32_m(sc, URTW_TX_CONF, data);
3880 urtw_read8_m(sc, URTW_CMD, &data8);
3881 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3887 urtw_rx_setconf(struct urtw_softc *sc)
3889 struct ifnet *ifp = sc->sc_ifp;
3890 struct ieee80211com *ic = ifp->if_l2com;
3894 urtw_read32_m(sc, URTW_RX, &data);
3895 data = data &~ URTW_RX_FILTER_MASK;
3896 if (sc->sc_flags & URTW_RTL8187B) {
3897 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA |
3898 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST |
3899 URTW_RX_FILTER_NICMAC | URTW_RX_CHECK_BSSID |
3900 URTW_RX_FIFO_THRESHOLD_NONE |
3901 URTW_MAX_RX_DMA_2048 |
3902 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT;
3904 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
3905 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
3907 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
3908 data = data | URTW_RX_FILTER_ICVERR;
3909 data = data | URTW_RX_FILTER_PWR;
3911 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
3912 data = data | URTW_RX_FILTER_CRCERR;
3914 if (ic->ic_opmode == IEEE80211_M_MONITOR ||
3915 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) {
3916 data = data | URTW_RX_FILTER_ALLMAC;
3918 data = data | URTW_RX_FILTER_NICMAC;
3919 data = data | URTW_RX_CHECK_BSSID;
3922 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
3923 data = data | URTW_RX_FIFO_THRESHOLD_NONE |
3924 URTW_RX_AUTORESETPHY;
3925 data = data &~ URTW_MAX_RX_DMA_MASK;
3926 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT;
3929 urtw_write32_m(sc, URTW_RX, data);
3934 static struct mbuf *
3935 urtw_rxeof(struct usb2_xfer *xfer, struct urtw_data *data, int *rssi_p,
3938 int actlen, flen, len, nf = -95, rssi;
3939 struct ieee80211_frame *wh;
3940 struct mbuf *m, *mnew;
3941 struct urtw_8187b_rxhdr *bhdr;
3942 struct urtw_softc *sc = data->sc;
3943 struct ifnet *ifp = sc->sc_ifp;
3944 struct ieee80211com *ic = ifp->if_l2com;
3945 uint8_t *desc, quality = 0, rate;
3947 actlen = xfer->actlen;
3948 if (actlen < URTW_MIN_RXBUFSZ) {
3953 if (sc->sc_flags & URTW_RTL8187B) {
3954 len = actlen - (sizeof(struct urtw_8187b_rxhdr));
3955 bhdr = (struct urtw_8187b_rxhdr *)(data->buf + len);
3956 desc = data->buf + len;
3957 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff);
3958 if (flen > actlen) {
3962 rate = (le32toh(bhdr->flags) >> 20) & 0xf;
3963 rssi = 14 + (bhdr->rssi / 2);
3967 /* 4 dword and 4 byte CRC */
3968 len = actlen - (4 * 4);
3969 desc = data->buf + len;
3970 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff);
3971 if (flen > actlen) {
3976 rate = (desc[2] & 0xf0) >> 4;
3977 quality = desc[4] & 0xff;
3979 rssi = (desc[6] & 0xfe) >> 1;
3980 if (!urtw_isbmode(rate)) {
3981 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi);
3982 rssi = ((90 - rssi) * 100) / 65;
3984 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi);
3985 rssi = ((95 - rssi) * 100) / 65;
3989 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3997 data->buf = mtod(mnew, uint8_t *);
4000 m->m_pkthdr.rcvif = ifp;
4001 m->m_pkthdr.len = m->m_len = flen - 4;
4003 if (ieee80211_radiotap_active(ic)) {
4004 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap;
4006 /* XXX Are variables correct? */
4007 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
4008 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
4009 tap->wr_dbm_antsignal = (int8_t)rssi;
4012 wh = mtod(m, struct ieee80211_frame *);
4013 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA)
4014 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
4016 if ((sc->sc_flags & URTW_RTL8187B) == 0)
4017 nf = (quality > 64) ? 0 : ((64 - quality) * 100) / 64;
4026 urtw_bulk_rx_callback(struct usb2_xfer *xfer)
4028 struct urtw_softc *sc = xfer->priv_sc;
4029 struct ifnet *ifp = sc->sc_ifp;
4030 struct ieee80211com *ic = ifp->if_l2com;
4031 struct ieee80211_frame *wh;
4032 struct ieee80211_node *ni;
4033 struct mbuf *m = NULL;
4034 struct urtw_data *data;
4038 URTW_ASSERT_LOCKED(sc);
4040 switch (USB_GET_STATE(xfer)) {
4041 case USB_ST_TRANSFERRED:
4042 data = STAILQ_FIRST(&sc->sc_rx_active);
4045 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4046 m = urtw_rxeof(xfer, data, &rssi, &nf);
4047 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4051 data = STAILQ_FIRST(&sc->sc_rx_inactive);
4053 KASSERT(m == NULL, ("mbuf isn't NULL"));
4056 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
4057 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
4058 usb2_set_frame_data(xfer, data->buf, 0);
4059 xfer->frlengths[0] = xfer->max_data_length;
4060 usb2_start_hardware(xfer);
4063 * To avoid LOR we should unlock our private mutex here to call
4064 * ieee80211_input() because here is at the end of a USB
4065 * callback and safe to unlock.
4069 wh = mtod(m, struct ieee80211_frame *);
4070 ni = ieee80211_find_rxnode(ic,
4071 (struct ieee80211_frame_min *)wh);
4073 (void) ieee80211_input(ni, m, rssi, nf);
4074 /* node is no longer needed */
4075 ieee80211_free_node(ni);
4077 (void) ieee80211_input_all(ic, m, rssi, nf);
4083 /* needs it to the inactive queue due to a error. */
4084 data = STAILQ_FIRST(&sc->sc_rx_active);
4086 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4087 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4089 if (xfer->error != USB_ERR_CANCELLED) {
4090 xfer->flags.stall_pipe = 1;
4099 urtw_txeof(struct usb2_xfer *xfer, struct urtw_data *data)
4101 struct urtw_softc *sc = xfer->priv_sc;
4102 struct ifnet *ifp = sc->sc_ifp;
4105 URTW_ASSERT_LOCKED(sc);
4108 * Do any tx complete callback. Note this must be done before releasing
4109 * the node reference.
4113 if (m->m_flags & M_TXCB) {
4115 ieee80211_process_callback(data->ni, m, 0);
4121 ieee80211_free_node(data->ni);
4126 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4130 urtw_bulk_tx_callback(struct usb2_xfer *xfer)
4132 struct urtw_softc *sc = xfer->priv_sc;
4133 struct ifnet *ifp = sc->sc_ifp;
4134 struct urtw_data *data;
4136 URTW_ASSERT_LOCKED(sc);
4138 switch (USB_GET_STATE(xfer)) {
4139 case USB_ST_TRANSFERRED:
4140 data = STAILQ_FIRST(&sc->sc_tx_active);
4143 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
4144 urtw_txeof(xfer, data);
4145 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
4149 data = STAILQ_FIRST(&sc->sc_tx_pending);
4151 DPRINTF(sc, URTW_DEBUG_XMIT,
4152 "%s: empty pending queue\n", __func__);
4155 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
4156 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
4158 usb2_set_frame_data(xfer, data->buf, 0);
4159 xfer->frlengths[0] = data->buflen;
4160 usb2_start_hardware(xfer);
4167 data = STAILQ_FIRST(&sc->sc_tx_active);
4170 if (data->ni != NULL) {
4171 ieee80211_free_node(data->ni);
4175 if (xfer->error != USB_ERR_CANCELLED) {
4176 xfer->flags.stall_pipe = 1;
4183 static struct urtw_data *
4184 _urtw_getbuf(struct urtw_softc *sc)
4186 struct urtw_data *bf;
4188 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
4190 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
4194 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__,
4195 "out of xmit buffers");
4199 static struct urtw_data *
4200 urtw_getbuf(struct urtw_softc *sc)
4202 struct urtw_data *bf;
4204 URTW_ASSERT_LOCKED(sc);
4206 bf = _urtw_getbuf(sc);
4208 struct ifnet *ifp = sc->sc_ifp;
4210 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__);
4211 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4217 urtw_isbmode(uint16_t rate)
4220 rate = urtw_rtl2rate(rate);
4222 return ((rate <= 22 && rate != 12 && rate != 18) ||
4223 rate == 44) ? (1) : (0);
4226 static device_method_t urtw_methods[] = {
4227 DEVMETHOD(device_probe, urtw_match),
4228 DEVMETHOD(device_attach, urtw_attach),
4229 DEVMETHOD(device_detach, urtw_detach),
4232 static driver_t urtw_driver = {
4235 sizeof(struct urtw_softc)
4237 static devclass_t urtw_devclass;
4239 DRIVER_MODULE(urtw, uhub, urtw_driver, urtw_devclass, NULL, 0);
4240 MODULE_DEPEND(urtw, wlan, 1, 1, 1);
4241 MODULE_DEPEND(urtw, usb, 1, 1, 1);