2 * Copyright (c) 2013 Tsubai Masanari
3 * Copyright (c) 2013 Bryan Venteicher <bryanv@FreeBSD.org>
4 * Copyright (c) 2018 Patrick Kelsey
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
27 * The number of Rx/Tx queues this driver prefers.
29 #define VMXNET3_DEF_RX_QUEUES 8
30 #define VMXNET3_DEF_TX_QUEUES 8
33 * The number of Rx rings in each Rx queue.
35 #define VMXNET3_RXRINGS_PERQ 2
38 * The number of descriptors in each Rx/Tx ring.
40 #define VMXNET3_DEF_TX_NDESC 512
41 #define VMXNET3_MAX_TX_NDESC 4096
42 #define VMXNET3_MIN_TX_NDESC 32
43 #define VMXNET3_MASK_TX_NDESC 0x1F
44 #define VMXNET3_DEF_RX_NDESC 512
45 #define VMXNET3_MAX_RX_NDESC 2048
46 #define VMXNET3_MIN_RX_NDESC 32
47 #define VMXNET3_MASK_RX_NDESC 0x1F
49 #define VMXNET3_MAX_TX_NCOMPDESC VMXNET3_MAX_TX_NDESC
50 #define VMXNET3_MAX_RX_NCOMPDESC \
51 (VMXNET3_MAX_RX_NDESC * VMXNET3_RXRINGS_PERQ)
53 struct vmxnet3_txring {
57 struct vmxnet3_txdesc *vxtxr_txd;
58 bus_addr_t vxtxr_paddr;
61 struct vmxnet3_rxring {
62 struct vmxnet3_rxdesc *vxrxr_rxd;
65 bus_addr_t vxrxr_paddr;
66 uint64_t vxrxr_desc_skips;
67 uint16_t vxrxr_refill_start;
70 struct vmxnet3_comp_ring {
72 struct vmxnet3_txcompdesc *txcd;
73 struct vmxnet3_rxcompdesc *rxcd;
76 * vxcr_next is used on the transmit side to track the next index to
77 * begin cleaning at. It is not used on the receive side.
82 bus_addr_t vxcr_paddr;
83 uint64_t vxcr_zero_length;
84 uint64_t vxcr_pkt_errors;
87 struct vmxnet3_txqueue {
88 struct vmxnet3_softc *vxtxq_sc;
92 struct vmxnet3_txring vxtxq_cmd_ring;
93 struct vmxnet3_comp_ring vxtxq_comp_ring;
94 struct vmxnet3_txq_shared *vxtxq_ts;
95 struct sysctl_oid_list *vxtxq_sysctl;
97 } __aligned(CACHE_LINE_SIZE);
99 struct vmxnet3_rxqueue {
100 struct vmxnet3_softc *vxrxq_sc;
103 struct if_irq vxrxq_irq;
104 struct vmxnet3_rxring vxrxq_cmd_ring[VMXNET3_RXRINGS_PERQ];
105 struct vmxnet3_comp_ring vxrxq_comp_ring;
106 struct vmxnet3_rxq_shared *vxrxq_rs;
107 struct sysctl_oid_list *vxrxq_sysctl;
109 } __aligned(CACHE_LINE_SIZE);
111 struct vmxnet3_softc {
114 if_shared_ctx_t vmx_sctx;
115 if_softc_ctx_t vmx_scctx;
116 struct ifnet *vmx_ifp;
117 struct vmxnet3_driver_shared *vmx_ds;
119 #define VMXNET3_FLAG_RSS 0x0002
120 #define VMXNET3_FLAG_SOFT_RSS 0x0004 /* Software RSS is enabled with
121 compatible algorithm. */
123 struct vmxnet3_rxqueue *vmx_rxq;
124 struct vmxnet3_txqueue *vmx_txq;
126 struct resource *vmx_res0;
127 bus_space_tag_t vmx_iot0;
128 bus_space_handle_t vmx_ioh0;
129 struct resource *vmx_res1;
130 bus_space_tag_t vmx_iot1;
131 bus_space_handle_t vmx_ioh1;
135 int vmx_intr_mask_mode;
136 int vmx_event_intr_idx;
137 struct if_irq vmx_event_intr_irq;
140 struct vmxnet3_rss_shared *vmx_rss;
141 struct iflib_dma_info vmx_ds_dma;
142 struct iflib_dma_info vmx_qs_dma;
143 struct iflib_dma_info vmx_mcast_dma;
144 struct iflib_dma_info vmx_rss_dma;
145 struct ifmedia *vmx_media;
146 uint32_t vmx_vlan_filter[4096/32];
147 uint8_t vmx_lladdr[ETHER_ADDR_LEN];
151 * Our driver version we report to the hypervisor; we just keep
152 * this value constant.
154 #define VMXNET3_DRIVER_VERSION 0x00010000
157 * Max descriptors per Tx packet. We must limit the size of the
158 * any TSO packets based on the number of segments.
160 #define VMXNET3_TX_MAXSEGS 32 /* 64K @ 2K segment size */
161 #define VMXNET3_TX_MAXSIZE (VMXNET3_TX_MAXSEGS * MCLBYTES)
162 #define VMXNET3_TSO_MAXSIZE (VMXNET3_TX_MAXSIZE - ETHER_VLAN_ENCAP_LEN)
165 * Maximum supported Tx segment size. The length field in the
166 * Tx descriptor is 14 bits.
168 * XXX It's possible a descriptor length field of 0 means 2^14, but this
169 * isn't confirmed, so limit to 2^14 - 1 for now.
171 #define VMXNET3_TX_MAXSEGSIZE ((1 << 14) - 1)
174 * Maximum supported Rx segment size. The length field in the
175 * Rx descriptor is 14 bits.
177 * The reference drivers skip zero-length descriptors, which seems to be a
178 * strong indication that on the receive side, a descriptor length field of
179 * zero does not mean 2^14.
181 #define VMXNET3_RX_MAXSEGSIZE ((1 << 14) - 1)
184 * Predetermined size of the multicast MACs filter table. If the
185 * number of multicast addresses exceeds this size, then the
186 * ALL_MULTI mode is use instead.
188 #define VMXNET3_MULTICAST_MAX 32
191 * IP protocols that we can perform Tx checksum offloading of.
193 #define VMXNET3_CSUM_OFFLOAD (CSUM_TCP | CSUM_UDP)
194 #define VMXNET3_CSUM_OFFLOAD_IPV6 (CSUM_TCP_IPV6 | CSUM_UDP_IPV6)
196 #define VMXNET3_CSUM_ALL_OFFLOAD \
197 (VMXNET3_CSUM_OFFLOAD | VMXNET3_CSUM_OFFLOAD_IPV6 | CSUM_TSO)
199 #endif /* _IF_VMXVAR_H */