2 * Copyright (C) 2015 Cavium Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Marvell/Cavium ThunderX vnic/bgx network controller
33 * UNIMPLEMENTED FEATURES
34 * ----------------------
35 * A number of features supported by the hardware are not yet implemented in
38 * - PR223573 multicast rx filter
39 * - PR223575 non-promiscuous mode (driver currently forces promisc)
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/bitset.h>
48 #include <sys/bitstring.h>
50 #include <sys/endian.h>
51 #include <sys/kernel.h>
52 #include <sys/malloc.h>
53 #include <sys/module.h>
55 #include <sys/pciio.h>
58 #include <sys/socket.h>
59 #include <sys/sockio.h>
60 #include <sys/cpuset.h>
62 #include <sys/mutex.h>
64 #include <net/ethernet.h>
66 #include <net/if_media.h>
68 #include <machine/bus.h>
69 #include <machine/_inttypes.h>
71 #include <dev/pci/pcireg.h>
72 #include <dev/pci/pcivar.h>
77 #include <sys/iov_schema.h>
78 #include <dev/pci/pci_iov.h>
81 #include "thunder_bgx.h"
86 #define VNIC_PF_DEVSTR "Cavium Thunder NIC Physical Function Driver"
88 #define VNIC_PF_REG_RID PCIR_BAR(PCI_CFG_REG_BAR_NUM)
90 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) ((((bgx) & 0xF) << 4) | ((lmac) & 0xF))
91 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) (((map) >> 4) & 0xF)
92 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) ((map) & 0xF)
94 /* Structure to be used by the SR-IOV for VF configuration schemas */
104 uint8_t num_vf_en; /* No of VF enabled */
105 struct nicvf_info vf_info[MAX_NUM_VFS_SUPPORTED];
106 struct resource * reg_base; /* Register start address */
107 struct pkind_cfg pkind;
108 uint8_t vf_lmac_map[MAX_LMAC];
109 boolean_t mbx_lock[MAX_NUM_VFS_SUPPORTED];
111 struct callout check_link;
112 struct mtx check_link_mtx;
114 uint8_t link[MAX_LMAC];
115 uint8_t duplex[MAX_LMAC];
116 uint32_t speed[MAX_LMAC];
117 uint16_t cpi_base[MAX_NUM_VFS_SUPPORTED];
118 uint16_t rssi_base[MAX_NUM_VFS_SUPPORTED];
119 uint16_t rss_ind_tbl_size;
122 boolean_t msix_enabled;
124 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS];
125 struct resource * msix_table_res;
128 static int nicpf_probe(device_t);
129 static int nicpf_attach(device_t);
130 static int nicpf_detach(device_t);
133 static int nicpf_iov_init(device_t, uint16_t, const nvlist_t *);
134 static void nicpf_iov_uninit(device_t);
135 static int nicpf_iov_add_vf(device_t, uint16_t, const nvlist_t *);
138 static device_method_t nicpf_methods[] = {
139 /* Device interface */
140 DEVMETHOD(device_probe, nicpf_probe),
141 DEVMETHOD(device_attach, nicpf_attach),
142 DEVMETHOD(device_detach, nicpf_detach),
143 /* PCI SR-IOV interface */
145 DEVMETHOD(pci_iov_init, nicpf_iov_init),
146 DEVMETHOD(pci_iov_uninit, nicpf_iov_uninit),
147 DEVMETHOD(pci_iov_add_vf, nicpf_iov_add_vf),
152 static driver_t vnicpf_driver = {
155 sizeof(struct nicpf),
158 DRIVER_MODULE(vnicpf, pci, vnicpf_driver, 0, 0);
159 MODULE_VERSION(vnicpf, 1);
160 MODULE_DEPEND(vnicpf, pci, 1, 1, 1);
161 MODULE_DEPEND(vnicpf, ether, 1, 1, 1);
162 MODULE_DEPEND(vnicpf, thunder_bgx, 1, 1, 1);
164 static int nicpf_alloc_res(struct nicpf *);
165 static void nicpf_free_res(struct nicpf *);
166 static void nic_set_lmac_vf_mapping(struct nicpf *);
167 static void nic_init_hw(struct nicpf *);
168 static int nic_sriov_init(device_t, struct nicpf *);
169 static void nic_poll_for_link(void *);
170 static int nic_register_interrupts(struct nicpf *);
171 static void nic_unregister_interrupts(struct nicpf *);
177 nicpf_probe(device_t dev)
182 vendor_id = pci_get_vendor(dev);
183 device_id = pci_get_device(dev);
185 if (vendor_id == PCI_VENDOR_ID_CAVIUM &&
186 device_id == PCI_DEVICE_ID_THUNDER_NIC_PF) {
187 device_set_desc(dev, VNIC_PF_DEVSTR);
188 return (BUS_PROBE_DEFAULT);
195 nicpf_attach(device_t dev)
200 nic = device_get_softc(dev);
203 /* Enable bus mastering */
204 pci_enable_busmaster(dev);
206 /* Allocate PCI resources */
207 err = nicpf_alloc_res(nic);
209 device_printf(dev, "Could not allocate PCI resources\n");
213 nic->node = nic_get_node_id(nic->reg_base);
215 /* Enable Traffic Network Switch (TNS) bypass mode by default */
216 nic->flags &= ~NIC_TNS_ENABLED;
217 nic_set_lmac_vf_mapping(nic);
219 /* Initialize hardware */
222 /* Set RSS TBL size for each VF */
223 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
225 /* Setup interrupts */
226 err = nic_register_interrupts(nic);
230 /* Configure SRIOV */
231 err = nic_sriov_init(dev, nic);
235 if (nic->flags & NIC_TNS_ENABLED)
238 mtx_init(&nic->check_link_mtx, "VNIC PF link poll", NULL, MTX_DEF);
239 /* Register physical link status poll callout */
240 callout_init_mtx(&nic->check_link, &nic->check_link_mtx, 0);
241 mtx_lock(&nic->check_link_mtx);
242 nic_poll_for_link(nic);
243 mtx_unlock(&nic->check_link_mtx);
248 nic_unregister_interrupts(nic);
251 pci_disable_busmaster(dev);
257 nicpf_detach(device_t dev)
263 nic = device_get_softc(dev);
265 callout_drain(&nic->check_link);
266 mtx_destroy(&nic->check_link_mtx);
268 nic_unregister_interrupts(nic);
270 pci_disable_busmaster(dev);
273 err = pci_iov_detach(dev);
275 device_printf(dev, "SR-IOV in use. Detach first.\n");
285 nicpf_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params)
289 nic = device_get_softc(dev);
294 nic->flags |= NIC_SRIOV_ENABLED;
300 nicpf_iov_uninit(device_t dev)
303 /* ARM64TODO: Implement this function */
307 nicpf_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params)
314 nic = device_get_softc(dev);
316 if ((nic->flags & NIC_SRIOV_ENABLED) == 0)
319 if (vfnum > (nic->num_vf_en - 1))
322 if (nvlist_exists_binary(params, "mac-addr") != 0) {
323 mac = nvlist_get_binary(params, "mac-addr", &size);
324 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]);
325 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]);
326 bgx_set_lmac_mac(nic->node, bgx, lmac, mac);
337 nicpf_alloc_res(struct nicpf *nic)
344 rid = VNIC_PF_REG_RID;
345 nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
347 if (nic->reg_base == NULL) {
348 /* For verbose output print some more details */
351 "Could not allocate registers memory\n");
360 nicpf_free_res(struct nicpf *nic)
366 if (nic->reg_base != NULL) {
367 bus_release_resource(dev, SYS_RES_MEMORY,
368 rman_get_rid(nic->reg_base), nic->reg_base);
372 /* Register read/write APIs */
374 nic_reg_write(struct nicpf *nic, bus_space_handle_t offset,
378 bus_write_8(nic->reg_base, offset, val);
381 static __inline uint64_t
382 nic_reg_read(struct nicpf *nic, uint64_t offset)
386 val = bus_read_8(nic->reg_base, offset);
390 /* PF -> VF mailbox communication APIs */
392 nic_enable_mbx_intr(struct nicpf *nic)
395 /* Enable mailbox interrupt for all 128 VFs */
396 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0UL);
397 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(uint64_t), ~0UL);
401 nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg)
404 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), (1UL << vf));
408 nic_get_mbx_addr(int vf)
411 return (NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT));
415 * Send a mailbox message to VF
416 * @vf: vf to which this message to be sent
417 * @mbx: Message to be sent
420 nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx)
422 bus_space_handle_t mbx_addr = nic_get_mbx_addr(vf);
423 uint64_t *msg = (uint64_t *)mbx;
426 * In first revision HW, mbox interrupt is triggerred
427 * when PF writes to MBOX(1), in next revisions when
428 * PF writes to MBOX(0)
430 if (pass1_silicon(nic->dev)) {
431 nic_reg_write(nic, mbx_addr + 0, msg[0]);
432 nic_reg_write(nic, mbx_addr + 8, msg[1]);
434 nic_reg_write(nic, mbx_addr + 8, msg[1]);
435 nic_reg_write(nic, mbx_addr + 0, msg[0]);
440 * Responds to VF's READY message with VF's
441 * ID, node, MAC address e.t.c
442 * @vf: VF which sent READY message
445 nic_mbx_send_ready(struct nicpf *nic, int vf)
447 union nic_mbx mbx = {};
451 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY;
452 mbx.nic_cfg.vf_id = vf;
454 if (nic->flags & NIC_TNS_ENABLED)
455 mbx.nic_cfg.tns_mode = NIC_TNS_MODE;
457 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE;
460 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
461 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
463 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac);
465 memcpy((uint8_t *)&mbx.nic_cfg.mac_addr, mac,
469 mbx.nic_cfg.node_id = nic->node;
471 mbx.nic_cfg.loopback_supported = vf < MAX_LMAC;
473 nic_send_msg_to_vf(nic, vf, &mbx);
477 * ACKs VF's mailbox message
478 * @vf: VF to which ACK to be sent
481 nic_mbx_send_ack(struct nicpf *nic, int vf)
483 union nic_mbx mbx = {};
485 mbx.msg.msg = NIC_MBOX_MSG_ACK;
486 nic_send_msg_to_vf(nic, vf, &mbx);
490 * NACKs VF's mailbox message that PF is not able to
491 * complete the action
492 * @vf: VF to which ACK to be sent
495 nic_mbx_send_nack(struct nicpf *nic, int vf)
497 union nic_mbx mbx = {};
499 mbx.msg.msg = NIC_MBOX_MSG_NACK;
500 nic_send_msg_to_vf(nic, vf, &mbx);
504 * Flush all in flight receive packets to memory and
505 * bring down an active RQ
508 nic_rcv_queue_sw_sync(struct nicpf *nic)
510 uint16_t timeout = ~0x00;
512 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01);
513 /* Wait till sync cycle is finished */
515 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1)
519 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00);
521 device_printf(nic->dev, "Receive queue software sync failed\n");
527 /* Get BGX Rx/Tx stats and respond to VF's request */
529 nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx)
532 union nic_mbx mbx = {};
534 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
535 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
537 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
538 mbx.bgx_stats.vf_id = bgx->vf_id;
539 mbx.bgx_stats.rx = bgx->rx;
540 mbx.bgx_stats.idx = bgx->idx;
542 mbx.bgx_stats.stats =
543 bgx_get_rx_stats(nic->node, bgx_idx, lmac, bgx->idx);
545 mbx.bgx_stats.stats =
546 bgx_get_tx_stats(nic->node, bgx_idx, lmac, bgx->idx);
548 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx);
551 /* Update hardware min/max frame size */
553 nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)
556 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) {
557 device_printf(nic->dev,
558 "Invalid MTU setting from VF%d rejected, "
559 "should be between %d and %d\n",
560 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS);
563 new_frs += ETHER_HDR_LEN;
564 if (new_frs <= nic->pkind.maxlen)
567 nic->pkind.maxlen = new_frs;
568 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(uint64_t *)&nic->pkind);
572 /* Set minimum transmit packet size */
574 nic_set_tx_pkt_pad(struct nicpf *nic, int size)
579 /* Max value that can be set is 60 */
583 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) {
584 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3));
585 lmac_cfg &= ~(0xF << 2);
586 lmac_cfg |= ((size / 4) << 2);
587 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg);
592 * Function to check number of LMACs present and set VF::LMAC mapping.
593 * Mapping will be used while initializing channels.
596 nic_set_lmac_vf_mapping(struct nicpf *nic)
598 unsigned bgx_map = bgx_get_map(nic->node);
599 int bgx, next_bgx_lmac = 0;
600 int lmac, lmac_cnt = 0;
601 uint64_t lmac_credit;
604 if (nic->flags & NIC_TNS_ENABLED) {
605 nic->num_vf_en = DEFAULT_NUM_VF_ENABLED;
609 for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) {
610 if ((bgx_map & (1 << bgx)) == 0)
612 lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
613 for (lmac = 0; lmac < lmac_cnt; lmac++)
614 nic->vf_lmac_map[next_bgx_lmac++] =
615 NIC_SET_VF_LMAC_MAP(bgx, lmac);
616 nic->num_vf_en += lmac_cnt;
618 /* Program LMAC credits */
619 lmac_credit = (1UL << 1); /* channel credit enable */
620 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */
621 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */
622 lmac_credit |= (((((48 * 1024) / lmac_cnt) -
623 NIC_HW_MAX_FRS) / 16) << 12);
624 lmac = bgx * MAX_LMAC_PER_BGX;
625 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++) {
626 nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8),
632 #define TNS_PORT0_BLOCK 6
633 #define TNS_PORT1_BLOCK 7
638 nic_init_hw(struct nicpf *nic)
642 /* Enable NIC HW block */
643 nic_reg_write(nic, NIC_PF_CFG, 0x3);
645 /* Enable backpressure */
646 nic_reg_write(nic, NIC_PF_BP_CFG, (1UL << 6) | 0x03);
648 if (nic->flags & NIC_TNS_ENABLED) {
649 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
650 (NIC_TNS_MODE << 7) | TNS_PORT0_BLOCK);
651 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
652 (NIC_TNS_MODE << 7) | TNS_PORT1_BLOCK);
653 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
654 (1UL << 63) | TNS_PORT0_BLOCK);
655 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
656 (1UL << 63) | TNS_PORT1_BLOCK);
659 /* Disable TNS mode on both interfaces */
660 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
661 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK);
662 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
663 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK);
664 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
665 (1UL << 63) | BGX0_BLOCK);
666 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
667 (1UL << 63) | BGX1_BLOCK);
670 /* PKIND configuration */
671 nic->pkind.minlen = 0;
672 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETHER_HDR_LEN;
673 nic->pkind.lenerr_en = 1;
674 nic->pkind.rx_hdr = 0;
675 nic->pkind.hdr_sl = 0;
677 for (i = 0; i < NIC_MAX_PKIND; i++) {
678 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3),
679 *(uint64_t *)&nic->pkind);
682 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS);
685 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK);
687 /* Enable VLAN ethertype matching and stripping */
688 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7,
689 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETHERTYPE_VLAN);
692 /* Channel parse index configuration */
694 nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
696 uint32_t vnic, bgx, lmac, chan;
697 uint32_t padd, cpi_count = 0;
698 uint64_t cpi_base, cpi, rssi_base, rssi;
699 uint8_t qset, rq_idx = 0;
702 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
703 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
705 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
706 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX);
707 rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX);
709 /* Rx channel configuration */
710 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3),
711 (1UL << 63) | (vnic << 0));
712 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3),
713 ((uint64_t)cfg->cpi_alg << 62) | (cpi_base << 48));
715 if (cfg->cpi_alg == CPI_ALG_NONE)
717 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */
719 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */
721 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */
722 cpi_count = NIC_MAX_CPI_PER_LMAC;
724 /* RSS Qset, Qidx mapping */
727 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) {
728 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
729 (qset << 3) | rq_idx);
735 for (; cpi < (cpi_base + cpi_count); cpi++) {
736 /* Determine port to channel adder */
737 if (cfg->cpi_alg != CPI_ALG_DIFF)
738 padd = cpi % cpi_count;
740 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */
742 /* Leave RSS_SIZE as '0' to disable RSS */
743 if (pass1_silicon(nic->dev)) {
744 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
745 (vnic << 24) | (padd << 16) | (rssi_base + rssi));
747 /* Set MPI_ALG to '0' to disable MCAM parsing */
748 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
750 /* MPI index is same as CPI if MPI_ALG is not enabled */
751 nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3),
752 (vnic << 24) | (rssi_base + rssi));
755 if ((rssi + 1) >= cfg->rq_cnt)
758 if (cfg->cpi_alg == CPI_ALG_VLAN)
760 else if (cfg->cpi_alg == CPI_ALG_VLAN16)
761 rssi = ((cpi - cpi_base) & 0xe) >> 1;
762 else if (cfg->cpi_alg == CPI_ALG_DIFF)
763 rssi = ((cpi - cpi_base) & 0x38) >> 3;
765 nic->cpi_base[cfg->vf_id] = cpi_base;
766 nic->rssi_base[cfg->vf_id] = rssi_base;
769 /* Responsds to VF with its RSS indirection table size */
771 nic_send_rss_size(struct nicpf *nic, int vf)
773 union nic_mbx mbx = {};
775 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
776 mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size;
777 nic_send_msg_to_vf(nic, vf, &mbx);
781 * Receive side scaling configuration
784 * - indir table i.e hash::RQ mapping
785 * - no of hash bits to consider
788 nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
791 uint64_t cpi_cfg, cpi_base, rssi_base, rssi;
795 rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset;
800 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) {
801 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
802 (qset << 3) | (cfg->ind_tbl[idx] & 0x7));
806 cpi_base = nic->cpi_base[cfg->vf_id];
807 if (pass1_silicon(nic->dev))
808 idx_addr = NIC_PF_CPI_0_2047_CFG;
810 idx_addr = NIC_PF_MPI_0_2047_CFG;
811 cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3));
812 cpi_cfg &= ~(0xFUL << 20);
813 cpi_cfg |= (cfg->hash_bits << 20);
814 nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg);
818 * 4 level transmit side scheduler configutation
819 * for TNS bypass mode
821 * Sample configuration for SQ0
822 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0
823 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0
824 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0
825 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0
826 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
827 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
828 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
829 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
832 nic_tx_channel_cfg(struct nicpf *nic, uint8_t vnic, struct sq_cfg_msg *sq)
834 uint32_t bgx, lmac, chan;
835 uint32_t tl2, tl3, tl4;
837 uint8_t sq_idx = sq->sq_num;
842 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
843 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
845 /* 24 bytes for FCS, IPG and preamble */
846 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4);
848 tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX);
851 tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3);
852 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 |
853 ((uint64_t)vnic << NIC_QS_ID_SHIFT) |
854 ((uint32_t)sq_idx << NIC_Q_NUM_SHIFT), tl4);
855 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3),
856 ((uint64_t)vnic << 27) | ((uint32_t)sq_idx << 24) | rr_quantum);
858 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum);
859 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
860 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
861 /* Enable backpressure on the channel */
862 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
865 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2);
866 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum);
867 /* No priorities as of now */
868 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00);
872 nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk)
874 int bgx_idx, lmac_idx;
876 if (lbk->vf_id > MAX_LMAC)
879 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
880 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
882 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable);
887 /* Interrupt handler to handle mailbox messages from VFs */
889 nic_handle_mbx_intr(struct nicpf *nic, int vf)
891 union nic_mbx mbx = {};
900 nic->mbx_lock[vf] = TRUE;
902 mbx_addr = nic_get_mbx_addr(vf);
903 mbx_data = (uint64_t *)&mbx;
905 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
906 *mbx_data = nic_reg_read(nic, mbx_addr);
908 mbx_addr += sizeof(uint64_t);
911 switch (mbx.msg.msg) {
912 case NIC_MBOX_MSG_READY:
913 nic_mbx_send_ready(nic, vf);
921 case NIC_MBOX_MSG_QS_CFG:
922 reg_addr = NIC_PF_QSET_0_127_CFG |
923 (mbx.qs.num << NIC_QS_ID_SHIFT);
925 nic_reg_write(nic, reg_addr, cfg);
927 case NIC_MBOX_MSG_RQ_CFG:
928 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG |
929 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
930 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
931 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
933 case NIC_MBOX_MSG_RQ_BP_CFG:
934 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG |
935 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
936 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
937 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
939 case NIC_MBOX_MSG_RQ_SW_SYNC:
940 ret = nic_rcv_queue_sw_sync(nic);
942 case NIC_MBOX_MSG_RQ_DROP_CFG:
943 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG |
944 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
945 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
946 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
948 case NIC_MBOX_MSG_SQ_CFG:
949 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG |
950 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) |
951 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT);
952 nic_reg_write(nic, reg_addr, mbx.sq.cfg);
953 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq);
955 case NIC_MBOX_MSG_SET_MAC:
956 lmac = mbx.mac.vf_id;
957 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
958 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
959 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr);
961 case NIC_MBOX_MSG_SET_MAX_FRS:
962 ret = nic_update_hw_frs(nic, mbx.frs.max_frs, mbx.frs.vf_id);
964 case NIC_MBOX_MSG_CPI_CFG:
965 nic_config_cpi(nic, &mbx.cpi_cfg);
967 case NIC_MBOX_MSG_RSS_SIZE:
968 nic_send_rss_size(nic, vf);
970 case NIC_MBOX_MSG_RSS_CFG:
971 case NIC_MBOX_MSG_RSS_CFG_CONT: /* fall through */
972 nic_config_rss(nic, &mbx.rss_cfg);
974 case NIC_MBOX_MSG_CFG_DONE:
975 /* Last message of VF config msg sequence */
976 nic->vf_info[vf].vf_enabled = TRUE;
978 case NIC_MBOX_MSG_SHUTDOWN:
979 /* First msg in VF teardown sequence */
980 nic->vf_info[vf].vf_enabled = FALSE;
982 case NIC_MBOX_MSG_BGX_STATS:
983 nic_get_bgx_stats(nic, &mbx.bgx_stats);
985 case NIC_MBOX_MSG_LOOPBACK:
986 ret = nic_config_loopback(nic, &mbx.lbk);
989 device_printf(nic->dev,
990 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg);
995 nic_mbx_send_ack(nic, vf);
996 else if (mbx.msg.msg != NIC_MBOX_MSG_READY)
997 nic_mbx_send_nack(nic, vf);
999 nic->mbx_lock[vf] = FALSE;
1003 nic_mbx_intr_handler(struct nicpf *nic, int mbx)
1006 uint8_t vf, vf_per_mbx_reg = 64;
1008 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3));
1009 for (vf = 0; vf < vf_per_mbx_reg; vf++) {
1010 if (intr & (1UL << vf)) {
1011 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg));
1012 nic_clear_mbx_intr(nic, vf, mbx);
1018 nic_mbx0_intr_handler (void *arg)
1020 struct nicpf *nic = (struct nicpf *)arg;
1022 nic_mbx_intr_handler(nic, 0);
1026 nic_mbx1_intr_handler (void *arg)
1028 struct nicpf *nic = (struct nicpf *)arg;
1030 nic_mbx_intr_handler(nic, 1);
1034 nic_enable_msix(struct nicpf *nic)
1036 struct pci_devinfo *dinfo;
1040 dinfo = device_get_ivars(nic->dev);
1041 rid = dinfo->cfg.msix.msix_table_bar;
1042 nic->msix_table_res =
1043 bus_alloc_resource_any(nic->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1044 if (nic->msix_table_res == NULL) {
1045 device_printf(nic->dev,
1046 "Could not allocate memory for MSI-X table\n");
1050 count = nic->num_vec = NIC_PF_MSIX_VECTORS;
1052 ret = pci_alloc_msix(nic->dev, &count);
1053 if ((ret != 0) || (count != nic->num_vec)) {
1054 device_printf(nic->dev,
1055 "Request for #%d msix vectors failed, error: %d\n",
1060 nic->msix_enabled = 1;
1065 nic_disable_msix(struct nicpf *nic)
1067 if (nic->msix_enabled) {
1068 pci_release_msi(nic->dev);
1069 nic->msix_enabled = 0;
1073 bus_release_resource(nic->dev, SYS_RES_MEMORY,
1074 rman_get_rid(nic->msix_table_res), nic->msix_table_res);
1078 nic_free_all_interrupts(struct nicpf *nic)
1082 for (irq = 0; irq < nic->num_vec; irq++) {
1083 if (nic->msix_entries[irq].irq_res == NULL)
1085 if (nic->msix_entries[irq].handle != NULL) {
1086 bus_teardown_intr(nic->dev,
1087 nic->msix_entries[irq].irq_res,
1088 nic->msix_entries[irq].handle);
1091 bus_release_resource(nic->dev, SYS_RES_IRQ, irq + 1,
1092 nic->msix_entries[irq].irq_res);
1097 nic_register_interrupts(struct nicpf *nic)
1103 ret = nic_enable_msix(nic);
1107 /* Register mailbox interrupt handlers */
1108 irq = NIC_PF_INTR_ID_MBOX0;
1110 nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev,
1111 SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE));
1112 if (nic->msix_entries[irq].irq_res == NULL) {
1116 ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res,
1117 (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx0_intr_handler, nic,
1118 &nic->msix_entries[irq].handle);
1122 irq = NIC_PF_INTR_ID_MBOX1;
1124 nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev,
1125 SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE));
1126 if (nic->msix_entries[irq].irq_res == NULL) {
1130 ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res,
1131 (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx1_intr_handler, nic,
1132 &nic->msix_entries[irq].handle);
1136 /* Enable mailbox interrupt */
1137 nic_enable_mbx_intr(nic);
1141 nic_free_all_interrupts(nic);
1146 nic_unregister_interrupts(struct nicpf *nic)
1149 nic_free_all_interrupts(nic);
1150 nic_disable_msix(nic);
1153 static int nic_sriov_init(device_t dev, struct nicpf *nic)
1156 nvlist_t *pf_schema, *vf_schema;
1159 uint16_t total_vf_cnt;
1161 err = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos);
1164 "SR-IOV capability is not found in PCIe config space\n");
1167 /* Fix-up the number of enabled VFs */
1168 total_vf_cnt = pci_read_config(dev, iov_pos + PCIR_SRIOV_TOTAL_VFS, 2);
1169 if (total_vf_cnt == 0)
1173 pf_schema = pci_iov_schema_alloc_node();
1174 vf_schema = pci_iov_schema_alloc_node();
1175 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL);
1177 * All VFs can change their MACs.
1178 * This flag will be ignored but we set it just for the record.
1180 pci_iov_schema_add_bool(vf_schema, "allow-set-mac",
1181 IOV_SCHEMA_HASDEFAULT, TRUE);
1183 err = pci_iov_attach(dev, pf_schema, vf_schema);
1186 "Failed to initialize SR-IOV (error=%d)\n",
1195 * Poll for BGX LMAC link status and update corresponding VF
1196 * if there is a change, valid only if internal L2 switch
1197 * is not present otherwise VF link is always treated as up
1200 nic_poll_for_link(void *arg)
1202 union nic_mbx mbx = {};
1204 struct bgx_link_status link;
1205 uint8_t vf, bgx, lmac;
1207 nic = (struct nicpf *)arg;
1209 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE;
1211 for (vf = 0; vf < nic->num_vf_en; vf++) {
1212 /* Poll only if VF is UP */
1213 if (!nic->vf_info[vf].vf_enabled)
1216 /* Get BGX, LMAC indices for the VF */
1217 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1218 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1219 /* Get interface link status */
1220 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link);
1222 /* Inform VF only if link status changed */
1223 if (nic->link[vf] == link.link_up)
1226 if (!nic->mbx_lock[vf]) {
1227 nic->link[vf] = link.link_up;
1228 nic->duplex[vf] = link.duplex;
1229 nic->speed[vf] = link.speed;
1231 /* Send a mbox message to VF with current link status */
1232 mbx.link_status.link_up = link.link_up;
1233 mbx.link_status.duplex = link.duplex;
1234 mbx.link_status.speed = link.speed;
1235 nic_send_msg_to_vf(nic, vf, &mbx);
1238 callout_reset(&nic->check_link, hz * 2, nic_poll_for_link, nic);