sys/dev/vnic/q_struct.h

   1 /*
   2  * Copyright (C) 2015 Cavium Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  *
  28  */
  29
  30 #ifndef Q_STRUCT_H
  31 #define Q_STRUCT_H
  32
  33 #define __LITTLE_ENDIAN_BITFIELD
  34
  35 /* Load transaction types for reading segment bytes specified by
  36  * NIC_SEND_GATHER_S[LD_TYPE].
  37  */
  38 enum nic_send_ld_type_e {
  39         NIC_SEND_LD_TYPE_E_LDD = 0x0,
  40         NIC_SEND_LD_TYPE_E_LDT = 0x1,
  41         NIC_SEND_LD_TYPE_E_LDWB = 0x2,
  42         NIC_SEND_LD_TYPE_E_ENUM_LAST = 0x3,
  43 };
  44
  45 enum ether_type_algorithm {
  46         ETYPE_ALG_NONE = 0x0,
  47         ETYPE_ALG_SKIP = 0x1,
  48         ETYPE_ALG_ENDPARSE = 0x2,
  49         ETYPE_ALG_VLAN = 0x3,
  50         ETYPE_ALG_VLAN_STRIP = 0x4,
  51 };
  52
  53 enum layer3_type {
  54         L3TYPE_NONE = 0x00,
  55         L3TYPE_GRH = 0x01,
  56         L3TYPE_IPV4 = 0x04,
  57         L3TYPE_IPV4_OPTIONS = 0x05,
  58         L3TYPE_IPV6 = 0x06,
  59         L3TYPE_IPV6_OPTIONS = 0x07,
  60         L3TYPE_ET_STOP = 0x0D,
  61         L3TYPE_OTHER = 0x0E,
  62 };
  63
  64 enum layer4_type {
  65         L4TYPE_NONE = 0x00,
  66         L4TYPE_IPSEC_ESP = 0x01,
  67         L4TYPE_IPFRAG = 0x02,
  68         L4TYPE_IPCOMP = 0x03,
  69         L4TYPE_TCP = 0x04,
  70         L4TYPE_UDP = 0x05,
  71         L4TYPE_SCTP = 0x06,
  72         L4TYPE_GRE = 0x07,
  73         L4TYPE_ROCE_BTH = 0x08,
  74         L4TYPE_OTHER = 0x0E,
  75 };
  76
  77 /* CPI and RSSI configuration */
  78 enum cpi_algorithm_type {
  79         CPI_ALG_NONE = 0x0,
  80         CPI_ALG_VLAN = 0x1,
  81         CPI_ALG_VLAN16 = 0x2,
  82         CPI_ALG_DIFF = 0x3,
  83 };
  84
  85 enum rss_algorithm_type {
  86         RSS_ALG_NONE = 0x00,
  87         RSS_ALG_PORT = 0x01,
  88         RSS_ALG_IP = 0x02,
  89         RSS_ALG_TCP_IP = 0x03,
  90         RSS_ALG_UDP_IP = 0x04,
  91         RSS_ALG_SCTP_IP = 0x05,
  92         RSS_ALG_GRE_IP = 0x06,
  93         RSS_ALG_ROCE = 0x07,
  94 };
  95
  96 enum rss_hash_cfg {
  97         RSS_HASH_L2ETC = 0x00,
  98         RSS_HASH_IP = 0x01,
  99         RSS_HASH_TCP = 0x02,
 100         RSS_HASH_TCP_SYN_DIS = 0x03,
 101         RSS_HASH_UDP = 0x04,
 102         RSS_HASH_L4ETC = 0x05,
 103         RSS_HASH_ROCE = 0x06,
 104         RSS_L3_BIDI = 0x07,
 105         RSS_L4_BIDI = 0x08,
 106 };
 107
 108 /* Completion queue entry types */
 109 enum cqe_type {
 110         CQE_TYPE_INVALID = 0x0,
 111         CQE_TYPE_RX = 0x2,
 112         CQE_TYPE_RX_SPLIT = 0x3,
 113         CQE_TYPE_RX_TCP = 0x4,
 114         CQE_TYPE_SEND = 0x8,
 115         CQE_TYPE_SEND_PTP = 0x9,
 116 };
 117
 118 enum cqe_rx_tcp_status {
 119         CQE_RX_STATUS_VALID_TCP_CNXT = 0x00,
 120         CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F,
 121 };
 122
 123 enum cqe_send_status {
 124         CQE_SEND_STATUS_GOOD = 0x00,
 125         CQE_SEND_STATUS_DESC_FAULT = 0x01,
 126         CQE_SEND_STATUS_HDR_CONS_ERR = 0x11,
 127         CQE_SEND_STATUS_SUBDESC_ERR = 0x12,
 128         CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80,
 129         CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81,
 130         CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82,
 131         CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83,
 132         CQE_SEND_STATUS_LOCK_VIOL = 0x84,
 133         CQE_SEND_STATUS_LOCK_UFLOW = 0x85,
 134         CQE_SEND_STATUS_DATA_FAULT = 0x86,
 135         CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87,
 136         CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88,
 137         CQE_SEND_STATUS_MEM_FAULT = 0x89,
 138         CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A,
 139         CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B,
 140 };
 141
 142 enum cqe_rx_tcp_end_reason {
 143         CQE_RX_TCP_END_FIN_FLAG_DET = 0,
 144         CQE_RX_TCP_END_INVALID_FLAG = 1,
 145         CQE_RX_TCP_END_TIMEOUT = 2,
 146         CQE_RX_TCP_END_OUT_OF_SEQ = 3,
 147         CQE_RX_TCP_END_PKT_ERR = 4,
 148         CQE_RX_TCP_END_QS_DISABLED = 0x0F,
 149 };
 150
 151 /* Packet protocol level error enumeration */
 152 enum cqe_rx_err_level {
 153         CQE_RX_ERRLVL_RE = 0x0,
 154         CQE_RX_ERRLVL_L2 = 0x1,
 155         CQE_RX_ERRLVL_L3 = 0x2,
 156         CQE_RX_ERRLVL_L4 = 0x3,
 157 };
 158
 159 /* Packet protocol level error type enumeration */
 160 enum cqe_rx_err_opcode {
 161         CQE_RX_ERR_RE_NONE = 0x0,
 162         CQE_RX_ERR_RE_PARTIAL = 0x1,
 163         CQE_RX_ERR_RE_JABBER = 0x2,
 164         CQE_RX_ERR_RE_FCS = 0x7,
 165         CQE_RX_ERR_RE_TERMINATE = 0x9,
 166         CQE_RX_ERR_RE_RX_CTL = 0xb,
 167         CQE_RX_ERR_PREL2_ERR = 0x1f,
 168         CQE_RX_ERR_L2_FRAGMENT = 0x20,
 169         CQE_RX_ERR_L2_OVERRUN = 0x21,
 170         CQE_RX_ERR_L2_PFCS = 0x22,
 171         CQE_RX_ERR_L2_PUNY = 0x23,
 172         CQE_RX_ERR_L2_MAL = 0x24,
 173         CQE_RX_ERR_L2_OVERSIZE = 0x25,
 174         CQE_RX_ERR_L2_UNDERSIZE = 0x26,
 175         CQE_RX_ERR_L2_LENMISM = 0x27,
 176         CQE_RX_ERR_L2_PCLP = 0x28,
 177         CQE_RX_ERR_IP_NOT = 0x41,
 178         CQE_RX_ERR_IP_CHK = 0x42,
 179         CQE_RX_ERR_IP_MAL = 0x43,
 180         CQE_RX_ERR_IP_MALD = 0x44,
 181         CQE_RX_ERR_IP_HOP = 0x45,
 182         CQE_RX_ERR_L3_ICRC = 0x46,
 183         CQE_RX_ERR_L3_PCLP = 0x47,
 184         CQE_RX_ERR_L4_MAL = 0x61,
 185         CQE_RX_ERR_L4_CHK = 0x62,
 186         CQE_RX_ERR_UDP_LEN = 0x63,
 187         CQE_RX_ERR_L4_PORT = 0x64,
 188         CQE_RX_ERR_TCP_FLAG = 0x65,
 189         CQE_RX_ERR_TCP_OFFSET = 0x66,
 190         CQE_RX_ERR_L4_PCLP = 0x67,
 191         CQE_RX_ERR_RBDR_TRUNC = 0x70,
 192 };
 193
 194 struct cqe_rx_t {
 195 #if defined(__BIG_ENDIAN_BITFIELD)
 196         uint64_t   cqe_type:4; /* W0 */
 197         uint64_t   stdn_fault:1;
 198         uint64_t   rsvd0:1;
 199         uint64_t   rq_qs:7;
 200         uint64_t   rq_idx:3;
 201         uint64_t   rsvd1:12;
 202         uint64_t   rss_alg:4;
 203         uint64_t   rsvd2:4;
 204         uint64_t   rb_cnt:4;
 205         uint64_t   vlan_found:1;
 206         uint64_t   vlan_stripped:1;
 207         uint64_t   vlan2_found:1;
 208         uint64_t   vlan2_stripped:1;
 209         uint64_t   l4_type:4;
 210         uint64_t   l3_type:4;
 211         uint64_t   l2_present:1;
 212         uint64_t   err_level:3;
 213         uint64_t   err_opcode:8;
 214
 215         uint64_t   pkt_len:16; /* W1 */
 216         uint64_t   l2_ptr:8;
 217         uint64_t   l3_ptr:8;
 218         uint64_t   l4_ptr:8;
 219         uint64_t   cq_pkt_len:8;
 220         uint64_t   align_pad:3;
 221         uint64_t   rsvd3:1;
 222         uint64_t   chan:12;
 223
 224         uint64_t   rss_tag:32; /* W2 */
 225         uint64_t   vlan_tci:16;
 226         uint64_t   vlan_ptr:8;
 227         uint64_t   vlan2_ptr:8;
 228
 229         uint64_t   rb3_sz:16; /* W3 */
 230         uint64_t   rb2_sz:16;
 231         uint64_t   rb1_sz:16;
 232         uint64_t   rb0_sz:16;
 233
 234         uint64_t   rb7_sz:16; /* W4 */
 235         uint64_t   rb6_sz:16;
 236         uint64_t   rb5_sz:16;
 237         uint64_t   rb4_sz:16;
 238
 239         uint64_t   rb11_sz:16; /* W5 */
 240         uint64_t   rb10_sz:16;
 241         uint64_t   rb9_sz:16;
 242         uint64_t   rb8_sz:16;
 243 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 244         uint64_t   err_opcode:8;
 245         uint64_t   err_level:3;
 246         uint64_t   l2_present:1;
 247         uint64_t   l3_type:4;
 248         uint64_t   l4_type:4;
 249         uint64_t   vlan2_stripped:1;
 250         uint64_t   vlan2_found:1;
 251         uint64_t   vlan_stripped:1;
 252         uint64_t   vlan_found:1;
 253         uint64_t   rb_cnt:4;
 254         uint64_t   rsvd2:4;
 255         uint64_t   rss_alg:4;
 256         uint64_t   rsvd1:12;
 257         uint64_t   rq_idx:3;
 258         uint64_t   rq_qs:7;
 259         uint64_t   rsvd0:1;
 260         uint64_t   stdn_fault:1;
 261         uint64_t   cqe_type:4; /* W0 */
 262         uint64_t   chan:12;
 263         uint64_t   rsvd3:1;
 264         uint64_t   align_pad:3;
 265         uint64_t   cq_pkt_len:8;
 266         uint64_t   l4_ptr:8;
 267         uint64_t   l3_ptr:8;
 268         uint64_t   l2_ptr:8;
 269         uint64_t   pkt_len:16; /* W1 */
 270         uint64_t   vlan2_ptr:8;
 271         uint64_t   vlan_ptr:8;
 272         uint64_t   vlan_tci:16;
 273         uint64_t   rss_tag:32; /* W2 */
 274         uint64_t   rb0_sz:16;
 275         uint64_t   rb1_sz:16;
 276         uint64_t   rb2_sz:16;
 277         uint64_t   rb3_sz:16; /* W3 */
 278         uint64_t   rb4_sz:16;
 279         uint64_t   rb5_sz:16;
 280         uint64_t   rb6_sz:16;
 281         uint64_t   rb7_sz:16; /* W4 */
 282         uint64_t   rb8_sz:16;
 283         uint64_t   rb9_sz:16;
 284         uint64_t   rb10_sz:16;
 285         uint64_t   rb11_sz:16; /* W5 */
 286 #endif
 287         uint64_t   rb0_ptr:64;
 288         uint64_t   rb1_ptr:64;
 289         uint64_t   rb2_ptr:64;
 290         uint64_t   rb3_ptr:64;
 291         uint64_t   rb4_ptr:64;
 292         uint64_t   rb5_ptr:64;
 293         uint64_t   rb6_ptr:64;
 294         uint64_t   rb7_ptr:64;
 295         uint64_t   rb8_ptr:64;
 296         uint64_t   rb9_ptr:64;
 297         uint64_t   rb10_ptr:64;
 298         uint64_t   rb11_ptr:64;
 299 };
 300
 301 struct cqe_rx_tcp_err_t {
 302 #if defined(__BIG_ENDIAN_BITFIELD)
 303         uint64_t   cqe_type:4; /* W0 */
 304         uint64_t   rsvd0:60;
 305
 306         uint64_t   rsvd1:4; /* W1 */
 307         uint64_t   partial_first:1;
 308         uint64_t   rsvd2:27;
 309         uint64_t   rbdr_bytes:8;
 310         uint64_t   rsvd3:24;
 311 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 312         uint64_t   rsvd0:60;
 313         uint64_t   cqe_type:4;
 314
 315         uint64_t   rsvd3:24;
 316         uint64_t   rbdr_bytes:8;
 317         uint64_t   rsvd2:27;
 318         uint64_t   partial_first:1;
 319         uint64_t   rsvd1:4;
 320 #endif
 321 };
 322
 323 struct cqe_rx_tcp_t {
 324 #if defined(__BIG_ENDIAN_BITFIELD)
 325         uint64_t   cqe_type:4; /* W0 */
 326         uint64_t   rsvd0:52;
 327         uint64_t   cq_tcp_status:8;
 328
 329         uint64_t   rsvd1:32; /* W1 */
 330         uint64_t   tcp_cntx_bytes:8;
 331         uint64_t   rsvd2:8;
 332         uint64_t   tcp_err_bytes:16;
 333 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 334         uint64_t   cq_tcp_status:8;
 335         uint64_t   rsvd0:52;
 336         uint64_t   cqe_type:4; /* W0 */
 337
 338         uint64_t   tcp_err_bytes:16;
 339         uint64_t   rsvd2:8;
 340         uint64_t   tcp_cntx_bytes:8;
 341         uint64_t   rsvd1:32; /* W1 */
 342 #endif
 343 };
 344
 345 struct cqe_send_t {
 346 #if defined(__BIG_ENDIAN_BITFIELD)
 347         uint64_t   cqe_type:4; /* W0 */
 348         uint64_t   rsvd0:4;
 349         uint64_t   sqe_ptr:16;
 350         uint64_t   rsvd1:4;
 351         uint64_t   rsvd2:10;
 352         uint64_t   sq_qs:7;
 353         uint64_t   sq_idx:3;
 354         uint64_t   rsvd3:8;
 355         uint64_t   send_status:8;
 356
 357         uint64_t   ptp_timestamp:64; /* W1 */
 358 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 359         uint64_t   send_status:8;
 360         uint64_t   rsvd3:8;
 361         uint64_t   sq_idx:3;
 362         uint64_t   sq_qs:7;
 363         uint64_t   rsvd2:10;
 364         uint64_t   rsvd1:4;
 365         uint64_t   sqe_ptr:16;
 366         uint64_t   rsvd0:4;
 367         uint64_t   cqe_type:4; /* W0 */
 368
 369         uint64_t   ptp_timestamp:64; /* W1 */
 370 #endif
 371 };
 372
 373 union cq_desc_t {
 374         uint64_t    u[64];
 375         struct cqe_send_t snd_hdr;
 376         struct cqe_rx_t rx_hdr;
 377         struct cqe_rx_tcp_t rx_tcp_hdr;
 378         struct cqe_rx_tcp_err_t rx_tcp_err_hdr;
 379 };
 380
 381 struct rbdr_entry_t {
 382 #if defined(__BIG_ENDIAN_BITFIELD)
 383         uint64_t   rsvd0:15;
 384         uint64_t   buf_addr:42;
 385         uint64_t   cache_align:7;
 386 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 387         uint64_t   cache_align:7;
 388         uint64_t   buf_addr:42;
 389         uint64_t   rsvd0:15;
 390 #endif
 391 };
 392
 393 /* TCP reassembly context */
 394 struct rbe_tcp_cnxt_t {
 395 #if defined(__BIG_ENDIAN_BITFIELD)
 396         uint64_t   tcp_pkt_cnt:12;
 397         uint64_t   rsvd1:4;
 398         uint64_t   align_hdr_bytes:4;
 399         uint64_t   align_ptr_bytes:4;
 400         uint64_t   ptr_bytes:16;
 401         uint64_t   rsvd2:24;
 402         uint64_t   cqe_type:4;
 403         uint64_t   rsvd0:54;
 404         uint64_t   tcp_end_reason:2;
 405         uint64_t   tcp_status:4;
 406 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 407         uint64_t   tcp_status:4;
 408         uint64_t   tcp_end_reason:2;
 409         uint64_t   rsvd0:54;
 410         uint64_t   cqe_type:4;
 411         uint64_t   rsvd2:24;
 412         uint64_t   ptr_bytes:16;
 413         uint64_t   align_ptr_bytes:4;
 414         uint64_t   align_hdr_bytes:4;
 415         uint64_t   rsvd1:4;
 416         uint64_t   tcp_pkt_cnt:12;
 417 #endif
 418 };
 419
 420 /* Always Big endian */
 421 struct rx_hdr_t {
 422         uint64_t   opaque:32;
 423         uint64_t   rss_flow:8;
 424         uint64_t   skip_length:6;
 425         uint64_t   disable_rss:1;
 426         uint64_t   disable_tcp_reassembly:1;
 427         uint64_t   nodrop:1;
 428         uint64_t   dest_alg:2;
 429         uint64_t   rsvd0:2;
 430         uint64_t   dest_rq:11;
 431 };
 432
 433 enum send_l4_csum_type {
 434         SEND_L4_CSUM_DISABLE = 0x00,
 435         SEND_L4_CSUM_UDP = 0x01,
 436         SEND_L4_CSUM_TCP = 0x02,
 437         SEND_L4_CSUM_SCTP = 0x03,
 438 };
 439
 440 enum send_crc_alg {
 441         SEND_CRCALG_CRC32 = 0x00,
 442         SEND_CRCALG_CRC32C = 0x01,
 443         SEND_CRCALG_ICRC = 0x02,
 444 };
 445
 446 enum send_load_type {
 447         SEND_LD_TYPE_LDD = 0x00,
 448         SEND_LD_TYPE_LDT = 0x01,
 449         SEND_LD_TYPE_LDWB = 0x02,
 450 };
 451
 452 enum send_mem_alg_type {
 453         SEND_MEMALG_SET = 0x00,
 454         SEND_MEMALG_ADD = 0x08,
 455         SEND_MEMALG_SUB = 0x09,
 456         SEND_MEMALG_ADDLEN = 0x0A,
 457         SEND_MEMALG_SUBLEN = 0x0B,
 458 };
 459
 460 enum send_mem_dsz_type {
 461         SEND_MEMDSZ_B64 = 0x00,
 462         SEND_MEMDSZ_B32 = 0x01,
 463         SEND_MEMDSZ_B8 = 0x03,
 464 };
 465
 466 enum sq_subdesc_type {
 467         SQ_DESC_TYPE_INVALID = 0x00,
 468         SQ_DESC_TYPE_HEADER = 0x01,
 469         SQ_DESC_TYPE_CRC = 0x02,
 470         SQ_DESC_TYPE_IMMEDIATE = 0x03,
 471         SQ_DESC_TYPE_GATHER = 0x04,
 472         SQ_DESC_TYPE_MEMORY = 0x05,
 473 };
 474
 475 struct sq_crc_subdesc {
 476 #if defined(__BIG_ENDIAN_BITFIELD)
 477         uint64_t    rsvd1:32;
 478         uint64_t    crc_ival:32;
 479         uint64_t    subdesc_type:4;
 480         uint64_t    crc_alg:2;
 481         uint64_t    rsvd0:10;
 482         uint64_t    crc_insert_pos:16;
 483         uint64_t    hdr_start:16;
 484         uint64_t    crc_len:16;
 485 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 486         uint64_t    crc_len:16;
 487         uint64_t    hdr_start:16;
 488         uint64_t    crc_insert_pos:16;
 489         uint64_t    rsvd0:10;
 490         uint64_t    crc_alg:2;
 491         uint64_t    subdesc_type:4;
 492         uint64_t    crc_ival:32;
 493         uint64_t    rsvd1:32;
 494 #endif
 495 };
 496
 497 struct sq_gather_subdesc {
 498 #if defined(__BIG_ENDIAN_BITFIELD)
 499         uint64_t    subdesc_type:4; /* W0 */
 500         uint64_t    ld_type:2;
 501         uint64_t    rsvd0:42;
 502         uint64_t    size:16;
 503
 504         uint64_t    rsvd1:15; /* W1 */
 505         uint64_t    addr:49;
 506 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 507         uint64_t    size:16;
 508         uint64_t    rsvd0:42;
 509         uint64_t    ld_type:2;
 510         uint64_t    subdesc_type:4; /* W0 */
 511
 512         uint64_t    addr:49;
 513         uint64_t    rsvd1:15; /* W1 */
 514 #endif
 515 };
 516
 517 /* SQ immediate subdescriptor */
 518 struct sq_imm_subdesc {
 519 #if defined(__BIG_ENDIAN_BITFIELD)
 520         uint64_t    subdesc_type:4; /* W0 */
 521         uint64_t    rsvd0:46;
 522         uint64_t    len:14;
 523
 524         uint64_t    data:64; /* W1 */
 525 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 526         uint64_t    len:14;
 527         uint64_t    rsvd0:46;
 528         uint64_t    subdesc_type:4; /* W0 */
 529
 530         uint64_t    data:64; /* W1 */
 531 #endif
 532 };
 533
 534 struct sq_mem_subdesc {
 535 #if defined(__BIG_ENDIAN_BITFIELD)
 536         uint64_t    subdesc_type:4; /* W0 */
 537         uint64_t    mem_alg:4;
 538         uint64_t    mem_dsz:2;
 539         uint64_t    wmem:1;
 540         uint64_t    rsvd0:21;
 541         uint64_t    offset:32;
 542
 543         uint64_t    rsvd1:15; /* W1 */
 544         uint64_t    addr:49;
 545 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 546         uint64_t    offset:32;
 547         uint64_t    rsvd0:21;
 548         uint64_t    wmem:1;
 549         uint64_t    mem_dsz:2;
 550         uint64_t    mem_alg:4;
 551         uint64_t    subdesc_type:4; /* W0 */
 552
 553         uint64_t    addr:49;
 554         uint64_t    rsvd1:15; /* W1 */
 555 #endif
 556 };
 557
 558 struct sq_hdr_subdesc {
 559 #if defined(__BIG_ENDIAN_BITFIELD)
 560         uint64_t    subdesc_type:4;
 561         uint64_t    tso:1;
 562         uint64_t    post_cqe:1; /* Post CQE on no error also */
 563         uint64_t    dont_send:1;
 564         uint64_t    tstmp:1;
 565         uint64_t    subdesc_cnt:8;
 566         uint64_t    csum_l4:2;
 567         uint64_t    csum_l3:1;
 568         uint64_t    csum_inner_l4:2;
 569         uint64_t    csum_inner_l3:1;
 570         uint64_t    rsvd0:2;
 571         uint64_t    l4_offset:8;
 572         uint64_t    l3_offset:8;
 573         uint64_t    rsvd1:4;
 574         uint64_t    tot_len:20; /* W0 */
 575
 576         uint64_t    rsvd2:24;
 577         uint64_t    inner_l4_offset:8;
 578         uint64_t    inner_l3_offset:8;
 579         uint64_t    tso_start:8;
 580         uint64_t    rsvd3:2;
 581         uint64_t    tso_max_paysize:14; /* W1 */
 582 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 583         uint64_t    tot_len:20;
 584         uint64_t    rsvd1:4;
 585         uint64_t    l3_offset:8;
 586         uint64_t    l4_offset:8;
 587         uint64_t    rsvd0:2;
 588         uint64_t    csum_inner_l3:1;
 589         uint64_t    csum_inner_l4:2;
 590         uint64_t    csum_l3:1;
 591         uint64_t    csum_l4:2;
 592         uint64_t    subdesc_cnt:8;
 593         uint64_t    tstmp:1;
 594         uint64_t    dont_send:1;
 595         uint64_t    post_cqe:1; /* Post CQE on no error also */
 596         uint64_t    tso:1;
 597         uint64_t    subdesc_type:4; /* W0 */
 598
 599         uint64_t    tso_max_paysize:14;
 600         uint64_t    rsvd3:2;
 601         uint64_t    tso_start:8;
 602         uint64_t    inner_l3_offset:8;
 603         uint64_t    inner_l4_offset:8;
 604         uint64_t    rsvd2:24;
 605 #endif
 606 };
 607
 608 /* Queue config register formats */
 609 struct rq_cfg {
 610 #if defined(__BIG_ENDIAN_BITFIELD)
 611         uint64_t reserved_2_63:62;
 612         uint64_t ena:1;
 613         uint64_t tcp_ena:1;
 614 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 615         uint64_t tcp_ena:1;
 616         uint64_t ena:1;
 617         uint64_t reserved_2_63:62;
 618 #endif
 619 };
 620
 621 struct cq_cfg {
 622 #if defined(__BIG_ENDIAN_BITFIELD)
 623         uint64_t reserved_43_63:21;
 624         uint64_t ena:1;
 625         uint64_t reset:1;
 626         uint64_t caching:1;
 627         uint64_t reserved_35_39:5;
 628         uint64_t qsize:3;
 629         uint64_t reserved_25_31:7;
 630         uint64_t avg_con:9;
 631         uint64_t reserved_0_15:16;
 632 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 633         uint64_t reserved_0_15:16;
 634         uint64_t avg_con:9;
 635         uint64_t reserved_25_31:7;
 636         uint64_t qsize:3;
 637         uint64_t reserved_35_39:5;
 638         uint64_t caching:1;
 639         uint64_t reset:1;
 640         uint64_t ena:1;
 641         uint64_t reserved_43_63:21;
 642 #endif
 643 };
 644
 645 struct sq_cfg {
 646 #if defined(__BIG_ENDIAN_BITFIELD)
 647         uint64_t reserved_20_63:44;
 648         uint64_t ena:1;
 649         uint64_t reserved_18_18:1;
 650         uint64_t reset:1;
 651         uint64_t ldwb:1;
 652         uint64_t reserved_11_15:5;
 653         uint64_t qsize:3;
 654         uint64_t reserved_3_7:5;
 655         uint64_t tstmp_bgx_intf:3;
 656 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 657         uint64_t tstmp_bgx_intf:3;
 658         uint64_t reserved_3_7:5;
 659         uint64_t qsize:3;
 660         uint64_t reserved_11_15:5;
 661         uint64_t ldwb:1;
 662         uint64_t reset:1;
 663         uint64_t reserved_18_18:1;
 664         uint64_t ena:1;
 665         uint64_t reserved_20_63:44;
 666 #endif
 667 };
 668
 669 struct rbdr_cfg {
 670 #if defined(__BIG_ENDIAN_BITFIELD)
 671         uint64_t reserved_45_63:19;
 672         uint64_t ena:1;
 673         uint64_t reset:1;
 674         uint64_t ldwb:1;
 675         uint64_t reserved_36_41:6;
 676         uint64_t qsize:4;
 677         uint64_t reserved_25_31:7;
 678         uint64_t avg_con:9;
 679         uint64_t reserved_12_15:4;
 680         uint64_t lines:12;
 681 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 682         uint64_t lines:12;
 683         uint64_t reserved_12_15:4;
 684         uint64_t avg_con:9;
 685         uint64_t reserved_25_31:7;
 686         uint64_t qsize:4;
 687         uint64_t reserved_36_41:6;
 688         uint64_t ldwb:1;
 689         uint64_t reset:1;
 690         uint64_t ena: 1;
 691         uint64_t reserved_45_63:19;
 692 #endif
 693 };
 694
 695 struct qs_cfg {
 696 #if defined(__BIG_ENDIAN_BITFIELD)
 697         uint64_t reserved_32_63:32;
 698         uint64_t ena:1;
 699         uint64_t reserved_27_30:4;
 700         uint64_t sq_ins_ena:1;
 701         uint64_t sq_ins_pos:6;
 702         uint64_t lock_ena:1;
 703         uint64_t lock_viol_cqe_ena:1;
 704         uint64_t send_tstmp_ena:1;
 705         uint64_t be:1;
 706         uint64_t reserved_7_15:9;
 707         uint64_t vnic:7;
 708 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 709         uint64_t vnic:7;
 710         uint64_t reserved_7_15:9;
 711         uint64_t be:1;
 712         uint64_t send_tstmp_ena:1;
 713         uint64_t lock_viol_cqe_ena:1;
 714         uint64_t lock_ena:1;
 715         uint64_t sq_ins_pos:6;
 716         uint64_t sq_ins_ena:1;
 717         uint64_t reserved_27_30:4;
 718         uint64_t ena:1;
 719         uint64_t reserved_32_63:32;
 720 #endif
 721 };
 722
 723 #endif /* Q_STRUCT_H */