2 * Copyright (C) 2015 Cavium Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #define __LITTLE_ENDIAN_BITFIELD
35 /* Load transaction types for reading segment bytes specified by
36 * NIC_SEND_GATHER_S[LD_TYPE].
38 enum nic_send_ld_type_e {
39 NIC_SEND_LD_TYPE_E_LDD = 0x0,
40 NIC_SEND_LD_TYPE_E_LDT = 0x1,
41 NIC_SEND_LD_TYPE_E_LDWB = 0x2,
42 NIC_SEND_LD_TYPE_E_ENUM_LAST = 0x3,
45 enum ether_type_algorithm {
48 ETYPE_ALG_ENDPARSE = 0x2,
50 ETYPE_ALG_VLAN_STRIP = 0x4,
57 L3TYPE_IPV4_OPTIONS = 0x05,
59 L3TYPE_IPV6_OPTIONS = 0x07,
60 L3TYPE_ET_STOP = 0x0D,
66 L4TYPE_IPSEC_ESP = 0x01,
73 L4TYPE_ROCE_BTH = 0x08,
77 /* CPI and RSSI configuration */
78 enum cpi_algorithm_type {
85 enum rss_algorithm_type {
89 RSS_ALG_TCP_IP = 0x03,
90 RSS_ALG_UDP_IP = 0x04,
91 RSS_ALG_SCTP_IP = 0x05,
92 RSS_ALG_GRE_IP = 0x06,
97 RSS_HASH_L2ETC = 0x00,
100 RSS_HASH_TCP_SYN_DIS = 0x03,
102 RSS_HASH_L4ETC = 0x05,
103 RSS_HASH_ROCE = 0x06,
108 /* Completion queue entry types */
110 CQE_TYPE_INVALID = 0x0,
112 CQE_TYPE_RX_SPLIT = 0x3,
113 CQE_TYPE_RX_TCP = 0x4,
115 CQE_TYPE_SEND_PTP = 0x9,
118 enum cqe_rx_tcp_status {
119 CQE_RX_STATUS_VALID_TCP_CNXT = 0x00,
120 CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F,
123 enum cqe_send_status {
124 CQE_SEND_STATUS_GOOD = 0x00,
125 CQE_SEND_STATUS_DESC_FAULT = 0x01,
126 CQE_SEND_STATUS_HDR_CONS_ERR = 0x11,
127 CQE_SEND_STATUS_SUBDESC_ERR = 0x12,
128 CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80,
129 CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81,
130 CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82,
131 CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83,
132 CQE_SEND_STATUS_LOCK_VIOL = 0x84,
133 CQE_SEND_STATUS_LOCK_UFLOW = 0x85,
134 CQE_SEND_STATUS_DATA_FAULT = 0x86,
135 CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87,
136 CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88,
137 CQE_SEND_STATUS_MEM_FAULT = 0x89,
138 CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A,
139 CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B,
142 enum cqe_rx_tcp_end_reason {
143 CQE_RX_TCP_END_FIN_FLAG_DET = 0,
144 CQE_RX_TCP_END_INVALID_FLAG = 1,
145 CQE_RX_TCP_END_TIMEOUT = 2,
146 CQE_RX_TCP_END_OUT_OF_SEQ = 3,
147 CQE_RX_TCP_END_PKT_ERR = 4,
148 CQE_RX_TCP_END_QS_DISABLED = 0x0F,
151 /* Packet protocol level error enumeration */
152 enum cqe_rx_err_level {
153 CQE_RX_ERRLVL_RE = 0x0,
154 CQE_RX_ERRLVL_L2 = 0x1,
155 CQE_RX_ERRLVL_L3 = 0x2,
156 CQE_RX_ERRLVL_L4 = 0x3,
159 /* Packet protocol level error type enumeration */
160 enum cqe_rx_err_opcode {
161 CQE_RX_ERR_RE_NONE = 0x0,
162 CQE_RX_ERR_RE_PARTIAL = 0x1,
163 CQE_RX_ERR_RE_JABBER = 0x2,
164 CQE_RX_ERR_RE_FCS = 0x7,
165 CQE_RX_ERR_RE_TERMINATE = 0x9,
166 CQE_RX_ERR_RE_RX_CTL = 0xb,
167 CQE_RX_ERR_PREL2_ERR = 0x1f,
168 CQE_RX_ERR_L2_FRAGMENT = 0x20,
169 CQE_RX_ERR_L2_OVERRUN = 0x21,
170 CQE_RX_ERR_L2_PFCS = 0x22,
171 CQE_RX_ERR_L2_PUNY = 0x23,
172 CQE_RX_ERR_L2_MAL = 0x24,
173 CQE_RX_ERR_L2_OVERSIZE = 0x25,
174 CQE_RX_ERR_L2_UNDERSIZE = 0x26,
175 CQE_RX_ERR_L2_LENMISM = 0x27,
176 CQE_RX_ERR_L2_PCLP = 0x28,
177 CQE_RX_ERR_IP_NOT = 0x41,
178 CQE_RX_ERR_IP_CHK = 0x42,
179 CQE_RX_ERR_IP_MAL = 0x43,
180 CQE_RX_ERR_IP_MALD = 0x44,
181 CQE_RX_ERR_IP_HOP = 0x45,
182 CQE_RX_ERR_L3_ICRC = 0x46,
183 CQE_RX_ERR_L3_PCLP = 0x47,
184 CQE_RX_ERR_L4_MAL = 0x61,
185 CQE_RX_ERR_L4_CHK = 0x62,
186 CQE_RX_ERR_UDP_LEN = 0x63,
187 CQE_RX_ERR_L4_PORT = 0x64,
188 CQE_RX_ERR_TCP_FLAG = 0x65,
189 CQE_RX_ERR_TCP_OFFSET = 0x66,
190 CQE_RX_ERR_L4_PCLP = 0x67,
191 CQE_RX_ERR_RBDR_TRUNC = 0x70,
195 #if defined(__BIG_ENDIAN_BITFIELD)
196 uint64_t cqe_type:4; /* W0 */
197 uint64_t stdn_fault:1;
205 uint64_t vlan_found:1;
206 uint64_t vlan_stripped:1;
207 uint64_t vlan2_found:1;
208 uint64_t vlan2_stripped:1;
211 uint64_t l2_present:1;
212 uint64_t err_level:3;
213 uint64_t err_opcode:8;
215 uint64_t pkt_len:16; /* W1 */
219 uint64_t cq_pkt_len:8;
220 uint64_t align_pad:3;
224 uint64_t rss_tag:32; /* W2 */
225 uint64_t vlan_tci:16;
227 uint64_t vlan2_ptr:8;
229 uint64_t rb3_sz:16; /* W3 */
234 uint64_t rb7_sz:16; /* W4 */
239 uint64_t rb11_sz:16; /* W5 */
243 #elif defined(__LITTLE_ENDIAN_BITFIELD)
244 uint64_t err_opcode:8;
245 uint64_t err_level:3;
246 uint64_t l2_present:1;
249 uint64_t vlan2_stripped:1;
250 uint64_t vlan2_found:1;
251 uint64_t vlan_stripped:1;
252 uint64_t vlan_found:1;
260 uint64_t stdn_fault:1;
261 uint64_t cqe_type:4; /* W0 */
264 uint64_t align_pad:3;
265 uint64_t cq_pkt_len:8;
269 uint64_t pkt_len:16; /* W1 */
270 uint64_t vlan2_ptr:8;
272 uint64_t vlan_tci:16;
273 uint64_t rss_tag:32; /* W2 */
277 uint64_t rb3_sz:16; /* W3 */
281 uint64_t rb7_sz:16; /* W4 */
285 uint64_t rb11_sz:16; /* W5 */
297 uint64_t rb10_ptr:64;
298 uint64_t rb11_ptr:64;
301 struct cqe_rx_tcp_err_t {
302 #if defined(__BIG_ENDIAN_BITFIELD)
303 uint64_t cqe_type:4; /* W0 */
306 uint64_t rsvd1:4; /* W1 */
307 uint64_t partial_first:1;
309 uint64_t rbdr_bytes:8;
311 #elif defined(__LITTLE_ENDIAN_BITFIELD)
316 uint64_t rbdr_bytes:8;
318 uint64_t partial_first:1;
323 struct cqe_rx_tcp_t {
324 #if defined(__BIG_ENDIAN_BITFIELD)
325 uint64_t cqe_type:4; /* W0 */
327 uint64_t cq_tcp_status:8;
329 uint64_t rsvd1:32; /* W1 */
330 uint64_t tcp_cntx_bytes:8;
332 uint64_t tcp_err_bytes:16;
333 #elif defined(__LITTLE_ENDIAN_BITFIELD)
334 uint64_t cq_tcp_status:8;
336 uint64_t cqe_type:4; /* W0 */
338 uint64_t tcp_err_bytes:16;
340 uint64_t tcp_cntx_bytes:8;
341 uint64_t rsvd1:32; /* W1 */
346 #if defined(__BIG_ENDIAN_BITFIELD)
347 uint64_t cqe_type:4; /* W0 */
355 uint64_t send_status:8;
357 uint64_t ptp_timestamp:64; /* W1 */
358 #elif defined(__LITTLE_ENDIAN_BITFIELD)
359 uint64_t send_status:8;
367 uint64_t cqe_type:4; /* W0 */
369 uint64_t ptp_timestamp:64; /* W1 */
375 struct cqe_send_t snd_hdr;
376 struct cqe_rx_t rx_hdr;
377 struct cqe_rx_tcp_t rx_tcp_hdr;
378 struct cqe_rx_tcp_err_t rx_tcp_err_hdr;
381 struct rbdr_entry_t {
382 #if defined(__BIG_ENDIAN_BITFIELD)
384 uint64_t buf_addr:42;
385 uint64_t cache_align:7;
386 #elif defined(__LITTLE_ENDIAN_BITFIELD)
387 uint64_t cache_align:7;
388 uint64_t buf_addr:42;
393 /* TCP reassembly context */
394 struct rbe_tcp_cnxt_t {
395 #if defined(__BIG_ENDIAN_BITFIELD)
396 uint64_t tcp_pkt_cnt:12;
398 uint64_t align_hdr_bytes:4;
399 uint64_t align_ptr_bytes:4;
400 uint64_t ptr_bytes:16;
404 uint64_t tcp_end_reason:2;
405 uint64_t tcp_status:4;
406 #elif defined(__LITTLE_ENDIAN_BITFIELD)
407 uint64_t tcp_status:4;
408 uint64_t tcp_end_reason:2;
412 uint64_t ptr_bytes:16;
413 uint64_t align_ptr_bytes:4;
414 uint64_t align_hdr_bytes:4;
416 uint64_t tcp_pkt_cnt:12;
420 /* Always Big endian */
424 uint64_t skip_length:6;
425 uint64_t disable_rss:1;
426 uint64_t disable_tcp_reassembly:1;
433 enum send_l4_csum_type {
434 SEND_L4_CSUM_DISABLE = 0x00,
435 SEND_L4_CSUM_UDP = 0x01,
436 SEND_L4_CSUM_TCP = 0x02,
437 SEND_L4_CSUM_SCTP = 0x03,
441 SEND_CRCALG_CRC32 = 0x00,
442 SEND_CRCALG_CRC32C = 0x01,
443 SEND_CRCALG_ICRC = 0x02,
446 enum send_load_type {
447 SEND_LD_TYPE_LDD = 0x00,
448 SEND_LD_TYPE_LDT = 0x01,
449 SEND_LD_TYPE_LDWB = 0x02,
452 enum send_mem_alg_type {
453 SEND_MEMALG_SET = 0x00,
454 SEND_MEMALG_ADD = 0x08,
455 SEND_MEMALG_SUB = 0x09,
456 SEND_MEMALG_ADDLEN = 0x0A,
457 SEND_MEMALG_SUBLEN = 0x0B,
460 enum send_mem_dsz_type {
461 SEND_MEMDSZ_B64 = 0x00,
462 SEND_MEMDSZ_B32 = 0x01,
463 SEND_MEMDSZ_B8 = 0x03,
466 enum sq_subdesc_type {
467 SQ_DESC_TYPE_INVALID = 0x00,
468 SQ_DESC_TYPE_HEADER = 0x01,
469 SQ_DESC_TYPE_CRC = 0x02,
470 SQ_DESC_TYPE_IMMEDIATE = 0x03,
471 SQ_DESC_TYPE_GATHER = 0x04,
472 SQ_DESC_TYPE_MEMORY = 0x05,
475 struct sq_crc_subdesc {
476 #if defined(__BIG_ENDIAN_BITFIELD)
478 uint64_t crc_ival:32;
479 uint64_t subdesc_type:4;
482 uint64_t crc_insert_pos:16;
483 uint64_t hdr_start:16;
485 #elif defined(__LITTLE_ENDIAN_BITFIELD)
487 uint64_t hdr_start:16;
488 uint64_t crc_insert_pos:16;
491 uint64_t subdesc_type:4;
492 uint64_t crc_ival:32;
497 struct sq_gather_subdesc {
498 #if defined(__BIG_ENDIAN_BITFIELD)
499 uint64_t subdesc_type:4; /* W0 */
504 uint64_t rsvd1:15; /* W1 */
506 #elif defined(__LITTLE_ENDIAN_BITFIELD)
510 uint64_t subdesc_type:4; /* W0 */
513 uint64_t rsvd1:15; /* W1 */
517 /* SQ immediate subdescriptor */
518 struct sq_imm_subdesc {
519 #if defined(__BIG_ENDIAN_BITFIELD)
520 uint64_t subdesc_type:4; /* W0 */
524 uint64_t data:64; /* W1 */
525 #elif defined(__LITTLE_ENDIAN_BITFIELD)
528 uint64_t subdesc_type:4; /* W0 */
530 uint64_t data:64; /* W1 */
534 struct sq_mem_subdesc {
535 #if defined(__BIG_ENDIAN_BITFIELD)
536 uint64_t subdesc_type:4; /* W0 */
543 uint64_t rsvd1:15; /* W1 */
545 #elif defined(__LITTLE_ENDIAN_BITFIELD)
551 uint64_t subdesc_type:4; /* W0 */
554 uint64_t rsvd1:15; /* W1 */
558 struct sq_hdr_subdesc {
559 #if defined(__BIG_ENDIAN_BITFIELD)
560 uint64_t subdesc_type:4;
562 uint64_t post_cqe:1; /* Post CQE on no error also */
563 uint64_t dont_send:1;
565 uint64_t subdesc_cnt:8;
568 uint64_t csum_inner_l4:2;
569 uint64_t csum_inner_l3:1;
571 uint64_t l4_offset:8;
572 uint64_t l3_offset:8;
574 uint64_t tot_len:20; /* W0 */
577 uint64_t inner_l4_offset:8;
578 uint64_t inner_l3_offset:8;
579 uint64_t tso_start:8;
581 uint64_t tso_max_paysize:14; /* W1 */
582 #elif defined(__LITTLE_ENDIAN_BITFIELD)
585 uint64_t l3_offset:8;
586 uint64_t l4_offset:8;
588 uint64_t csum_inner_l3:1;
589 uint64_t csum_inner_l4:2;
592 uint64_t subdesc_cnt:8;
594 uint64_t dont_send:1;
595 uint64_t post_cqe:1; /* Post CQE on no error also */
597 uint64_t subdesc_type:4; /* W0 */
599 uint64_t tso_max_paysize:14;
601 uint64_t tso_start:8;
602 uint64_t inner_l3_offset:8;
603 uint64_t inner_l4_offset:8;
608 /* Queue config register formats */
610 #if defined(__BIG_ENDIAN_BITFIELD)
611 uint64_t reserved_2_63:62;
614 #elif defined(__LITTLE_ENDIAN_BITFIELD)
617 uint64_t reserved_2_63:62;
622 #if defined(__BIG_ENDIAN_BITFIELD)
623 uint64_t reserved_43_63:21;
627 uint64_t reserved_35_39:5;
629 uint64_t reserved_25_31:7;
631 uint64_t reserved_0_15:16;
632 #elif defined(__LITTLE_ENDIAN_BITFIELD)
633 uint64_t reserved_0_15:16;
635 uint64_t reserved_25_31:7;
637 uint64_t reserved_35_39:5;
641 uint64_t reserved_43_63:21;
646 #if defined(__BIG_ENDIAN_BITFIELD)
647 uint64_t reserved_20_63:44;
649 uint64_t reserved_18_18:1;
652 uint64_t reserved_11_15:5;
654 uint64_t reserved_3_7:5;
655 uint64_t tstmp_bgx_intf:3;
656 #elif defined(__LITTLE_ENDIAN_BITFIELD)
657 uint64_t tstmp_bgx_intf:3;
658 uint64_t reserved_3_7:5;
660 uint64_t reserved_11_15:5;
663 uint64_t reserved_18_18:1;
665 uint64_t reserved_20_63:44;
670 #if defined(__BIG_ENDIAN_BITFIELD)
671 uint64_t reserved_45_63:19;
675 uint64_t reserved_36_41:6;
677 uint64_t reserved_25_31:7;
679 uint64_t reserved_12_15:4;
681 #elif defined(__LITTLE_ENDIAN_BITFIELD)
683 uint64_t reserved_12_15:4;
685 uint64_t reserved_25_31:7;
687 uint64_t reserved_36_41:6;
691 uint64_t reserved_45_63:19;
696 #if defined(__BIG_ENDIAN_BITFIELD)
697 uint64_t reserved_32_63:32;
699 uint64_t reserved_27_30:4;
700 uint64_t sq_ins_ena:1;
701 uint64_t sq_ins_pos:6;
703 uint64_t lock_viol_cqe_ena:1;
704 uint64_t send_tstmp_ena:1;
706 uint64_t reserved_7_15:9;
708 #elif defined(__LITTLE_ENDIAN_BITFIELD)
710 uint64_t reserved_7_15:9;
712 uint64_t send_tstmp_ena:1;
713 uint64_t lock_viol_cqe_ena:1;
715 uint64_t sq_ins_pos:6;
716 uint64_t sq_ins_ena:1;
717 uint64_t reserved_27_30:4;
719 uint64_t reserved_32_63:32;
723 #endif /* Q_STRUCT_H */