2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * VIA Rhine fast ethernet PCI NIC driver
38 * Supports various network adapters based on the VIA Rhine
39 * and Rhine II PCI controllers, including the D-Link DFE530TX.
40 * Datasheets are available at http://www.via.com.tw.
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
48 * The VIA Rhine controllers are similar in some respects to the
49 * the DEC tulip chips, except less complicated. The controller
50 * uses an MII bus and an external physical layer interface. The
51 * receiver has a one entry perfect filter and a 64-bit hash table
52 * multicast filter. Transmit and receive descriptors are similar
55 * The Rhine has a serious flaw in its transmit DMA mechanism:
56 * transmit buffers must be longword aligned. Unfortunately,
57 * FreeBSD doesn't guarantee that mbufs will be filled in starting
58 * at longword boundaries, so we have to do a buffer copy before
62 #include <sys/param.h>
63 #include <sys/systm.h>
64 #include <sys/sockio.h>
66 #include <sys/malloc.h>
67 #include <sys/kernel.h>
68 #include <sys/socket.h>
71 #include <net/if_arp.h>
72 #include <net/ethernet.h>
73 #include <net/if_dl.h>
74 #include <net/if_media.h>
78 #include <vm/vm.h> /* for vtophys */
79 #include <vm/pmap.h> /* for vtophys */
80 #include <machine/bus_pio.h>
81 #include <machine/bus_memio.h>
82 #include <machine/bus.h>
83 #include <machine/resource.h>
87 #include <dev/mii/mii.h>
88 #include <dev/mii/miivar.h>
90 #include <pci/pcireg.h>
91 #include <pci/pcivar.h>
95 #include <pci/if_vrreg.h>
97 MODULE_DEPEND(vr, miibus, 1, 1, 1);
99 /* "controller miibus0" required. See GENERIC if you get errors here. */
100 #include "miibus_if.h"
103 static const char rcsid[] =
108 * Various supported device vendors/types and their names.
110 static struct vr_type vr_devs[] = {
111 { VIA_VENDORID, VIA_DEVICEID_RHINE,
112 "VIA VT3043 Rhine I 10/100BaseTX" },
113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
114 "VIA VT86C100A Rhine II 10/100BaseTX" },
115 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
116 "VIA VT6102 Rhine II 10/100BaseTX" },
117 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
118 "Delta Electronics Rhine II 10/100BaseTX" },
119 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
120 "Addtron Technology Rhine II 10/100BaseTX" },
124 static int vr_probe __P((device_t));
125 static int vr_attach __P((device_t));
126 static int vr_detach __P((device_t));
128 static int vr_newbuf __P((struct vr_softc *,
129 struct vr_chain_onefrag *,
131 static int vr_encap __P((struct vr_softc *, struct vr_chain *,
134 static void vr_rxeof __P((struct vr_softc *));
135 static void vr_rxeoc __P((struct vr_softc *));
136 static void vr_txeof __P((struct vr_softc *));
137 static void vr_txeoc __P((struct vr_softc *));
138 static void vr_tick __P((void *));
139 static void vr_intr __P((void *));
140 static void vr_start __P((struct ifnet *));
141 static int vr_ioctl __P((struct ifnet *, u_long, caddr_t));
142 static void vr_init __P((void *));
143 static void vr_stop __P((struct vr_softc *));
144 static void vr_watchdog __P((struct ifnet *));
145 static void vr_shutdown __P((device_t));
146 static int vr_ifmedia_upd __P((struct ifnet *));
147 static void vr_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
149 static void vr_mii_sync __P((struct vr_softc *));
150 static void vr_mii_send __P((struct vr_softc *, u_int32_t, int));
151 static int vr_mii_readreg __P((struct vr_softc *, struct vr_mii_frame *));
152 static int vr_mii_writereg __P((struct vr_softc *, struct vr_mii_frame *));
153 static int vr_miibus_readreg __P((device_t, int, int));
154 static int vr_miibus_writereg __P((device_t, int, int, int));
155 static void vr_miibus_statchg __P((device_t));
157 static void vr_setcfg __P((struct vr_softc *, int));
158 static u_int8_t vr_calchash __P((u_int8_t *));
159 static void vr_setmulti __P((struct vr_softc *));
160 static void vr_reset __P((struct vr_softc *));
161 static int vr_list_rx_init __P((struct vr_softc *));
162 static int vr_list_tx_init __P((struct vr_softc *));
165 #define VR_RES SYS_RES_IOPORT
166 #define VR_RID VR_PCI_LOIO
168 #define VR_RES SYS_RES_MEMORY
169 #define VR_RID VR_PCI_LOMEM
172 static device_method_t vr_methods[] = {
173 /* Device interface */
174 DEVMETHOD(device_probe, vr_probe),
175 DEVMETHOD(device_attach, vr_attach),
176 DEVMETHOD(device_detach, vr_detach),
177 DEVMETHOD(device_shutdown, vr_shutdown),
180 DEVMETHOD(bus_print_child, bus_generic_print_child),
181 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
184 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
185 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
186 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
191 static driver_t vr_driver = {
194 sizeof(struct vr_softc)
197 static devclass_t vr_devclass;
199 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0);
200 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
202 #define VR_SETBIT(sc, reg, x) \
203 CSR_WRITE_1(sc, reg, \
204 CSR_READ_1(sc, reg) | x)
206 #define VR_CLRBIT(sc, reg, x) \
207 CSR_WRITE_1(sc, reg, \
208 CSR_READ_1(sc, reg) & ~x)
210 #define VR_SETBIT16(sc, reg, x) \
211 CSR_WRITE_2(sc, reg, \
212 CSR_READ_2(sc, reg) | x)
214 #define VR_CLRBIT16(sc, reg, x) \
215 CSR_WRITE_2(sc, reg, \
216 CSR_READ_2(sc, reg) & ~x)
218 #define VR_SETBIT32(sc, reg, x) \
219 CSR_WRITE_4(sc, reg, \
220 CSR_READ_4(sc, reg) | x)
222 #define VR_CLRBIT32(sc, reg, x) \
223 CSR_WRITE_4(sc, reg, \
224 CSR_READ_4(sc, reg) & ~x)
227 CSR_WRITE_1(sc, VR_MIICMD, \
228 CSR_READ_1(sc, VR_MIICMD) | x)
231 CSR_WRITE_1(sc, VR_MIICMD, \
232 CSR_READ_1(sc, VR_MIICMD) & ~x)
235 * Sync the PHYs by setting data bit and strobing the clock 32 times.
237 static void vr_mii_sync(sc)
242 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
244 for (i = 0; i < 32; i++) {
245 SIO_SET(VR_MIICMD_CLK);
247 SIO_CLR(VR_MIICMD_CLK);
255 * Clock a series of bits through the MII.
257 static void vr_mii_send(sc, bits, cnt)
264 SIO_CLR(VR_MIICMD_CLK);
266 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
268 SIO_SET(VR_MIICMD_DATAIN);
270 SIO_CLR(VR_MIICMD_DATAIN);
273 SIO_CLR(VR_MIICMD_CLK);
275 SIO_SET(VR_MIICMD_CLK);
280 * Read an PHY register through the MII.
282 static int vr_mii_readreg(sc, frame)
284 struct vr_mii_frame *frame;
292 * Set up frame for RX.
294 frame->mii_stdelim = VR_MII_STARTDELIM;
295 frame->mii_opcode = VR_MII_READOP;
296 frame->mii_turnaround = 0;
299 CSR_WRITE_1(sc, VR_MIICMD, 0);
300 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
305 SIO_SET(VR_MIICMD_DIR);
310 * Send command/address info.
312 vr_mii_send(sc, frame->mii_stdelim, 2);
313 vr_mii_send(sc, frame->mii_opcode, 2);
314 vr_mii_send(sc, frame->mii_phyaddr, 5);
315 vr_mii_send(sc, frame->mii_regaddr, 5);
318 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
320 SIO_SET(VR_MIICMD_CLK);
324 SIO_CLR(VR_MIICMD_DIR);
327 SIO_CLR(VR_MIICMD_CLK);
329 SIO_SET(VR_MIICMD_CLK);
331 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
334 * Now try reading data bits. If the ack failed, we still
335 * need to clock through 16 cycles to keep the PHY(s) in sync.
338 for(i = 0; i < 16; i++) {
339 SIO_CLR(VR_MIICMD_CLK);
341 SIO_SET(VR_MIICMD_CLK);
347 for (i = 0x8000; i; i >>= 1) {
348 SIO_CLR(VR_MIICMD_CLK);
351 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
352 frame->mii_data |= i;
355 SIO_SET(VR_MIICMD_CLK);
361 SIO_CLR(VR_MIICMD_CLK);
363 SIO_SET(VR_MIICMD_CLK);
374 * Write to a PHY register through the MII.
376 static int vr_mii_writereg(sc, frame)
378 struct vr_mii_frame *frame;
383 CSR_WRITE_1(sc, VR_MIICMD, 0);
384 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
387 * Set up frame for TX.
390 frame->mii_stdelim = VR_MII_STARTDELIM;
391 frame->mii_opcode = VR_MII_WRITEOP;
392 frame->mii_turnaround = VR_MII_TURNAROUND;
395 * Turn on data output.
397 SIO_SET(VR_MIICMD_DIR);
401 vr_mii_send(sc, frame->mii_stdelim, 2);
402 vr_mii_send(sc, frame->mii_opcode, 2);
403 vr_mii_send(sc, frame->mii_phyaddr, 5);
404 vr_mii_send(sc, frame->mii_regaddr, 5);
405 vr_mii_send(sc, frame->mii_turnaround, 2);
406 vr_mii_send(sc, frame->mii_data, 16);
409 SIO_SET(VR_MIICMD_CLK);
411 SIO_CLR(VR_MIICMD_CLK);
417 SIO_CLR(VR_MIICMD_DIR);
424 static int vr_miibus_readreg(dev, phy, reg)
429 struct vr_mii_frame frame;
431 sc = device_get_softc(dev);
432 bzero((char *)&frame, sizeof(frame));
434 frame.mii_phyaddr = phy;
435 frame.mii_regaddr = reg;
436 vr_mii_readreg(sc, &frame);
438 return(frame.mii_data);
441 static int vr_miibus_writereg(dev, phy, reg, data)
443 u_int16_t phy, reg, data;
446 struct vr_mii_frame frame;
448 sc = device_get_softc(dev);
449 bzero((char *)&frame, sizeof(frame));
451 frame.mii_phyaddr = phy;
452 frame.mii_regaddr = reg;
453 frame.mii_data = data;
455 vr_mii_writereg(sc, &frame);
460 static void vr_miibus_statchg(dev)
464 struct mii_data *mii;
466 sc = device_get_softc(dev);
468 mii = device_get_softc(sc->vr_miibus);
469 vr_setcfg(sc, mii->mii_media_active);
476 * Calculate CRC of a multicast group address, return the lower 6 bits.
478 static u_int8_t vr_calchash(addr)
481 u_int32_t crc, carry;
485 /* Compute CRC for the address value. */
486 crc = 0xFFFFFFFF; /* initial value */
488 for (i = 0; i < 6; i++) {
490 for (j = 0; j < 8; j++) {
491 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
495 crc = (crc ^ 0x04c11db6) | carry;
499 /* return the filter bit position */
500 return((crc >> 26) & 0x0000003F);
504 * Program the 64-bit multicast hash filter.
506 static void vr_setmulti(sc)
511 u_int32_t hashes[2] = { 0, 0 };
512 struct ifmultiaddr *ifma;
516 ifp = &sc->arpcom.ac_if;
518 rxfilt = CSR_READ_1(sc, VR_RXCFG);
520 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
521 rxfilt |= VR_RXCFG_RX_MULTI;
522 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
523 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
524 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
528 /* first, zot all the existing hash bits */
529 CSR_WRITE_4(sc, VR_MAR0, 0);
530 CSR_WRITE_4(sc, VR_MAR1, 0);
532 /* now program new ones */
533 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
534 if (ifma->ifma_addr->sa_family != AF_LINK)
536 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
538 hashes[0] |= (1 << h);
540 hashes[1] |= (1 << (h - 32));
545 rxfilt |= VR_RXCFG_RX_MULTI;
547 rxfilt &= ~VR_RXCFG_RX_MULTI;
549 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
550 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
551 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
557 * In order to fiddle with the
558 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
559 * first have to put the transmit and/or receive logic in the idle state.
561 static void vr_setcfg(sc, media)
567 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
569 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
572 if ((media & IFM_GMASK) == IFM_FDX)
573 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
575 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
578 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
583 static void vr_reset(sc)
588 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
590 for (i = 0; i < VR_TIMEOUT; i++) {
592 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
596 printf("vr%d: reset never completed!\n", sc->vr_unit);
598 /* Wait a little while for the chip to get its brains in order. */
605 * Probe for a VIA Rhine chip. Check the PCI vendor and device
606 * IDs against our list and return a device name if we find a match.
608 static int vr_probe(dev)
615 while(t->vr_name != NULL) {
616 if ((pci_get_vendor(dev) == t->vr_vid) &&
617 (pci_get_device(dev) == t->vr_did)) {
618 device_set_desc(dev, t->vr_name);
628 * Attach the interface. Allocate softc structures, do ifmedia
629 * setup and ethernet/BPF attach.
631 static int vr_attach(dev)
635 u_char eaddr[ETHER_ADDR_LEN];
639 int unit, error = 0, rid;
641 sc = device_get_softc(dev);
642 unit = device_get_unit(dev);
643 bzero(sc, sizeof(struct vr_softc *));
645 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
649 * Handle power management nonsense.
652 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF;
653 if (command == 0x01) {
655 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4);
656 if (command & VR_PSTATE_MASK) {
657 u_int32_t iobase, membase, irq;
659 /* Save important PCI config data. */
660 iobase = pci_read_config(dev, VR_PCI_LOIO, 4);
661 membase = pci_read_config(dev, VR_PCI_LOMEM, 4);
662 irq = pci_read_config(dev, VR_PCI_INTLINE, 4);
664 /* Reset the power state. */
665 printf("vr%d: chip is in D%d power mode "
666 "-- setting to D0\n", unit, command & VR_PSTATE_MASK);
667 command &= 0xFFFFFFFC;
668 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4);
670 /* Restore PCI config data. */
671 pci_write_config(dev, VR_PCI_LOIO, iobase, 4);
672 pci_write_config(dev, VR_PCI_LOMEM, membase, 4);
673 pci_write_config(dev, VR_PCI_INTLINE, irq, 4);
678 * Map control/status registers.
680 command = pci_read_config(dev, PCIR_COMMAND, 4);
681 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
682 pci_write_config(dev, PCIR_COMMAND, command, 4);
683 command = pci_read_config(dev, PCIR_COMMAND, 4);
686 if (!(command & PCIM_CMD_PORTEN)) {
687 printf("vr%d: failed to enable I/O ports!\n", unit);
692 if (!(command & PCIM_CMD_MEMEN)) {
693 printf("vr%d: failed to enable memory mapping!\n", unit);
699 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid,
700 0, ~0, 1, RF_ACTIVE);
702 if (sc->vr_res == NULL) {
703 printf("vr%d: couldn't map ports/memory\n", unit);
708 sc->vr_btag = rman_get_bustag(sc->vr_res);
709 sc->vr_bhandle = rman_get_bushandle(sc->vr_res);
711 /* Allocate interrupt */
713 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
714 RF_SHAREABLE | RF_ACTIVE);
716 if (sc->vr_irq == NULL) {
717 printf("vr%d: couldn't map interrupt\n", unit);
718 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
723 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET,
724 vr_intr, sc, &sc->vr_intrhand);
727 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
728 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
729 printf("vr%d: couldn't set up irq\n", unit);
733 /* Reset the adapter. */
737 * Get station address. The way the Rhine chips work,
738 * you're not allowed to directly access the EEPROM once
739 * they've been programmed a special way. Consequently,
740 * we need to read the node address from the PAR0 and PAR1
743 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
745 for (i = 0; i < ETHER_ADDR_LEN; i++)
746 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
749 * A Rhine chip was detected. Inform the world.
751 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":");
754 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
756 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF,
757 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
759 if (sc->vr_ldata == NULL) {
760 printf("vr%d: no memory for list buffers!\n", unit);
761 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
762 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
763 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
768 bzero(sc->vr_ldata, sizeof(struct vr_list_data));
770 ifp = &sc->arpcom.ac_if;
774 ifp->if_mtu = ETHERMTU;
775 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
776 ifp->if_ioctl = vr_ioctl;
777 ifp->if_output = ether_output;
778 ifp->if_start = vr_start;
779 ifp->if_watchdog = vr_watchdog;
780 ifp->if_init = vr_init;
781 ifp->if_baudrate = 10000000;
782 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1;
787 if (mii_phy_probe(dev, &sc->vr_miibus,
788 vr_ifmedia_upd, vr_ifmedia_sts)) {
789 printf("vr%d: MII without any phy!\n", sc->vr_unit);
790 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
791 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
792 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
793 contigfree(sc->vr_ldata,
794 sizeof(struct vr_list_data), M_DEVBUF);
799 callout_handle_init(&sc->vr_stat_ch);
802 * Call MI attach routine.
804 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
810 mtx_destroy(&sc->vr_mtx);
815 static int vr_detach(dev)
821 sc = device_get_softc(dev);
823 ifp = &sc->arpcom.ac_if;
826 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
828 bus_generic_detach(dev);
829 device_delete_child(dev, sc->vr_miibus);
831 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
832 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
833 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res);
835 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF);
838 mtx_destroy(&sc->vr_mtx);
844 * Initialize the transmit descriptors.
846 static int vr_list_tx_init(sc)
849 struct vr_chain_data *cd;
850 struct vr_list_data *ld;
855 for (i = 0; i < VR_TX_LIST_CNT; i++) {
856 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
857 if (i == (VR_TX_LIST_CNT - 1))
858 cd->vr_tx_chain[i].vr_nextdesc =
861 cd->vr_tx_chain[i].vr_nextdesc =
862 &cd->vr_tx_chain[i + 1];
865 cd->vr_tx_free = &cd->vr_tx_chain[0];
866 cd->vr_tx_tail = cd->vr_tx_head = NULL;
873 * Initialize the RX descriptors and allocate mbufs for them. Note that
874 * we arrange the descriptors in a closed ring, so that the last descriptor
875 * points back to the first.
877 static int vr_list_rx_init(sc)
880 struct vr_chain_data *cd;
881 struct vr_list_data *ld;
887 for (i = 0; i < VR_RX_LIST_CNT; i++) {
888 cd->vr_rx_chain[i].vr_ptr =
889 (struct vr_desc *)&ld->vr_rx_list[i];
890 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS)
892 if (i == (VR_RX_LIST_CNT - 1)) {
893 cd->vr_rx_chain[i].vr_nextdesc =
895 ld->vr_rx_list[i].vr_next =
896 vtophys(&ld->vr_rx_list[0]);
898 cd->vr_rx_chain[i].vr_nextdesc =
899 &cd->vr_rx_chain[i + 1];
900 ld->vr_rx_list[i].vr_next =
901 vtophys(&ld->vr_rx_list[i + 1]);
905 cd->vr_rx_head = &cd->vr_rx_chain[0];
911 * Initialize an RX descriptor and attach an MBUF cluster.
912 * Note: the length fields are only 11 bits wide, which means the
913 * largest size we can specify is 2047. This is important because
914 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
915 * overflow the field and make a mess.
917 static int vr_newbuf(sc, c, m)
919 struct vr_chain_onefrag *c;
922 struct mbuf *m_new = NULL;
925 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
927 printf("vr%d: no memory for rx list "
928 "-- packet dropped!\n", sc->vr_unit);
932 MCLGET(m_new, M_DONTWAIT);
933 if (!(m_new->m_flags & M_EXT)) {
934 printf("vr%d: no memory for rx list "
935 "-- packet dropped!\n", sc->vr_unit);
939 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
942 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
943 m_new->m_data = m_new->m_ext.ext_buf;
946 m_adj(m_new, sizeof(u_int64_t));
949 c->vr_ptr->vr_status = VR_RXSTAT;
950 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t));
951 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN;
957 * A frame has been uploaded: pass the resulting mbuf chain up to
958 * the higher level protocols.
960 static void vr_rxeof(sc)
963 struct ether_header *eh;
966 struct vr_chain_onefrag *cur_rx;
970 ifp = &sc->arpcom.ac_if;
972 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) &
974 struct mbuf *m0 = NULL;
976 cur_rx = sc->vr_cdata.vr_rx_head;
977 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
981 * If an error occurs, update stats, clear the
982 * status word and leave the mbuf cluster in place:
983 * it should simply get re-used next time this descriptor
984 * comes up in the ring.
986 if (rxstat & VR_RXSTAT_RXERR) {
988 printf("vr%d: rx error: ", sc->vr_unit);
989 switch(rxstat & 0x000000FF) {
990 case VR_RXSTAT_CRCERR:
991 printf("crc error\n");
993 case VR_RXSTAT_FRAMEALIGNERR:
994 printf("frame alignment error\n");
996 case VR_RXSTAT_FIFOOFLOW:
997 printf("FIFO overflow\n");
999 case VR_RXSTAT_GIANT:
1000 printf("received giant packet\n");
1002 case VR_RXSTAT_RUNT:
1003 printf("received runt packet\n");
1005 case VR_RXSTAT_BUSERR:
1006 printf("system bus error\n");
1008 case VR_RXSTAT_BUFFERR:
1009 printf("rx buffer error\n");
1012 printf("unknown rx error\n");
1015 vr_newbuf(sc, cur_rx, m);
1019 /* No errors; receive the packet. */
1020 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status);
1023 * XXX The VIA Rhine chip includes the CRC with every
1024 * received frame, and there's no way to turn this
1025 * behavior off (at least, I can't find anything in
1026 * the manual that explains how to do it) so we have
1027 * to trim off the CRC manually.
1029 total_len -= ETHER_CRC_LEN;
1031 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1032 total_len + ETHER_ALIGN, 0, ifp, NULL);
1033 vr_newbuf(sc, cur_rx, m);
1038 m_adj(m0, ETHER_ALIGN);
1042 eh = mtod(m, struct ether_header *);
1044 /* Remove header from mbuf and pass it on. */
1045 m_adj(m, sizeof(struct ether_header));
1046 ether_input(ifp, eh, m);
1053 struct vr_softc *sc;
1057 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1058 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1059 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1060 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
1066 * A frame was downloaded to the chip. It's safe for us to clean up
1070 static void vr_txeof(sc)
1071 struct vr_softc *sc;
1073 struct vr_chain *cur_tx;
1076 ifp = &sc->arpcom.ac_if;
1078 /* Clear the timeout timer. */
1082 if (sc->vr_cdata.vr_tx_head == NULL)
1086 * Go through our tx list and free mbufs for those
1087 * frames that have been transmitted.
1089 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) {
1092 cur_tx = sc->vr_cdata.vr_tx_head;
1093 txstat = cur_tx->vr_ptr->vr_status;
1095 if (txstat & VR_TXSTAT_OWN)
1098 if (txstat & VR_TXSTAT_ERRSUM) {
1100 if (txstat & VR_TXSTAT_DEFER)
1101 ifp->if_collisions++;
1102 if (txstat & VR_TXSTAT_LATECOLL)
1103 ifp->if_collisions++;
1106 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3;
1109 if (cur_tx->vr_mbuf != NULL) {
1110 m_freem(cur_tx->vr_mbuf);
1111 cur_tx->vr_mbuf = NULL;
1114 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) {
1115 sc->vr_cdata.vr_tx_head = NULL;
1116 sc->vr_cdata.vr_tx_tail = NULL;
1120 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc;
1127 * TX 'end of channel' interrupt handler.
1129 static void vr_txeoc(sc)
1130 struct vr_softc *sc;
1134 ifp = &sc->arpcom.ac_if;
1138 if (sc->vr_cdata.vr_tx_head == NULL) {
1139 ifp->if_flags &= ~IFF_OACTIVE;
1140 sc->vr_cdata.vr_tx_tail = NULL;
1146 static void vr_tick(xsc)
1149 struct vr_softc *sc;
1150 struct mii_data *mii;
1154 mii = device_get_softc(sc->vr_miibus);
1157 sc->vr_stat_ch = timeout(vr_tick, sc, hz);
1164 static void vr_intr(arg)
1167 struct vr_softc *sc;
1173 ifp = &sc->arpcom.ac_if;
1175 /* Supress unwanted interrupts. */
1176 if (!(ifp->if_flags & IFF_UP)) {
1182 /* Disable interrupts. */
1183 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1187 status = CSR_READ_2(sc, VR_ISR);
1189 CSR_WRITE_2(sc, VR_ISR, status);
1191 if ((status & VR_INTRS) == 0)
1194 if (status & VR_ISR_RX_OK)
1197 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1198 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW) ||
1199 (status & VR_ISR_RX_DROPPED)) {
1204 if (status & VR_ISR_TX_OK) {
1209 if ((status & VR_ISR_TX_UNDERRUN)||(status & VR_ISR_TX_ABRT)){
1212 if (sc->vr_cdata.vr_tx_head != NULL) {
1213 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON);
1214 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO);
1218 if (status & VR_ISR_BUSERR) {
1224 /* Re-enable interrupts. */
1225 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1227 if (ifp->if_snd.ifq_head != NULL) {
1237 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1238 * pointers to the fragment pointers.
1240 static int vr_encap(sc, c, m_head)
1241 struct vr_softc *sc;
1243 struct mbuf *m_head;
1246 struct vr_desc *f = NULL;
1254 * The VIA Rhine wants packet buffers to be longword
1255 * aligned, but very often our mbufs aren't. Rather than
1256 * waste time trying to decide when to copy and when not
1257 * to copy, just do it all the time.
1260 struct mbuf *m_new = NULL;
1262 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1263 if (m_new == NULL) {
1264 printf("vr%d: no memory for tx list\n", sc->vr_unit);
1267 if (m_head->m_pkthdr.len > MHLEN) {
1268 MCLGET(m_new, M_DONTWAIT);
1269 if (!(m_new->m_flags & M_EXT)) {
1271 printf("vr%d: no memory for tx list\n",
1276 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1277 mtod(m_new, caddr_t));
1278 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1282 * The Rhine chip doesn't auto-pad, so we have to make
1283 * sure to pad short frames out to the minimum frame length
1286 if (m_head->m_len < VR_MIN_FRAMELEN) {
1287 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len;
1288 m_new->m_len = m_new->m_pkthdr.len;
1291 f->vr_data = vtophys(mtod(m_new, caddr_t));
1292 f->vr_ctl = total_len = m_new->m_len;
1293 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG;
1298 c->vr_mbuf = m_head;
1299 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT;
1300 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr);
1306 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1307 * to the mbuf data regions directly in the transmit lists. We also save a
1308 * copy of the pointers since the transmit list fragment pointers are
1309 * physical addresses.
1312 static void vr_start(ifp)
1315 struct vr_softc *sc;
1316 struct mbuf *m_head = NULL;
1317 struct vr_chain *cur_tx = NULL, *start_tx;
1322 if (ifp->if_flags & IFF_OACTIVE) {
1328 * Check for an available queue slot. If there are none,
1331 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) {
1332 ifp->if_flags |= IFF_OACTIVE;
1336 start_tx = sc->vr_cdata.vr_tx_free;
1338 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) {
1339 IF_DEQUEUE(&ifp->if_snd, m_head);
1343 /* Pick a descriptor off the free list. */
1344 cur_tx = sc->vr_cdata.vr_tx_free;
1345 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc;
1347 /* Pack the data into the descriptor. */
1348 if (vr_encap(sc, cur_tx, m_head)) {
1349 IF_PREPEND(&ifp->if_snd, m_head);
1350 ifp->if_flags |= IFF_OACTIVE;
1355 if (cur_tx != start_tx)
1356 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1359 * If there's a BPF listener, bounce a copy of this frame
1363 bpf_mtap(ifp, cur_tx->vr_mbuf);
1365 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN;
1366 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1370 * If there are no frames queued, bail.
1372 if (cur_tx == NULL) {
1377 sc->vr_cdata.vr_tx_tail = cur_tx;
1379 if (sc->vr_cdata.vr_tx_head == NULL)
1380 sc->vr_cdata.vr_tx_head = start_tx;
1383 * Set a timeout in case the chip goes out to lunch.
1391 static void vr_init(xsc)
1394 struct vr_softc *sc = xsc;
1395 struct ifnet *ifp = &sc->arpcom.ac_if;
1396 struct mii_data *mii;
1400 mii = device_get_softc(sc->vr_miibus);
1403 * Cancel pending I/O and free all RX/TX buffers.
1408 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1409 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD);
1411 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1412 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1414 /* Init circular RX list. */
1415 if (vr_list_rx_init(sc) == ENOBUFS) {
1416 printf("vr%d: initialization failed: no "
1417 "memory for rx buffers\n", sc->vr_unit);
1424 * Init tx descriptors.
1426 vr_list_tx_init(sc);
1428 /* If we want promiscuous mode, set the allframes bit. */
1429 if (ifp->if_flags & IFF_PROMISC)
1430 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1432 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1434 /* Set capture broadcast bit to capture broadcast frames. */
1435 if (ifp->if_flags & IFF_BROADCAST)
1436 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1438 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1441 * Program the multicast filter, if necessary.
1446 * Load the address of the RX list.
1448 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr));
1450 /* Enable receiver and transmitter. */
1451 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1452 VR_CMD_TX_ON|VR_CMD_RX_ON|
1455 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0]));
1458 * Enable interrupts.
1460 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1461 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1465 ifp->if_flags |= IFF_RUNNING;
1466 ifp->if_flags &= ~IFF_OACTIVE;
1468 sc->vr_stat_ch = timeout(vr_tick, sc, hz);
1476 * Set media options.
1478 static int vr_ifmedia_upd(ifp)
1481 struct vr_softc *sc;
1485 if (ifp->if_flags & IFF_UP)
1492 * Report current media status.
1494 static void vr_ifmedia_sts(ifp, ifmr)
1496 struct ifmediareq *ifmr;
1498 struct vr_softc *sc;
1499 struct mii_data *mii;
1502 mii = device_get_softc(sc->vr_miibus);
1504 ifmr->ifm_active = mii->mii_media_active;
1505 ifmr->ifm_status = mii->mii_media_status;
1510 static int vr_ioctl(ifp, command, data)
1515 struct vr_softc *sc = ifp->if_softc;
1516 struct ifreq *ifr = (struct ifreq *) data;
1517 struct mii_data *mii;
1526 error = ether_ioctl(ifp, command, data);
1529 if (ifp->if_flags & IFF_UP) {
1532 if (ifp->if_flags & IFF_RUNNING)
1544 mii = device_get_softc(sc->vr_miibus);
1545 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1557 static void vr_watchdog(ifp)
1560 struct vr_softc *sc;
1566 printf("vr%d: watchdog timeout\n", sc->vr_unit);
1572 if (ifp->if_snd.ifq_head != NULL)
1581 * Stop the adapter and free any mbufs allocated to the
1584 static void vr_stop(sc)
1585 struct vr_softc *sc;
1592 ifp = &sc->arpcom.ac_if;
1595 untimeout(vr_tick, sc, sc->vr_stat_ch);
1597 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1598 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1599 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1600 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1601 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1604 * Free data in the RX lists.
1606 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1607 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) {
1608 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf);
1609 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL;
1612 bzero((char *)&sc->vr_ldata->vr_rx_list,
1613 sizeof(sc->vr_ldata->vr_rx_list));
1616 * Free the TX list buffers.
1618 for (i = 0; i < VR_TX_LIST_CNT; i++) {
1619 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) {
1620 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf);
1621 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL;
1625 bzero((char *)&sc->vr_ldata->vr_tx_list,
1626 sizeof(sc->vr_ldata->vr_tx_list));
1628 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1635 * Stop all chip I/O so that the kernel's probe routines don't
1636 * get confused by errant DMAs when rebooting.
1638 static void vr_shutdown(dev)
1641 struct vr_softc *sc;
1643 sc = device_get_softc(dev);