2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * VIA Rhine fast ethernet PCI NIC driver
39 * Supports various network adapters based on the VIA Rhine
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
41 * Datasheets are available at http://www.via.com.tw.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The VIA Rhine controllers are similar in some respects to the
50 * the DEC tulip chips, except less complicated. The controller
51 * uses an MII bus and an external physical layer interface. The
52 * receiver has a one entry perfect filter and a 64-bit hash table
53 * multicast filter. Transmit and receive descriptors are similar
56 * Some Rhine chips has a serious flaw in its transmit DMA mechanism:
57 * transmit buffers must be longword aligned. Unfortunately,
58 * FreeBSD doesn't guarantee that mbufs will be filled in starting
59 * at longword boundaries, so we have to do a buffer copy before
63 #ifdef HAVE_KERNEL_OPTION_HEADERS
64 #include "opt_device_polling.h"
67 #include <sys/param.h>
68 #include <sys/systm.h>
70 #include <sys/endian.h>
71 #include <sys/kernel.h>
72 #include <sys/malloc.h>
74 #include <sys/module.h>
76 #include <sys/socket.h>
77 #include <sys/sockio.h>
78 #include <sys/sysctl.h>
79 #include <sys/taskqueue.h>
83 #include <net/if_var.h>
84 #include <net/ethernet.h>
85 #include <net/if_dl.h>
86 #include <net/if_media.h>
87 #include <net/if_types.h>
88 #include <net/if_vlan_var.h>
90 #include <dev/mii/mii.h>
91 #include <dev/mii/miivar.h>
93 #include <dev/pci/pcireg.h>
94 #include <dev/pci/pcivar.h>
96 #include <machine/bus.h>
98 #include <dev/vr/if_vrreg.h>
100 /* "device miibus" required. See GENERIC if you get errors here. */
101 #include "miibus_if.h"
103 MODULE_DEPEND(vr, pci, 1, 1, 1);
104 MODULE_DEPEND(vr, ether, 1, 1, 1);
105 MODULE_DEPEND(vr, miibus, 1, 1, 1);
107 /* Define to show Rx/Tx error status. */
108 #undef VR_SHOW_ERRORS
109 #define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
112 * Various supported device vendors/types, their names & quirks.
114 #define VR_Q_NEEDALIGN (1<<0)
115 #define VR_Q_CSUM (1<<1)
116 #define VR_Q_CAM (1<<2)
118 static const struct vr_type {
124 { VIA_VENDORID, VIA_DEVICEID_RHINE,
126 "VIA VT3043 Rhine I 10/100BaseTX" },
127 { VIA_VENDORID, VIA_DEVICEID_RHINE_II,
129 "VIA VT86C100A Rhine II 10/100BaseTX" },
130 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2,
132 "VIA VT6102 Rhine II 10/100BaseTX" },
133 { VIA_VENDORID, VIA_DEVICEID_RHINE_III,
135 "VIA VT6105 Rhine III 10/100BaseTX" },
136 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M,
138 "VIA VT6105M Rhine III 10/100BaseTX" },
139 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II,
141 "Delta Electronics Rhine II 10/100BaseTX" },
142 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II,
144 "Addtron Technology Rhine II 10/100BaseTX" },
148 static int vr_probe(device_t);
149 static int vr_attach(device_t);
150 static int vr_detach(device_t);
151 static int vr_shutdown(device_t);
152 static int vr_suspend(device_t);
153 static int vr_resume(device_t);
155 static void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int);
156 static int vr_dma_alloc(struct vr_softc *);
157 static void vr_dma_free(struct vr_softc *);
158 static __inline void vr_discard_rxbuf(struct vr_rxdesc *);
159 static int vr_newbuf(struct vr_softc *, int);
161 #ifndef __NO_STRICT_ALIGNMENT
162 static __inline void vr_fixup_rx(struct mbuf *);
164 static int vr_rxeof(struct vr_softc *);
165 static void vr_txeof(struct vr_softc *);
166 static void vr_tick(void *);
167 static int vr_error(struct vr_softc *, uint16_t);
168 static void vr_tx_underrun(struct vr_softc *);
169 static int vr_intr(void *);
170 static void vr_int_task(void *, int);
171 static void vr_start(struct ifnet *);
172 static void vr_start_locked(struct ifnet *);
173 static int vr_encap(struct vr_softc *, struct mbuf **);
174 static int vr_ioctl(struct ifnet *, u_long, caddr_t);
175 static void vr_init(void *);
176 static void vr_init_locked(struct vr_softc *);
177 static void vr_tx_start(struct vr_softc *);
178 static void vr_rx_start(struct vr_softc *);
179 static int vr_tx_stop(struct vr_softc *);
180 static int vr_rx_stop(struct vr_softc *);
181 static void vr_stop(struct vr_softc *);
182 static void vr_watchdog(struct vr_softc *);
183 static int vr_ifmedia_upd(struct ifnet *);
184 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
186 static int vr_miibus_readreg(device_t, int, int);
187 static int vr_miibus_writereg(device_t, int, int, int);
188 static void vr_miibus_statchg(device_t);
190 static void vr_cam_mask(struct vr_softc *, uint32_t, int);
191 static int vr_cam_data(struct vr_softc *, int, int, uint8_t *);
192 static void vr_set_filter(struct vr_softc *);
193 static void vr_reset(const struct vr_softc *);
194 static int vr_tx_ring_init(struct vr_softc *);
195 static int vr_rx_ring_init(struct vr_softc *);
196 static void vr_setwol(struct vr_softc *);
197 static void vr_clrwol(struct vr_softc *);
198 static int vr_sysctl_stats(SYSCTL_HANDLER_ARGS);
200 static const struct vr_tx_threshold_table {
204 } vr_tx_threshold_tables[] = {
205 { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 },
206 { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 },
207 { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 },
208 { VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 },
209 { VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 },
210 { VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 }
213 static device_method_t vr_methods[] = {
214 /* Device interface */
215 DEVMETHOD(device_probe, vr_probe),
216 DEVMETHOD(device_attach, vr_attach),
217 DEVMETHOD(device_detach, vr_detach),
218 DEVMETHOD(device_shutdown, vr_shutdown),
219 DEVMETHOD(device_suspend, vr_suspend),
220 DEVMETHOD(device_resume, vr_resume),
223 DEVMETHOD(miibus_readreg, vr_miibus_readreg),
224 DEVMETHOD(miibus_writereg, vr_miibus_writereg),
225 DEVMETHOD(miibus_statchg, vr_miibus_statchg),
230 static driver_t vr_driver = {
233 sizeof(struct vr_softc)
236 static devclass_t vr_devclass;
238 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0);
239 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
242 vr_miibus_readreg(device_t dev, int phy, int reg)
247 sc = device_get_softc(dev);
249 /* Set the register address. */
250 CSR_WRITE_1(sc, VR_MIIADDR, reg);
251 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
253 for (i = 0; i < VR_MII_TIMEOUT; i++) {
255 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
258 if (i == VR_MII_TIMEOUT)
259 device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg);
261 return (CSR_READ_2(sc, VR_MIIDATA));
265 vr_miibus_writereg(device_t dev, int phy, int reg, int data)
270 sc = device_get_softc(dev);
272 /* Set the register address and data to write. */
273 CSR_WRITE_1(sc, VR_MIIADDR, reg);
274 CSR_WRITE_2(sc, VR_MIIDATA, data);
275 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
277 for (i = 0; i < VR_MII_TIMEOUT; i++) {
279 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
282 if (i == VR_MII_TIMEOUT)
283 device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy,
290 * In order to fiddle with the
291 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
292 * first have to put the transmit and/or receive logic in the idle state.
295 vr_miibus_statchg(device_t dev)
298 struct mii_data *mii;
301 uint8_t cr0, cr1, fc;
303 sc = device_get_softc(dev);
304 mii = device_get_softc(sc->vr_miibus);
306 if (mii == NULL || ifp == NULL ||
307 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
310 sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE);
311 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
312 (IFM_ACTIVE | IFM_AVALID)) {
313 switch (IFM_SUBTYPE(mii->mii_media_active)) {
316 sc->vr_flags |= VR_F_LINK;
323 if ((sc->vr_flags & VR_F_LINK) != 0) {
324 cr0 = CSR_READ_1(sc, VR_CR0);
325 cr1 = CSR_READ_1(sc, VR_CR1);
326 mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0;
327 lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0;
329 if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) {
330 if (vr_tx_stop(sc) != 0 ||
331 vr_rx_stop(sc) != 0) {
332 device_printf(sc->vr_dev,
333 "%s: Tx/Rx shutdown error -- "
334 "resetting\n", __func__);
335 sc->vr_flags |= VR_F_RESTART;
341 cr1 |= VR_CR1_FULLDUPLEX;
343 cr1 &= ~VR_CR1_FULLDUPLEX;
344 CSR_WRITE_1(sc, VR_CR1, cr1);
347 /* Configure flow-control. */
348 if (sc->vr_revid >= REV_ID_VT6105_A0) {
349 fc = CSR_READ_1(sc, VR_FLOWCR1);
350 fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE);
351 if ((IFM_OPTIONS(mii->mii_media_active) &
352 IFM_ETH_RXPAUSE) != 0)
353 fc |= VR_FLOWCR1_RXPAUSE;
354 if ((IFM_OPTIONS(mii->mii_media_active) &
355 IFM_ETH_TXPAUSE) != 0) {
356 fc |= VR_FLOWCR1_TXPAUSE;
357 sc->vr_flags |= VR_F_TXPAUSE;
359 CSR_WRITE_1(sc, VR_FLOWCR1, fc);
360 } else if (sc->vr_revid >= REV_ID_VT6102_A) {
361 /* No Tx puase capability available for Rhine II. */
362 fc = CSR_READ_1(sc, VR_MISC_CR0);
363 fc &= ~VR_MISCCR0_RXPAUSE;
364 if ((IFM_OPTIONS(mii->mii_media_active) &
365 IFM_ETH_RXPAUSE) != 0)
366 fc |= VR_MISCCR0_RXPAUSE;
367 CSR_WRITE_1(sc, VR_MISC_CR0, fc);
372 if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) {
373 device_printf(sc->vr_dev,
374 "%s: Tx/Rx shutdown error -- resetting\n",
376 sc->vr_flags |= VR_F_RESTART;
383 vr_cam_mask(struct vr_softc *sc, uint32_t mask, int type)
386 if (type == VR_MCAST_CAM)
387 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
389 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
390 CSR_WRITE_4(sc, VR_CAMMASK, mask);
391 CSR_WRITE_1(sc, VR_CAMCTL, 0);
395 vr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac)
399 if (type == VR_MCAST_CAM) {
400 if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL)
402 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST);
404 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN);
406 /* Set CAM entry address. */
407 CSR_WRITE_1(sc, VR_CAMADDR, idx);
408 /* Set CAM entry data. */
409 if (type == VR_MCAST_CAM) {
410 for (i = 0; i < ETHER_ADDR_LEN; i++)
411 CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]);
413 CSR_WRITE_1(sc, VR_VCAM0, mac[0]);
414 CSR_WRITE_1(sc, VR_VCAM1, mac[1]);
417 /* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */
418 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE);
419 for (i = 0; i < VR_TIMEOUT; i++) {
421 if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0)
426 device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n",
428 CSR_WRITE_1(sc, VR_CAMCTL, 0);
430 return (i == VR_TIMEOUT ? ETIMEDOUT : 0);
434 * Program the 64-bit multicast hash filter.
437 vr_set_filter(struct vr_softc *sc)
441 uint32_t hashes[2] = { 0, 0 };
442 struct ifmultiaddr *ifma;
450 rxfilt = CSR_READ_1(sc, VR_RXCFG);
451 rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD |
453 if (ifp->if_flags & IFF_BROADCAST)
454 rxfilt |= VR_RXCFG_RX_BROAD;
455 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
456 rxfilt |= VR_RXCFG_RX_MULTI;
457 if (ifp->if_flags & IFF_PROMISC)
458 rxfilt |= VR_RXCFG_RX_PROMISC;
459 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
460 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
461 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
465 /* Now program new ones. */
469 if ((sc->vr_quirks & VR_Q_CAM) != 0) {
471 * For hardwares that have CAM capability, use
472 * 32 entries multicast perfect filter.
475 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
476 if (ifma->ifma_addr->sa_family != AF_LINK)
478 error = vr_cam_data(sc, VR_MCAST_CAM, mcnt,
479 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
484 cam_mask |= 1 << mcnt;
487 vr_cam_mask(sc, VR_MCAST_CAM, cam_mask);
490 if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) {
492 * If there are too many multicast addresses or
493 * setting multicast CAM filter failed, use hash
494 * table based filtering.
497 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
498 if (ifma->ifma_addr->sa_family != AF_LINK)
500 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
501 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
503 hashes[0] |= (1 << h);
505 hashes[1] |= (1 << (h - 32));
509 if_maddr_runlock(ifp);
512 rxfilt |= VR_RXCFG_RX_MULTI;
514 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
515 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
516 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
520 vr_reset(const struct vr_softc *sc)
524 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */
526 CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET);
527 if (sc->vr_revid < REV_ID_VT6102_A) {
528 /* VT86C100A needs more delay after reset. */
531 for (i = 0; i < VR_TIMEOUT; i++) {
533 if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET))
536 if (i == VR_TIMEOUT) {
537 if (sc->vr_revid < REV_ID_VT6102_A)
538 device_printf(sc->vr_dev, "reset never completed!\n");
540 /* Use newer force reset command. */
541 device_printf(sc->vr_dev,
542 "Using force reset command.\n");
543 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
545 * Wait a little while for the chip to get its brains
555 * Probe for a VIA Rhine chip. Check the PCI vendor and device
556 * IDs against our list and return a match or NULL
558 static const struct vr_type *
559 vr_match(device_t dev)
561 const struct vr_type *t = vr_devs;
563 for (t = vr_devs; t->vr_name != NULL; t++)
564 if ((pci_get_vendor(dev) == t->vr_vid) &&
565 (pci_get_device(dev) == t->vr_did))
571 * Probe for a VIA Rhine chip. Check the PCI vendor and device
572 * IDs against our list and return a device name if we find a match.
575 vr_probe(device_t dev)
577 const struct vr_type *t;
581 device_set_desc(dev, t->vr_name);
582 return (BUS_PROBE_DEFAULT);
588 * Attach the interface. Allocate softc structures, do ifmedia
589 * setup and ethernet/BPF attach.
592 vr_attach(device_t dev)
596 const struct vr_type *t;
597 uint8_t eaddr[ETHER_ADDR_LEN];
601 sc = device_get_softc(dev);
604 KASSERT(t != NULL, ("Lost if_vr device match"));
605 sc->vr_quirks = t->vr_quirks;
606 device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks);
608 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
610 callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0);
611 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
612 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
613 OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
614 vr_sysctl_stats, "I", "Statistics");
619 * Map control/status registers.
621 pci_enable_busmaster(dev);
622 sc->vr_revid = pci_get_revid(dev);
623 device_printf(dev, "Revision: 0x%x\n", sc->vr_revid);
625 sc->vr_res_id = PCIR_BAR(0);
626 sc->vr_res_type = SYS_RES_IOPORT;
627 sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type,
628 &sc->vr_res_id, RF_ACTIVE);
629 if (sc->vr_res == NULL) {
630 device_printf(dev, "couldn't map ports\n");
635 /* Allocate interrupt. */
637 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
638 RF_SHAREABLE | RF_ACTIVE);
640 if (sc->vr_irq == NULL) {
641 device_printf(dev, "couldn't map interrupt\n");
646 /* Allocate ifnet structure. */
647 ifp = sc->vr_ifp = if_alloc(IFT_ETHER);
649 device_printf(dev, "couldn't allocate ifnet structure\n");
654 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
655 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
656 ifp->if_ioctl = vr_ioctl;
657 ifp->if_start = vr_start;
658 ifp->if_init = vr_init;
659 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1);
660 ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1;
661 IFQ_SET_READY(&ifp->if_snd);
663 TASK_INIT(&sc->vr_inttask, 0, vr_int_task, sc);
665 /* Configure Tx FIFO threshold. */
666 sc->vr_txthresh = VR_TXTHRESH_MIN;
667 if (sc->vr_revid < REV_ID_VT6105_A0) {
669 * Use store and forward mode for Rhine I/II.
670 * Otherwise they produce a lot of Tx underruns and
671 * it would take a while to get working FIFO threshold
674 sc->vr_txthresh = VR_TXTHRESH_MAX;
676 if ((sc->vr_quirks & VR_Q_CSUM) != 0) {
677 ifp->if_hwassist = VR_CSUM_FEATURES;
678 ifp->if_capabilities |= IFCAP_HWCSUM;
680 * To update checksum field the hardware may need to
681 * store entire frames into FIFO before transmitting.
683 sc->vr_txthresh = VR_TXTHRESH_MAX;
686 if (sc->vr_revid >= REV_ID_VT6102_A &&
687 pci_find_cap(dev, PCIY_PMG, &pmc) == 0)
688 ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC;
690 /* Rhine supports oversized VLAN frame. */
691 ifp->if_capabilities |= IFCAP_VLAN_MTU;
692 ifp->if_capenable = ifp->if_capabilities;
693 #ifdef DEVICE_POLLING
694 ifp->if_capabilities |= IFCAP_POLLING;
698 * Windows may put the chip in suspend mode when it
699 * shuts down. Be sure to kick it in the head to wake it
702 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0)
703 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
706 * Get station address. The way the Rhine chips work,
707 * you're not allowed to directly access the EEPROM once
708 * they've been programmed a special way. Consequently,
709 * we need to read the node address from the PAR0 and PAR1
711 * Reloading EEPROM also overwrites VR_CFGA, VR_CFGB,
712 * VR_CFGC and VR_CFGD such that memory mapped IO configured
713 * by driver is reset to default state.
715 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
716 for (i = VR_TIMEOUT; i > 0; i--) {
718 if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0)
722 device_printf(dev, "Reloading EEPROM timeout!\n");
723 for (i = 0; i < ETHER_ADDR_LEN; i++)
724 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
726 /* Reset the adapter. */
728 /* Ack intr & disable further interrupts. */
729 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
730 CSR_WRITE_2(sc, VR_IMR, 0);
731 if (sc->vr_revid >= REV_ID_VT6102_A)
732 CSR_WRITE_2(sc, VR_MII_IMR, 0);
734 if (sc->vr_revid < REV_ID_VT6102_A) {
735 pci_write_config(dev, VR_PCI_MODE2,
736 pci_read_config(dev, VR_PCI_MODE2, 1) |
737 VR_MODE2_MODE10T, 1);
739 /* Report error instead of retrying forever. */
740 pci_write_config(dev, VR_PCI_MODE2,
741 pci_read_config(dev, VR_PCI_MODE2, 1) |
742 VR_MODE2_PCEROPT, 1);
743 /* Detect MII coding error. */
744 pci_write_config(dev, VR_PCI_MODE3,
745 pci_read_config(dev, VR_PCI_MODE3, 1) |
747 if (sc->vr_revid >= REV_ID_VT6105_LOM &&
748 sc->vr_revid < REV_ID_VT6105M_A0)
749 pci_write_config(dev, VR_PCI_MODE2,
750 pci_read_config(dev, VR_PCI_MODE2, 1) |
751 VR_MODE2_MODE10T, 1);
752 /* Enable Memory-Read-Multiple. */
753 if (sc->vr_revid >= REV_ID_VT6107_A1 &&
754 sc->vr_revid < REV_ID_VT6105M_A0)
755 pci_write_config(dev, VR_PCI_MODE2,
756 pci_read_config(dev, VR_PCI_MODE2, 1) |
759 /* Disable MII AUTOPOLL. */
760 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
762 if (vr_dma_alloc(sc) != 0) {
768 if (sc->vr_revid >= REV_ID_VT6105_A0)
771 phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK;
772 error = mii_attach(dev, &sc->vr_miibus, ifp, vr_ifmedia_upd,
773 vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
774 sc->vr_revid >= REV_ID_VT6102_A ? MIIF_DOPAUSE : 0);
776 device_printf(dev, "attaching PHYs failed\n");
780 /* Call MI attach routine. */
781 ether_ifattach(ifp, eaddr);
783 * Tell the upper layer(s) we support long frames.
784 * Must appear after the call to ether_ifattach() because
785 * ether_ifattach() sets ifi_hdrlen to the default value.
787 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
789 /* Hook interrupt last to avoid having to lock softc. */
790 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE,
791 vr_intr, NULL, sc, &sc->vr_intrhand);
794 device_printf(dev, "couldn't set up irq\n");
807 * Shutdown hardware and free up resources. This can be called any
808 * time after the mutex has been initialized. It is called in both
809 * the error case in attach and the normal detach case so it needs
810 * to be careful about only freeing resources that have actually been
814 vr_detach(device_t dev)
816 struct vr_softc *sc = device_get_softc(dev);
817 struct ifnet *ifp = sc->vr_ifp;
819 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized"));
821 #ifdef DEVICE_POLLING
822 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING)
823 ether_poll_deregister(ifp);
826 /* These should only be active if attach succeeded. */
827 if (device_is_attached(dev)) {
829 sc->vr_flags |= VR_F_DETACHED;
832 callout_drain(&sc->vr_stat_callout);
833 taskqueue_drain(taskqueue_fast, &sc->vr_inttask);
837 device_delete_child(dev, sc->vr_miibus);
838 bus_generic_detach(dev);
841 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand);
843 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq);
845 bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id,
853 mtx_destroy(&sc->vr_mtx);
858 struct vr_dmamap_arg {
859 bus_addr_t vr_busaddr;
863 vr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
865 struct vr_dmamap_arg *ctx;
870 ctx->vr_busaddr = segs[0].ds_addr;
874 vr_dma_alloc(struct vr_softc *sc)
876 struct vr_dmamap_arg ctx;
877 struct vr_txdesc *txd;
878 struct vr_rxdesc *rxd;
879 bus_size_t tx_alignment;
882 /* Create parent DMA tag. */
883 error = bus_dma_tag_create(
884 bus_get_dma_tag(sc->vr_dev), /* parent */
885 1, 0, /* alignment, boundary */
886 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
887 BUS_SPACE_MAXADDR, /* highaddr */
888 NULL, NULL, /* filter, filterarg */
889 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
891 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
893 NULL, NULL, /* lockfunc, lockarg */
894 &sc->vr_cdata.vr_parent_tag);
896 device_printf(sc->vr_dev, "failed to create parent DMA tag\n");
899 /* Create tag for Tx ring. */
900 error = bus_dma_tag_create(
901 sc->vr_cdata.vr_parent_tag, /* parent */
902 VR_RING_ALIGN, 0, /* alignment, boundary */
903 BUS_SPACE_MAXADDR, /* lowaddr */
904 BUS_SPACE_MAXADDR, /* highaddr */
905 NULL, NULL, /* filter, filterarg */
906 VR_TX_RING_SIZE, /* maxsize */
908 VR_TX_RING_SIZE, /* maxsegsize */
910 NULL, NULL, /* lockfunc, lockarg */
911 &sc->vr_cdata.vr_tx_ring_tag);
913 device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n");
917 /* Create tag for Rx ring. */
918 error = bus_dma_tag_create(
919 sc->vr_cdata.vr_parent_tag, /* parent */
920 VR_RING_ALIGN, 0, /* alignment, boundary */
921 BUS_SPACE_MAXADDR, /* lowaddr */
922 BUS_SPACE_MAXADDR, /* highaddr */
923 NULL, NULL, /* filter, filterarg */
924 VR_RX_RING_SIZE, /* maxsize */
926 VR_RX_RING_SIZE, /* maxsegsize */
928 NULL, NULL, /* lockfunc, lockarg */
929 &sc->vr_cdata.vr_rx_ring_tag);
931 device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n");
935 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0)
936 tx_alignment = sizeof(uint32_t);
939 /* Create tag for Tx buffers. */
940 error = bus_dma_tag_create(
941 sc->vr_cdata.vr_parent_tag, /* parent */
942 tx_alignment, 0, /* alignment, boundary */
943 BUS_SPACE_MAXADDR, /* lowaddr */
944 BUS_SPACE_MAXADDR, /* highaddr */
945 NULL, NULL, /* filter, filterarg */
946 MCLBYTES * VR_MAXFRAGS, /* maxsize */
947 VR_MAXFRAGS, /* nsegments */
948 MCLBYTES, /* maxsegsize */
950 NULL, NULL, /* lockfunc, lockarg */
951 &sc->vr_cdata.vr_tx_tag);
953 device_printf(sc->vr_dev, "failed to create Tx DMA tag\n");
957 /* Create tag for Rx buffers. */
958 error = bus_dma_tag_create(
959 sc->vr_cdata.vr_parent_tag, /* parent */
960 VR_RX_ALIGN, 0, /* alignment, boundary */
961 BUS_SPACE_MAXADDR, /* lowaddr */
962 BUS_SPACE_MAXADDR, /* highaddr */
963 NULL, NULL, /* filter, filterarg */
964 MCLBYTES, /* maxsize */
966 MCLBYTES, /* maxsegsize */
968 NULL, NULL, /* lockfunc, lockarg */
969 &sc->vr_cdata.vr_rx_tag);
971 device_printf(sc->vr_dev, "failed to create Rx DMA tag\n");
975 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
976 error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag,
977 (void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK |
978 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map);
980 device_printf(sc->vr_dev,
981 "failed to allocate DMA'able memory for Tx ring\n");
986 error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag,
987 sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring,
988 VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0);
989 if (error != 0 || ctx.vr_busaddr == 0) {
990 device_printf(sc->vr_dev,
991 "failed to load DMA'able memory for Tx ring\n");
994 sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr;
996 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
997 error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag,
998 (void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK |
999 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map);
1001 device_printf(sc->vr_dev,
1002 "failed to allocate DMA'able memory for Rx ring\n");
1007 error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag,
1008 sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring,
1009 VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0);
1010 if (error != 0 || ctx.vr_busaddr == 0) {
1011 device_printf(sc->vr_dev,
1012 "failed to load DMA'able memory for Rx ring\n");
1015 sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr;
1017 /* Create DMA maps for Tx buffers. */
1018 for (i = 0; i < VR_TX_RING_CNT; i++) {
1019 txd = &sc->vr_cdata.vr_txdesc[i];
1021 txd->tx_dmamap = NULL;
1022 error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0,
1025 device_printf(sc->vr_dev,
1026 "failed to create Tx dmamap\n");
1030 /* Create DMA maps for Rx buffers. */
1031 if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0,
1032 &sc->vr_cdata.vr_rx_sparemap)) != 0) {
1033 device_printf(sc->vr_dev,
1034 "failed to create spare Rx dmamap\n");
1037 for (i = 0; i < VR_RX_RING_CNT; i++) {
1038 rxd = &sc->vr_cdata.vr_rxdesc[i];
1040 rxd->rx_dmamap = NULL;
1041 error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0,
1044 device_printf(sc->vr_dev,
1045 "failed to create Rx dmamap\n");
1055 vr_dma_free(struct vr_softc *sc)
1057 struct vr_txdesc *txd;
1058 struct vr_rxdesc *rxd;
1062 if (sc->vr_cdata.vr_tx_ring_tag) {
1063 if (sc->vr_rdata.vr_tx_ring_paddr)
1064 bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag,
1065 sc->vr_cdata.vr_tx_ring_map);
1066 if (sc->vr_rdata.vr_tx_ring)
1067 bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag,
1068 sc->vr_rdata.vr_tx_ring,
1069 sc->vr_cdata.vr_tx_ring_map);
1070 sc->vr_rdata.vr_tx_ring = NULL;
1071 sc->vr_rdata.vr_tx_ring_paddr = 0;
1072 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag);
1073 sc->vr_cdata.vr_tx_ring_tag = NULL;
1076 if (sc->vr_cdata.vr_rx_ring_tag) {
1077 if (sc->vr_rdata.vr_rx_ring_paddr)
1078 bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag,
1079 sc->vr_cdata.vr_rx_ring_map);
1080 if (sc->vr_rdata.vr_rx_ring)
1081 bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag,
1082 sc->vr_rdata.vr_rx_ring,
1083 sc->vr_cdata.vr_rx_ring_map);
1084 sc->vr_rdata.vr_rx_ring = NULL;
1085 sc->vr_rdata.vr_rx_ring_paddr = 0;
1086 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag);
1087 sc->vr_cdata.vr_rx_ring_tag = NULL;
1090 if (sc->vr_cdata.vr_tx_tag) {
1091 for (i = 0; i < VR_TX_RING_CNT; i++) {
1092 txd = &sc->vr_cdata.vr_txdesc[i];
1093 if (txd->tx_dmamap) {
1094 bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag,
1096 txd->tx_dmamap = NULL;
1099 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag);
1100 sc->vr_cdata.vr_tx_tag = NULL;
1103 if (sc->vr_cdata.vr_rx_tag) {
1104 for (i = 0; i < VR_RX_RING_CNT; i++) {
1105 rxd = &sc->vr_cdata.vr_rxdesc[i];
1106 if (rxd->rx_dmamap) {
1107 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag,
1109 rxd->rx_dmamap = NULL;
1112 if (sc->vr_cdata.vr_rx_sparemap) {
1113 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag,
1114 sc->vr_cdata.vr_rx_sparemap);
1115 sc->vr_cdata.vr_rx_sparemap = 0;
1117 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag);
1118 sc->vr_cdata.vr_rx_tag = NULL;
1121 if (sc->vr_cdata.vr_parent_tag) {
1122 bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag);
1123 sc->vr_cdata.vr_parent_tag = NULL;
1128 * Initialize the transmit descriptors.
1131 vr_tx_ring_init(struct vr_softc *sc)
1133 struct vr_ring_data *rd;
1134 struct vr_txdesc *txd;
1138 sc->vr_cdata.vr_tx_prod = 0;
1139 sc->vr_cdata.vr_tx_cons = 0;
1140 sc->vr_cdata.vr_tx_cnt = 0;
1141 sc->vr_cdata.vr_tx_pkts = 0;
1144 bzero(rd->vr_tx_ring, VR_TX_RING_SIZE);
1145 for (i = 0; i < VR_TX_RING_CNT; i++) {
1146 if (i == VR_TX_RING_CNT - 1)
1147 addr = VR_TX_RING_ADDR(sc, 0);
1149 addr = VR_TX_RING_ADDR(sc, i + 1);
1150 rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr));
1151 txd = &sc->vr_cdata.vr_txdesc[i];
1155 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1156 sc->vr_cdata.vr_tx_ring_map,
1157 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1163 * Initialize the RX descriptors and allocate mbufs for them. Note that
1164 * we arrange the descriptors in a closed ring, so that the last descriptor
1165 * points back to the first.
1168 vr_rx_ring_init(struct vr_softc *sc)
1170 struct vr_ring_data *rd;
1171 struct vr_rxdesc *rxd;
1175 sc->vr_cdata.vr_rx_cons = 0;
1178 bzero(rd->vr_rx_ring, VR_RX_RING_SIZE);
1179 for (i = 0; i < VR_RX_RING_CNT; i++) {
1180 rxd = &sc->vr_cdata.vr_rxdesc[i];
1182 rxd->desc = &rd->vr_rx_ring[i];
1183 if (i == VR_RX_RING_CNT - 1)
1184 addr = VR_RX_RING_ADDR(sc, 0);
1186 addr = VR_RX_RING_ADDR(sc, i + 1);
1187 rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr));
1188 if (vr_newbuf(sc, i) != 0)
1192 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
1193 sc->vr_cdata.vr_rx_ring_map,
1194 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1199 static __inline void
1200 vr_discard_rxbuf(struct vr_rxdesc *rxd)
1202 struct vr_desc *desc;
1205 desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t)));
1206 desc->vr_status = htole32(VR_RXSTAT_OWN);
1210 * Initialize an RX descriptor and attach an MBUF cluster.
1211 * Note: the length fields are only 11 bits wide, which means the
1212 * largest size we can specify is 2047. This is important because
1213 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
1214 * overflow the field and make a mess.
1217 vr_newbuf(struct vr_softc *sc, int idx)
1219 struct vr_desc *desc;
1220 struct vr_rxdesc *rxd;
1222 bus_dma_segment_t segs[1];
1226 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1229 m->m_len = m->m_pkthdr.len = MCLBYTES;
1230 m_adj(m, sizeof(uint64_t));
1232 if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag,
1233 sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1237 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1239 rxd = &sc->vr_cdata.vr_rxdesc[idx];
1240 if (rxd->rx_m != NULL) {
1241 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap,
1242 BUS_DMASYNC_POSTREAD);
1243 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap);
1245 map = rxd->rx_dmamap;
1246 rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap;
1247 sc->vr_cdata.vr_rx_sparemap = map;
1248 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap,
1249 BUS_DMASYNC_PREREAD);
1252 desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr));
1253 desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len);
1254 desc->vr_status = htole32(VR_RXSTAT_OWN);
1259 #ifndef __NO_STRICT_ALIGNMENT
1260 static __inline void
1261 vr_fixup_rx(struct mbuf *m)
1263 uint16_t *src, *dst;
1266 src = mtod(m, uint16_t *);
1269 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1272 m->m_data -= ETHER_ALIGN;
1277 * A frame has been uploaded: pass the resulting mbuf chain up to
1278 * the higher level protocols.
1281 vr_rxeof(struct vr_softc *sc)
1283 struct vr_rxdesc *rxd;
1286 struct vr_desc *cur_rx;
1287 int cons, prog, total_len, rx_npkts;
1288 uint32_t rxstat, rxctl;
1292 cons = sc->vr_cdata.vr_rx_cons;
1295 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
1296 sc->vr_cdata.vr_rx_ring_map,
1297 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1299 for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) {
1300 #ifdef DEVICE_POLLING
1301 if (ifp->if_capenable & IFCAP_POLLING) {
1302 if (sc->rxcycles <= 0)
1307 cur_rx = &sc->vr_rdata.vr_rx_ring[cons];
1308 rxstat = le32toh(cur_rx->vr_status);
1309 rxctl = le32toh(cur_rx->vr_ctl);
1310 if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN)
1314 rxd = &sc->vr_cdata.vr_rxdesc[cons];
1318 * If an error occurs, update stats, clear the
1319 * status word and leave the mbuf cluster in place:
1320 * it should simply get re-used next time this descriptor
1321 * comes up in the ring.
1322 * We don't support SG in Rx path yet, so discard
1325 if ((rxstat & VR_RXSTAT_RX_OK) == 0 ||
1326 (rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) !=
1327 (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) {
1328 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1329 sc->vr_stat.rx_errors++;
1330 if (rxstat & VR_RXSTAT_CRCERR)
1331 sc->vr_stat.rx_crc_errors++;
1332 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
1333 sc->vr_stat.rx_alignment++;
1334 if (rxstat & VR_RXSTAT_FIFOOFLOW)
1335 sc->vr_stat.rx_fifo_overflows++;
1336 if (rxstat & VR_RXSTAT_GIANT)
1337 sc->vr_stat.rx_giants++;
1338 if (rxstat & VR_RXSTAT_RUNT)
1339 sc->vr_stat.rx_runts++;
1340 if (rxstat & VR_RXSTAT_BUFFERR)
1341 sc->vr_stat.rx_no_buffers++;
1342 #ifdef VR_SHOW_ERRORS
1343 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n",
1344 __func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS);
1346 vr_discard_rxbuf(rxd);
1350 if (vr_newbuf(sc, cons) != 0) {
1351 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1352 sc->vr_stat.rx_errors++;
1353 sc->vr_stat.rx_no_mbufs++;
1354 vr_discard_rxbuf(rxd);
1359 * XXX The VIA Rhine chip includes the CRC with every
1360 * received frame, and there's no way to turn this
1361 * behavior off (at least, I can't find anything in
1362 * the manual that explains how to do it) so we have
1363 * to trim off the CRC manually.
1365 total_len = VR_RXBYTES(rxstat);
1366 total_len -= ETHER_CRC_LEN;
1367 m->m_pkthdr.len = m->m_len = total_len;
1368 #ifndef __NO_STRICT_ALIGNMENT
1370 * RX buffers must be 32-bit aligned.
1371 * Ignore the alignment problems on the non-strict alignment
1372 * platform. The performance hit incurred due to unaligned
1373 * accesses is much smaller than the hit produced by forcing
1374 * buffer copies all the time.
1378 m->m_pkthdr.rcvif = ifp;
1379 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1380 sc->vr_stat.rx_ok++;
1381 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
1382 (rxstat & VR_RXSTAT_FRAG) == 0 &&
1383 (rxctl & VR_RXCTL_IP) != 0) {
1384 /* Checksum is valid for non-fragmented IP packets. */
1385 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1386 if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) {
1387 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1388 if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) {
1389 m->m_pkthdr.csum_flags |=
1390 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1391 if ((rxctl & VR_RXCTL_TCPUDPOK) != 0)
1392 m->m_pkthdr.csum_data = 0xffff;
1397 (*ifp->if_input)(ifp, m);
1404 * Let controller know how many number of RX buffers
1405 * are posted but avoid expensive register access if
1406 * TX pause capability was not negotiated with link
1409 if ((sc->vr_flags & VR_F_TXPAUSE) != 0) {
1410 if (prog >= VR_RX_RING_CNT)
1411 prog = VR_RX_RING_CNT - 1;
1412 CSR_WRITE_1(sc, VR_FLOWCR0, prog);
1414 sc->vr_cdata.vr_rx_cons = cons;
1415 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag,
1416 sc->vr_cdata.vr_rx_ring_map,
1417 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1423 * A frame was downloaded to the chip. It's safe for us to clean up
1427 vr_txeof(struct vr_softc *sc)
1429 struct vr_txdesc *txd;
1430 struct vr_desc *cur_tx;
1432 uint32_t txctl, txstat;
1437 cons = sc->vr_cdata.vr_tx_cons;
1438 prod = sc->vr_cdata.vr_tx_prod;
1442 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1443 sc->vr_cdata.vr_tx_ring_map,
1444 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1448 * Go through our tx list and free mbufs for those
1449 * frames that have been transmitted.
1451 for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) {
1452 cur_tx = &sc->vr_rdata.vr_tx_ring[cons];
1453 txctl = le32toh(cur_tx->vr_ctl);
1454 txstat = le32toh(cur_tx->vr_status);
1455 if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN)
1458 sc->vr_cdata.vr_tx_cnt--;
1459 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1460 /* Only the first descriptor in the chain is valid. */
1461 if ((txctl & VR_TXCTL_FIRSTFRAG) == 0)
1464 txd = &sc->vr_cdata.vr_txdesc[cons];
1465 KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n",
1468 if ((txstat & VR_TXSTAT_ERRSUM) != 0) {
1469 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1470 sc->vr_stat.tx_errors++;
1471 if ((txstat & VR_TXSTAT_ABRT) != 0) {
1472 /* Give up and restart Tx. */
1473 sc->vr_stat.tx_abort++;
1474 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag,
1475 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
1476 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag,
1480 VR_INC(cons, VR_TX_RING_CNT);
1481 sc->vr_cdata.vr_tx_cons = cons;
1482 if (vr_tx_stop(sc) != 0) {
1483 device_printf(sc->vr_dev,
1484 "%s: Tx shutdown error -- "
1485 "resetting\n", __func__);
1486 sc->vr_flags |= VR_F_RESTART;
1492 if ((sc->vr_revid < REV_ID_VT3071_A &&
1493 (txstat & VR_TXSTAT_UNDERRUN)) ||
1494 (txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) {
1495 sc->vr_stat.tx_underrun++;
1496 /* Retry and restart Tx. */
1497 sc->vr_cdata.vr_tx_cnt++;
1498 sc->vr_cdata.vr_tx_cons = cons;
1499 cur_tx->vr_status = htole32(VR_TXSTAT_OWN);
1500 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1501 sc->vr_cdata.vr_tx_ring_map,
1502 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1506 if ((txstat & VR_TXSTAT_DEFER) != 0) {
1507 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1508 sc->vr_stat.tx_collisions++;
1510 if ((txstat & VR_TXSTAT_LATECOLL) != 0) {
1511 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1512 sc->vr_stat.tx_late_collisions++;
1515 sc->vr_stat.tx_ok++;
1516 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1519 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
1520 BUS_DMASYNC_POSTWRITE);
1521 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap);
1522 if (sc->vr_revid < REV_ID_VT3071_A) {
1523 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1524 (txstat & VR_TXSTAT_COLLCNT) >> 3);
1525 sc->vr_stat.tx_collisions +=
1526 (txstat & VR_TXSTAT_COLLCNT) >> 3;
1528 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & 0x0f));
1529 sc->vr_stat.tx_collisions += (txstat & 0x0f);
1535 sc->vr_cdata.vr_tx_cons = cons;
1536 if (sc->vr_cdata.vr_tx_cnt == 0)
1537 sc->vr_watchdog_timer = 0;
1543 struct vr_softc *sc;
1544 struct mii_data *mii;
1546 sc = (struct vr_softc *)xsc;
1550 if ((sc->vr_flags & VR_F_RESTART) != 0) {
1551 device_printf(sc->vr_dev, "restarting\n");
1552 sc->vr_stat.num_restart++;
1553 sc->vr_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1555 sc->vr_flags &= ~VR_F_RESTART;
1558 mii = device_get_softc(sc->vr_miibus);
1560 if ((sc->vr_flags & VR_F_LINK) == 0)
1561 vr_miibus_statchg(sc->vr_dev);
1563 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc);
1566 #ifdef DEVICE_POLLING
1567 static poll_handler_t vr_poll;
1568 static poll_handler_t vr_poll_locked;
1571 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1573 struct vr_softc *sc;
1580 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1581 rx_npkts = vr_poll_locked(ifp, cmd, count);
1587 vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1589 struct vr_softc *sc;
1596 sc->rxcycles = count;
1597 rx_npkts = vr_rxeof(sc);
1599 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1600 vr_start_locked(ifp);
1602 if (cmd == POLL_AND_CHECK_STATUS) {
1605 /* Also check status register. */
1606 status = CSR_READ_2(sc, VR_ISR);
1608 CSR_WRITE_2(sc, VR_ISR, status);
1610 if ((status & VR_INTRS) == 0)
1613 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 |
1614 VR_ISR_STATSOFLOW)) != 0) {
1615 if (vr_error(sc, status) != 0)
1618 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) {
1619 #ifdef VR_SHOW_ERRORS
1620 device_printf(sc->vr_dev, "%s: receive error : 0x%b\n",
1621 __func__, status, VR_ISR_ERR_BITS);
1628 #endif /* DEVICE_POLLING */
1630 /* Back off the transmit threshold. */
1632 vr_tx_underrun(struct vr_softc *sc)
1636 device_printf(sc->vr_dev, "Tx underrun -- ");
1637 if (sc->vr_txthresh < VR_TXTHRESH_MAX) {
1638 thresh = sc->vr_txthresh;
1640 if (sc->vr_txthresh >= VR_TXTHRESH_MAX) {
1641 sc->vr_txthresh = VR_TXTHRESH_MAX;
1642 printf("using store and forward mode\n");
1644 printf("increasing Tx threshold(%d -> %d)\n",
1645 vr_tx_threshold_tables[thresh].value,
1646 vr_tx_threshold_tables[thresh + 1].value);
1649 sc->vr_stat.tx_underrun++;
1650 if (vr_tx_stop(sc) != 0) {
1651 device_printf(sc->vr_dev, "%s: Tx shutdown error -- "
1652 "resetting\n", __func__);
1653 sc->vr_flags |= VR_F_RESTART;
1662 struct vr_softc *sc;
1665 sc = (struct vr_softc *)arg;
1667 status = CSR_READ_2(sc, VR_ISR);
1668 if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0)
1669 return (FILTER_STRAY);
1671 /* Disable interrupts. */
1672 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1674 taskqueue_enqueue(taskqueue_fast, &sc->vr_inttask);
1676 return (FILTER_HANDLED);
1680 vr_int_task(void *arg, int npending)
1682 struct vr_softc *sc;
1686 sc = (struct vr_softc *)arg;
1690 if ((sc->vr_flags & VR_F_SUSPENDED) != 0)
1693 status = CSR_READ_2(sc, VR_ISR);
1695 #ifdef DEVICE_POLLING
1696 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1700 /* Suppress unwanted interrupts. */
1701 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
1702 (sc->vr_flags & VR_F_RESTART) != 0) {
1703 CSR_WRITE_2(sc, VR_IMR, 0);
1704 CSR_WRITE_2(sc, VR_ISR, status);
1708 for (; (status & VR_INTRS) != 0;) {
1709 CSR_WRITE_2(sc, VR_ISR, status);
1710 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 |
1711 VR_ISR_STATSOFLOW)) != 0) {
1712 if (vr_error(sc, status) != 0) {
1718 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) {
1719 #ifdef VR_SHOW_ERRORS
1720 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n",
1721 __func__, status, VR_ISR_ERR_BITS);
1723 /* Restart Rx if RxDMA SM was stopped. */
1728 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1729 vr_start_locked(ifp);
1731 status = CSR_READ_2(sc, VR_ISR);
1734 /* Re-enable interrupts. */
1735 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1742 vr_error(struct vr_softc *sc, uint16_t status)
1746 status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW;
1747 if ((status & VR_ISR_BUSERR) != 0) {
1748 status &= ~VR_ISR_BUSERR;
1749 sc->vr_stat.bus_errors++;
1750 /* Disable further interrupts. */
1751 CSR_WRITE_2(sc, VR_IMR, 0);
1752 pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2);
1753 device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- "
1754 "resetting\n", pcis);
1755 pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2);
1756 sc->vr_flags |= VR_F_RESTART;
1759 if ((status & VR_ISR_LINKSTAT2) != 0) {
1760 /* Link state change, duplex changes etc. */
1761 status &= ~VR_ISR_LINKSTAT2;
1763 if ((status & VR_ISR_STATSOFLOW) != 0) {
1764 status &= ~VR_ISR_STATSOFLOW;
1765 if (sc->vr_revid >= REV_ID_VT6105M_A0) {
1766 /* Update MIB counters. */
1771 device_printf(sc->vr_dev,
1772 "unhandled interrupt, status = 0x%04x\n", status);
1777 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1778 * pointers to the fragment pointers.
1781 vr_encap(struct vr_softc *sc, struct mbuf **m_head)
1783 struct vr_txdesc *txd;
1784 struct vr_desc *desc;
1786 bus_dma_segment_t txsegs[VR_MAXFRAGS];
1787 uint32_t csum_flags, txctl;
1788 int error, i, nsegs, prod, si;
1793 M_ASSERTPKTHDR((*m_head));
1796 * Some VIA Rhine wants packet buffers to be longword
1797 * aligned, but very often our mbufs aren't. Rather than
1798 * waste time trying to decide when to copy and when not
1799 * to copy, just do it all the time.
1801 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) {
1802 m = m_defrag(*m_head, M_NOWAIT);
1812 * The Rhine chip doesn't auto-pad, so we have to make
1813 * sure to pad short frames out to the minimum frame length
1816 if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) {
1818 padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len;
1819 if (M_WRITABLE(m) == 0) {
1820 /* Get a writable copy. */
1821 m = m_dup(*m_head, M_NOWAIT);
1829 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
1830 m = m_defrag(m, M_NOWAIT);
1838 * Manually pad short frames, and zero the pad space
1839 * to avoid leaking data.
1841 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1842 m->m_pkthdr.len += padlen;
1843 m->m_len = m->m_pkthdr.len;
1847 prod = sc->vr_cdata.vr_tx_prod;
1848 txd = &sc->vr_cdata.vr_txdesc[prod];
1849 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
1850 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1851 if (error == EFBIG) {
1852 m = m_collapse(*m_head, M_NOWAIT, VR_MAXFRAGS);
1859 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag,
1860 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1866 } else if (error != 0)
1874 /* Check number of available descriptors. */
1875 if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) {
1876 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap);
1880 txd->tx_m = *m_head;
1881 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap,
1882 BUS_DMASYNC_PREWRITE);
1884 /* Set checksum offload. */
1886 if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) {
1887 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
1888 csum_flags |= VR_TXCTL_IPCSUM;
1889 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
1890 csum_flags |= VR_TXCTL_TCPCSUM;
1891 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
1892 csum_flags |= VR_TXCTL_UDPCSUM;
1896 * Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit
1897 * is required for all descriptors regardless of single or
1898 * multiple buffers. Also VR_TXSTAT_OWN bit is valid only for
1899 * the first descriptor for a multi-fragmented frames. Without
1900 * that VIA Rhine chip generates Tx underrun interrupts and can't
1904 for (i = 0; i < nsegs; i++) {
1905 desc = &sc->vr_rdata.vr_tx_ring[prod];
1906 desc->vr_status = 0;
1907 txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags;
1909 txctl |= VR_TXCTL_FIRSTFRAG;
1910 desc->vr_ctl = htole32(txctl);
1911 desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr));
1912 sc->vr_cdata.vr_tx_cnt++;
1913 VR_INC(prod, VR_TX_RING_CNT);
1915 /* Update producer index. */
1916 sc->vr_cdata.vr_tx_prod = prod;
1918 prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT;
1919 desc = &sc->vr_rdata.vr_tx_ring[prod];
1922 * Set EOP on the last desciptor and reuqest Tx completion
1923 * interrupt for every VR_TX_INTR_THRESH-th frames.
1925 VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH);
1926 if (sc->vr_cdata.vr_tx_pkts == 0)
1927 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT);
1929 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG);
1931 /* Lastly turn the first descriptor ownership to hardware. */
1932 desc = &sc->vr_rdata.vr_tx_ring[si];
1933 desc->vr_status |= htole32(VR_TXSTAT_OWN);
1935 /* Sync descriptors. */
1936 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag,
1937 sc->vr_cdata.vr_tx_ring_map,
1938 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1944 vr_start(struct ifnet *ifp)
1946 struct vr_softc *sc;
1950 vr_start_locked(ifp);
1955 vr_start_locked(struct ifnet *ifp)
1957 struct vr_softc *sc;
1958 struct mbuf *m_head;
1965 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1966 IFF_DRV_RUNNING || (sc->vr_flags & VR_F_LINK) == 0)
1969 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1970 sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) {
1971 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1975 * Pack the data into the transmit ring. If we
1976 * don't have room, set the OACTIVE flag and wait
1977 * for the NIC to drain the ring.
1979 if (vr_encap(sc, &m_head)) {
1982 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1983 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1989 * If there's a BPF listener, bounce a copy of this frame
1992 ETHER_BPF_MTAP(ifp, m_head);
1996 /* Tell the chip to start transmitting. */
1997 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO);
1998 /* Set a timeout in case the chip goes out to lunch. */
1999 sc->vr_watchdog_timer = 5;
2006 struct vr_softc *sc;
2008 sc = (struct vr_softc *)xsc;
2015 vr_init_locked(struct vr_softc *sc)
2018 struct mii_data *mii;
2025 mii = device_get_softc(sc->vr_miibus);
2027 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2030 /* Cancel pending I/O and free all RX/TX buffers. */
2034 /* Set our station address. */
2035 for (i = 0; i < ETHER_ADDR_LEN; i++)
2036 CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]);
2039 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
2040 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
2043 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
2044 * so we must set both.
2046 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
2047 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
2049 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
2050 VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg);
2052 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
2053 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
2055 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
2056 VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg);
2058 /* Init circular RX list. */
2059 if (vr_rx_ring_init(sc) != 0) {
2060 device_printf(sc->vr_dev,
2061 "initialization failed: no memory for rx buffers\n");
2066 /* Init tx descriptors. */
2067 vr_tx_ring_init(sc);
2069 if ((sc->vr_quirks & VR_Q_CAM) != 0) {
2070 uint8_t vcam[2] = { 0, 0 };
2072 /* Disable VLAN hardware tag insertion/stripping. */
2073 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL);
2074 /* Disable VLAN hardware filtering. */
2075 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB);
2076 /* Disable all CAM entries. */
2077 vr_cam_mask(sc, VR_MCAST_CAM, 0);
2078 vr_cam_mask(sc, VR_VLAN_CAM, 0);
2079 /* Enable the first VLAN CAM. */
2080 vr_cam_data(sc, VR_VLAN_CAM, 0, vcam);
2081 vr_cam_mask(sc, VR_VLAN_CAM, 1);
2085 * Set up receive filter.
2090 * Load the address of the RX ring.
2092 addr = VR_RX_RING_ADDR(sc, 0);
2093 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr));
2095 * Load the address of the TX ring.
2097 addr = VR_TX_RING_ADDR(sc, 0);
2098 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr));
2099 /* Default : full-duplex, no Tx poll. */
2100 CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL);
2102 /* Set flow-control parameters for Rhine III. */
2103 if (sc->vr_revid >= REV_ID_VT6105_A0) {
2105 * Configure Rx buffer count available for incoming
2107 * Even though data sheet says almost nothing about
2108 * this register, this register should be updated
2109 * whenever driver adds new RX buffers to controller.
2110 * Otherwise, XON frame is not sent to link partner
2111 * even if controller has enough RX buffers and you
2112 * would be isolated from network.
2113 * The controller is not smart enough to know number
2114 * of available RX buffers so driver have to let
2115 * controller know how many RX buffers are posted.
2116 * In other words, this register works like a residue
2117 * counter for RX buffers and should be initialized
2118 * to the number of total RX buffers - 1 before
2119 * enabling RX MAC. Note, this register is 8bits so
2120 * it effectively limits the maximum number of RX
2121 * buffer to be configured by controller is 255.
2123 CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT - 1);
2125 * Tx pause low threshold : 8 free receive buffers
2126 * Tx pause XON high threshold : 24 free receive buffers
2128 CSR_WRITE_1(sc, VR_FLOWCR1,
2129 VR_FLOWCR1_TXLO8 | VR_FLOWCR1_TXHI24 | VR_FLOWCR1_XONXOFF);
2130 /* Set Tx pause timer. */
2131 CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff);
2134 /* Enable receiver and transmitter. */
2135 CSR_WRITE_1(sc, VR_CR0,
2136 VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO);
2138 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
2139 #ifdef DEVICE_POLLING
2141 * Disable interrupts if we are polling.
2143 if (ifp->if_capenable & IFCAP_POLLING)
2144 CSR_WRITE_2(sc, VR_IMR, 0);
2148 * Enable interrupts and disable MII intrs.
2150 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
2151 if (sc->vr_revid > REV_ID_VT6102_A)
2152 CSR_WRITE_2(sc, VR_MII_IMR, 0);
2154 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2155 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2157 sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE);
2160 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc);
2164 * Set media options.
2167 vr_ifmedia_upd(struct ifnet *ifp)
2169 struct vr_softc *sc;
2170 struct mii_data *mii;
2171 struct mii_softc *miisc;
2176 mii = device_get_softc(sc->vr_miibus);
2177 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2179 sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE);
2180 error = mii_mediachg(mii);
2187 * Report current media status.
2190 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2192 struct vr_softc *sc;
2193 struct mii_data *mii;
2196 mii = device_get_softc(sc->vr_miibus);
2198 if ((ifp->if_flags & IFF_UP) == 0) {
2203 ifmr->ifm_active = mii->mii_media_active;
2204 ifmr->ifm_status = mii->mii_media_status;
2209 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2211 struct vr_softc *sc;
2213 struct mii_data *mii;
2217 ifr = (struct ifreq *)data;
2223 if (ifp->if_flags & IFF_UP) {
2224 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2225 if ((ifp->if_flags ^ sc->vr_if_flags) &
2226 (IFF_PROMISC | IFF_ALLMULTI))
2229 if ((sc->vr_flags & VR_F_DETACHED) == 0)
2233 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2236 sc->vr_if_flags = ifp->if_flags;
2247 mii = device_get_softc(sc->vr_miibus);
2248 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2251 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2252 #ifdef DEVICE_POLLING
2253 if (mask & IFCAP_POLLING) {
2254 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2255 error = ether_poll_register(vr_poll, ifp);
2259 /* Disable interrupts. */
2260 CSR_WRITE_2(sc, VR_IMR, 0x0000);
2261 ifp->if_capenable |= IFCAP_POLLING;
2264 error = ether_poll_deregister(ifp);
2265 /* Enable interrupts. */
2267 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
2268 ifp->if_capenable &= ~IFCAP_POLLING;
2272 #endif /* DEVICE_POLLING */
2273 if ((mask & IFCAP_TXCSUM) != 0 &&
2274 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
2275 ifp->if_capenable ^= IFCAP_TXCSUM;
2276 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
2277 ifp->if_hwassist |= VR_CSUM_FEATURES;
2279 ifp->if_hwassist &= ~VR_CSUM_FEATURES;
2281 if ((mask & IFCAP_RXCSUM) != 0 &&
2282 (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
2283 ifp->if_capenable ^= IFCAP_RXCSUM;
2284 if ((mask & IFCAP_WOL_UCAST) != 0 &&
2285 (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0)
2286 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2287 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2288 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2289 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2292 error = ether_ioctl(ifp, command, data);
2300 vr_watchdog(struct vr_softc *sc)
2306 if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer)
2311 * Reclaim first as we don't request interrupt for every packets.
2314 if (sc->vr_cdata.vr_tx_cnt == 0)
2317 if ((sc->vr_flags & VR_F_LINK) == 0) {
2319 if_printf(sc->vr_ifp, "watchdog timeout "
2321 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2322 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2327 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2328 if_printf(ifp, "watchdog timeout\n");
2330 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2333 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2334 vr_start_locked(ifp);
2338 vr_tx_start(struct vr_softc *sc)
2343 cmd = CSR_READ_1(sc, VR_CR0);
2344 if ((cmd & VR_CR0_TX_ON) == 0) {
2345 addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons);
2346 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr));
2347 cmd |= VR_CR0_TX_ON;
2348 CSR_WRITE_1(sc, VR_CR0, cmd);
2350 if (sc->vr_cdata.vr_tx_cnt != 0) {
2351 sc->vr_watchdog_timer = 5;
2352 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO);
2357 vr_rx_start(struct vr_softc *sc)
2362 cmd = CSR_READ_1(sc, VR_CR0);
2363 if ((cmd & VR_CR0_RX_ON) == 0) {
2364 addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons);
2365 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr));
2366 cmd |= VR_CR0_RX_ON;
2367 CSR_WRITE_1(sc, VR_CR0, cmd);
2369 CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO);
2373 vr_tx_stop(struct vr_softc *sc)
2378 cmd = CSR_READ_1(sc, VR_CR0);
2379 if ((cmd & VR_CR0_TX_ON) != 0) {
2380 cmd &= ~VR_CR0_TX_ON;
2381 CSR_WRITE_1(sc, VR_CR0, cmd);
2382 for (i = VR_TIMEOUT; i > 0; i--) {
2384 cmd = CSR_READ_1(sc, VR_CR0);
2385 if ((cmd & VR_CR0_TX_ON) == 0)
2395 vr_rx_stop(struct vr_softc *sc)
2400 cmd = CSR_READ_1(sc, VR_CR0);
2401 if ((cmd & VR_CR0_RX_ON) != 0) {
2402 cmd &= ~VR_CR0_RX_ON;
2403 CSR_WRITE_1(sc, VR_CR0, cmd);
2404 for (i = VR_TIMEOUT; i > 0; i--) {
2406 cmd = CSR_READ_1(sc, VR_CR0);
2407 if ((cmd & VR_CR0_RX_ON) == 0)
2417 * Stop the adapter and free any mbufs allocated to the
2421 vr_stop(struct vr_softc *sc)
2423 struct vr_txdesc *txd;
2424 struct vr_rxdesc *rxd;
2431 sc->vr_watchdog_timer = 0;
2433 callout_stop(&sc->vr_stat_callout);
2434 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2436 CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP);
2437 if (vr_rx_stop(sc) != 0)
2438 device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__);
2439 if (vr_tx_stop(sc) != 0)
2440 device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__);
2441 /* Clear pending interrupts. */
2442 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
2443 CSR_WRITE_2(sc, VR_IMR, 0x0000);
2444 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
2445 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
2448 * Free RX and TX mbufs still in the queues.
2450 for (i = 0; i < VR_RX_RING_CNT; i++) {
2451 rxd = &sc->vr_cdata.vr_rxdesc[i];
2452 if (rxd->rx_m != NULL) {
2453 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag,
2454 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2455 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag,
2461 for (i = 0; i < VR_TX_RING_CNT; i++) {
2462 txd = &sc->vr_cdata.vr_txdesc[i];
2463 if (txd->tx_m != NULL) {
2464 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag,
2465 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2466 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag,
2475 * Stop all chip I/O so that the kernel's probe routines don't
2476 * get confused by errant DMAs when rebooting.
2479 vr_shutdown(device_t dev)
2482 return (vr_suspend(dev));
2486 vr_suspend(device_t dev)
2488 struct vr_softc *sc;
2490 sc = device_get_softc(dev);
2495 sc->vr_flags |= VR_F_SUSPENDED;
2502 vr_resume(device_t dev)
2504 struct vr_softc *sc;
2507 sc = device_get_softc(dev);
2513 if (ifp->if_flags & IFF_UP)
2516 sc->vr_flags &= ~VR_F_SUSPENDED;
2523 vr_setwol(struct vr_softc *sc)
2532 if (sc->vr_revid < REV_ID_VT6102_A ||
2533 pci_find_cap(sc->vr_dev, PCIY_PMG, &pmc) != 0)
2538 /* Clear WOL configuration. */
2539 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF);
2540 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM);
2541 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF);
2542 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN);
2543 if (sc->vr_revid > REV_ID_VT6105_B0) {
2544 /* Newer Rhine III supports two additional patterns. */
2545 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE);
2546 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3);
2547 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3);
2549 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2550 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST);
2551 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2552 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC);
2554 * It seems that multicast wakeup frames require programming pattern
2555 * registers and valid CRC as well as pattern mask for each pattern.
2556 * While it's possible to setup such a pattern it would complicate
2557 * WOL configuration so ignore multicast wakeup frames.
2559 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
2560 CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM);
2561 v = CSR_READ_1(sc, VR_STICKHW);
2562 CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB);
2563 CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN);
2566 /* Put hardware into sleep. */
2567 v = CSR_READ_1(sc, VR_STICKHW);
2568 v |= VR_STICKHW_DS0 | VR_STICKHW_DS1;
2569 CSR_WRITE_1(sc, VR_STICKHW, v);
2571 /* Request PME if WOL is requested. */
2572 pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2);
2573 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2574 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2575 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2576 pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2580 vr_clrwol(struct vr_softc *sc)
2586 if (sc->vr_revid < REV_ID_VT6102_A)
2589 /* Take hardware out of sleep. */
2590 v = CSR_READ_1(sc, VR_STICKHW);
2591 v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB);
2592 CSR_WRITE_1(sc, VR_STICKHW, v);
2594 /* Clear WOL configuration as WOL may interfere normal operation. */
2595 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF);
2596 CSR_WRITE_1(sc, VR_WOLCFG_CLR,
2597 VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR);
2598 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF);
2599 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN);
2600 if (sc->vr_revid > REV_ID_VT6105_B0) {
2601 /* Newer Rhine III supports two additional patterns. */
2602 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE);
2603 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3);
2604 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3);
2609 vr_sysctl_stats(SYSCTL_HANDLER_ARGS)
2611 struct vr_softc *sc;
2612 struct vr_statistics *stat;
2617 error = sysctl_handle_int(oidp, &result, 0, req);
2619 if (error != 0 || req->newptr == NULL)
2623 sc = (struct vr_softc *)arg1;
2624 stat = &sc->vr_stat;
2626 printf("%s statistics:\n", device_get_nameunit(sc->vr_dev));
2627 printf("Outbound good frames : %ju\n",
2628 (uintmax_t)stat->tx_ok);
2629 printf("Inbound good frames : %ju\n",
2630 (uintmax_t)stat->rx_ok);
2631 printf("Outbound errors : %u\n", stat->tx_errors);
2632 printf("Inbound errors : %u\n", stat->rx_errors);
2633 printf("Inbound no buffers : %u\n", stat->rx_no_buffers);
2634 printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs);
2635 printf("Inbound FIFO overflows : %d\n",
2636 stat->rx_fifo_overflows);
2637 printf("Inbound CRC errors : %u\n", stat->rx_crc_errors);
2638 printf("Inbound frame alignment errors : %u\n",
2639 stat->rx_alignment);
2640 printf("Inbound giant frames : %u\n", stat->rx_giants);
2641 printf("Inbound runt frames : %u\n", stat->rx_runts);
2642 printf("Outbound aborted with excessive collisions : %u\n",
2644 printf("Outbound collisions : %u\n", stat->tx_collisions);
2645 printf("Outbound late collisions : %u\n",
2646 stat->tx_late_collisions);
2647 printf("Outbound underrun : %u\n", stat->tx_underrun);
2648 printf("PCI bus errors : %u\n", stat->bus_errors);
2649 printf("driver restarted due to Rx/Tx shutdown failure : %u\n",