2 * Copyright (c) 2005 Marcel Moolenaar
5 * Copyright (c) 2009 The FreeBSD Foundation
8 * Portions of this software were developed by Ed Schouten
9 * under sponsorship from the FreeBSD Foundation.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/kernel.h>
40 #include <sys/systm.h>
42 #include <sys/module.h>
45 #include <dev/vt/vt.h>
46 #include <dev/vt/colors/vt_termcolors.h>
47 #include <dev/vt/hw/vga/vt_vga_reg.h>
48 #include <dev/pci/pcivar.h>
50 #include <machine/bus.h>
51 #if defined(__amd64__) || defined(__i386__)
52 #include <contrib/dev/acpica/include/acpi.h>
53 #include <machine/md_var.h>
57 bus_space_tag_t vga_fb_tag;
58 bus_space_handle_t vga_fb_handle;
59 bus_space_tag_t vga_reg_tag;
60 bus_space_handle_t vga_reg_handle;
62 term_color_t vga_curfg, vga_curbg;
63 boolean_t vga_enabled;
66 /* Convenience macros. */
67 #define MEM_READ1(sc, ofs) \
68 bus_space_read_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs)
69 #define MEM_WRITE1(sc, ofs, val) \
70 bus_space_write_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs, val)
71 #define MEM_WRITE2(sc, ofs, val) \
72 bus_space_write_2(sc->vga_fb_tag, sc->vga_fb_handle, ofs, val)
73 #define REG_READ1(sc, reg) \
74 bus_space_read_1(sc->vga_reg_tag, sc->vga_reg_handle, reg)
75 #define REG_WRITE1(sc, reg, val) \
76 bus_space_write_1(sc->vga_reg_tag, sc->vga_reg_handle, reg, val)
78 #define VT_VGA_WIDTH 640
79 #define VT_VGA_HEIGHT 480
80 #define VT_VGA_MEMSIZE (VT_VGA_WIDTH * VT_VGA_HEIGHT / 8)
83 * VGA is designed to handle 8 pixels at a time (8 pixels in one byte of
86 #define VT_VGA_PIXELS_BLOCK 8
89 * We use an off-screen addresses to:
90 * o store the background color;
91 * o store pixels pattern.
92 * Those addresses are then loaded in the latches once.
94 #define VT_VGA_BGCOLOR_OFFSET VT_VGA_MEMSIZE
96 static vd_probe_t vga_probe;
97 static vd_init_t vga_init;
98 static vd_blank_t vga_blank;
99 static vd_bitblt_text_t vga_bitblt_text;
100 static vd_bitblt_bmp_t vga_bitblt_bitmap;
101 static vd_drawrect_t vga_drawrect;
102 static vd_setpixel_t vga_setpixel;
103 static vd_postswitch_t vga_postswitch;
105 static const struct vt_driver vt_vga_driver = {
107 .vd_probe = vga_probe,
109 .vd_blank = vga_blank,
110 .vd_bitblt_text = vga_bitblt_text,
111 .vd_bitblt_bmp = vga_bitblt_bitmap,
112 .vd_drawrect = vga_drawrect,
113 .vd_setpixel = vga_setpixel,
114 .vd_postswitch = vga_postswitch,
115 .vd_priority = VD_PRIORITY_GENERIC,
119 * Driver supports both text mode and graphics mode. Make sure the
120 * buffer is always big enough to support both.
122 static struct vga_softc vga_conssoftc;
123 VT_DRIVER_DECLARE(vt_vga, vt_vga_driver);
126 vga_setwmode(struct vt_device *vd, int wmode)
128 struct vga_softc *sc = vd->vd_softc;
130 if (sc->vga_wmode == wmode)
133 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE);
134 REG_WRITE1(sc, VGA_GC_DATA, wmode);
135 sc->vga_wmode = wmode;
139 /* Re-enable all plans. */
140 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK);
141 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 |
142 VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0);
148 vga_setfg(struct vt_device *vd, term_color_t color)
150 struct vga_softc *sc = vd->vd_softc;
154 if (sc->vga_curfg == color)
157 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET);
158 REG_WRITE1(sc, VGA_GC_DATA, cons_to_vga_colors[color]);
159 sc->vga_curfg = color;
163 vga_setbg(struct vt_device *vd, term_color_t color)
165 struct vga_softc *sc = vd->vd_softc;
169 if (sc->vga_curbg == color)
172 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET);
173 REG_WRITE1(sc, VGA_GC_DATA, cons_to_vga_colors[color]);
176 * Write 8 pixels using the background color to an off-screen
177 * byte in the video memory.
179 MEM_WRITE1(sc, VT_VGA_BGCOLOR_OFFSET, 0xff);
182 * Read those 8 pixels back to load the background color in the
185 MEM_READ1(sc, VT_VGA_BGCOLOR_OFFSET);
187 sc->vga_curbg = color;
190 * The Set/Reset register doesn't contain the fg color anymore,
191 * store an invalid color.
193 sc->vga_curfg = 0xff;
197 * Binary searchable table for Unicode to CP437 conversion.
201 uint16_t unicode_base;
206 static const struct unicp437 cp437table[] = {
207 { 0x0020, 0x20, 0x5e }, { 0x00a0, 0x20, 0x00 },
208 { 0x00a1, 0xad, 0x00 }, { 0x00a2, 0x9b, 0x00 },
209 { 0x00a3, 0x9c, 0x00 }, { 0x00a5, 0x9d, 0x00 },
210 { 0x00a6, 0x7c, 0x00 },
211 { 0x00a7, 0x15, 0x00 }, { 0x00aa, 0xa6, 0x00 },
212 { 0x00ab, 0xae, 0x00 }, { 0x00ac, 0xaa, 0x00 },
213 { 0x00b0, 0xf8, 0x00 }, { 0x00b1, 0xf1, 0x00 },
214 { 0x00b2, 0xfd, 0x00 }, { 0x00b5, 0xe6, 0x00 },
215 { 0x00b6, 0x14, 0x00 }, { 0x00b7, 0xfa, 0x00 },
216 { 0x00ba, 0xa7, 0x00 }, { 0x00bb, 0xaf, 0x00 },
217 { 0x00bc, 0xac, 0x00 }, { 0x00bd, 0xab, 0x00 },
218 { 0x00bf, 0xa8, 0x00 }, { 0x00c4, 0x8e, 0x01 },
219 { 0x00c6, 0x92, 0x00 }, { 0x00c7, 0x80, 0x00 },
220 { 0x00c9, 0x90, 0x00 }, { 0x00d1, 0xa5, 0x00 },
221 { 0x00d6, 0x99, 0x00 }, { 0x00dc, 0x9a, 0x00 },
222 { 0x00df, 0xe1, 0x00 }, { 0x00e0, 0x85, 0x00 },
223 { 0x00e1, 0xa0, 0x00 }, { 0x00e2, 0x83, 0x00 },
224 { 0x00e4, 0x84, 0x00 }, { 0x00e5, 0x86, 0x00 },
225 { 0x00e6, 0x91, 0x00 }, { 0x00e7, 0x87, 0x00 },
226 { 0x00e8, 0x8a, 0x00 }, { 0x00e9, 0x82, 0x00 },
227 { 0x00ea, 0x88, 0x01 }, { 0x00ec, 0x8d, 0x00 },
228 { 0x00ed, 0xa1, 0x00 }, { 0x00ee, 0x8c, 0x00 },
229 { 0x00ef, 0x8b, 0x00 }, { 0x00f0, 0xeb, 0x00 },
230 { 0x00f1, 0xa4, 0x00 }, { 0x00f2, 0x95, 0x00 },
231 { 0x00f3, 0xa2, 0x00 }, { 0x00f4, 0x93, 0x00 },
232 { 0x00f6, 0x94, 0x00 }, { 0x00f7, 0xf6, 0x00 },
233 { 0x00f8, 0xed, 0x00 }, { 0x00f9, 0x97, 0x00 },
234 { 0x00fa, 0xa3, 0x00 }, { 0x00fb, 0x96, 0x00 },
235 { 0x00fc, 0x81, 0x00 }, { 0x00ff, 0x98, 0x00 },
236 { 0x0192, 0x9f, 0x00 }, { 0x0393, 0xe2, 0x00 },
237 { 0x0398, 0xe9, 0x00 }, { 0x03a3, 0xe4, 0x00 },
238 { 0x03a6, 0xe8, 0x00 }, { 0x03a9, 0xea, 0x00 },
239 { 0x03b1, 0xe0, 0x01 }, { 0x03b4, 0xeb, 0x00 },
240 { 0x03b5, 0xee, 0x00 }, { 0x03bc, 0xe6, 0x00 },
241 { 0x03c0, 0xe3, 0x00 }, { 0x03c3, 0xe5, 0x00 },
242 { 0x03c4, 0xe7, 0x00 }, { 0x03c6, 0xed, 0x00 },
243 { 0x03d5, 0xed, 0x00 }, { 0x2010, 0x2d, 0x00 },
244 { 0x2013, 0x2d, 0x00 },
245 { 0x2014, 0x2d, 0x00 }, { 0x2018, 0x60, 0x00 },
246 { 0x2019, 0x27, 0x00 }, { 0x201c, 0x22, 0x00 },
247 { 0x201d, 0x22, 0x00 }, { 0x2022, 0x07, 0x00 },
248 { 0x203c, 0x13, 0x00 }, { 0x207f, 0xfc, 0x00 },
249 { 0x20a7, 0x9e, 0x00 }, { 0x20ac, 0xee, 0x00 },
250 { 0x2126, 0xea, 0x00 }, { 0x2190, 0x1b, 0x00 },
251 { 0x2191, 0x18, 0x00 }, { 0x2192, 0x1a, 0x00 },
252 { 0x2193, 0x19, 0x00 }, { 0x2194, 0x1d, 0x00 },
253 { 0x2195, 0x12, 0x00 }, { 0x21a8, 0x17, 0x00 },
254 { 0x2202, 0xeb, 0x00 }, { 0x2208, 0xee, 0x00 },
255 { 0x2211, 0xe4, 0x00 }, { 0x2212, 0x2d, 0x00 },
256 { 0x2219, 0xf9, 0x00 }, { 0x221a, 0xfb, 0x00 },
257 { 0x221e, 0xec, 0x00 }, { 0x221f, 0x1c, 0x00 },
258 { 0x2229, 0xef, 0x00 }, { 0x2248, 0xf7, 0x00 },
259 { 0x2261, 0xf0, 0x00 }, { 0x2264, 0xf3, 0x00 },
260 { 0x2265, 0xf2, 0x00 }, { 0x2302, 0x7f, 0x00 },
261 { 0x2310, 0xa9, 0x00 }, { 0x2320, 0xf4, 0x00 },
262 { 0x2321, 0xf5, 0x00 }, { 0x2500, 0xc4, 0x00 },
263 { 0x2502, 0xb3, 0x00 }, { 0x250c, 0xda, 0x00 },
264 { 0x2510, 0xbf, 0x00 }, { 0x2514, 0xc0, 0x00 },
265 { 0x2518, 0xd9, 0x00 }, { 0x251c, 0xc3, 0x00 },
266 { 0x2524, 0xb4, 0x00 }, { 0x252c, 0xc2, 0x00 },
267 { 0x2534, 0xc1, 0x00 }, { 0x253c, 0xc5, 0x00 },
268 { 0x2550, 0xcd, 0x00 }, { 0x2551, 0xba, 0x00 },
269 { 0x2552, 0xd5, 0x00 }, { 0x2553, 0xd6, 0x00 },
270 { 0x2554, 0xc9, 0x00 }, { 0x2555, 0xb8, 0x00 },
271 { 0x2556, 0xb7, 0x00 }, { 0x2557, 0xbb, 0x00 },
272 { 0x2558, 0xd4, 0x00 }, { 0x2559, 0xd3, 0x00 },
273 { 0x255a, 0xc8, 0x00 }, { 0x255b, 0xbe, 0x00 },
274 { 0x255c, 0xbd, 0x00 }, { 0x255d, 0xbc, 0x00 },
275 { 0x255e, 0xc6, 0x01 }, { 0x2560, 0xcc, 0x00 },
276 { 0x2561, 0xb5, 0x00 }, { 0x2562, 0xb6, 0x00 },
277 { 0x2563, 0xb9, 0x00 }, { 0x2564, 0xd1, 0x01 },
278 { 0x2566, 0xcb, 0x00 }, { 0x2567, 0xcf, 0x00 },
279 { 0x2568, 0xd0, 0x00 }, { 0x2569, 0xca, 0x00 },
280 { 0x256a, 0xd8, 0x00 }, { 0x256b, 0xd7, 0x00 },
281 { 0x256c, 0xce, 0x00 }, { 0x2580, 0xdf, 0x00 },
282 { 0x2584, 0xdc, 0x00 }, { 0x2588, 0xdb, 0x00 },
283 { 0x258c, 0xdd, 0x00 }, { 0x2590, 0xde, 0x00 },
284 { 0x2591, 0xb0, 0x02 }, { 0x25a0, 0xfe, 0x00 },
285 { 0x25ac, 0x16, 0x00 }, { 0x25b2, 0x1e, 0x00 },
286 { 0x25ba, 0x10, 0x00 }, { 0x25bc, 0x1f, 0x00 },
287 { 0x25c4, 0x11, 0x00 }, { 0x25cb, 0x09, 0x00 },
288 { 0x25d8, 0x08, 0x00 }, { 0x25d9, 0x0a, 0x00 },
289 { 0x263a, 0x01, 0x01 }, { 0x263c, 0x0f, 0x00 },
290 { 0x2640, 0x0c, 0x00 }, { 0x2642, 0x0b, 0x00 },
291 { 0x2660, 0x06, 0x00 }, { 0x2663, 0x05, 0x00 },
292 { 0x2665, 0x03, 0x01 }, { 0x266a, 0x0d, 0x00 },
293 { 0x266c, 0x0e, 0x00 }, { 0x2713, 0xfb, 0x00 },
294 { 0x27e8, 0x3c, 0x00 }, { 0x27e9, 0x3e, 0x00 },
298 vga_get_cp437(term_char_t c)
303 max = nitems(cp437table) - 1;
305 if (c < cp437table[0].unicode_base ||
306 c > cp437table[max].unicode_base + cp437table[max].length)
310 mid = (min + max) / 2;
311 if (c < cp437table[mid].unicode_base)
313 else if (c > cp437table[mid].unicode_base +
314 cp437table[mid].length)
317 return (c - cp437table[mid].unicode_base +
318 cp437table[mid].cp437_base);
325 vga_blank(struct vt_device *vd, term_color_t color)
327 struct vga_softc *sc = vd->vd_softc;
330 vga_setfg(vd, color);
331 for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++)
332 MEM_WRITE1(sc, ofs, 0xff);
336 vga_bitblt_put(struct vt_device *vd, u_long dst, term_color_t color,
339 struct vga_softc *sc = vd->vd_softc;
341 /* Skip empty writes, in order to avoid palette changes. */
343 vga_setfg(vd, color);
345 * When this MEM_READ1() gets disabled, all sorts of
346 * artifacts occur. This is because this read loads the
347 * set of 8 pixels that are about to be changed. There
348 * is one scenario where we can avoid the read, namely
349 * if all pixels are about to be overwritten anyway.
354 /* The bg color was trashed by the reads. */
355 sc->vga_curbg = 0xff;
357 MEM_WRITE1(sc, dst, v);
362 vga_setpixel(struct vt_device *vd, int x, int y, term_color_t color)
365 if (vd->vd_flags & VDF_TEXTMODE)
368 vga_bitblt_put(vd, (y * VT_VGA_WIDTH / 8) + (x / 8), color,
373 vga_drawrect(struct vt_device *vd, int x1, int y1, int x2, int y2, int fill,
378 if (vd->vd_flags & VDF_TEXTMODE)
381 for (y = y1; y <= y2; y++) {
382 if (fill || (y == y1) || (y == y2)) {
383 for (x = x1; x <= x2; x++)
384 vga_setpixel(vd, x, y, color);
386 vga_setpixel(vd, x1, y, color);
387 vga_setpixel(vd, x2, y, color);
393 vga_compute_shifted_pattern(const uint8_t *src, unsigned int bytes,
394 unsigned int src_x, unsigned int x_count, unsigned int dst_x,
395 uint8_t *pattern, uint8_t *mask)
402 * This mask has bits set, where a pixel (ether 0 or 1)
403 * comes from the source bitmap.
408 << (8 - x_count - dst_x);
411 if (n == (src_x + x_count - 1) / 8) {
412 /* All the pixels we want are in the same byte. */
415 *pattern >>= (dst_x - src_x % 8);
417 *pattern <<= (src_x % 8 - dst_x);
419 /* The pixels we want are split into two bytes. */
420 if (dst_x >= src_x % 8) {
422 src[n] << (8 - dst_x - src_x % 8) |
423 src[n + 1] >> (dst_x - src_x % 8);
426 src[n] << (src_x % 8 - dst_x) |
427 src[n + 1] >> (8 - src_x % 8 - dst_x);
433 vga_copy_bitmap_portion(uint8_t *pattern_2colors, uint8_t *pattern_ncolors,
434 const uint8_t *src, const uint8_t *src_mask, unsigned int src_width,
435 unsigned int src_x, unsigned int dst_x, unsigned int x_count,
436 unsigned int src_y, unsigned int dst_y, unsigned int y_count,
437 term_color_t fg, term_color_t bg, int overwrite)
439 unsigned int i, bytes;
440 uint8_t pattern, relevant_bits, mask;
442 bytes = (src_width + 7) / 8;
444 for (i = 0; i < y_count; ++i) {
445 vga_compute_shifted_pattern(src + (src_y + i) * bytes,
446 bytes, src_x, x_count, dst_x, &pattern, &relevant_bits);
448 if (src_mask == NULL) {
450 * No src mask. Consider that all wanted bits
451 * from the source are "authoritative".
453 mask = relevant_bits;
456 * There's an src mask. We shift it the same way
457 * we shifted the source pattern.
459 vga_compute_shifted_pattern(
460 src_mask + (src_y + i) * bytes,
461 bytes, src_x, x_count, dst_x,
464 /* Now, only keep the wanted bits among them. */
465 mask &= relevant_bits;
469 * Clear bits from the pattern which must be
470 * transparent, according to the source mask.
474 /* Set the bits in the 2-colors array. */
476 pattern_2colors[dst_y + i] &= ~mask;
477 pattern_2colors[dst_y + i] |= pattern;
479 if (pattern_ncolors == NULL)
483 * Set the same bits in the n-colors array. This one
484 * supports transparency, when a given bit is cleared in
489 * Ensure that the pixels used by this bitmap are
490 * cleared in other colors.
492 for (int j = 0; j < 16; ++j)
493 pattern_ncolors[(dst_y + i) * 16 + j] &=
496 pattern_ncolors[(dst_y + i) * 16 + fg] |= pattern;
497 pattern_ncolors[(dst_y + i) * 16 + bg] |= (~pattern & mask);
502 vga_bitblt_pixels_block_2colors(struct vt_device *vd, const uint8_t *masks,
503 term_color_t fg, term_color_t bg,
504 unsigned int x, unsigned int y, unsigned int height)
506 unsigned int i, offset;
507 struct vga_softc *sc;
510 * The great advantage of Write Mode 3 is that we just need
511 * to load the foreground in the Set/Reset register, load the
512 * background color in the latches register (this is done
513 * through a write in offscreen memory followed by a read of
514 * that data), then write the pattern to video memory. This
515 * pattern indicates if the pixel should use the foreground
516 * color (bit set) or the background color (bit cleared).
523 offset = (VT_VGA_WIDTH * y + x) / 8;
525 for (i = 0; i < height; ++i, offset += VT_VGA_WIDTH / 8) {
526 MEM_WRITE1(sc, offset, masks[i]);
531 vga_bitblt_pixels_block_ncolors(struct vt_device *vd, const uint8_t *masks,
532 unsigned int x, unsigned int y, unsigned int height)
534 unsigned int i, j, plan, color, offset;
535 struct vga_softc *sc;
536 uint8_t mask, plans[height * 4];
540 memset(plans, 0, sizeof(plans));
543 * To write a group of pixels using 3 or more colors, we select
544 * Write Mode 0 and write one byte to each plan separately.
548 * We first compute each byte: each plan contains one bit of the
549 * color code for each of the 8 pixels.
551 * For example, if the 8 pixels are like this:
556 * Y (yellow) = 0b0011
558 * The corresponding for bytes are:
560 * Plan 0: 10000001 = 0x81
561 * Plan 1: 10000001 = 0x81
562 * Plan 2: 10000000 = 0x80
563 * Plan 3: 00000000 = 0x00
566 * | +-----> 0b0000 (B)
567 * +--------> 0b0111 (G)
570 for (i = 0; i < height; ++i) {
571 for (color = 0; color < 16; ++color) {
572 mask = masks[i * 16 + color];
576 for (j = 0; j < 8; ++j) {
577 if (!((mask >> (7 - j)) & 0x1))
580 /* The pixel "j" uses color "color". */
581 for (plan = 0; plan < 4; ++plan)
582 plans[i * 4 + plan] |=
583 ((color >> plan) & 0x1) << (7 - j);
589 * The bytes are ready: we now switch to Write Mode 0 and write
590 * all bytes, one plan at a time.
594 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK);
595 for (plan = 0; plan < 4; ++plan) {
597 REG_WRITE1(sc, VGA_SEQ_DATA, 1 << plan);
599 /* Write all bytes for this plan, from Y to Y+height. */
600 for (i = 0; i < height; ++i) {
601 offset = (VT_VGA_WIDTH * (y + i) + x) / 8;
602 MEM_WRITE1(sc, offset, plans[i * 4 + plan]);
608 vga_bitblt_one_text_pixels_block(struct vt_device *vd,
609 const struct vt_window *vw, unsigned int x, unsigned int y)
611 const struct vt_buf *vb;
612 const struct vt_font *vf;
613 unsigned int i, col, row, src_x, x_count;
614 unsigned int used_colors_list[16], used_colors;
615 uint8_t pattern_2colors[vw->vw_font->vf_height];
616 uint8_t pattern_ncolors[vw->vw_font->vf_height * 16];
625 * The current pixels block.
627 * We fill it with portions of characters, because both "grids"
630 * i is the index in this pixels block.
635 memset(used_colors_list, 0, sizeof(used_colors_list));
636 memset(pattern_2colors, 0, sizeof(pattern_2colors));
637 memset(pattern_ncolors, 0, sizeof(pattern_ncolors));
639 if (i < vw->vw_draw_area.tr_begin.tp_col) {
641 * i is in the margin used to center the text area on
645 i = vw->vw_draw_area.tr_begin.tp_col;
648 while (i < x + VT_VGA_PIXELS_BLOCK &&
649 i < vw->vw_draw_area.tr_end.tp_col) {
651 * Find which character is drawn on this pixel in the
654 * While here, record what colors it uses.
657 col = (i - vw->vw_draw_area.tr_begin.tp_col) / vf->vf_width;
658 row = (y - vw->vw_draw_area.tr_begin.tp_row) / vf->vf_height;
660 c = VTBUF_GET_FIELD(vb, row, col);
661 src = vtfont_lookup(vf, c);
663 vt_determine_colors(c, VTBUF_ISCURSOR(vb, row, col), &fg, &bg);
664 if ((used_colors_list[fg] & 0x1) != 0x1)
666 if ((used_colors_list[bg] & 0x2) != 0x2)
668 used_colors_list[fg] |= 0x1;
669 used_colors_list[bg] |= 0x2;
672 * Compute the portion of the character we want to draw,
673 * because the pixels block may start in the middle of a
676 * The first pixel to draw in the character is
677 * the current position -
678 * the start position of the character
680 * The last pixel to draw is either
681 * - the last pixel of the character, or
682 * - the pixel of the character matching the end of
684 * whichever comes first. This position is then
685 * changed to be relative to the start position of the
690 (col * vf->vf_width + vw->vw_draw_area.tr_begin.tp_col);
692 (col + 1) * vf->vf_width +
693 vw->vw_draw_area.tr_begin.tp_col,
694 x + VT_VGA_PIXELS_BLOCK),
695 vw->vw_draw_area.tr_end.tp_col);
696 x_count -= col * vf->vf_width +
697 vw->vw_draw_area.tr_begin.tp_col;
700 /* Copy a portion of the character. */
701 vga_copy_bitmap_portion(pattern_2colors, pattern_ncolors,
702 src, NULL, vf->vf_width,
703 src_x, i % VT_VGA_PIXELS_BLOCK, x_count,
704 0, 0, vf->vf_height, fg, bg, 0);
706 /* We move to the next portion. */
710 #ifndef SC_NO_CUTPASTE
712 * Copy the mouse pointer bitmap if it's over the current pixels
715 * We use the saved cursor position (saved in vt_flush()), because
716 * the current position could be different than the one used
717 * to mark the area dirty.
719 term_rect_t drawn_area;
721 drawn_area.tr_begin.tp_col = x;
722 drawn_area.tr_begin.tp_row = y;
723 drawn_area.tr_end.tp_col = x + VT_VGA_PIXELS_BLOCK;
724 drawn_area.tr_end.tp_row = y + vf->vf_height;
725 if (vd->vd_mshown && vt_is_cursor_in_area(vd, &drawn_area)) {
726 struct vt_mouse_cursor *cursor;
728 unsigned int dst_x, src_y, dst_y, y_count;
730 cursor = vd->vd_mcursor;
731 mx = vd->vd_mx_drawn + vw->vw_draw_area.tr_begin.tp_col;
732 my = vd->vd_my_drawn + vw->vw_draw_area.tr_begin.tp_row;
734 /* Compute the portion of the cursor we want to copy. */
735 src_x = x > mx ? x - mx : 0;
736 dst_x = mx > x ? mx - x : 0;
737 x_count = min(min(min(
738 cursor->width - src_x,
739 x + VT_VGA_PIXELS_BLOCK - mx),
740 vw->vw_draw_area.tr_end.tp_col - mx),
741 VT_VGA_PIXELS_BLOCK);
744 * The cursor isn't aligned on the Y-axis with
745 * characters, so we need to compute the vertical
748 src_y = y > my ? y - my : 0;
749 dst_y = my > y ? my - y : 0;
751 min(cursor->height - src_y, y + vf->vf_height - my),
754 /* Copy the cursor portion. */
755 vga_copy_bitmap_portion(pattern_2colors, pattern_ncolors,
756 cursor->map, cursor->mask, cursor->width,
757 src_x, dst_x, x_count, src_y, dst_y, y_count,
758 vd->vd_mcursor_fg, vd->vd_mcursor_bg, 1);
760 if ((used_colors_list[vd->vd_mcursor_fg] & 0x1) != 0x1)
762 if ((used_colors_list[vd->vd_mcursor_bg] & 0x2) != 0x2)
768 * The pixels block is completed, we can now draw it on the
771 if (used_colors == 2)
772 vga_bitblt_pixels_block_2colors(vd, pattern_2colors, fg, bg,
773 x, y, vf->vf_height);
775 vga_bitblt_pixels_block_ncolors(vd, pattern_ncolors,
776 x, y, vf->vf_height);
780 vga_bitblt_text_gfxmode(struct vt_device *vd, const struct vt_window *vw,
781 const term_rect_t *area)
783 const struct vt_font *vf;
784 unsigned int col, row;
785 unsigned int x1, y1, x2, y2, x, y;
790 * Compute the top-left pixel position aligned with the video
791 * adapter pixels block size.
793 * This is calculated from the top-left column of te dirty area:
795 * 1. Compute the top-left pixel of the character:
796 * col * font width + x offset
798 * NOTE: x offset is used to center the text area on the
799 * screen. It's expressed in pixels, not in characters
802 * 2. Find the pixel further on the left marking the start of
803 * an aligned pixels block (eg. chunk of 8 pixels):
804 * character's x / blocksize * blocksize
806 * The division, being made on integers, achieves the
809 * For the Y-axis, we need to compute the character's y
810 * coordinate, but we don't need to align it.
813 col = area->tr_begin.tp_col;
814 row = area->tr_begin.tp_row;
815 x1 = (int)((col * vf->vf_width + vw->vw_draw_area.tr_begin.tp_col)
816 / VT_VGA_PIXELS_BLOCK)
817 * VT_VGA_PIXELS_BLOCK;
818 y1 = row * vf->vf_height + vw->vw_draw_area.tr_begin.tp_row;
821 * Compute the bottom right pixel position, again, aligned with
822 * the pixels block size.
824 * The same rules apply, we just add 1 to base the computation
825 * on the "right border" of the dirty area.
828 col = area->tr_end.tp_col;
829 row = area->tr_end.tp_row;
830 x2 = (int)howmany(col * vf->vf_width + vw->vw_draw_area.tr_begin.tp_col,
832 * VT_VGA_PIXELS_BLOCK;
833 y2 = row * vf->vf_height + vw->vw_draw_area.tr_begin.tp_row;
835 /* Clip the area to the screen size. */
836 x2 = min(x2, vw->vw_draw_area.tr_end.tp_col);
837 y2 = min(y2, vw->vw_draw_area.tr_end.tp_row);
840 * Now, we take care of N pixels line at a time (the first for
841 * loop, N = font height), and for these lines, draw one pixels
842 * block at a time (the second for loop), not a character at a
845 * Therefore, on the X-axis, characters my be drawn partially if
846 * they are not aligned on 8-pixels boundary.
848 * However, the operation is repeated for the full height of the
849 * font before moving to the next character, because it allows
850 * to keep the color settings and write mode, before perhaps
851 * changing them with the next one.
854 for (y = y1; y < y2; y += vf->vf_height) {
855 for (x = x1; x < x2; x += VT_VGA_PIXELS_BLOCK) {
856 vga_bitblt_one_text_pixels_block(vd, vw, x, y);
862 vga_bitblt_text_txtmode(struct vt_device *vd, const struct vt_window *vw,
863 const term_rect_t *area)
865 struct vga_softc *sc;
866 const struct vt_buf *vb;
867 unsigned int col, row;
875 for (row = area->tr_begin.tp_row; row < area->tr_end.tp_row; ++row) {
876 for (col = area->tr_begin.tp_col;
877 col < area->tr_end.tp_col;
880 * Get next character and its associated fg/bg
883 c = VTBUF_GET_FIELD(vb, row, col);
884 vt_determine_colors(c, VTBUF_ISCURSOR(vb, row, col),
888 * Convert character to CP437, which is the
889 * character set used by the VGA hardware by
892 ch = vga_get_cp437(TCHAR_CHARACTER(c));
894 /* Convert colors to VGA attributes. */
896 cons_to_vga_colors[bg] << 4 |
897 cons_to_vga_colors[fg];
899 MEM_WRITE2(sc, (row * 80 + col) * 2 + 0,
900 ch + ((uint16_t)(attr) << 8));
906 vga_bitblt_text(struct vt_device *vd, const struct vt_window *vw,
907 const term_rect_t *area)
910 if (!(vd->vd_flags & VDF_TEXTMODE)) {
911 vga_bitblt_text_gfxmode(vd, vw, area);
913 vga_bitblt_text_txtmode(vd, vw, area);
918 vga_bitblt_bitmap(struct vt_device *vd, const struct vt_window *vw,
919 const uint8_t *pattern, const uint8_t *mask,
920 unsigned int width, unsigned int height,
921 unsigned int x, unsigned int y, term_color_t fg, term_color_t bg)
923 unsigned int x1, y1, x2, y2, i, j, src_x, dst_x, x_count;
924 uint8_t pattern_2colors;
926 /* Align coordinates with the 8-pxels grid. */
927 x1 = rounddown(x, VT_VGA_PIXELS_BLOCK);
930 x2 = roundup(x + width, VT_VGA_PIXELS_BLOCK);
932 x2 = min(x2, vd->vd_width - 1);
933 y2 = min(y2, vd->vd_height - 1);
935 for (j = y1; j < y2; ++j) {
938 x_count = VT_VGA_PIXELS_BLOCK - dst_x;
940 for (i = x1; i < x2; i += VT_VGA_PIXELS_BLOCK) {
943 vga_copy_bitmap_portion(
944 &pattern_2colors, NULL,
945 pattern, mask, width,
946 src_x, dst_x, x_count,
947 j - y1, 0, 1, fg, bg, 0);
949 vga_bitblt_pixels_block_2colors(vd,
950 &pattern_2colors, fg, bg,
954 dst_x = (dst_x + x_count) % VT_VGA_PIXELS_BLOCK;
955 x_count = min(width - src_x, VT_VGA_PIXELS_BLOCK);
961 vga_initialize_graphics(struct vt_device *vd)
963 struct vga_softc *sc = vd->vd_softc;
966 REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, VGA_GEN_MO_VSP | VGA_GEN_MO_HSP |
967 VGA_GEN_MO_PB | VGA_GEN_MO_ER | VGA_GEN_MO_IOA);
968 /* Set sequencer clocking and memory mode. */
969 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CLOCKING_MODE);
970 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_CM_89);
971 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MEMORY_MODE);
972 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_OE | VGA_SEQ_MM_EM);
974 /* Set the graphics controller in graphics mode. */
975 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MISCELLANEOUS);
976 REG_WRITE1(sc, VGA_GC_DATA, 0x04 + VGA_GC_MISC_GA);
977 /* Program the CRT controller. */
978 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_TOTAL);
979 REG_WRITE1(sc, VGA_CRTC_DATA, 0x5f); /* 760 */
980 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_DISP_END);
981 REG_WRITE1(sc, VGA_CRTC_DATA, 0x4f); /* 640 - 8 */
982 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_BLANK);
983 REG_WRITE1(sc, VGA_CRTC_DATA, 0x50); /* 640 */
984 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_BLANK);
985 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHB_CR + 2);
986 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_RETRACE);
987 REG_WRITE1(sc, VGA_CRTC_DATA, 0x54); /* 672 */
988 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_RETRACE);
989 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHR_EHB + 0);
990 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_TOTAL);
991 REG_WRITE1(sc, VGA_CRTC_DATA, 0x0b); /* 523 */
992 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OVERFLOW);
993 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_OF_VT9 | VGA_CRTC_OF_LC8 |
994 VGA_CRTC_OF_VBS8 | VGA_CRTC_OF_VRS8 | VGA_CRTC_OF_VDE8);
995 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MAX_SCAN_LINE);
996 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MSL_LC9);
997 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_START);
998 REG_WRITE1(sc, VGA_CRTC_DATA, 0xea); /* 480 + 10 */
999 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END);
1000 REG_WRITE1(sc, VGA_CRTC_DATA, 0x0c);
1001 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_DISPLAY_END);
1002 REG_WRITE1(sc, VGA_CRTC_DATA, 0xdf); /* 480 - 1*/
1003 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OFFSET);
1004 REG_WRITE1(sc, VGA_CRTC_DATA, 0x28);
1005 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_VERT_BLANK);
1006 REG_WRITE1(sc, VGA_CRTC_DATA, 0xe7); /* 480 + 7 */
1007 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_VERT_BLANK);
1008 REG_WRITE1(sc, VGA_CRTC_DATA, 0x04);
1009 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL);
1010 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MC_WB | VGA_CRTC_MC_AW |
1011 VGA_CRTC_MC_SRS | VGA_CRTC_MC_CMS);
1012 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_LINE_COMPARE);
1013 REG_WRITE1(sc, VGA_CRTC_DATA, 0xff); /* 480 + 31 */
1015 REG_WRITE1(sc, VGA_GEN_FEATURE_CTRL_W, 0);
1017 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK);
1018 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 |
1019 VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0);
1020 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CHAR_MAP_SELECT);
1021 REG_WRITE1(sc, VGA_SEQ_DATA, 0);
1023 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET);
1024 REG_WRITE1(sc, VGA_GC_DATA, 0);
1025 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET);
1026 REG_WRITE1(sc, VGA_GC_DATA, 0x0f);
1027 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_COMPARE);
1028 REG_WRITE1(sc, VGA_GC_DATA, 0);
1029 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_DATA_ROTATE);
1030 REG_WRITE1(sc, VGA_GC_DATA, 0);
1031 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_READ_MAP_SELECT);
1032 REG_WRITE1(sc, VGA_GC_DATA, 0);
1033 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE);
1034 REG_WRITE1(sc, VGA_GC_DATA, 0);
1035 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_DONT_CARE);
1036 REG_WRITE1(sc, VGA_GC_DATA, 0x0f);
1037 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_BIT_MASK);
1038 REG_WRITE1(sc, VGA_GC_DATA, 0xff);
1042 vga_initialize(struct vt_device *vd, int textmode)
1044 struct vga_softc *sc = vd->vd_softc;
1048 /* Make sure the VGA adapter is not in monochrome emulation mode. */
1049 x = REG_READ1(sc, VGA_GEN_MISC_OUTPUT_R);
1050 REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, x | VGA_GEN_MO_IOA);
1052 /* Unprotect CRTC registers 0-7. */
1053 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END);
1054 x = REG_READ1(sc, VGA_CRTC_DATA);
1055 REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_VRE_PR);
1058 * Wait for the vertical retrace.
1059 * NOTE: this code reads the VGA_GEN_INPUT_STAT_1 register, which has
1060 * the side-effect of clearing the internal flip-flip of the attribute
1061 * controller's write register. This means that because this code is
1062 * here, we know for sure that the first write to the attribute
1063 * controller will be a write to the address register. Removing this
1064 * code therefore also removes that guarantee and appropriate measures
1070 x = REG_READ1(sc, VGA_GEN_INPUT_STAT_1);
1071 x &= VGA_GEN_IS1_VR | VGA_GEN_IS1_DE;
1072 } while (x != (VGA_GEN_IS1_VR | VGA_GEN_IS1_DE) && --timeout != 0);
1074 printf("Timeout initializing vt_vga\n");
1078 /* Now, disable the sync. signals. */
1079 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL);
1080 x = REG_READ1(sc, VGA_CRTC_DATA);
1081 REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_MC_HR);
1083 /* Asynchronous sequencer reset. */
1084 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET);
1085 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR);
1088 vga_initialize_graphics(vd);
1090 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_PRESET_ROW_SCAN);
1091 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
1092 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_START);
1093 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_CS_COO);
1094 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_END);
1095 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
1096 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_HIGH);
1097 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
1098 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_LOW);
1099 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
1100 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_HIGH);
1101 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
1102 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_LOW);
1103 REG_WRITE1(sc, VGA_CRTC_DATA, 0x59);
1104 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_UNDERLINE_LOC);
1105 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_UL_UL);
1108 /* Set the attribute controller to blink disable. */
1109 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL);
1110 REG_WRITE1(sc, VGA_AC_WRITE, 0);
1112 /* Set the attribute controller in graphics mode. */
1113 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL);
1114 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MC_GA);
1115 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_HORIZ_PIXEL_PANNING);
1116 REG_WRITE1(sc, VGA_AC_WRITE, 0);
1118 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(0));
1119 REG_WRITE1(sc, VGA_AC_WRITE, 0);
1120 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(1));
1121 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_B);
1122 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(2));
1123 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G);
1124 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(3));
1125 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G | VGA_AC_PAL_B);
1126 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(4));
1127 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R);
1128 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(5));
1129 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_B);
1130 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(6));
1131 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SG | VGA_AC_PAL_R);
1132 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(7));
1133 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B);
1135 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(8));
1136 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1138 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(9));
1139 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1140 VGA_AC_PAL_SB | VGA_AC_PAL_B);
1141 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(10));
1142 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1143 VGA_AC_PAL_SB | VGA_AC_PAL_G);
1144 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(11));
1145 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1146 VGA_AC_PAL_SB | VGA_AC_PAL_G | VGA_AC_PAL_B);
1147 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(12));
1148 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1149 VGA_AC_PAL_SB | VGA_AC_PAL_R);
1150 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(13));
1151 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1152 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_B);
1153 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(14));
1154 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1155 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G);
1156 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(15));
1157 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1158 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B);
1160 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_OVERSCAN_COLOR);
1161 REG_WRITE1(sc, VGA_AC_WRITE, 0);
1162 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_PLANE_ENABLE);
1163 REG_WRITE1(sc, VGA_AC_WRITE, 0x0f);
1164 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_SELECT);
1165 REG_WRITE1(sc, VGA_AC_WRITE, 0);
1171 * Done. Clear the frame buffer. All bit planes are
1172 * enabled, so a single-paged loop should clear all
1175 for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++) {
1176 MEM_WRITE1(sc, ofs, 0);
1180 /* Re-enable the sequencer. */
1181 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET);
1182 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR);
1183 /* Re-enable the sync signals. */
1184 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL);
1185 x = REG_READ1(sc, VGA_CRTC_DATA);
1186 REG_WRITE1(sc, VGA_CRTC_DATA, x | VGA_CRTC_MC_HR);
1189 /* Switch to write mode 3, because we'll mainly do bitblt. */
1190 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE);
1191 REG_WRITE1(sc, VGA_GC_DATA, 3);
1195 * In Write Mode 3, Enable Set/Reset is ignored, but we
1196 * use Write Mode 0 to write a group of 8 pixels using
1197 * 3 or more colors. In this case, we want to disable
1198 * Set/Reset: set Enable Set/Reset to 0.
1200 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET);
1201 REG_WRITE1(sc, VGA_GC_DATA, 0x00);
1204 * Clear the colors we think are loaded into Set/Reset or
1207 sc->vga_curfg = sc->vga_curbg = 0xff;
1214 vga_acpi_disabled(void)
1216 #if defined(__amd64__) || defined(__i386__)
1221 TUNABLE_INT_FETCH("hw.vga.acpi_ignore_no_vga", &ignore);
1222 if (ignore || !acpi_get_fadt_bootflags(&flags))
1224 return ((flags & ACPI_FADT_NO_VGA) != 0);
1231 vga_probe(struct vt_device *vd)
1234 return (vga_acpi_disabled() ? CN_DEAD : CN_INTERNAL);
1238 vga_init(struct vt_device *vd)
1240 struct vga_softc *sc;
1243 if (vd->vd_softc == NULL)
1244 vd->vd_softc = (void *)&vga_conssoftc;
1247 if (vd->vd_flags & VDF_DOWNGRADE && vd->vd_video_dev != NULL)
1248 vga_pci_repost(vd->vd_video_dev);
1250 #if defined(__amd64__) || defined(__i386__)
1251 sc->vga_fb_tag = X86_BUS_SPACE_MEM;
1252 sc->vga_reg_tag = X86_BUS_SPACE_IO;
1254 # error "Architecture not yet supported!"
1257 bus_space_map(sc->vga_reg_tag, VGA_REG_BASE, VGA_REG_SIZE, 0,
1258 &sc->vga_reg_handle);
1261 * If "hw.vga.textmode" is not set and we're running on hypervisor,
1262 * we use text mode by default, this is because when we're on
1263 * hypervisor, vt(4) is usually much slower in graphics mode than
1264 * in text mode, especially when we're on Hyper-V.
1266 textmode = vm_guest != VM_GUEST_NO;
1267 TUNABLE_INT_FETCH("hw.vga.textmode", &textmode);
1269 vd->vd_flags |= VDF_TEXTMODE;
1272 bus_space_map(sc->vga_fb_tag, VGA_TXT_BASE, VGA_TXT_SIZE, 0,
1273 &sc->vga_fb_handle);
1275 vd->vd_width = VT_VGA_WIDTH;
1276 vd->vd_height = VT_VGA_HEIGHT;
1277 bus_space_map(sc->vga_fb_tag, VGA_MEM_BASE, VGA_MEM_SIZE, 0,
1278 &sc->vga_fb_handle);
1280 if (vga_initialize(vd, textmode) != 0)
1282 sc->vga_enabled = true;
1284 return (CN_INTERNAL);
1288 vga_postswitch(struct vt_device *vd)
1291 /* Reinit VGA mode, to restore view after app which change mode. */
1292 vga_initialize(vd, (vd->vd_flags & VDF_TEXTMODE));
1293 /* Ask vt(9) to update chars on visible area. */
1294 vd->vd_flags |= VDF_INVALID;
1297 /* Dummy NewBus functions to reserve the resources used by the vt_vga driver */
1299 vtvga_identify(driver_t *driver, device_t parent)
1302 if (!vga_conssoftc.vga_enabled)
1305 if (BUS_ADD_CHILD(parent, 0, driver->name, 0) == NULL)
1306 panic("Unable to attach vt_vga console");
1310 vtvga_probe(device_t dev)
1313 device_set_desc(dev, "VT VGA driver");
1315 return (BUS_PROBE_NOWILDCARD);
1319 vtvga_attach(device_t dev)
1321 struct resource *pseudo_phys_res;
1325 pseudo_phys_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
1326 &res_id, VGA_MEM_BASE, VGA_MEM_BASE + VGA_MEM_SIZE - 1,
1327 VGA_MEM_SIZE, RF_ACTIVE);
1328 if (pseudo_phys_res == NULL)
1329 panic("Unable to reserve vt_vga memory");
1333 /*-------------------- Private Device Attachment Data -----------------------*/
1334 static device_method_t vtvga_methods[] = {
1335 /* Device interface */
1336 DEVMETHOD(device_identify, vtvga_identify),
1337 DEVMETHOD(device_probe, vtvga_probe),
1338 DEVMETHOD(device_attach, vtvga_attach),
1343 DEFINE_CLASS_0(vtvga, vtvga_driver, vtvga_methods, 0);
1344 devclass_t vtvga_devclass;
1346 DRIVER_MODULE(vtvga, nexus, vtvga_driver, vtvga_devclass, NULL, NULL);