2 * Copyright (c) 2005 Marcel Moolenaar
5 * Copyright (c) 2009 The FreeBSD Foundation
8 * Portions of this software were developed by Ed Schouten
9 * under sponsorship from the FreeBSD Foundation.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/kernel.h>
40 #include <sys/systm.h>
42 #include <sys/module.h>
45 #include <dev/vt/vt.h>
46 #include <dev/vt/hw/vga/vt_vga_reg.h>
47 #include <dev/pci/pcivar.h>
49 #include <machine/bus.h>
51 #if ((defined(__amd64__) || defined(__i386__)) && defined(DEV_ACPI))
52 #include <contrib/dev/acpica/include/acpi.h>
56 bus_space_tag_t vga_fb_tag;
57 bus_space_handle_t vga_fb_handle;
58 bus_space_tag_t vga_reg_tag;
59 bus_space_handle_t vga_reg_handle;
61 term_color_t vga_curfg, vga_curbg;
62 boolean_t vga_enabled;
65 /* Convenience macros. */
66 #define MEM_READ1(sc, ofs) \
67 bus_space_read_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs)
68 #define MEM_WRITE1(sc, ofs, val) \
69 bus_space_write_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs, val)
70 #define REG_READ1(sc, reg) \
71 bus_space_read_1(sc->vga_reg_tag, sc->vga_reg_handle, reg)
72 #define REG_WRITE1(sc, reg, val) \
73 bus_space_write_1(sc->vga_reg_tag, sc->vga_reg_handle, reg, val)
75 #define VT_VGA_WIDTH 640
76 #define VT_VGA_HEIGHT 480
77 #define VT_VGA_MEMSIZE (VT_VGA_WIDTH * VT_VGA_HEIGHT / 8)
80 * VGA is designed to handle 8 pixels at a time (8 pixels in one byte of
83 #define VT_VGA_PIXELS_BLOCK 8
86 * We use an off-screen addresses to:
87 * o store the background color;
88 * o store pixels pattern.
89 * Those addresses are then loaded in the latches once.
91 #define VT_VGA_BGCOLOR_OFFSET VT_VGA_MEMSIZE
93 static vd_probe_t vga_probe;
94 static vd_init_t vga_init;
95 static vd_blank_t vga_blank;
96 static vd_bitblt_text_t vga_bitblt_text;
97 static vd_bitblt_bmp_t vga_bitblt_bitmap;
98 static vd_drawrect_t vga_drawrect;
99 static vd_setpixel_t vga_setpixel;
100 static vd_postswitch_t vga_postswitch;
102 static const struct vt_driver vt_vga_driver = {
104 .vd_probe = vga_probe,
106 .vd_blank = vga_blank,
107 .vd_bitblt_text = vga_bitblt_text,
108 .vd_bitblt_bmp = vga_bitblt_bitmap,
109 .vd_drawrect = vga_drawrect,
110 .vd_setpixel = vga_setpixel,
111 .vd_postswitch = vga_postswitch,
112 .vd_priority = VD_PRIORITY_GENERIC,
116 * Driver supports both text mode and graphics mode. Make sure the
117 * buffer is always big enough to support both.
119 static struct vga_softc vga_conssoftc;
120 VT_DRIVER_DECLARE(vt_vga, vt_vga_driver);
123 vga_setwmode(struct vt_device *vd, int wmode)
125 struct vga_softc *sc = vd->vd_softc;
127 if (sc->vga_wmode == wmode)
130 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE);
131 REG_WRITE1(sc, VGA_GC_DATA, wmode);
132 sc->vga_wmode = wmode;
136 /* Re-enable all plans. */
137 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK);
138 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 |
139 VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0);
145 vga_setfg(struct vt_device *vd, term_color_t color)
147 struct vga_softc *sc = vd->vd_softc;
151 if (sc->vga_curfg == color)
154 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET);
155 REG_WRITE1(sc, VGA_GC_DATA, color);
156 sc->vga_curfg = color;
160 vga_setbg(struct vt_device *vd, term_color_t color)
162 struct vga_softc *sc = vd->vd_softc;
166 if (sc->vga_curbg == color)
169 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET);
170 REG_WRITE1(sc, VGA_GC_DATA, color);
173 * Write 8 pixels using the background color to an off-screen
174 * byte in the video memory.
176 MEM_WRITE1(sc, VT_VGA_BGCOLOR_OFFSET, 0xff);
179 * Read those 8 pixels back to load the background color in the
182 MEM_READ1(sc, VT_VGA_BGCOLOR_OFFSET);
184 sc->vga_curbg = color;
187 * The Set/Reset register doesn't contain the fg color anymore,
188 * store an invalid color.
190 sc->vga_curfg = 0xff;
194 * Binary searchable table for Unicode to CP437 conversion.
198 uint16_t unicode_base;
203 static const struct unicp437 cp437table[] = {
204 { 0x0020, 0x20, 0x5e }, { 0x00a0, 0x20, 0x00 },
205 { 0x00a1, 0xad, 0x00 }, { 0x00a2, 0x9b, 0x00 },
206 { 0x00a3, 0x9c, 0x00 }, { 0x00a5, 0x9d, 0x00 },
207 { 0x00a7, 0x15, 0x00 }, { 0x00aa, 0xa6, 0x00 },
208 { 0x00ab, 0xae, 0x00 }, { 0x00ac, 0xaa, 0x00 },
209 { 0x00b0, 0xf8, 0x00 }, { 0x00b1, 0xf1, 0x00 },
210 { 0x00b2, 0xfd, 0x00 }, { 0x00b5, 0xe6, 0x00 },
211 { 0x00b6, 0x14, 0x00 }, { 0x00b7, 0xfa, 0x00 },
212 { 0x00ba, 0xa7, 0x00 }, { 0x00bb, 0xaf, 0x00 },
213 { 0x00bc, 0xac, 0x00 }, { 0x00bd, 0xab, 0x00 },
214 { 0x00bf, 0xa8, 0x00 }, { 0x00c4, 0x8e, 0x01 },
215 { 0x00c6, 0x92, 0x00 }, { 0x00c7, 0x80, 0x00 },
216 { 0x00c9, 0x90, 0x00 }, { 0x00d1, 0xa5, 0x00 },
217 { 0x00d6, 0x99, 0x00 }, { 0x00dc, 0x9a, 0x00 },
218 { 0x00df, 0xe1, 0x00 }, { 0x00e0, 0x85, 0x00 },
219 { 0x00e1, 0xa0, 0x00 }, { 0x00e2, 0x83, 0x00 },
220 { 0x00e4, 0x84, 0x00 }, { 0x00e5, 0x86, 0x00 },
221 { 0x00e6, 0x91, 0x00 }, { 0x00e7, 0x87, 0x00 },
222 { 0x00e8, 0x8a, 0x00 }, { 0x00e9, 0x82, 0x00 },
223 { 0x00ea, 0x88, 0x01 }, { 0x00ec, 0x8d, 0x00 },
224 { 0x00ed, 0xa1, 0x00 }, { 0x00ee, 0x8c, 0x00 },
225 { 0x00ef, 0x8b, 0x00 }, { 0x00f0, 0xeb, 0x00 },
226 { 0x00f1, 0xa4, 0x00 }, { 0x00f2, 0x95, 0x00 },
227 { 0x00f3, 0xa2, 0x00 }, { 0x00f4, 0x93, 0x00 },
228 { 0x00f6, 0x94, 0x00 }, { 0x00f7, 0xf6, 0x00 },
229 { 0x00f8, 0xed, 0x00 }, { 0x00f9, 0x97, 0x00 },
230 { 0x00fa, 0xa3, 0x00 }, { 0x00fb, 0x96, 0x00 },
231 { 0x00fc, 0x81, 0x00 }, { 0x00ff, 0x98, 0x00 },
232 { 0x0192, 0x9f, 0x00 }, { 0x0393, 0xe2, 0x00 },
233 { 0x0398, 0xe9, 0x00 }, { 0x03a3, 0xe4, 0x00 },
234 { 0x03a6, 0xe8, 0x00 }, { 0x03a9, 0xea, 0x00 },
235 { 0x03b1, 0xe0, 0x01 }, { 0x03b4, 0xeb, 0x00 },
236 { 0x03b5, 0xee, 0x00 }, { 0x03bc, 0xe6, 0x00 },
237 { 0x03c0, 0xe3, 0x00 }, { 0x03c3, 0xe5, 0x00 },
238 { 0x03c4, 0xe7, 0x00 }, { 0x03c6, 0xed, 0x00 },
239 { 0x03d5, 0xed, 0x00 }, { 0x2010, 0x2d, 0x00 },
240 { 0x2014, 0x2d, 0x00 }, { 0x2018, 0x60, 0x00 },
241 { 0x2019, 0x27, 0x00 }, { 0x201c, 0x22, 0x00 },
242 { 0x201d, 0x22, 0x00 }, { 0x2022, 0x07, 0x00 },
243 { 0x203c, 0x13, 0x00 }, { 0x207f, 0xfc, 0x00 },
244 { 0x20a7, 0x9e, 0x00 }, { 0x20ac, 0xee, 0x00 },
245 { 0x2126, 0xea, 0x00 }, { 0x2190, 0x1b, 0x00 },
246 { 0x2191, 0x18, 0x00 }, { 0x2192, 0x1a, 0x00 },
247 { 0x2193, 0x19, 0x00 }, { 0x2194, 0x1d, 0x00 },
248 { 0x2195, 0x12, 0x00 }, { 0x21a8, 0x17, 0x00 },
249 { 0x2202, 0xeb, 0x00 }, { 0x2208, 0xee, 0x00 },
250 { 0x2211, 0xe4, 0x00 }, { 0x2212, 0x2d, 0x00 },
251 { 0x2219, 0xf9, 0x00 }, { 0x221a, 0xfb, 0x00 },
252 { 0x221e, 0xec, 0x00 }, { 0x221f, 0x1c, 0x00 },
253 { 0x2229, 0xef, 0x00 }, { 0x2248, 0xf7, 0x00 },
254 { 0x2261, 0xf0, 0x00 }, { 0x2264, 0xf3, 0x00 },
255 { 0x2265, 0xf2, 0x00 }, { 0x2302, 0x7f, 0x00 },
256 { 0x2310, 0xa9, 0x00 }, { 0x2320, 0xf4, 0x00 },
257 { 0x2321, 0xf5, 0x00 }, { 0x2500, 0xc4, 0x00 },
258 { 0x2502, 0xb3, 0x00 }, { 0x250c, 0xda, 0x00 },
259 { 0x2510, 0xbf, 0x00 }, { 0x2514, 0xc0, 0x00 },
260 { 0x2518, 0xd9, 0x00 }, { 0x251c, 0xc3, 0x00 },
261 { 0x2524, 0xb4, 0x00 }, { 0x252c, 0xc2, 0x00 },
262 { 0x2534, 0xc1, 0x00 }, { 0x253c, 0xc5, 0x00 },
263 { 0x2550, 0xcd, 0x00 }, { 0x2551, 0xba, 0x00 },
264 { 0x2552, 0xd5, 0x00 }, { 0x2553, 0xd6, 0x00 },
265 { 0x2554, 0xc9, 0x00 }, { 0x2555, 0xb8, 0x00 },
266 { 0x2556, 0xb7, 0x00 }, { 0x2557, 0xbb, 0x00 },
267 { 0x2558, 0xd4, 0x00 }, { 0x2559, 0xd3, 0x00 },
268 { 0x255a, 0xc8, 0x00 }, { 0x255b, 0xbe, 0x00 },
269 { 0x255c, 0xbd, 0x00 }, { 0x255d, 0xbc, 0x00 },
270 { 0x255e, 0xc6, 0x01 }, { 0x2560, 0xcc, 0x00 },
271 { 0x2561, 0xb5, 0x00 }, { 0x2562, 0xb6, 0x00 },
272 { 0x2563, 0xb9, 0x00 }, { 0x2564, 0xd1, 0x01 },
273 { 0x2566, 0xcb, 0x00 }, { 0x2567, 0xcf, 0x00 },
274 { 0x2568, 0xd0, 0x00 }, { 0x2569, 0xca, 0x00 },
275 { 0x256a, 0xd8, 0x00 }, { 0x256b, 0xd7, 0x00 },
276 { 0x256c, 0xce, 0x00 }, { 0x2580, 0xdf, 0x00 },
277 { 0x2584, 0xdc, 0x00 }, { 0x2588, 0xdb, 0x00 },
278 { 0x258c, 0xdd, 0x00 }, { 0x2590, 0xde, 0x00 },
279 { 0x2591, 0xb0, 0x02 }, { 0x25a0, 0xfe, 0x00 },
280 { 0x25ac, 0x16, 0x00 }, { 0x25b2, 0x1e, 0x00 },
281 { 0x25ba, 0x10, 0x00 }, { 0x25bc, 0x1f, 0x00 },
282 { 0x25c4, 0x11, 0x00 }, { 0x25cb, 0x09, 0x00 },
283 { 0x25d8, 0x08, 0x00 }, { 0x25d9, 0x0a, 0x00 },
284 { 0x263a, 0x01, 0x01 }, { 0x263c, 0x0f, 0x00 },
285 { 0x2640, 0x0c, 0x00 }, { 0x2642, 0x0b, 0x00 },
286 { 0x2660, 0x06, 0x00 }, { 0x2663, 0x05, 0x00 },
287 { 0x2665, 0x03, 0x01 }, { 0x266a, 0x0d, 0x00 },
288 { 0x266c, 0x0e, 0x00 },
292 vga_get_cp437(term_char_t c)
297 max = nitems(cp437table) - 1;
299 if (c < cp437table[0].unicode_base ||
300 c > cp437table[max].unicode_base + cp437table[max].length)
304 mid = (min + max) / 2;
305 if (c < cp437table[mid].unicode_base)
307 else if (c > cp437table[mid].unicode_base +
308 cp437table[mid].length)
311 return (c - cp437table[mid].unicode_base +
312 cp437table[mid].cp437_base);
319 vga_blank(struct vt_device *vd, term_color_t color)
321 struct vga_softc *sc = vd->vd_softc;
324 vga_setfg(vd, color);
325 for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++)
326 MEM_WRITE1(sc, ofs, 0xff);
330 vga_bitblt_put(struct vt_device *vd, u_long dst, term_color_t color,
333 struct vga_softc *sc = vd->vd_softc;
335 /* Skip empty writes, in order to avoid palette changes. */
337 vga_setfg(vd, color);
339 * When this MEM_READ1() gets disabled, all sorts of
340 * artifacts occur. This is because this read loads the
341 * set of 8 pixels that are about to be changed. There
342 * is one scenario where we can avoid the read, namely
343 * if all pixels are about to be overwritten anyway.
348 /* The bg color was trashed by the reads. */
349 sc->vga_curbg = 0xff;
351 MEM_WRITE1(sc, dst, v);
356 vga_setpixel(struct vt_device *vd, int x, int y, term_color_t color)
359 if (vd->vd_flags & VDF_TEXTMODE)
362 vga_bitblt_put(vd, (y * VT_VGA_WIDTH / 8) + (x / 8), color,
367 vga_drawrect(struct vt_device *vd, int x1, int y1, int x2, int y2, int fill,
372 if (vd->vd_flags & VDF_TEXTMODE)
375 for (y = y1; y <= y2; y++) {
376 if (fill || (y == y1) || (y == y2)) {
377 for (x = x1; x <= x2; x++)
378 vga_setpixel(vd, x, y, color);
380 vga_setpixel(vd, x1, y, color);
381 vga_setpixel(vd, x2, y, color);
387 vga_compute_shifted_pattern(const uint8_t *src, unsigned int bytes,
388 unsigned int src_x, unsigned int x_count, unsigned int dst_x,
389 uint8_t *pattern, uint8_t *mask)
396 * This mask has bits set, where a pixel (ether 0 or 1)
397 * comes from the source bitmap.
402 << (8 - x_count - dst_x);
405 if (n == (src_x + x_count - 1) / 8) {
406 /* All the pixels we want are in the same byte. */
409 *pattern >>= (dst_x - src_x % 8);
411 *pattern <<= (src_x % 8 - dst_x);
413 /* The pixels we want are split into two bytes. */
414 if (dst_x >= src_x % 8) {
416 src[n] << (8 - dst_x - src_x % 8) |
417 src[n + 1] >> (dst_x - src_x % 8);
420 src[n] << (src_x % 8 - dst_x) |
421 src[n + 1] >> (8 - src_x % 8 - dst_x);
427 vga_copy_bitmap_portion(uint8_t *pattern_2colors, uint8_t *pattern_ncolors,
428 const uint8_t *src, const uint8_t *src_mask, unsigned int src_width,
429 unsigned int src_x, unsigned int dst_x, unsigned int x_count,
430 unsigned int src_y, unsigned int dst_y, unsigned int y_count,
431 term_color_t fg, term_color_t bg, int overwrite)
433 unsigned int i, bytes;
434 uint8_t pattern, relevant_bits, mask;
436 bytes = (src_width + 7) / 8;
438 for (i = 0; i < y_count; ++i) {
439 vga_compute_shifted_pattern(src + (src_y + i) * bytes,
440 bytes, src_x, x_count, dst_x, &pattern, &relevant_bits);
442 if (src_mask == NULL) {
444 * No src mask. Consider that all wanted bits
445 * from the source are "authoritative".
447 mask = relevant_bits;
450 * There's an src mask. We shift it the same way
451 * we shifted the source pattern.
453 vga_compute_shifted_pattern(
454 src_mask + (src_y + i) * bytes,
455 bytes, src_x, x_count, dst_x,
458 /* Now, only keep the wanted bits among them. */
459 mask &= relevant_bits;
463 * Clear bits from the pattern which must be
464 * transparent, according to the source mask.
468 /* Set the bits in the 2-colors array. */
470 pattern_2colors[dst_y + i] &= ~mask;
471 pattern_2colors[dst_y + i] |= pattern;
473 if (pattern_ncolors == NULL)
477 * Set the same bits in the n-colors array. This one
478 * supports transparency, when a given bit is cleared in
483 * Ensure that the pixels used by this bitmap are
484 * cleared in other colors.
486 for (int j = 0; j < 16; ++j)
487 pattern_ncolors[(dst_y + i) * 16 + j] &=
490 pattern_ncolors[(dst_y + i) * 16 + fg] |= pattern;
491 pattern_ncolors[(dst_y + i) * 16 + bg] |= (~pattern & mask);
496 vga_bitblt_pixels_block_2colors(struct vt_device *vd, const uint8_t *masks,
497 term_color_t fg, term_color_t bg,
498 unsigned int x, unsigned int y, unsigned int height)
500 unsigned int i, offset;
501 struct vga_softc *sc;
504 * The great advantage of Write Mode 3 is that we just need
505 * to load the foreground in the Set/Reset register, load the
506 * background color in the latches register (this is done
507 * through a write in offscreen memory followed by a read of
508 * that data), then write the pattern to video memory. This
509 * pattern indicates if the pixel should use the foreground
510 * color (bit set) or the background color (bit cleared).
517 offset = (VT_VGA_WIDTH * y + x) / 8;
519 for (i = 0; i < height; ++i, offset += VT_VGA_WIDTH / 8) {
520 MEM_WRITE1(sc, offset, masks[i]);
525 vga_bitblt_pixels_block_ncolors(struct vt_device *vd, const uint8_t *masks,
526 unsigned int x, unsigned int y, unsigned int height)
528 unsigned int i, j, plan, color, offset;
529 struct vga_softc *sc;
530 uint8_t mask, plans[height * 4];
534 memset(plans, 0, sizeof(plans));
537 * To write a group of pixels using 3 or more colors, we select
538 * Write Mode 0 and write one byte to each plan separately.
542 * We first compute each byte: each plan contains one bit of the
543 * color code for each of the 8 pixels.
545 * For example, if the 8 pixels are like this:
550 * Y (yellow) = 0b0011
552 * The corresponding for bytes are:
554 * Plan 0: 10000001 = 0x81
555 * Plan 1: 10000001 = 0x81
556 * Plan 2: 10000000 = 0x80
557 * Plan 3: 00000000 = 0x00
560 * | +-----> 0b0000 (B)
561 * +--------> 0b0111 (G)
564 for (i = 0; i < height; ++i) {
565 for (color = 0; color < 16; ++color) {
566 mask = masks[i * 16 + color];
570 for (j = 0; j < 8; ++j) {
571 if (!((mask >> (7 - j)) & 0x1))
574 /* The pixel "j" uses color "color". */
575 for (plan = 0; plan < 4; ++plan)
576 plans[i * 4 + plan] |=
577 ((color >> plan) & 0x1) << (7 - j);
583 * The bytes are ready: we now switch to Write Mode 0 and write
584 * all bytes, one plan at a time.
588 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK);
589 for (plan = 0; plan < 4; ++plan) {
591 REG_WRITE1(sc, VGA_SEQ_DATA, 1 << plan);
593 /* Write all bytes for this plan, from Y to Y+height. */
594 for (i = 0; i < height; ++i) {
595 offset = (VT_VGA_WIDTH * (y + i) + x) / 8;
596 MEM_WRITE1(sc, offset, plans[i * 4 + plan]);
602 vga_bitblt_one_text_pixels_block(struct vt_device *vd,
603 const struct vt_window *vw, unsigned int x, unsigned int y)
605 const struct vt_buf *vb;
606 const struct vt_font *vf;
607 unsigned int i, col, row, src_x, x_count;
608 unsigned int used_colors_list[16], used_colors;
609 uint8_t pattern_2colors[vw->vw_font->vf_height];
610 uint8_t pattern_ncolors[vw->vw_font->vf_height * 16];
619 * The current pixels block.
621 * We fill it with portions of characters, because both "grids"
624 * i is the index in this pixels block.
629 memset(used_colors_list, 0, sizeof(used_colors_list));
630 memset(pattern_2colors, 0, sizeof(pattern_2colors));
631 memset(pattern_ncolors, 0, sizeof(pattern_ncolors));
633 if (i < vw->vw_draw_area.tr_begin.tp_col) {
635 * i is in the margin used to center the text area on
639 i = vw->vw_draw_area.tr_begin.tp_col;
642 while (i < x + VT_VGA_PIXELS_BLOCK &&
643 i < vw->vw_draw_area.tr_end.tp_col) {
645 * Find which character is drawn on this pixel in the
648 * While here, record what colors it uses.
651 col = (i - vw->vw_draw_area.tr_begin.tp_col) / vf->vf_width;
652 row = (y - vw->vw_draw_area.tr_begin.tp_row) / vf->vf_height;
654 c = VTBUF_GET_FIELD(vb, row, col);
655 src = vtfont_lookup(vf, c);
657 vt_determine_colors(c, VTBUF_ISCURSOR(vb, row, col), &fg, &bg);
658 if ((used_colors_list[fg] & 0x1) != 0x1)
660 if ((used_colors_list[bg] & 0x2) != 0x2)
662 used_colors_list[fg] |= 0x1;
663 used_colors_list[bg] |= 0x2;
666 * Compute the portion of the character we want to draw,
667 * because the pixels block may start in the middle of a
670 * The first pixel to draw in the character is
671 * the current position -
672 * the start position of the character
674 * The last pixel to draw is either
675 * - the last pixel of the character, or
676 * - the pixel of the character matching the end of
678 * whichever comes first. This position is then
679 * changed to be relative to the start position of the
684 (col * vf->vf_width + vw->vw_draw_area.tr_begin.tp_col);
686 (col + 1) * vf->vf_width +
687 vw->vw_draw_area.tr_begin.tp_col,
688 x + VT_VGA_PIXELS_BLOCK),
689 vw->vw_draw_area.tr_end.tp_col);
690 x_count -= col * vf->vf_width +
691 vw->vw_draw_area.tr_begin.tp_col;
694 /* Copy a portion of the character. */
695 vga_copy_bitmap_portion(pattern_2colors, pattern_ncolors,
696 src, NULL, vf->vf_width,
697 src_x, i % VT_VGA_PIXELS_BLOCK, x_count,
698 0, 0, vf->vf_height, fg, bg, 0);
700 /* We move to the next portion. */
704 #ifndef SC_NO_CUTPASTE
706 * Copy the mouse pointer bitmap if it's over the current pixels
709 * We use the saved cursor position (saved in vt_flush()), because
710 * the current position could be different than the one used
711 * to mark the area dirty.
713 term_rect_t drawn_area;
715 drawn_area.tr_begin.tp_col = x;
716 drawn_area.tr_begin.tp_row = y;
717 drawn_area.tr_end.tp_col = x + VT_VGA_PIXELS_BLOCK;
718 drawn_area.tr_end.tp_row = y + vf->vf_height;
719 if (vd->vd_mshown && vt_is_cursor_in_area(vd, &drawn_area)) {
720 struct vt_mouse_cursor *cursor;
722 unsigned int dst_x, src_y, dst_y, y_count;
724 cursor = vd->vd_mcursor;
725 mx = vd->vd_mx_drawn + vw->vw_draw_area.tr_begin.tp_col;
726 my = vd->vd_my_drawn + vw->vw_draw_area.tr_begin.tp_row;
728 /* Compute the portion of the cursor we want to copy. */
729 src_x = x > mx ? x - mx : 0;
730 dst_x = mx > x ? mx - x : 0;
731 x_count = min(min(min(
732 cursor->width - src_x,
733 x + VT_VGA_PIXELS_BLOCK - mx),
734 vw->vw_draw_area.tr_end.tp_col - mx),
735 VT_VGA_PIXELS_BLOCK);
738 * The cursor isn't aligned on the Y-axis with
739 * characters, so we need to compute the vertical
742 src_y = y > my ? y - my : 0;
743 dst_y = my > y ? my - y : 0;
745 min(cursor->height - src_y, y + vf->vf_height - my),
748 /* Copy the cursor portion. */
749 vga_copy_bitmap_portion(pattern_2colors, pattern_ncolors,
750 cursor->map, cursor->mask, cursor->width,
751 src_x, dst_x, x_count, src_y, dst_y, y_count,
752 vd->vd_mcursor_fg, vd->vd_mcursor_bg, 1);
754 if ((used_colors_list[vd->vd_mcursor_fg] & 0x1) != 0x1)
756 if ((used_colors_list[vd->vd_mcursor_bg] & 0x2) != 0x2)
762 * The pixels block is completed, we can now draw it on the
765 if (used_colors == 2)
766 vga_bitblt_pixels_block_2colors(vd, pattern_2colors, fg, bg,
767 x, y, vf->vf_height);
769 vga_bitblt_pixels_block_ncolors(vd, pattern_ncolors,
770 x, y, vf->vf_height);
774 vga_bitblt_text_gfxmode(struct vt_device *vd, const struct vt_window *vw,
775 const term_rect_t *area)
777 const struct vt_font *vf;
778 unsigned int col, row;
779 unsigned int x1, y1, x2, y2, x, y;
784 * Compute the top-left pixel position aligned with the video
785 * adapter pixels block size.
787 * This is calculated from the top-left column of te dirty area:
789 * 1. Compute the top-left pixel of the character:
790 * col * font width + x offset
792 * NOTE: x offset is used to center the text area on the
793 * screen. It's expressed in pixels, not in characters
796 * 2. Find the pixel further on the left marking the start of
797 * an aligned pixels block (eg. chunk of 8 pixels):
798 * character's x / blocksize * blocksize
800 * The division, being made on integers, achieves the
803 * For the Y-axis, we need to compute the character's y
804 * coordinate, but we don't need to align it.
807 col = area->tr_begin.tp_col;
808 row = area->tr_begin.tp_row;
809 x1 = (int)((col * vf->vf_width + vw->vw_draw_area.tr_begin.tp_col)
810 / VT_VGA_PIXELS_BLOCK)
811 * VT_VGA_PIXELS_BLOCK;
812 y1 = row * vf->vf_height + vw->vw_draw_area.tr_begin.tp_row;
815 * Compute the bottom right pixel position, again, aligned with
816 * the pixels block size.
818 * The same rules apply, we just add 1 to base the computation
819 * on the "right border" of the dirty area.
822 col = area->tr_end.tp_col;
823 row = area->tr_end.tp_row;
824 x2 = (int)howmany(col * vf->vf_width + vw->vw_draw_area.tr_begin.tp_col,
826 * VT_VGA_PIXELS_BLOCK;
827 y2 = row * vf->vf_height + vw->vw_draw_area.tr_begin.tp_row;
829 /* Clip the area to the screen size. */
830 x2 = min(x2, vw->vw_draw_area.tr_end.tp_col);
831 y2 = min(y2, vw->vw_draw_area.tr_end.tp_row);
834 * Now, we take care of N pixels line at a time (the first for
835 * loop, N = font height), and for these lines, draw one pixels
836 * block at a time (the second for loop), not a character at a
839 * Therefore, on the X-axis, characters my be drawn partially if
840 * they are not aligned on 8-pixels boundary.
842 * However, the operation is repeated for the full height of the
843 * font before moving to the next character, because it allows
844 * to keep the color settings and write mode, before perhaps
845 * changing them with the next one.
848 for (y = y1; y < y2; y += vf->vf_height) {
849 for (x = x1; x < x2; x += VT_VGA_PIXELS_BLOCK) {
850 vga_bitblt_one_text_pixels_block(vd, vw, x, y);
856 vga_bitblt_text_txtmode(struct vt_device *vd, const struct vt_window *vw,
857 const term_rect_t *area)
859 struct vga_softc *sc;
860 const struct vt_buf *vb;
861 unsigned int col, row;
869 for (row = area->tr_begin.tp_row; row < area->tr_end.tp_row; ++row) {
870 for (col = area->tr_begin.tp_col;
871 col < area->tr_end.tp_col;
874 * Get next character and its associated fg/bg
877 c = VTBUF_GET_FIELD(vb, row, col);
878 vt_determine_colors(c, VTBUF_ISCURSOR(vb, row, col),
882 * Convert character to CP437, which is the
883 * character set used by the VGA hardware by
886 ch = vga_get_cp437(TCHAR_CHARACTER(c));
888 /* Convert colors to VGA attributes. */
891 MEM_WRITE1(sc, (row * 80 + col) * 2 + 0,
893 MEM_WRITE1(sc, (row * 80 + col) * 2 + 1,
900 vga_bitblt_text(struct vt_device *vd, const struct vt_window *vw,
901 const term_rect_t *area)
904 if (!(vd->vd_flags & VDF_TEXTMODE)) {
905 vga_bitblt_text_gfxmode(vd, vw, area);
907 vga_bitblt_text_txtmode(vd, vw, area);
912 vga_bitblt_bitmap(struct vt_device *vd, const struct vt_window *vw,
913 const uint8_t *pattern, const uint8_t *mask,
914 unsigned int width, unsigned int height,
915 unsigned int x, unsigned int y, term_color_t fg, term_color_t bg)
917 unsigned int x1, y1, x2, y2, i, j, src_x, dst_x, x_count;
918 uint8_t pattern_2colors;
920 /* Align coordinates with the 8-pxels grid. */
921 x1 = rounddown(x, VT_VGA_PIXELS_BLOCK);
924 x2 = roundup(x + width, VT_VGA_PIXELS_BLOCK);
926 x2 = min(x2, vd->vd_width - 1);
927 y2 = min(y2, vd->vd_height - 1);
929 for (j = y1; j < y2; ++j) {
932 x_count = VT_VGA_PIXELS_BLOCK - dst_x;
934 for (i = x1; i < x2; i += VT_VGA_PIXELS_BLOCK) {
937 vga_copy_bitmap_portion(
938 &pattern_2colors, NULL,
939 pattern, mask, width,
940 src_x, dst_x, x_count,
941 j - y1, 0, 1, fg, bg, 0);
943 vga_bitblt_pixels_block_2colors(vd,
944 &pattern_2colors, fg, bg,
948 dst_x = (dst_x + x_count) % VT_VGA_PIXELS_BLOCK;
949 x_count = min(width - src_x, VT_VGA_PIXELS_BLOCK);
955 vga_initialize_graphics(struct vt_device *vd)
957 struct vga_softc *sc = vd->vd_softc;
960 REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, VGA_GEN_MO_VSP | VGA_GEN_MO_HSP |
961 VGA_GEN_MO_PB | VGA_GEN_MO_ER | VGA_GEN_MO_IOA);
962 /* Set sequencer clocking and memory mode. */
963 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CLOCKING_MODE);
964 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_CM_89);
965 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MEMORY_MODE);
966 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_OE | VGA_SEQ_MM_EM);
968 /* Set the graphics controller in graphics mode. */
969 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MISCELLANEOUS);
970 REG_WRITE1(sc, VGA_GC_DATA, 0x04 + VGA_GC_MISC_GA);
971 /* Program the CRT controller. */
972 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_TOTAL);
973 REG_WRITE1(sc, VGA_CRTC_DATA, 0x5f); /* 760 */
974 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_DISP_END);
975 REG_WRITE1(sc, VGA_CRTC_DATA, 0x4f); /* 640 - 8 */
976 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_BLANK);
977 REG_WRITE1(sc, VGA_CRTC_DATA, 0x50); /* 640 */
978 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_BLANK);
979 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHB_CR + 2);
980 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_RETRACE);
981 REG_WRITE1(sc, VGA_CRTC_DATA, 0x54); /* 672 */
982 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_RETRACE);
983 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHR_EHB + 0);
984 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_TOTAL);
985 REG_WRITE1(sc, VGA_CRTC_DATA, 0x0b); /* 523 */
986 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OVERFLOW);
987 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_OF_VT9 | VGA_CRTC_OF_LC8 |
988 VGA_CRTC_OF_VBS8 | VGA_CRTC_OF_VRS8 | VGA_CRTC_OF_VDE8);
989 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MAX_SCAN_LINE);
990 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MSL_LC9);
991 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_START);
992 REG_WRITE1(sc, VGA_CRTC_DATA, 0xea); /* 480 + 10 */
993 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END);
994 REG_WRITE1(sc, VGA_CRTC_DATA, 0x0c);
995 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_DISPLAY_END);
996 REG_WRITE1(sc, VGA_CRTC_DATA, 0xdf); /* 480 - 1*/
997 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OFFSET);
998 REG_WRITE1(sc, VGA_CRTC_DATA, 0x28);
999 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_VERT_BLANK);
1000 REG_WRITE1(sc, VGA_CRTC_DATA, 0xe7); /* 480 + 7 */
1001 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_VERT_BLANK);
1002 REG_WRITE1(sc, VGA_CRTC_DATA, 0x04);
1003 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL);
1004 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MC_WB | VGA_CRTC_MC_AW |
1005 VGA_CRTC_MC_SRS | VGA_CRTC_MC_CMS);
1006 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_LINE_COMPARE);
1007 REG_WRITE1(sc, VGA_CRTC_DATA, 0xff); /* 480 + 31 */
1009 REG_WRITE1(sc, VGA_GEN_FEATURE_CTRL_W, 0);
1011 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK);
1012 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 |
1013 VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0);
1014 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CHAR_MAP_SELECT);
1015 REG_WRITE1(sc, VGA_SEQ_DATA, 0);
1017 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET);
1018 REG_WRITE1(sc, VGA_GC_DATA, 0);
1019 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET);
1020 REG_WRITE1(sc, VGA_GC_DATA, 0x0f);
1021 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_COMPARE);
1022 REG_WRITE1(sc, VGA_GC_DATA, 0);
1023 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_DATA_ROTATE);
1024 REG_WRITE1(sc, VGA_GC_DATA, 0);
1025 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_READ_MAP_SELECT);
1026 REG_WRITE1(sc, VGA_GC_DATA, 0);
1027 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE);
1028 REG_WRITE1(sc, VGA_GC_DATA, 0);
1029 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_DONT_CARE);
1030 REG_WRITE1(sc, VGA_GC_DATA, 0x0f);
1031 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_BIT_MASK);
1032 REG_WRITE1(sc, VGA_GC_DATA, 0xff);
1036 vga_initialize(struct vt_device *vd, int textmode)
1038 struct vga_softc *sc = vd->vd_softc;
1042 /* Make sure the VGA adapter is not in monochrome emulation mode. */
1043 x = REG_READ1(sc, VGA_GEN_MISC_OUTPUT_R);
1044 REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, x | VGA_GEN_MO_IOA);
1046 /* Unprotect CRTC registers 0-7. */
1047 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END);
1048 x = REG_READ1(sc, VGA_CRTC_DATA);
1049 REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_VRE_PR);
1052 * Wait for the vertical retrace.
1053 * NOTE: this code reads the VGA_GEN_INPUT_STAT_1 register, which has
1054 * the side-effect of clearing the internal flip-flip of the attribute
1055 * controller's write register. This means that because this code is
1056 * here, we know for sure that the first write to the attribute
1057 * controller will be a write to the address register. Removing this
1058 * code therefore also removes that guarantee and appropriate measures
1064 x = REG_READ1(sc, VGA_GEN_INPUT_STAT_1);
1065 x &= VGA_GEN_IS1_VR | VGA_GEN_IS1_DE;
1066 } while (x != (VGA_GEN_IS1_VR | VGA_GEN_IS1_DE) && --timeout != 0);
1068 printf("Timeout initializing vt_vga\n");
1072 /* Now, disable the sync. signals. */
1073 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL);
1074 x = REG_READ1(sc, VGA_CRTC_DATA);
1075 REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_MC_HR);
1077 /* Asynchronous sequencer reset. */
1078 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET);
1079 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR);
1082 vga_initialize_graphics(vd);
1084 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_PRESET_ROW_SCAN);
1085 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
1086 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_START);
1087 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_CS_COO);
1088 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_END);
1089 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
1090 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_HIGH);
1091 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
1092 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_LOW);
1093 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
1094 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_HIGH);
1095 REG_WRITE1(sc, VGA_CRTC_DATA, 0);
1096 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_LOW);
1097 REG_WRITE1(sc, VGA_CRTC_DATA, 0x59);
1098 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_UNDERLINE_LOC);
1099 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_UL_UL);
1102 /* Set the attribute controller to blink disable. */
1103 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL);
1104 REG_WRITE1(sc, VGA_AC_WRITE, 0);
1106 /* Set the attribute controller in graphics mode. */
1107 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL);
1108 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MC_GA);
1109 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_HORIZ_PIXEL_PANNING);
1110 REG_WRITE1(sc, VGA_AC_WRITE, 0);
1112 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(0));
1113 REG_WRITE1(sc, VGA_AC_WRITE, 0);
1114 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(1));
1115 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R);
1116 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(2));
1117 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G);
1118 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(3));
1119 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SG | VGA_AC_PAL_R);
1120 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(4));
1121 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_B);
1122 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(5));
1123 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_B);
1124 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(6));
1125 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G | VGA_AC_PAL_B);
1126 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(7));
1127 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B);
1128 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(8));
1129 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1131 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(9));
1132 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1133 VGA_AC_PAL_SB | VGA_AC_PAL_R);
1134 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(10));
1135 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1136 VGA_AC_PAL_SB | VGA_AC_PAL_G);
1137 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(11));
1138 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1139 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G);
1140 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(12));
1141 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1142 VGA_AC_PAL_SB | VGA_AC_PAL_B);
1143 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(13));
1144 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1145 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_B);
1146 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(14));
1147 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1148 VGA_AC_PAL_SB | VGA_AC_PAL_G | VGA_AC_PAL_B);
1149 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(15));
1150 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG |
1151 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B);
1152 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_OVERSCAN_COLOR);
1153 REG_WRITE1(sc, VGA_AC_WRITE, 0);
1154 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_PLANE_ENABLE);
1155 REG_WRITE1(sc, VGA_AC_WRITE, 0x0f);
1156 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_SELECT);
1157 REG_WRITE1(sc, VGA_AC_WRITE, 0);
1163 * Done. Clear the frame buffer. All bit planes are
1164 * enabled, so a single-paged loop should clear all
1167 for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++) {
1168 MEM_WRITE1(sc, ofs, 0);
1172 /* Re-enable the sequencer. */
1173 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET);
1174 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR);
1175 /* Re-enable the sync signals. */
1176 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL);
1177 x = REG_READ1(sc, VGA_CRTC_DATA);
1178 REG_WRITE1(sc, VGA_CRTC_DATA, x | VGA_CRTC_MC_HR);
1181 /* Switch to write mode 3, because we'll mainly do bitblt. */
1182 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE);
1183 REG_WRITE1(sc, VGA_GC_DATA, 3);
1187 * In Write Mode 3, Enable Set/Reset is ignored, but we
1188 * use Write Mode 0 to write a group of 8 pixels using
1189 * 3 or more colors. In this case, we want to disable
1190 * Set/Reset: set Enable Set/Reset to 0.
1192 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET);
1193 REG_WRITE1(sc, VGA_GC_DATA, 0x00);
1196 * Clear the colors we think are loaded into Set/Reset or
1199 sc->vga_curfg = sc->vga_curbg = 0xff;
1206 vga_acpi_disabled(void)
1208 #if ((defined(__amd64__) || defined(__i386__)) && defined(DEV_ACPI))
1209 ACPI_TABLE_FADT *fadt;
1210 vm_paddr_t physaddr;
1213 physaddr = acpi_find_table(ACPI_SIG_FADT);
1217 fadt = acpi_map_table(physaddr, ACPI_SIG_FADT);
1219 printf("vt_vga: unable to map FADT ACPI table\n");
1223 flags = fadt->BootFlags;
1224 acpi_unmap_table(fadt);
1226 if (flags & ACPI_FADT_NO_VGA)
1234 vga_probe(struct vt_device *vd)
1237 return (vga_acpi_disabled() ? CN_DEAD : CN_INTERNAL);
1241 vga_init(struct vt_device *vd)
1243 struct vga_softc *sc;
1246 if (vd->vd_softc == NULL)
1247 vd->vd_softc = (void *)&vga_conssoftc;
1250 if (vd->vd_flags & VDF_DOWNGRADE && vd->vd_video_dev != NULL)
1251 vga_pci_repost(vd->vd_video_dev);
1253 #if defined(__amd64__) || defined(__i386__)
1254 sc->vga_fb_tag = X86_BUS_SPACE_MEM;
1255 sc->vga_reg_tag = X86_BUS_SPACE_IO;
1257 # error "Architecture not yet supported!"
1260 bus_space_map(sc->vga_reg_tag, VGA_REG_BASE, VGA_REG_SIZE, 0,
1261 &sc->vga_reg_handle);
1264 * If "hw.vga.textmode" is not set and we're running on hypervisor,
1265 * we use text mode by default, this is because when we're on
1266 * hypervisor, vt(4) is usually much slower in graphics mode than
1267 * in text mode, especially when we're on Hyper-V.
1269 textmode = vm_guest != VM_GUEST_NO;
1270 TUNABLE_INT_FETCH("hw.vga.textmode", &textmode);
1272 vd->vd_flags |= VDF_TEXTMODE;
1275 bus_space_map(sc->vga_fb_tag, VGA_TXT_BASE, VGA_TXT_SIZE, 0,
1276 &sc->vga_fb_handle);
1278 vd->vd_width = VT_VGA_WIDTH;
1279 vd->vd_height = VT_VGA_HEIGHT;
1280 bus_space_map(sc->vga_fb_tag, VGA_MEM_BASE, VGA_MEM_SIZE, 0,
1281 &sc->vga_fb_handle);
1283 if (vga_initialize(vd, textmode) != 0)
1285 sc->vga_enabled = true;
1287 return (CN_INTERNAL);
1291 vga_postswitch(struct vt_device *vd)
1294 /* Reinit VGA mode, to restore view after app which change mode. */
1295 vga_initialize(vd, (vd->vd_flags & VDF_TEXTMODE));
1296 /* Ask vt(9) to update chars on visible area. */
1297 vd->vd_flags |= VDF_INVALID;
1300 /* Dummy NewBus functions to reserve the resources used by the vt_vga driver */
1302 vtvga_identify(driver_t *driver, device_t parent)
1305 if (!vga_conssoftc.vga_enabled)
1308 if (BUS_ADD_CHILD(parent, 0, driver->name, 0) == NULL)
1309 panic("Unable to attach vt_vga console");
1313 vtvga_probe(device_t dev)
1316 device_set_desc(dev, "VT VGA driver");
1318 return (BUS_PROBE_NOWILDCARD);
1322 vtvga_attach(device_t dev)
1324 struct resource *pseudo_phys_res;
1328 pseudo_phys_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
1329 &res_id, VGA_MEM_BASE, VGA_MEM_BASE + VGA_MEM_SIZE - 1,
1330 VGA_MEM_SIZE, RF_ACTIVE);
1331 if (pseudo_phys_res == NULL)
1332 panic("Unable to reserve vt_vga memory");
1336 /*-------------------- Private Device Attachment Data -----------------------*/
1337 static device_method_t vtvga_methods[] = {
1338 /* Device interface */
1339 DEVMETHOD(device_identify, vtvga_identify),
1340 DEVMETHOD(device_probe, vtvga_probe),
1341 DEVMETHOD(device_attach, vtvga_attach),
1346 DEFINE_CLASS_0(vtvga, vtvga_driver, vtvga_methods, 0);
1347 devclass_t vtvga_devclass;
1349 DRIVER_MODULE(vtvga, nexus, vtvga_driver, vtvga_devclass, NULL, NULL);